From 4eba908bd2e18bb23a3112d95013a65628bbecd1 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 11:54:04 -0500 Subject: [PATCH] migrate code from microzig repo (#1) * migrate code from microzig repo * move robot file * add microzig submodule * add chips to build * add buildkite pipeline * try listing boards * change board names * revert pipeline --- .buildkite/pipeline.yml | 6 + .gitignore | 2 + .gitmodules | 3 + README.adoc | 2 +- build.zig | 35 + deps/microzig | 1 + src/boards.zig | 35 + src/boards/STM3240G_EVAL.zig | 10 + src/boards/STM32F3DISCOVERY.zig | 37 + src/boards/STM32F429IDISCOVERY.zig | 12 + src/boards/STM32F4DISCOVERY.zig | 14 + src/chips.zig | 48 + src/chips/STM32F103.json | 27474 ++++++++++++++ src/chips/STM32F103.zig | 10854 ++++++ src/chips/STM32F303.json | 33184 +++++++++++++++++ src/chips/STM32F303.zig | 13076 +++++++ src/chips/STM32F407.json | 50953 ++++++++++++++++++++++++++ src/chips/STM32F407.zig | 20004 ++++++++++ src/chips/STM32F429.json | 52094 +++++++++++++++++++++++++++ src/chips/STM32F429.zig | 20419 +++++++++++ src/hals/stm32f103.zig | 0 src/hals/stm32f303.zig | 602 + src/hals/stm32f407.zig | 623 + src/hals/stm32f429.zig | 92 + test/programs/minimal.zig | 5 + {tests => test}/stm32f103.robot | 0 26 files changed, 229584 insertions(+), 1 deletion(-) create mode 100644 .buildkite/pipeline.yml create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 build.zig create mode 160000 deps/microzig create mode 100644 src/boards.zig create mode 100644 src/boards/STM3240G_EVAL.zig create mode 100644 src/boards/STM32F3DISCOVERY.zig create mode 100644 src/boards/STM32F429IDISCOVERY.zig create mode 100644 src/boards/STM32F4DISCOVERY.zig create mode 100644 src/chips.zig create mode 100644 src/chips/STM32F103.json create mode 100644 src/chips/STM32F103.zig create mode 100644 src/chips/STM32F303.json create mode 100644 src/chips/STM32F303.zig create mode 100644 src/chips/STM32F407.json create mode 100644 src/chips/STM32F407.zig create mode 100644 src/chips/STM32F429.json create mode 100644 src/chips/STM32F429.zig create mode 100644 src/hals/stm32f103.zig create mode 100644 src/hals/stm32f303.zig create mode 100644 src/hals/stm32f407.zig create mode 100644 src/hals/stm32f429.zig create mode 100644 test/programs/minimal.zig rename {tests => test}/stm32f103.robot (100%) diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml new file mode 100644 index 0000000..ad6d380 --- /dev/null +++ b/.buildkite/pipeline.yml @@ -0,0 +1,6 @@ +steps: + - group: Build and Test + steps: + - command: zig build + - label: 🔨 Test + command: renode-test test/stm32f103.robot diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4c82b07 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-cache +zig-out diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..32e895c --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "deps/microzig"] + path = deps/microzig + url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/README.adoc b/README.adoc index d3f2f40..fdee92c 100644 --- a/README.adoc +++ b/README.adoc @@ -1,6 +1,6 @@ = stm32 -HAL for stm32 (STMicro) devices +HALs and register definitions for stm32 (STMicro) devices == stm32 boards that renode supports: diff --git a/build.zig b/build.zig new file mode 100644 index 0000000..3b787fe --- /dev/null +++ b/build.zig @@ -0,0 +1,35 @@ +const std = @import("std"); +const microzig = @import("deps/microzig/src/main.zig"); +const boards = @import("src/boards.zig"); +const chips = @import("src/chips.zig"); + +pub fn build(b: *std.build.Builder) void { + const optimize = b.standardOptimizeOption(.{}); + inline for (@typeInfo(boards).Struct.decls) |decl| { + if (!decl.is_pub) + continue; + + const exe = microzig.addEmbeddedExecutable( + b, + @field(boards, decl.name).name ++ ".minimal", + "test/programs/minimal.zig", + .{ .board = @field(boards, decl.name) }, + .{ .optimize = optimize }, + ); + exe.install(); + } + + inline for (@typeInfo(chips).Struct.decls) |decl| { + if (!decl.is_pub) + continue; + + const exe = microzig.addEmbeddedExecutable( + b, + @field(chips, decl.name).name ++ ".minimal", + "test/programs/minimal.zig", + .{ .chip = @field(chips, decl.name) }, + .{ .optimize = optimize }, + ); + exe.install(); + } +} diff --git a/deps/microzig b/deps/microzig new file mode 160000 index 0000000..97ca549 --- /dev/null +++ b/deps/microzig @@ -0,0 +1 @@ +Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 diff --git a/src/boards.zig b/src/boards.zig new file mode 100644 index 0000000..13f4c61 --- /dev/null +++ b/src/boards.zig @@ -0,0 +1,35 @@ +const std = @import("std"); +const microzig = @import("../deps/microzig/src/main.zig"); +const Board = microzig.Board; + +const chips = @import("chips.zig"); + +fn root() []const u8 { + return std.fs.path.dirname(@src().file) orelse unreachable; +} + +const root_path = root() ++ "/"; + +pub const stm32f3discovery = Board{ + .name = "STM32F3DISCOVERY", + .source = .{ .path = root_path ++ "boards/STM32F3DISCOVERY.zig" }, + .chip = chips.stm32f303vc, +}; + +pub const stm32f4discovery = Board{ + .name = "STM32F4DISCOVERY", + .source = .{ .path = root_path ++ "boards/STM32F4DISCOVERY.zig" }, + .chip = chips.stm32f407vg, +}; + +pub const stm3240geval = Board{ + .name = "STM3240G_EVAL", + .source = .{ .path = root_path ++ "boards/STM3240G_EVAL.zig" }, + .chip = chips.stm32f407vg, +}; + +pub const stm32f429idiscovery = Board{ + .name = "STM32F429IDISCOVERY", + .source = .{ .path = root_path ++ "boards/STM32F429IDISCOVERY.zig" }, + .chip = chips.stm32f429zit6u, +}; diff --git a/src/boards/STM3240G_EVAL.zig b/src/boards/STM3240G_EVAL.zig new file mode 100644 index 0000000..6261142 --- /dev/null +++ b/src/boards/STM3240G_EVAL.zig @@ -0,0 +1,10 @@ +pub const pin_map = .{ + // LD1 green + .LD1 = "PG6", + // LD2 orange + .LD2 = "PG8", + // LD3 red + .LD3 = "PI9", + // LD4 blue + .LD4 = "PC7", +}; diff --git a/src/boards/STM32F3DISCOVERY.zig b/src/boards/STM32F3DISCOVERY.zig new file mode 100644 index 0000000..9394bb8 --- /dev/null +++ b/src/boards/STM32F3DISCOVERY.zig @@ -0,0 +1,37 @@ +pub const micro = @import("microzig"); + +pub const cpu_frequency = 8_000_000; + +pub const pin_map = .{ + // circle of LEDs, connected to GPIOE bits 8..15 + + // NW blue + .LD4 = "PE8", + // N red + .LD3 = "PE9", + // NE orange + .LD5 = "PE10", + // E green + .LD7 = "PE11", + // SE blue + .LD9 = "PE12", + // S red + .LD10 = "PE13", + // SW orange + .LD8 = "PE14", + // W green + .LD6 = "PE15", +}; + +pub fn debug_write(string: []const u8) void { + const uart1 = micro.core.experimental.Uart(1, .{}).get_or_init(.{ + .baud_rate = 9600, + .data_bits = .eight, + .parity = null, + .stop_bits = .one, + }) catch unreachable; + + const writer = uart1.writer(); + _ = writer.write(string) catch unreachable; + uart1.internal.txflush(); +} diff --git a/src/boards/STM32F429IDISCOVERY.zig b/src/boards/STM32F429IDISCOVERY.zig new file mode 100644 index 0000000..034295a --- /dev/null +++ b/src/boards/STM32F429IDISCOVERY.zig @@ -0,0 +1,12 @@ +pub const cpu_frequency = 16_000_000; + +pub const pin_map = .{ + // LEDs, connected to GPIOG bits 13, 14 + // green + .LD3 = "PG13", + // red + .LD4 = "PG14", + + // User button + .B1 = "PA0", +}; diff --git a/src/boards/STM32F4DISCOVERY.zig b/src/boards/STM32F4DISCOVERY.zig new file mode 100644 index 0000000..062f334 --- /dev/null +++ b/src/boards/STM32F4DISCOVERY.zig @@ -0,0 +1,14 @@ +pub const pin_map = .{ + // LED cross, connected to GPIOD bits 12..15 + // N orange + .LD3 = "PD13", + // E red + .LD5 = "PD14", + // S blue + .LD6 = "PD15", + // W green + .LD4 = "PD12", + + // User button + .B2 = "PA0", +}; diff --git a/src/chips.zig b/src/chips.zig new file mode 100644 index 0000000..c492323 --- /dev/null +++ b/src/chips.zig @@ -0,0 +1,48 @@ +const std = @import("std"); +const microzig = @import("../deps/microzig/src/main.zig"); +const Chip = microzig.Chip; +const MemoryRegion = microzig.MemoryRegion; + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse "."; +} + +pub const stm32f103x8 = Chip.from_standard_paths(root_dir(), .{ + .name = "STM32F103", + .cpu = microzig.cpus.cortex_m3, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + }, +}); + +pub const stm32f303vc = Chip.from_standard_paths(root_dir(), .{ + .name = "STM32F303", + .cpu = microzig.cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram }, + }, +}); + +pub const stm32f407vg = Chip.from_standard_paths(root_dir(), .{ + .name = "STM32F407", + .cpu = microzig.cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram }, + // CCM RAM + MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, + }, +}); + +pub const stm32f429zit6u = Chip.from_standard_paths(root_dir(), .{ + .name = "STM32F429", + .cpu = microzig.cpus.cortex_m4, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram }, + // CCM RAM + MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, + }, +}); diff --git a/src/chips/STM32F103.json b/src/chips/STM32F103.json new file mode 100644 index 0000000..45b99d1 --- /dev/null +++ b/src/chips/STM32F103.json @@ -0,0 +1,27474 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "FSMC": { + "description": "Flexible static memory controller", + "children": { + "registers": { + "BCR1": { + "description": "SRAM/NOR-Flash chip-select control register\n 1", + "offset": 0, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR1": { + "description": "SRAM/NOR-Flash chip-select timing register\n 1", + "offset": 4, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR2": { + "description": "SRAM/NOR-Flash chip-select control register\n 2", + "offset": 8, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR2": { + "description": "SRAM/NOR-Flash chip-select timing register\n 2", + "offset": 12, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR3": { + "description": "SRAM/NOR-Flash chip-select control register\n 3", + "offset": 16, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR3": { + "description": "SRAM/NOR-Flash chip-select timing register\n 3", + "offset": 20, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR4": { + "description": "SRAM/NOR-Flash chip-select control register\n 4", + "offset": 24, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR4": { + "description": "SRAM/NOR-Flash chip-select timing register\n 4", + "offset": 28, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "PCR2": { + "description": "PC Card/NAND Flash control register\n 2", + "offset": 96, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR2": { + "description": "FIFO status and interrupt register\n 2", + "offset": 100, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM2": { + "description": "Common memory space timing register\n 2", + "offset": 104, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT2": { + "description": "Attribute memory space timing register\n 2", + "offset": 108, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "Attribute memory x databus HiZ\n time", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "Attribute memory x hold\n time", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "Attribute memory x wait\n time", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "Attribute memory x setup\n time", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR2": { + "description": "ECC result register 2", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECC result", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR3": { + "description": "PC Card/NAND Flash control register\n 3", + "offset": 128, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR3": { + "description": "FIFO status and interrupt register\n 3", + "offset": 132, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM3": { + "description": "Common memory space timing register\n 3", + "offset": 136, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT3": { + "description": "Attribute memory space timing register\n 3", + "offset": 140, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR3": { + "description": "ECC result register 3", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECCx", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR4": { + "description": "PC Card/NAND Flash control register\n 4", + "offset": 160, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR4": { + "description": "FIFO status and interrupt register\n 4", + "offset": 164, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM4": { + "description": "Common memory space timing register\n 4", + "offset": 168, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT4": { + "description": "Attribute memory space timing register\n 4", + "offset": 172, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PIO4": { + "description": "I/O space timing register 4", + "offset": 176, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOHIZx": { + "description": "IOHIZx", + "offset": 24, + "size": 8 + }, + "IOHOLDx": { + "description": "IOHOLDx", + "offset": 16, + "size": 8 + }, + "IOWAITx": { + "description": "IOWAITx", + "offset": 8, + "size": 8 + }, + "IOSETx": { + "description": "IOSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "BWTR1": { + "description": "SRAM/NOR-Flash write timing registers\n 1", + "offset": 260, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR2": { + "description": "SRAM/NOR-Flash write timing registers\n 2", + "offset": 268, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR3": { + "description": "SRAM/NOR-Flash write timing registers\n 3", + "offset": 276, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR4": { + "description": "SRAM/NOR-Flash write timing registers\n 4", + "offset": 284, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "PWR": { + "description": "Power control", + "children": { + "registers": { + "CR": { + "description": "Power control register\n (PWR_CR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LPDS": { + "description": "Low Power Deep Sleep", + "offset": 0, + "size": 1 + }, + "PDDS": { + "description": "Power Down Deep Sleep", + "offset": 1, + "size": 1 + }, + "CWUF": { + "description": "Clear Wake-up Flag", + "offset": 2, + "size": 1 + }, + "CSBF": { + "description": "Clear STANDBY Flag", + "offset": 3, + "size": 1 + }, + "PVDE": { + "description": "Power Voltage Detector\n Enable", + "offset": 4, + "size": 1 + }, + "PLS": { + "description": "PVD Level Selection", + "offset": 5, + "size": 3 + }, + "DBP": { + "description": "Disable Backup Domain write\n protection", + "offset": 8, + "size": 1 + } + } + } + }, + "CSR": { + "description": "Power control register\n (PWR_CR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUF": { + "description": "Wake-Up Flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SBF": { + "description": "STANDBY Flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PVDO": { + "description": "PVD Output", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "EWUP": { + "description": "Enable WKUP pin", + "offset": 8, + "size": 1 + } + } + } + } + } + } + }, + "RCC": { + "description": "Reset and clock control", + "children": { + "registers": { + "CR": { + "description": "Clock control register", + "offset": 0, + "size": 32, + "reset_value": 131, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSION": { + "description": "Internal High Speed clock\n enable", + "offset": 0, + "size": 1 + }, + "HSIRDY": { + "description": "Internal High Speed clock ready\n flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSITRIM": { + "description": "Internal High Speed clock\n trimming", + "offset": 3, + "size": 5 + }, + "HSICAL": { + "description": "Internal High Speed clock\n Calibration", + "offset": 8, + "size": 8, + "access": "read-only" + }, + "HSEON": { + "description": "External High Speed clock\n enable", + "offset": 16, + "size": 1 + }, + "HSERDY": { + "description": "External High Speed clock ready\n flag", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "HSEBYP": { + "description": "External High Speed clock\n Bypass", + "offset": 18, + "size": 1 + }, + "CSSON": { + "description": "Clock Security System\n enable", + "offset": 19, + "size": 1 + }, + "PLLON": { + "description": "PLL enable", + "offset": 24, + "size": 1 + }, + "PLLRDY": { + "description": "PLL clock ready flag", + "offset": 25, + "size": 1, + "access": "read-only" + } + } + } + }, + "CFGR": { + "description": "Clock configuration register\n (RCC_CFGR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SW": { + "description": "System clock Switch", + "offset": 0, + "size": 2 + }, + "SWS": { + "description": "System Clock Switch Status", + "offset": 2, + "size": 2, + "access": "read-only" + }, + "HPRE": { + "description": "AHB prescaler", + "offset": 4, + "size": 4 + }, + "PPRE1": { + "description": "APB Low speed prescaler\n (APB1)", + "offset": 8, + "size": 3 + }, + "PPRE2": { + "description": "APB High speed prescaler\n (APB2)", + "offset": 11, + "size": 3 + }, + "ADCPRE": { + "description": "ADC prescaler", + "offset": 14, + "size": 2 + }, + "PLLSRC": { + "description": "PLL entry clock source", + "offset": 16, + "size": 1 + }, + "PLLXTPRE": { + "description": "HSE divider for PLL entry", + "offset": 17, + "size": 1 + }, + "PLLMUL": { + "description": "PLL Multiplication Factor", + "offset": 18, + "size": 4 + }, + "OTGFSPRE": { + "description": "USB OTG FS prescaler", + "offset": 22, + "size": 1 + }, + "MCO": { + "description": "Microcontroller clock\n output", + "offset": 24, + "size": 3 + } + } + } + }, + "CIR": { + "description": "Clock interrupt register\n (RCC_CIR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSIRDYF": { + "description": "LSI Ready Interrupt flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "LSERDYF": { + "description": "LSE Ready Interrupt flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSIRDYF": { + "description": "HSI Ready Interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "HSERDYF": { + "description": "HSE Ready Interrupt flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "PLLRDYF": { + "description": "PLL Ready Interrupt flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "CSSF": { + "description": "Clock Security System Interrupt\n flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "LSIRDYIE": { + "description": "LSI Ready Interrupt Enable", + "offset": 8, + "size": 1 + }, + "LSERDYIE": { + "description": "LSE Ready Interrupt Enable", + "offset": 9, + "size": 1 + }, + "HSIRDYIE": { + "description": "HSI Ready Interrupt Enable", + "offset": 10, + "size": 1 + }, + "HSERDYIE": { + "description": "HSE Ready Interrupt Enable", + "offset": 11, + "size": 1 + }, + "PLLRDYIE": { + "description": "PLL Ready Interrupt Enable", + "offset": 12, + "size": 1 + }, + "LSIRDYC": { + "description": "LSI Ready Interrupt Clear", + "offset": 16, + "size": 1, + "access": "write-only" + }, + "LSERDYC": { + "description": "LSE Ready Interrupt Clear", + "offset": 17, + "size": 1, + "access": "write-only" + }, + "HSIRDYC": { + "description": "HSI Ready Interrupt Clear", + "offset": 18, + "size": 1, + "access": "write-only" + }, + "HSERDYC": { + "description": "HSE Ready Interrupt Clear", + "offset": 19, + "size": 1, + "access": "write-only" + }, + "PLLRDYC": { + "description": "PLL Ready Interrupt Clear", + "offset": 20, + "size": 1, + "access": "write-only" + }, + "CSSC": { + "description": "Clock security system interrupt\n clear", + "offset": 23, + "size": 1, + "access": "write-only" + } + } + } + }, + "APB2RSTR": { + "description": "APB2 peripheral reset register\n (RCC_APB2RSTR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFIORST": { + "description": "Alternate function I/O\n reset", + "offset": 0, + "size": 1 + }, + "IOPARST": { + "description": "IO port A reset", + "offset": 2, + "size": 1 + }, + "IOPBRST": { + "description": "IO port B reset", + "offset": 3, + "size": 1 + }, + "IOPCRST": { + "description": "IO port C reset", + "offset": 4, + "size": 1 + }, + "IOPDRST": { + "description": "IO port D reset", + "offset": 5, + "size": 1 + }, + "IOPERST": { + "description": "IO port E reset", + "offset": 6, + "size": 1 + }, + "IOPFRST": { + "description": "IO port F reset", + "offset": 7, + "size": 1 + }, + "IOPGRST": { + "description": "IO port G reset", + "offset": 8, + "size": 1 + }, + "ADC1RST": { + "description": "ADC 1 interface reset", + "offset": 9, + "size": 1 + }, + "ADC2RST": { + "description": "ADC 2 interface reset", + "offset": 10, + "size": 1 + }, + "TIM1RST": { + "description": "TIM1 timer reset", + "offset": 11, + "size": 1 + }, + "SPI1RST": { + "description": "SPI 1 reset", + "offset": 12, + "size": 1 + }, + "TIM8RST": { + "description": "TIM8 timer reset", + "offset": 13, + "size": 1 + }, + "USART1RST": { + "description": "USART1 reset", + "offset": 14, + "size": 1 + }, + "ADC3RST": { + "description": "ADC 3 interface reset", + "offset": 15, + "size": 1 + }, + "TIM9RST": { + "description": "TIM9 timer reset", + "offset": 19, + "size": 1 + }, + "TIM10RST": { + "description": "TIM10 timer reset", + "offset": 20, + "size": 1 + }, + "TIM11RST": { + "description": "TIM11 timer reset", + "offset": 21, + "size": 1 + } + } + } + }, + "APB1RSTR": { + "description": "APB1 peripheral reset register\n (RCC_APB1RSTR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2RST": { + "description": "Timer 2 reset", + "offset": 0, + "size": 1 + }, + "TIM3RST": { + "description": "Timer 3 reset", + "offset": 1, + "size": 1 + }, + "TIM4RST": { + "description": "Timer 4 reset", + "offset": 2, + "size": 1 + }, + "TIM5RST": { + "description": "Timer 5 reset", + "offset": 3, + "size": 1 + }, + "TIM6RST": { + "description": "Timer 6 reset", + "offset": 4, + "size": 1 + }, + "TIM7RST": { + "description": "Timer 7 reset", + "offset": 5, + "size": 1 + }, + "TIM12RST": { + "description": "Timer 12 reset", + "offset": 6, + "size": 1 + }, + "TIM13RST": { + "description": "Timer 13 reset", + "offset": 7, + "size": 1 + }, + "TIM14RST": { + "description": "Timer 14 reset", + "offset": 8, + "size": 1 + }, + "WWDGRST": { + "description": "Window watchdog reset", + "offset": 11, + "size": 1 + }, + "SPI2RST": { + "description": "SPI2 reset", + "offset": 14, + "size": 1 + }, + "SPI3RST": { + "description": "SPI3 reset", + "offset": 15, + "size": 1 + }, + "USART2RST": { + "description": "USART 2 reset", + "offset": 17, + "size": 1 + }, + "USART3RST": { + "description": "USART 3 reset", + "offset": 18, + "size": 1 + }, + "UART4RST": { + "description": "UART 4 reset", + "offset": 19, + "size": 1 + }, + "UART5RST": { + "description": "UART 5 reset", + "offset": 20, + "size": 1 + }, + "I2C1RST": { + "description": "I2C1 reset", + "offset": 21, + "size": 1 + }, + "I2C2RST": { + "description": "I2C2 reset", + "offset": 22, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 23, + "size": 1 + }, + "CANRST": { + "description": "CAN reset", + "offset": 25, + "size": 1 + }, + "BKPRST": { + "description": "Backup interface reset", + "offset": 27, + "size": 1 + }, + "PWRRST": { + "description": "Power interface reset", + "offset": 28, + "size": 1 + }, + "DACRST": { + "description": "DAC interface reset", + "offset": 29, + "size": 1 + } + } + } + }, + "AHBENR": { + "description": "AHB Peripheral Clock enable register\n (RCC_AHBENR)", + "offset": 20, + "size": 32, + "reset_value": 20, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMA1EN": { + "description": "DMA1 clock enable", + "offset": 0, + "size": 1 + }, + "DMA2EN": { + "description": "DMA2 clock enable", + "offset": 1, + "size": 1 + }, + "SRAMEN": { + "description": "SRAM interface clock\n enable", + "offset": 2, + "size": 1 + }, + "FLITFEN": { + "description": "FLITF clock enable", + "offset": 4, + "size": 1 + }, + "CRCEN": { + "description": "CRC clock enable", + "offset": 6, + "size": 1 + }, + "FSMCEN": { + "description": "FSMC clock enable", + "offset": 8, + "size": 1 + }, + "SDIOEN": { + "description": "SDIO clock enable", + "offset": 10, + "size": 1 + } + } + } + }, + "APB2ENR": { + "description": "APB2 peripheral clock enable register\n (RCC_APB2ENR)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFIOEN": { + "description": "Alternate function I/O clock\n enable", + "offset": 0, + "size": 1 + }, + "IOPAEN": { + "description": "I/O port A clock enable", + "offset": 2, + "size": 1 + }, + "IOPBEN": { + "description": "I/O port B clock enable", + "offset": 3, + "size": 1 + }, + "IOPCEN": { + "description": "I/O port C clock enable", + "offset": 4, + "size": 1 + }, + "IOPDEN": { + "description": "I/O port D clock enable", + "offset": 5, + "size": 1 + }, + "IOPEEN": { + "description": "I/O port E clock enable", + "offset": 6, + "size": 1 + }, + "IOPFEN": { + "description": "I/O port F clock enable", + "offset": 7, + "size": 1 + }, + "IOPGEN": { + "description": "I/O port G clock enable", + "offset": 8, + "size": 1 + }, + "ADC1EN": { + "description": "ADC 1 interface clock\n enable", + "offset": 9, + "size": 1 + }, + "ADC2EN": { + "description": "ADC 2 interface clock\n enable", + "offset": 10, + "size": 1 + }, + "TIM1EN": { + "description": "TIM1 Timer clock enable", + "offset": 11, + "size": 1 + }, + "SPI1EN": { + "description": "SPI 1 clock enable", + "offset": 12, + "size": 1 + }, + "TIM8EN": { + "description": "TIM8 Timer clock enable", + "offset": 13, + "size": 1 + }, + "USART1EN": { + "description": "USART1 clock enable", + "offset": 14, + "size": 1 + }, + "ADC3EN": { + "description": "ADC3 interface clock\n enable", + "offset": 15, + "size": 1 + }, + "TIM9EN": { + "description": "TIM9 Timer clock enable", + "offset": 19, + "size": 1 + }, + "TIM10EN": { + "description": "TIM10 Timer clock enable", + "offset": 20, + "size": 1 + }, + "TIM11EN": { + "description": "TIM11 Timer clock enable", + "offset": 21, + "size": 1 + } + } + } + }, + "APB1ENR": { + "description": "APB1 peripheral clock enable register\n (RCC_APB1ENR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2EN": { + "description": "Timer 2 clock enable", + "offset": 0, + "size": 1 + }, + "TIM3EN": { + "description": "Timer 3 clock enable", + "offset": 1, + "size": 1 + }, + "TIM4EN": { + "description": "Timer 4 clock enable", + "offset": 2, + "size": 1 + }, + "TIM5EN": { + "description": "Timer 5 clock enable", + "offset": 3, + "size": 1 + }, + "TIM6EN": { + "description": "Timer 6 clock enable", + "offset": 4, + "size": 1 + }, + "TIM7EN": { + "description": "Timer 7 clock enable", + "offset": 5, + "size": 1 + }, + "TIM12EN": { + "description": "Timer 12 clock enable", + "offset": 6, + "size": 1 + }, + "TIM13EN": { + "description": "Timer 13 clock enable", + "offset": 7, + "size": 1 + }, + "TIM14EN": { + "description": "Timer 14 clock enable", + "offset": 8, + "size": 1 + }, + "WWDGEN": { + "description": "Window watchdog clock\n enable", + "offset": 11, + "size": 1 + }, + "SPI2EN": { + "description": "SPI 2 clock enable", + "offset": 14, + "size": 1 + }, + "SPI3EN": { + "description": "SPI 3 clock enable", + "offset": 15, + "size": 1 + }, + "USART2EN": { + "description": "USART 2 clock enable", + "offset": 17, + "size": 1 + }, + "USART3EN": { + "description": "USART 3 clock enable", + "offset": 18, + "size": 1 + }, + "UART4EN": { + "description": "UART 4 clock enable", + "offset": 19, + "size": 1 + }, + "UART5EN": { + "description": "UART 5 clock enable", + "offset": 20, + "size": 1 + }, + "I2C1EN": { + "description": "I2C 1 clock enable", + "offset": 21, + "size": 1 + }, + "I2C2EN": { + "description": "I2C 2 clock enable", + "offset": 22, + "size": 1 + }, + "USBEN": { + "description": "USB clock enable", + "offset": 23, + "size": 1 + }, + "CANEN": { + "description": "CAN clock enable", + "offset": 25, + "size": 1 + }, + "BKPEN": { + "description": "Backup interface clock\n enable", + "offset": 27, + "size": 1 + }, + "PWREN": { + "description": "Power interface clock\n enable", + "offset": 28, + "size": 1 + }, + "DACEN": { + "description": "DAC interface clock enable", + "offset": 29, + "size": 1 + } + } + } + }, + "BDCR": { + "description": "Backup domain control register\n (RCC_BDCR)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSEON": { + "description": "External Low Speed oscillator\n enable", + "offset": 0, + "size": 1 + }, + "LSERDY": { + "description": "External Low Speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSEBYP": { + "description": "External Low Speed oscillator\n bypass", + "offset": 2, + "size": 1 + }, + "RTCSEL": { + "description": "RTC clock source selection", + "offset": 8, + "size": 2 + }, + "RTCEN": { + "description": "RTC clock enable", + "offset": 15, + "size": 1 + }, + "BDRST": { + "description": "Backup domain software\n reset", + "offset": 16, + "size": 1 + } + } + } + }, + "CSR": { + "description": "Control/status register\n (RCC_CSR)", + "offset": 36, + "size": 32, + "reset_value": 201326592, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSION": { + "description": "Internal low speed oscillator\n enable", + "offset": 0, + "size": 1 + }, + "LSIRDY": { + "description": "Internal low speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RMVF": { + "description": "Remove reset flag", + "offset": 24, + "size": 1 + }, + "PINRSTF": { + "description": "PIN reset flag", + "offset": 26, + "size": 1 + }, + "PORRSTF": { + "description": "POR/PDR reset flag", + "offset": 27, + "size": 1 + }, + "SFTRSTF": { + "description": "Software reset flag", + "offset": 28, + "size": 1 + }, + "IWDGRSTF": { + "description": "Independent watchdog reset\n flag", + "offset": 29, + "size": 1 + }, + "WWDGRSTF": { + "description": "Window watchdog reset flag", + "offset": 30, + "size": 1 + }, + "LPWRRSTF": { + "description": "Low-power reset flag", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "GPIOA": { + "description": "General purpose I/O", + "children": { + "registers": { + "CRL": { + "description": "Port configuration register low\n (GPIOn_CRL)", + "offset": 0, + "size": 32, + "reset_value": 1145324612, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE0": { + "description": "Port n.0 mode bits", + "offset": 0, + "size": 2 + }, + "CNF0": { + "description": "Port n.0 configuration\n bits", + "offset": 2, + "size": 2 + }, + "MODE1": { + "description": "Port n.1 mode bits", + "offset": 4, + "size": 2 + }, + "CNF1": { + "description": "Port n.1 configuration\n bits", + "offset": 6, + "size": 2 + }, + "MODE2": { + "description": "Port n.2 mode bits", + "offset": 8, + "size": 2 + }, + "CNF2": { + "description": "Port n.2 configuration\n bits", + "offset": 10, + "size": 2 + }, + "MODE3": { + "description": "Port n.3 mode bits", + "offset": 12, + "size": 2 + }, + "CNF3": { + "description": "Port n.3 configuration\n bits", + "offset": 14, + "size": 2 + }, + "MODE4": { + "description": "Port n.4 mode bits", + "offset": 16, + "size": 2 + }, + "CNF4": { + "description": "Port n.4 configuration\n bits", + "offset": 18, + "size": 2 + }, + "MODE5": { + "description": "Port n.5 mode bits", + "offset": 20, + "size": 2 + }, + "CNF5": { + "description": "Port n.5 configuration\n bits", + "offset": 22, + "size": 2 + }, + "MODE6": { + "description": "Port n.6 mode bits", + "offset": 24, + "size": 2 + }, + "CNF6": { + "description": "Port n.6 configuration\n bits", + "offset": 26, + "size": 2 + }, + "MODE7": { + "description": "Port n.7 mode bits", + "offset": 28, + "size": 2 + }, + "CNF7": { + "description": "Port n.7 configuration\n bits", + "offset": 30, + "size": 2 + } + } + } + }, + "CRH": { + "description": "Port configuration register high\n (GPIOn_CRL)", + "offset": 4, + "size": 32, + "reset_value": 1145324612, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE8": { + "description": "Port n.8 mode bits", + "offset": 0, + "size": 2 + }, + "CNF8": { + "description": "Port n.8 configuration\n bits", + "offset": 2, + "size": 2 + }, + "MODE9": { + "description": "Port n.9 mode bits", + "offset": 4, + "size": 2 + }, + "CNF9": { + "description": "Port n.9 configuration\n bits", + "offset": 6, + "size": 2 + }, + "MODE10": { + "description": "Port n.10 mode bits", + "offset": 8, + "size": 2 + }, + "CNF10": { + "description": "Port n.10 configuration\n bits", + "offset": 10, + "size": 2 + }, + "MODE11": { + "description": "Port n.11 mode bits", + "offset": 12, + "size": 2 + }, + "CNF11": { + "description": "Port n.11 configuration\n bits", + "offset": 14, + "size": 2 + }, + "MODE12": { + "description": "Port n.12 mode bits", + "offset": 16, + "size": 2 + }, + "CNF12": { + "description": "Port n.12 configuration\n bits", + "offset": 18, + "size": 2 + }, + "MODE13": { + "description": "Port n.13 mode bits", + "offset": 20, + "size": 2 + }, + "CNF13": { + "description": "Port n.13 configuration\n bits", + "offset": 22, + "size": 2 + }, + "MODE14": { + "description": "Port n.14 mode bits", + "offset": 24, + "size": 2 + }, + "CNF14": { + "description": "Port n.14 configuration\n bits", + "offset": 26, + "size": 2 + }, + "MODE15": { + "description": "Port n.15 mode bits", + "offset": 28, + "size": 2 + }, + "CNF15": { + "description": "Port n.15 configuration\n bits", + "offset": 30, + "size": 2 + } + } + } + }, + "IDR": { + "description": "Port input data register\n (GPIOn_IDR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR0": { + "description": "Port input data", + "offset": 0, + "size": 1 + }, + "IDR1": { + "description": "Port input data", + "offset": 1, + "size": 1 + }, + "IDR2": { + "description": "Port input data", + "offset": 2, + "size": 1 + }, + "IDR3": { + "description": "Port input data", + "offset": 3, + "size": 1 + }, + "IDR4": { + "description": "Port input data", + "offset": 4, + "size": 1 + }, + "IDR5": { + "description": "Port input data", + "offset": 5, + "size": 1 + }, + "IDR6": { + "description": "Port input data", + "offset": 6, + "size": 1 + }, + "IDR7": { + "description": "Port input data", + "offset": 7, + "size": 1 + }, + "IDR8": { + "description": "Port input data", + "offset": 8, + "size": 1 + }, + "IDR9": { + "description": "Port input data", + "offset": 9, + "size": 1 + }, + "IDR10": { + "description": "Port input data", + "offset": 10, + "size": 1 + }, + "IDR11": { + "description": "Port input data", + "offset": 11, + "size": 1 + }, + "IDR12": { + "description": "Port input data", + "offset": 12, + "size": 1 + }, + "IDR13": { + "description": "Port input data", + "offset": 13, + "size": 1 + }, + "IDR14": { + "description": "Port input data", + "offset": 14, + "size": 1 + }, + "IDR15": { + "description": "Port input data", + "offset": 15, + "size": 1 + } + } + } + }, + "ODR": { + "description": "Port output data register\n (GPIOn_ODR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR0": { + "description": "Port output data", + "offset": 0, + "size": 1 + }, + "ODR1": { + "description": "Port output data", + "offset": 1, + "size": 1 + }, + "ODR2": { + "description": "Port output data", + "offset": 2, + "size": 1 + }, + "ODR3": { + "description": "Port output data", + "offset": 3, + "size": 1 + }, + "ODR4": { + "description": "Port output data", + "offset": 4, + "size": 1 + }, + "ODR5": { + "description": "Port output data", + "offset": 5, + "size": 1 + }, + "ODR6": { + "description": "Port output data", + "offset": 6, + "size": 1 + }, + "ODR7": { + "description": "Port output data", + "offset": 7, + "size": 1 + }, + "ODR8": { + "description": "Port output data", + "offset": 8, + "size": 1 + }, + "ODR9": { + "description": "Port output data", + "offset": 9, + "size": 1 + }, + "ODR10": { + "description": "Port output data", + "offset": 10, + "size": 1 + }, + "ODR11": { + "description": "Port output data", + "offset": 11, + "size": 1 + }, + "ODR12": { + "description": "Port output data", + "offset": 12, + "size": 1 + }, + "ODR13": { + "description": "Port output data", + "offset": 13, + "size": 1 + }, + "ODR14": { + "description": "Port output data", + "offset": 14, + "size": 1 + }, + "ODR15": { + "description": "Port output data", + "offset": 15, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "Port bit set/reset register\n (GPIOn_BSRR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BS0": { + "description": "Set bit 0", + "offset": 0, + "size": 1 + }, + "BS1": { + "description": "Set bit 1", + "offset": 1, + "size": 1 + }, + "BS2": { + "description": "Set bit 1", + "offset": 2, + "size": 1 + }, + "BS3": { + "description": "Set bit 3", + "offset": 3, + "size": 1 + }, + "BS4": { + "description": "Set bit 4", + "offset": 4, + "size": 1 + }, + "BS5": { + "description": "Set bit 5", + "offset": 5, + "size": 1 + }, + "BS6": { + "description": "Set bit 6", + "offset": 6, + "size": 1 + }, + "BS7": { + "description": "Set bit 7", + "offset": 7, + "size": 1 + }, + "BS8": { + "description": "Set bit 8", + "offset": 8, + "size": 1 + }, + "BS9": { + "description": "Set bit 9", + "offset": 9, + "size": 1 + }, + "BS10": { + "description": "Set bit 10", + "offset": 10, + "size": 1 + }, + "BS11": { + "description": "Set bit 11", + "offset": 11, + "size": 1 + }, + "BS12": { + "description": "Set bit 12", + "offset": 12, + "size": 1 + }, + "BS13": { + "description": "Set bit 13", + "offset": 13, + "size": 1 + }, + "BS14": { + "description": "Set bit 14", + "offset": 14, + "size": 1 + }, + "BS15": { + "description": "Set bit 15", + "offset": 15, + "size": 1 + }, + "BR0": { + "description": "Reset bit 0", + "offset": 16, + "size": 1 + }, + "BR1": { + "description": "Reset bit 1", + "offset": 17, + "size": 1 + }, + "BR2": { + "description": "Reset bit 2", + "offset": 18, + "size": 1 + }, + "BR3": { + "description": "Reset bit 3", + "offset": 19, + "size": 1 + }, + "BR4": { + "description": "Reset bit 4", + "offset": 20, + "size": 1 + }, + "BR5": { + "description": "Reset bit 5", + "offset": 21, + "size": 1 + }, + "BR6": { + "description": "Reset bit 6", + "offset": 22, + "size": 1 + }, + "BR7": { + "description": "Reset bit 7", + "offset": 23, + "size": 1 + }, + "BR8": { + "description": "Reset bit 8", + "offset": 24, + "size": 1 + }, + "BR9": { + "description": "Reset bit 9", + "offset": 25, + "size": 1 + }, + "BR10": { + "description": "Reset bit 10", + "offset": 26, + "size": 1 + }, + "BR11": { + "description": "Reset bit 11", + "offset": 27, + "size": 1 + }, + "BR12": { + "description": "Reset bit 12", + "offset": 28, + "size": 1 + }, + "BR13": { + "description": "Reset bit 13", + "offset": 29, + "size": 1 + }, + "BR14": { + "description": "Reset bit 14", + "offset": 30, + "size": 1 + }, + "BR15": { + "description": "Reset bit 15", + "offset": 31, + "size": 1 + } + } + } + }, + "BRR": { + "description": "Port bit reset register\n (GPIOn_BRR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR0": { + "description": "Reset bit 0", + "offset": 0, + "size": 1 + }, + "BR1": { + "description": "Reset bit 1", + "offset": 1, + "size": 1 + }, + "BR2": { + "description": "Reset bit 1", + "offset": 2, + "size": 1 + }, + "BR3": { + "description": "Reset bit 3", + "offset": 3, + "size": 1 + }, + "BR4": { + "description": "Reset bit 4", + "offset": 4, + "size": 1 + }, + "BR5": { + "description": "Reset bit 5", + "offset": 5, + "size": 1 + }, + "BR6": { + "description": "Reset bit 6", + "offset": 6, + "size": 1 + }, + "BR7": { + "description": "Reset bit 7", + "offset": 7, + "size": 1 + }, + "BR8": { + "description": "Reset bit 8", + "offset": 8, + "size": 1 + }, + "BR9": { + "description": "Reset bit 9", + "offset": 9, + "size": 1 + }, + "BR10": { + "description": "Reset bit 10", + "offset": 10, + "size": 1 + }, + "BR11": { + "description": "Reset bit 11", + "offset": 11, + "size": 1 + }, + "BR12": { + "description": "Reset bit 12", + "offset": 12, + "size": 1 + }, + "BR13": { + "description": "Reset bit 13", + "offset": 13, + "size": 1 + }, + "BR14": { + "description": "Reset bit 14", + "offset": 14, + "size": 1 + }, + "BR15": { + "description": "Reset bit 15", + "offset": 15, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "Port configuration lock\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCK0": { + "description": "Port A Lock bit 0", + "offset": 0, + "size": 1 + }, + "LCK1": { + "description": "Port A Lock bit 1", + "offset": 1, + "size": 1 + }, + "LCK2": { + "description": "Port A Lock bit 2", + "offset": 2, + "size": 1 + }, + "LCK3": { + "description": "Port A Lock bit 3", + "offset": 3, + "size": 1 + }, + "LCK4": { + "description": "Port A Lock bit 4", + "offset": 4, + "size": 1 + }, + "LCK5": { + "description": "Port A Lock bit 5", + "offset": 5, + "size": 1 + }, + "LCK6": { + "description": "Port A Lock bit 6", + "offset": 6, + "size": 1 + }, + "LCK7": { + "description": "Port A Lock bit 7", + "offset": 7, + "size": 1 + }, + "LCK8": { + "description": "Port A Lock bit 8", + "offset": 8, + "size": 1 + }, + "LCK9": { + "description": "Port A Lock bit 9", + "offset": 9, + "size": 1 + }, + "LCK10": { + "description": "Port A Lock bit 10", + "offset": 10, + "size": 1 + }, + "LCK11": { + "description": "Port A Lock bit 11", + "offset": 11, + "size": 1 + }, + "LCK12": { + "description": "Port A Lock bit 12", + "offset": 12, + "size": 1 + }, + "LCK13": { + "description": "Port A Lock bit 13", + "offset": 13, + "size": 1 + }, + "LCK14": { + "description": "Port A Lock bit 14", + "offset": 14, + "size": 1 + }, + "LCK15": { + "description": "Port A Lock bit 15", + "offset": 15, + "size": 1 + }, + "LCKK": { + "description": "Lock key", + "offset": 16, + "size": 1 + } + } + } + } + } + } + }, + "STK": { + "description": "SysTick timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "TICKINT": { + "description": "SysTick exception request\n enable", + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "description": "Clock source selection", + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "description": "COUNTFLAG", + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD_": { + "description": "SysTick reload value register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RELOAD": { + "description": "RELOAD value", + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick current value register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CURRENT": { + "description": "Current counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick calibration value\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TENMS": { + "description": "Calibration value", + "offset": 0, + "size": 24 + } + } + } + } + } + } + }, + "SCB": { + "description": "System control block", + "children": { + "registers": { + "CPUID": { + "description": "CPUID base register", + "offset": 0, + "size": 32, + "reset_value": 1091551809, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Revision": { + "description": "Revision number", + "offset": 0, + "size": 4 + }, + "PartNo": { + "description": "Part number of the\n processor", + "offset": 4, + "size": 12 + }, + "Constant": { + "description": "Reads as 0xF", + "offset": 16, + "size": 4 + }, + "Variant": { + "description": "Variant number", + "offset": 20, + "size": 4 + }, + "Implementer": { + "description": "Implementer code", + "offset": 24, + "size": 8 + } + } + } + }, + "ICSR": { + "description": "Interrupt control and state\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTACTIVE": { + "description": "Active vector", + "offset": 0, + "size": 9 + }, + "RETTOBASE": { + "description": "Return to base level", + "offset": 11, + "size": 1 + }, + "VECTPENDING": { + "description": "Pending vector", + "offset": 12, + "size": 7 + }, + "ISRPENDING": { + "description": "Interrupt pending flag", + "offset": 22, + "size": 1 + }, + "PENDSTCLR": { + "description": "SysTick exception clear-pending\n bit", + "offset": 25, + "size": 1 + }, + "PENDSTSET": { + "description": "SysTick exception set-pending\n bit", + "offset": 26, + "size": 1 + }, + "PENDSVCLR": { + "description": "PendSV clear-pending bit", + "offset": 27, + "size": 1 + }, + "PENDSVSET": { + "description": "PendSV set-pending bit", + "offset": 28, + "size": 1 + }, + "NMIPENDSET": { + "description": "NMI set-pending bit.", + "offset": 31, + "size": 1 + } + } + } + }, + "VTOR": { + "description": "Vector table offset register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TBLOFF": { + "description": "Vector table base offset\n field", + "offset": 9, + "size": 21 + } + } + } + }, + "AIRCR": { + "description": "Application interrupt and reset control\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTRESET": { + "description": "VECTRESET", + "offset": 0, + "size": 1 + }, + "VECTCLRACTIVE": { + "description": "VECTCLRACTIVE", + "offset": 1, + "size": 1 + }, + "SYSRESETREQ": { + "description": "SYSRESETREQ", + "offset": 2, + "size": 1 + }, + "PRIGROUP": { + "description": "PRIGROUP", + "offset": 8, + "size": 3 + }, + "ENDIANESS": { + "description": "ENDIANESS", + "offset": 15, + "size": 1 + }, + "VECTKEYSTAT": { + "description": "Register key", + "offset": 16, + "size": 16 + } + } + } + }, + "SCR": { + "description": "System control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEPONEXIT": { + "description": "SLEEPONEXIT", + "offset": 1, + "size": 1 + }, + "SLEEPDEEP": { + "description": "SLEEPDEEP", + "offset": 2, + "size": 1 + }, + "SEVEONPEND": { + "description": "Send Event on Pending bit", + "offset": 4, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Configuration and control\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONBASETHRDENA": { + "description": "Configures how the processor enters\n Thread mode", + "offset": 0, + "size": 1 + }, + "USERSETMPEND": { + "description": "USERSETMPEND", + "offset": 1, + "size": 1 + }, + "UNALIGN__TRP": { + "description": "UNALIGN_ TRP", + "offset": 3, + "size": 1 + }, + "DIV_0_TRP": { + "description": "DIV_0_TRP", + "offset": 4, + "size": 1 + }, + "BFHFNMIGN": { + "description": "BFHFNMIGN", + "offset": 8, + "size": 1 + }, + "STKALIGN": { + "description": "STKALIGN", + "offset": 9, + "size": 1 + } + } + } + }, + "SHPR1": { + "description": "System handler priority\n registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_4": { + "description": "Priority of system handler\n 4", + "offset": 0, + "size": 8 + }, + "PRI_5": { + "description": "Priority of system handler\n 5", + "offset": 8, + "size": 8 + }, + "PRI_6": { + "description": "Priority of system handler\n 6", + "offset": 16, + "size": 8 + } + } + } + }, + "SHPR2": { + "description": "System handler priority\n registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_11": { + "description": "Priority of system handler\n 11", + "offset": 24, + "size": 8 + } + } + } + }, + "SHPR3": { + "description": "System handler priority\n registers", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_14": { + "description": "Priority of system handler\n 14", + "offset": 16, + "size": 8 + }, + "PRI_15": { + "description": "Priority of system handler\n 15", + "offset": 24, + "size": 8 + } + } + } + }, + "SHCRS": { + "description": "System handler control and state\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMFAULTACT": { + "description": "Memory management fault exception active\n bit", + "offset": 0, + "size": 1 + }, + "BUSFAULTACT": { + "description": "Bus fault exception active\n bit", + "offset": 1, + "size": 1 + }, + "USGFAULTACT": { + "description": "Usage fault exception active\n bit", + "offset": 3, + "size": 1 + }, + "SVCALLACT": { + "description": "SVC call active bit", + "offset": 7, + "size": 1 + }, + "MONITORACT": { + "description": "Debug monitor active bit", + "offset": 8, + "size": 1 + }, + "PENDSVACT": { + "description": "PendSV exception active\n bit", + "offset": 10, + "size": 1 + }, + "SYSTICKACT": { + "description": "SysTick exception active\n bit", + "offset": 11, + "size": 1 + }, + "USGFAULTPENDED": { + "description": "Usage fault exception pending\n bit", + "offset": 12, + "size": 1 + }, + "MEMFAULTPENDED": { + "description": "Memory management fault exception\n pending bit", + "offset": 13, + "size": 1 + }, + "BUSFAULTPENDED": { + "description": "Bus fault exception pending\n bit", + "offset": 14, + "size": 1 + }, + "SVCALLPENDED": { + "description": "SVC call pending bit", + "offset": 15, + "size": 1 + }, + "MEMFAULTENA": { + "description": "Memory management fault enable\n bit", + "offset": 16, + "size": 1 + }, + "BUSFAULTENA": { + "description": "Bus fault enable bit", + "offset": 17, + "size": 1 + }, + "USGFAULTENA": { + "description": "Usage fault enable bit", + "offset": 18, + "size": 1 + } + } + } + }, + "CFSR_UFSR_BFSR_MMFSR": { + "description": "Configurable fault status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IACCVIOL": { + "description": "IACCVIOL", + "offset": 0, + "size": 1 + }, + "DACCVIOL": { + "description": "DACCVIOL", + "offset": 1, + "size": 1 + }, + "MUNSTKERR": { + "description": "MUNSTKERR", + "offset": 3, + "size": 1 + }, + "MSTKERR": { + "description": "MSTKERR", + "offset": 4, + "size": 1 + }, + "MLSPERR": { + "description": "MLSPERR", + "offset": 5, + "size": 1 + }, + "MMARVALID": { + "description": "MMARVALID", + "offset": 7, + "size": 1 + }, + "IBUSERR": { + "description": "Instruction bus error", + "offset": 8, + "size": 1 + }, + "PRECISERR": { + "description": "Precise data bus error", + "offset": 9, + "size": 1 + }, + "IMPRECISERR": { + "description": "Imprecise data bus error", + "offset": 10, + "size": 1 + }, + "UNSTKERR": { + "description": "Bus fault on unstacking for a return\n from exception", + "offset": 11, + "size": 1 + }, + "STKERR": { + "description": "Bus fault on stacking for exception\n entry", + "offset": 12, + "size": 1 + }, + "LSPERR": { + "description": "Bus fault on floating-point lazy state\n preservation", + "offset": 13, + "size": 1 + }, + "BFARVALID": { + "description": "Bus Fault Address Register (BFAR) valid\n flag", + "offset": 15, + "size": 1 + }, + "UNDEFINSTR": { + "description": "Undefined instruction usage\n fault", + "offset": 16, + "size": 1 + }, + "INVSTATE": { + "description": "Invalid state usage fault", + "offset": 17, + "size": 1 + }, + "INVPC": { + "description": "Invalid PC load usage\n fault", + "offset": 18, + "size": 1 + }, + "NOCP": { + "description": "No coprocessor usage\n fault.", + "offset": 19, + "size": 1 + }, + "UNALIGNED": { + "description": "Unaligned access usage\n fault", + "offset": 24, + "size": 1 + }, + "DIVBYZERO": { + "description": "Divide by zero usage fault", + "offset": 25, + "size": 1 + } + } + } + }, + "HFSR": { + "description": "Hard fault status register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTTBL": { + "description": "Vector table hard fault", + "offset": 1, + "size": 1 + }, + "FORCED": { + "description": "Forced hard fault", + "offset": 30, + "size": 1 + }, + "DEBUG_VT": { + "description": "Reserved for Debug use", + "offset": 31, + "size": 1 + } + } + } + }, + "MMFAR": { + "description": "Memory management fault address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMFAR": { + "description": "Memory management fault\n address", + "offset": 0, + "size": 32 + } + } + } + }, + "BFAR": { + "description": "Bus fault address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BFAR": { + "description": "Bus fault address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "children": { + "registers": { + "STIR": { + "description": "Software trigger interrupt\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTID": { + "description": "Software generated interrupt\n ID", + "offset": 0, + "size": 9 + } + } + } + } + } + } + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "children": { + "registers": { + "ACTRL": { + "description": "Auxiliary control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DISFOLD": { + "description": "DISFOLD", + "offset": 2, + "size": 1 + }, + "FPEXCODIS": { + "description": "FPEXCODIS", + "offset": 10, + "size": 1 + }, + "DISRAMODE": { + "description": "DISRAMODE", + "offset": 11, + "size": 1 + }, + "DISITMATBFLUSH": { + "description": "DISITMATBFLUSH", + "offset": 12, + "size": 1 + } + } + } + } + } + } + }, + "MPU": { + "description": "Memory protection unit", + "children": { + "registers": { + "MPU_TYPER": { + "description": "MPU type register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEPARATE": { + "description": "Separate flag", + "offset": 0, + "size": 1 + }, + "DREGION": { + "description": "Number of MPU data regions", + "offset": 8, + "size": 8 + }, + "IREGION": { + "description": "Number of MPU instruction\n regions", + "offset": 16, + "size": 8 + } + } + } + }, + "MPU_CTRL": { + "description": "MPU control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ENABLE": { + "description": "Enables the MPU", + "offset": 0, + "size": 1 + }, + "HFNMIENA": { + "description": "Enables the operation of MPU during hard\n fault", + "offset": 1, + "size": 1 + }, + "PRIVDEFENA": { + "description": "Enable priviliged software access to\n default memory map", + "offset": 2, + "size": 1 + } + } + } + }, + "MPU_RNR": { + "description": "MPU region number register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region", + "offset": 0, + "size": 8 + } + } + } + }, + "MPU_RBAR": { + "description": "MPU region base address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region field", + "offset": 0, + "size": 4 + }, + "VALID": { + "description": "MPU region number valid", + "offset": 4, + "size": 1 + }, + "ADDR": { + "description": "Region base address field", + "offset": 5, + "size": 27 + } + } + } + }, + "MPU_RASR": { + "description": "MPU region attribute and size\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Region enable bit.", + "offset": 0, + "size": 1 + }, + "SIZE": { + "description": "Size of the MPU protection\n region", + "offset": 1, + "size": 5 + }, + "SRD": { + "description": "Subregion disable bits", + "offset": 8, + "size": 8 + }, + "B": { + "description": "memory attribute", + "offset": 16, + "size": 1 + }, + "C": { + "description": "memory attribute", + "offset": 17, + "size": 1 + }, + "S": { + "description": "Shareable memory attribute", + "offset": 18, + "size": 1 + }, + "TEX": { + "description": "memory attribute", + "offset": 19, + "size": 3 + }, + "AP": { + "description": "Access permission", + "offset": 24, + "size": 3 + }, + "XN": { + "description": "Instruction access disable\n bit", + "offset": 28, + "size": 1 + } + } + } + } + } + } + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "children": { + "registers": { + "ISER0": { + "description": "Interrupt Set-Enable Register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER1": { + "description": "Interrupt Set-Enable Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER0": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER1": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR0": { + "description": "Interrupt Set-Pending Register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR1": { + "description": "Interrupt Set-Pending Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR0": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR1": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR0": { + "description": "Interrupt Active Bit Register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR1": { + "description": "Interrupt Active Bit Register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IPR0": { + "description": "Interrupt Priority Register", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR1": { + "description": "Interrupt Priority Register", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR2": { + "description": "Interrupt Priority Register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR3": { + "description": "Interrupt Priority Register", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR4": { + "description": "Interrupt Priority Register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR5": { + "description": "Interrupt Priority Register", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR6": { + "description": "Interrupt Priority Register", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR7": { + "description": "Interrupt Priority Register", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR8": { + "description": "Interrupt Priority Register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR9": { + "description": "Interrupt Priority Register", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR10": { + "description": "Interrupt Priority Register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR11": { + "description": "Interrupt Priority Register", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR12": { + "description": "Interrupt Priority Register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR13": { + "description": "Interrupt Priority Register", + "offset": 820, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR14": { + "description": "Interrupt Priority Register", + "offset": 824, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + } + } + } + }, + "AFIO": { + "description": "Alternate function I/O", + "children": { + "registers": { + "EVCR": { + "description": "Event Control Register\n (AFIO_EVCR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PIN": { + "description": "Pin selection", + "offset": 0, + "size": 4 + }, + "PORT": { + "description": "Port selection", + "offset": 4, + "size": 3 + }, + "EVOE": { + "description": "Event Output Enable", + "offset": 7, + "size": 1 + } + } + } + }, + "MAPR": { + "description": "AF remap and debug I/O configuration\n register (AFIO_MAPR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPI1_REMAP": { + "description": "SPI1 remapping", + "offset": 0, + "size": 1 + }, + "I2C1_REMAP": { + "description": "I2C1 remapping", + "offset": 1, + "size": 1 + }, + "USART1_REMAP": { + "description": "USART1 remapping", + "offset": 2, + "size": 1 + }, + "USART2_REMAP": { + "description": "USART2 remapping", + "offset": 3, + "size": 1 + }, + "USART3_REMAP": { + "description": "USART3 remapping", + "offset": 4, + "size": 2 + }, + "TIM1_REMAP": { + "description": "TIM1 remapping", + "offset": 6, + "size": 2 + }, + "TIM2_REMAP": { + "description": "TIM2 remapping", + "offset": 8, + "size": 2 + }, + "TIM3_REMAP": { + "description": "TIM3 remapping", + "offset": 10, + "size": 2 + }, + "TIM4_REMAP": { + "description": "TIM4 remapping", + "offset": 12, + "size": 1 + }, + "CAN_REMAP": { + "description": "CAN1 remapping", + "offset": 13, + "size": 2 + }, + "PD01_REMAP": { + "description": "Port D0/Port D1 mapping on\n OSCIN/OSCOUT", + "offset": 15, + "size": 1 + }, + "TIM5CH4_IREMAP": { + "description": "Set and cleared by\n software", + "offset": 16, + "size": 1 + }, + "ADC1_ETRGINJ_REMAP": { + "description": "ADC 1 External trigger injected\n conversion remapping", + "offset": 17, + "size": 1 + }, + "ADC1_ETRGREG_REMAP": { + "description": "ADC 1 external trigger regular\n conversion remapping", + "offset": 18, + "size": 1 + }, + "ADC2_ETRGINJ_REMAP": { + "description": "ADC 2 external trigger injected\n conversion remapping", + "offset": 19, + "size": 1 + }, + "ADC2_ETRGREG_REMAP": { + "description": "ADC 2 external trigger regular\n conversion remapping", + "offset": 20, + "size": 1 + }, + "SWJ_CFG": { + "description": "Serial wire JTAG\n configuration", + "offset": 24, + "size": 3, + "access": "write-only" + } + } + } + }, + "EXTICR1": { + "description": "External interrupt configuration register 1\n (AFIO_EXTICR1)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI0": { + "description": "EXTI0 configuration", + "offset": 0, + "size": 4 + }, + "EXTI1": { + "description": "EXTI1 configuration", + "offset": 4, + "size": 4 + }, + "EXTI2": { + "description": "EXTI2 configuration", + "offset": 8, + "size": 4 + }, + "EXTI3": { + "description": "EXTI3 configuration", + "offset": 12, + "size": 4 + } + } + } + }, + "EXTICR2": { + "description": "External interrupt configuration register 2\n (AFIO_EXTICR2)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI4": { + "description": "EXTI4 configuration", + "offset": 0, + "size": 4 + }, + "EXTI5": { + "description": "EXTI5 configuration", + "offset": 4, + "size": 4 + }, + "EXTI6": { + "description": "EXTI6 configuration", + "offset": 8, + "size": 4 + }, + "EXTI7": { + "description": "EXTI7 configuration", + "offset": 12, + "size": 4 + } + } + } + }, + "EXTICR3": { + "description": "External interrupt configuration register 3\n (AFIO_EXTICR3)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI8": { + "description": "EXTI8 configuration", + "offset": 0, + "size": 4 + }, + "EXTI9": { + "description": "EXTI9 configuration", + "offset": 4, + "size": 4 + }, + "EXTI10": { + "description": "EXTI10 configuration", + "offset": 8, + "size": 4 + }, + "EXTI11": { + "description": "EXTI11 configuration", + "offset": 12, + "size": 4 + } + } + } + }, + "EXTICR4": { + "description": "External interrupt configuration register 4\n (AFIO_EXTICR4)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI12": { + "description": "EXTI12 configuration", + "offset": 0, + "size": 4 + }, + "EXTI13": { + "description": "EXTI13 configuration", + "offset": 4, + "size": 4 + }, + "EXTI14": { + "description": "EXTI14 configuration", + "offset": 8, + "size": 4 + }, + "EXTI15": { + "description": "EXTI15 configuration", + "offset": 12, + "size": 4 + } + } + } + }, + "MAPR2": { + "description": "AF remap and debug I/O configuration\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM9_REMAP": { + "description": "TIM9 remapping", + "offset": 5, + "size": 1 + }, + "TIM10_REMAP": { + "description": "TIM10 remapping", + "offset": 6, + "size": 1 + }, + "TIM11_REMAP": { + "description": "TIM11 remapping", + "offset": 7, + "size": 1 + }, + "TIM13_REMAP": { + "description": "TIM13 remapping", + "offset": 8, + "size": 1 + }, + "TIM14_REMAP": { + "description": "TIM14 remapping", + "offset": 9, + "size": 1 + }, + "FSMC_NADV": { + "description": "NADV connect/disconnect", + "offset": 10, + "size": 1 + } + } + } + } + } + } + }, + "EXTI": { + "description": "EXTI", + "children": { + "registers": { + "IMR": { + "description": "Interrupt mask register\n (EXTI_IMR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Interrupt Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Interrupt Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Interrupt Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Interrupt Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Interrupt Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Interrupt Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Interrupt Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Interrupt Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Interrupt Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Interrupt Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Interrupt Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Interrupt Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Interrupt Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Interrupt Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Interrupt Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Interrupt Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Interrupt Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Interrupt Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Interrupt Mask on line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "EMR": { + "description": "Event mask register (EXTI_EMR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Event Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Event Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Event Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Event Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Event Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Event Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Event Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Event Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Event Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Event Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Event Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Event Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Event Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Event Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Event Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Event Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Event Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Event Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Event Mask on line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "RTSR": { + "description": "Rising Trigger selection register\n (EXTI_RTSR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Rising trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Rising trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Rising trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Rising trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Rising trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Rising trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Rising trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Rising trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Rising trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Rising trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Rising trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Rising trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Rising trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Rising trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Rising trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Rising trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Rising trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Rising trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Rising trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "FTSR": { + "description": "Falling Trigger selection register\n (EXTI_FTSR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Falling trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Falling trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Falling trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Falling trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Falling trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Falling trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Falling trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Falling trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Falling trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Falling trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Falling trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Falling trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Falling trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Falling trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Falling trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Falling trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Falling trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Falling trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Falling trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "SWIER": { + "description": "Software interrupt event register\n (EXTI_SWIER)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIER0": { + "description": "Software Interrupt on line\n 0", + "offset": 0, + "size": 1 + }, + "SWIER1": { + "description": "Software Interrupt on line\n 1", + "offset": 1, + "size": 1 + }, + "SWIER2": { + "description": "Software Interrupt on line\n 2", + "offset": 2, + "size": 1 + }, + "SWIER3": { + "description": "Software Interrupt on line\n 3", + "offset": 3, + "size": 1 + }, + "SWIER4": { + "description": "Software Interrupt on line\n 4", + "offset": 4, + "size": 1 + }, + "SWIER5": { + "description": "Software Interrupt on line\n 5", + "offset": 5, + "size": 1 + }, + "SWIER6": { + "description": "Software Interrupt on line\n 6", + "offset": 6, + "size": 1 + }, + "SWIER7": { + "description": "Software Interrupt on line\n 7", + "offset": 7, + "size": 1 + }, + "SWIER8": { + "description": "Software Interrupt on line\n 8", + "offset": 8, + "size": 1 + }, + "SWIER9": { + "description": "Software Interrupt on line\n 9", + "offset": 9, + "size": 1 + }, + "SWIER10": { + "description": "Software Interrupt on line\n 10", + "offset": 10, + "size": 1 + }, + "SWIER11": { + "description": "Software Interrupt on line\n 11", + "offset": 11, + "size": 1 + }, + "SWIER12": { + "description": "Software Interrupt on line\n 12", + "offset": 12, + "size": 1 + }, + "SWIER13": { + "description": "Software Interrupt on line\n 13", + "offset": 13, + "size": 1 + }, + "SWIER14": { + "description": "Software Interrupt on line\n 14", + "offset": 14, + "size": 1 + }, + "SWIER15": { + "description": "Software Interrupt on line\n 15", + "offset": 15, + "size": 1 + }, + "SWIER16": { + "description": "Software Interrupt on line\n 16", + "offset": 16, + "size": 1 + }, + "SWIER17": { + "description": "Software Interrupt on line\n 17", + "offset": 17, + "size": 1 + }, + "SWIER18": { + "description": "Software Interrupt on line\n 18", + "offset": 18, + "size": 1 + } + } + } + }, + "PR": { + "description": "Pending register (EXTI_PR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR0": { + "description": "Pending bit 0", + "offset": 0, + "size": 1 + }, + "PR1": { + "description": "Pending bit 1", + "offset": 1, + "size": 1 + }, + "PR2": { + "description": "Pending bit 2", + "offset": 2, + "size": 1 + }, + "PR3": { + "description": "Pending bit 3", + "offset": 3, + "size": 1 + }, + "PR4": { + "description": "Pending bit 4", + "offset": 4, + "size": 1 + }, + "PR5": { + "description": "Pending bit 5", + "offset": 5, + "size": 1 + }, + "PR6": { + "description": "Pending bit 6", + "offset": 6, + "size": 1 + }, + "PR7": { + "description": "Pending bit 7", + "offset": 7, + "size": 1 + }, + "PR8": { + "description": "Pending bit 8", + "offset": 8, + "size": 1 + }, + "PR9": { + "description": "Pending bit 9", + "offset": 9, + "size": 1 + }, + "PR10": { + "description": "Pending bit 10", + "offset": 10, + "size": 1 + }, + "PR11": { + "description": "Pending bit 11", + "offset": 11, + "size": 1 + }, + "PR12": { + "description": "Pending bit 12", + "offset": 12, + "size": 1 + }, + "PR13": { + "description": "Pending bit 13", + "offset": 13, + "size": 1 + }, + "PR14": { + "description": "Pending bit 14", + "offset": 14, + "size": 1 + }, + "PR15": { + "description": "Pending bit 15", + "offset": 15, + "size": 1 + }, + "PR16": { + "description": "Pending bit 16", + "offset": 16, + "size": 1 + }, + "PR17": { + "description": "Pending bit 17", + "offset": 17, + "size": 1 + }, + "PR18": { + "description": "Pending bit 18", + "offset": 18, + "size": 1 + } + } + } + } + } + } + }, + "DMA1": { + "description": "DMA controller", + "children": { + "registers": { + "ISR": { + "description": "DMA interrupt status register\n (DMA_ISR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "GIF1": { + "description": "Channel 1 Global interrupt\n flag", + "offset": 0, + "size": 1 + }, + "TCIF1": { + "description": "Channel 1 Transfer Complete\n flag", + "offset": 1, + "size": 1 + }, + "HTIF1": { + "description": "Channel 1 Half Transfer Complete\n flag", + "offset": 2, + "size": 1 + }, + "TEIF1": { + "description": "Channel 1 Transfer Error\n flag", + "offset": 3, + "size": 1 + }, + "GIF2": { + "description": "Channel 2 Global interrupt\n flag", + "offset": 4, + "size": 1 + }, + "TCIF2": { + "description": "Channel 2 Transfer Complete\n flag", + "offset": 5, + "size": 1 + }, + "HTIF2": { + "description": "Channel 2 Half Transfer Complete\n flag", + "offset": 6, + "size": 1 + }, + "TEIF2": { + "description": "Channel 2 Transfer Error\n flag", + "offset": 7, + "size": 1 + }, + "GIF3": { + "description": "Channel 3 Global interrupt\n flag", + "offset": 8, + "size": 1 + }, + "TCIF3": { + "description": "Channel 3 Transfer Complete\n flag", + "offset": 9, + "size": 1 + }, + "HTIF3": { + "description": "Channel 3 Half Transfer Complete\n flag", + "offset": 10, + "size": 1 + }, + "TEIF3": { + "description": "Channel 3 Transfer Error\n flag", + "offset": 11, + "size": 1 + }, + "GIF4": { + "description": "Channel 4 Global interrupt\n flag", + "offset": 12, + "size": 1 + }, + "TCIF4": { + "description": "Channel 4 Transfer Complete\n flag", + "offset": 13, + "size": 1 + }, + "HTIF4": { + "description": "Channel 4 Half Transfer Complete\n flag", + "offset": 14, + "size": 1 + }, + "TEIF4": { + "description": "Channel 4 Transfer Error\n flag", + "offset": 15, + "size": 1 + }, + "GIF5": { + "description": "Channel 5 Global interrupt\n flag", + "offset": 16, + "size": 1 + }, + "TCIF5": { + "description": "Channel 5 Transfer Complete\n flag", + "offset": 17, + "size": 1 + }, + "HTIF5": { + "description": "Channel 5 Half Transfer Complete\n flag", + "offset": 18, + "size": 1 + }, + "TEIF5": { + "description": "Channel 5 Transfer Error\n flag", + "offset": 19, + "size": 1 + }, + "GIF6": { + "description": "Channel 6 Global interrupt\n flag", + "offset": 20, + "size": 1 + }, + "TCIF6": { + "description": "Channel 6 Transfer Complete\n flag", + "offset": 21, + "size": 1 + }, + "HTIF6": { + "description": "Channel 6 Half Transfer Complete\n flag", + "offset": 22, + "size": 1 + }, + "TEIF6": { + "description": "Channel 6 Transfer Error\n flag", + "offset": 23, + "size": 1 + }, + "GIF7": { + "description": "Channel 7 Global interrupt\n flag", + "offset": 24, + "size": 1 + }, + "TCIF7": { + "description": "Channel 7 Transfer Complete\n flag", + "offset": 25, + "size": 1 + }, + "HTIF7": { + "description": "Channel 7 Half Transfer Complete\n flag", + "offset": 26, + "size": 1 + }, + "TEIF7": { + "description": "Channel 7 Transfer Error\n flag", + "offset": 27, + "size": 1 + } + } + } + }, + "IFCR": { + "description": "DMA interrupt flag clear register\n (DMA_IFCR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CGIF1": { + "description": "Channel 1 Global interrupt\n clear", + "offset": 0, + "size": 1 + }, + "CGIF2": { + "description": "Channel 2 Global interrupt\n clear", + "offset": 4, + "size": 1 + }, + "CGIF3": { + "description": "Channel 3 Global interrupt\n clear", + "offset": 8, + "size": 1 + }, + "CGIF4": { + "description": "Channel 4 Global interrupt\n clear", + "offset": 12, + "size": 1 + }, + "CGIF5": { + "description": "Channel 5 Global interrupt\n clear", + "offset": 16, + "size": 1 + }, + "CGIF6": { + "description": "Channel 6 Global interrupt\n clear", + "offset": 20, + "size": 1 + }, + "CGIF7": { + "description": "Channel 7 Global interrupt\n clear", + "offset": 24, + "size": 1 + }, + "CTCIF1": { + "description": "Channel 1 Transfer Complete\n clear", + "offset": 1, + "size": 1 + }, + "CTCIF2": { + "description": "Channel 2 Transfer Complete\n clear", + "offset": 5, + "size": 1 + }, + "CTCIF3": { + "description": "Channel 3 Transfer Complete\n clear", + "offset": 9, + "size": 1 + }, + "CTCIF4": { + "description": "Channel 4 Transfer Complete\n clear", + "offset": 13, + "size": 1 + }, + "CTCIF5": { + "description": "Channel 5 Transfer Complete\n clear", + "offset": 17, + "size": 1 + }, + "CTCIF6": { + "description": "Channel 6 Transfer Complete\n clear", + "offset": 21, + "size": 1 + }, + "CTCIF7": { + "description": "Channel 7 Transfer Complete\n clear", + "offset": 25, + "size": 1 + }, + "CHTIF1": { + "description": "Channel 1 Half Transfer\n clear", + "offset": 2, + "size": 1 + }, + "CHTIF2": { + "description": "Channel 2 Half Transfer\n clear", + "offset": 6, + "size": 1 + }, + "CHTIF3": { + "description": "Channel 3 Half Transfer\n clear", + "offset": 10, + "size": 1 + }, + "CHTIF4": { + "description": "Channel 4 Half Transfer\n clear", + "offset": 14, + "size": 1 + }, + "CHTIF5": { + "description": "Channel 5 Half Transfer\n clear", + "offset": 18, + "size": 1 + }, + "CHTIF6": { + "description": "Channel 6 Half Transfer\n clear", + "offset": 22, + "size": 1 + }, + "CHTIF7": { + "description": "Channel 7 Half Transfer\n clear", + "offset": 26, + "size": 1 + }, + "CTEIF1": { + "description": "Channel 1 Transfer Error\n clear", + "offset": 3, + "size": 1 + }, + "CTEIF2": { + "description": "Channel 2 Transfer Error\n clear", + "offset": 7, + "size": 1 + }, + "CTEIF3": { + "description": "Channel 3 Transfer Error\n clear", + "offset": 11, + "size": 1 + }, + "CTEIF4": { + "description": "Channel 4 Transfer Error\n clear", + "offset": 15, + "size": 1 + }, + "CTEIF5": { + "description": "Channel 5 Transfer Error\n clear", + "offset": 19, + "size": 1 + }, + "CTEIF6": { + "description": "Channel 6 Transfer Error\n clear", + "offset": 23, + "size": 1 + }, + "CTEIF7": { + "description": "Channel 7 Transfer Error\n clear", + "offset": 27, + "size": 1 + } + } + } + }, + "CCR1": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR1": { + "description": "DMA channel 1 number of data\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR1": { + "description": "DMA channel 1 peripheral address\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR1": { + "description": "DMA channel 1 memory address\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR2": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR2": { + "description": "DMA channel 2 number of data\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR2": { + "description": "DMA channel 2 peripheral address\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR2": { + "description": "DMA channel 2 memory address\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR3": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR3": { + "description": "DMA channel 3 number of data\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR3": { + "description": "DMA channel 3 peripheral address\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR3": { + "description": "DMA channel 3 memory address\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR4": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR4": { + "description": "DMA channel 4 number of data\n register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR4": { + "description": "DMA channel 4 peripheral address\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR4": { + "description": "DMA channel 4 memory address\n register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR5": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR5": { + "description": "DMA channel 5 number of data\n register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR5": { + "description": "DMA channel 5 peripheral address\n register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR5": { + "description": "DMA channel 5 memory address\n register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR6": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR6": { + "description": "DMA channel 6 number of data\n register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR6": { + "description": "DMA channel 6 peripheral address\n register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR6": { + "description": "DMA channel 6 memory address\n register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR7": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR7": { + "description": "DMA channel 7 number of data\n register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR7": { + "description": "DMA channel 7 peripheral address\n register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR7": { + "description": "DMA channel 7 memory address\n register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "ETHERNET_DMA": { + "description": "Ethernet: DMA controller operation", + "children": { + "registers": { + "DMABMR": { + "description": "Ethernet DMA bus mode register", + "offset": 0, + "size": 32, + "reset_value": 131329, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "Software reset", + "offset": 0, + "size": 1 + }, + "DA": { + "description": "DMA Arbitration", + "offset": 1, + "size": 1 + }, + "DSL": { + "description": "Descriptor skip length", + "offset": 2, + "size": 5 + }, + "PBL": { + "description": "Programmable burst length", + "offset": 8, + "size": 6 + }, + "RTPR": { + "description": "Rx Tx priority ratio", + "offset": 14, + "size": 2 + }, + "FB": { + "description": "Fixed burst", + "offset": 16, + "size": 1 + }, + "RDP": { + "description": "Rx DMA PBL", + "offset": 17, + "size": 6 + }, + "USP": { + "description": "Use separate PBL", + "offset": 23, + "size": 1 + }, + "FPM": { + "description": "4xPBL mode", + "offset": 24, + "size": 1 + }, + "AAB": { + "description": "Address-aligned beats", + "offset": 25, + "size": 1 + } + } + } + }, + "DMATPDR": { + "description": "Ethernet DMA transmit poll demand\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TPD": { + "description": "Transmit poll demand", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARPDR": { + "description": "EHERNET DMA receive poll demand\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RPD": { + "description": "Receive poll demand", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARDLAR": { + "description": "Ethernet DMA receive descriptor list address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRL": { + "description": "Start of receive list", + "offset": 0, + "size": 32 + } + } + } + }, + "DMATDLAR": { + "description": "Ethernet DMA transmit descriptor list\n address register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STL": { + "description": "Start of transmit list", + "offset": 0, + "size": 32 + } + } + } + }, + "DMASR": { + "description": "Ethernet DMA status register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "Transmit status", + "offset": 0, + "size": 1 + }, + "TPSS": { + "description": "Transmit process stopped\n status", + "offset": 1, + "size": 1 + }, + "TBUS": { + "description": "Transmit buffer unavailable\n status", + "offset": 2, + "size": 1 + }, + "TJTS": { + "description": "Transmit jabber timeout\n status", + "offset": 3, + "size": 1 + }, + "ROS": { + "description": "Receive overflow status", + "offset": 4, + "size": 1 + }, + "TUS": { + "description": "Transmit underflow status", + "offset": 5, + "size": 1 + }, + "RS": { + "description": "Receive status", + "offset": 6, + "size": 1 + }, + "RBUS": { + "description": "Receive buffer unavailable\n status", + "offset": 7, + "size": 1 + }, + "RPSS": { + "description": "Receive process stopped\n status", + "offset": 8, + "size": 1 + }, + "PWTS": { + "description": "Receive watchdog timeout\n status", + "offset": 9, + "size": 1 + }, + "ETS": { + "description": "Early transmit status", + "offset": 10, + "size": 1 + }, + "FBES": { + "description": "Fatal bus error status", + "offset": 13, + "size": 1 + }, + "ERS": { + "description": "Early receive status", + "offset": 14, + "size": 1 + }, + "AIS": { + "description": "Abnormal interrupt summary", + "offset": 15, + "size": 1 + }, + "NIS": { + "description": "Normal interrupt summary", + "offset": 16, + "size": 1 + }, + "RPS": { + "description": "Receive process state", + "offset": 17, + "size": 3, + "access": "read-only" + }, + "TPS": { + "description": "Transmit process state", + "offset": 20, + "size": 3, + "access": "read-only" + }, + "EBS": { + "description": "Error bits status", + "offset": 23, + "size": 3, + "access": "read-only" + }, + "MMCS": { + "description": "MMC status", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PMTS": { + "description": "PMT status", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TSTS": { + "description": "Time stamp trigger status", + "offset": 29, + "size": 1, + "access": "read-only" + } + } + } + }, + "DMAOMR": { + "description": "Ethernet DMA operation mode\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "SR", + "offset": 1, + "size": 1 + }, + "OSF": { + "description": "OSF", + "offset": 2, + "size": 1 + }, + "RTC": { + "description": "RTC", + "offset": 3, + "size": 2 + }, + "FUGF": { + "description": "FUGF", + "offset": 6, + "size": 1 + }, + "FEF": { + "description": "FEF", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "ST", + "offset": 13, + "size": 1 + }, + "TTC": { + "description": "TTC", + "offset": 14, + "size": 3 + }, + "FTF": { + "description": "FTF", + "offset": 20, + "size": 1 + }, + "TSF": { + "description": "TSF", + "offset": 21, + "size": 1 + }, + "DFRF": { + "description": "DFRF", + "offset": 24, + "size": 1 + }, + "RSF": { + "description": "RSF", + "offset": 25, + "size": 1 + }, + "DTCEFD": { + "description": "DTCEFD", + "offset": 26, + "size": 1 + } + } + } + }, + "DMAIER": { + "description": "Ethernet DMA interrupt enable\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "Transmit interrupt enable", + "offset": 0, + "size": 1 + }, + "TPSIE": { + "description": "Transmit process stopped interrupt\n enable", + "offset": 1, + "size": 1 + }, + "TBUIE": { + "description": "Transmit buffer unavailable interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TJTIE": { + "description": "Transmit jabber timeout interrupt\n enable", + "offset": 3, + "size": 1 + }, + "ROIE": { + "description": "Overflow interrupt enable", + "offset": 4, + "size": 1 + }, + "TUIE": { + "description": "Underflow interrupt enable", + "offset": 5, + "size": 1 + }, + "RIE": { + "description": "Receive interrupt enable", + "offset": 6, + "size": 1 + }, + "RBUIE": { + "description": "Receive buffer unavailable interrupt\n enable", + "offset": 7, + "size": 1 + }, + "RPSIE": { + "description": "Receive process stopped interrupt\n enable", + "offset": 8, + "size": 1 + }, + "RWTIE": { + "description": "receive watchdog timeout interrupt\n enable", + "offset": 9, + "size": 1 + }, + "ETIE": { + "description": "Early transmit interrupt\n enable", + "offset": 10, + "size": 1 + }, + "FBEIE": { + "description": "Fatal bus error interrupt\n enable", + "offset": 13, + "size": 1 + }, + "ERIE": { + "description": "Early receive interrupt\n enable", + "offset": 14, + "size": 1 + }, + "AISE": { + "description": "Abnormal interrupt summary\n enable", + "offset": 15, + "size": 1 + }, + "NISE": { + "description": "Normal interrupt summary\n enable", + "offset": 16, + "size": 1 + } + } + } + }, + "DMAMFBOCR": { + "description": "Ethernet DMA missed frame and buffer\n overflow counter register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "MFC": { + "description": "Missed frames by the\n controller", + "offset": 0, + "size": 16 + }, + "OMFC": { + "description": "Overflow bit for missed frame\n counter", + "offset": 16, + "size": 1 + }, + "MFA": { + "description": "Missed frames by the\n application", + "offset": 17, + "size": 11 + }, + "OFOC": { + "description": "Overflow bit for FIFO overflow\n counter", + "offset": 28, + "size": 1 + } + } + } + }, + "DMACHTDR": { + "description": "Ethernet DMA current host transmit\n descriptor register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTDAP": { + "description": "Host transmit descriptor address\n pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRDR": { + "description": "Ethernet DMA current host receive descriptor\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRDAP": { + "description": "Host receive descriptor address\n pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHTBAR": { + "description": "Ethernet DMA current host transmit buffer\n address register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTBAP": { + "description": "Host transmit buffer address\n pointer", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRBAR": { + "description": "Ethernet DMA current host receive buffer\n address register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRBAP": { + "description": "Host receive buffer address\n pointer", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "children": { + "registers": { + "POWER": { + "description": "Bits 1:0 = PWRCTRL: Power supply control\n bits", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRCTRL": { + "description": "PWRCTRL", + "offset": 0, + "size": 2 + } + } + } + }, + "CLKCR": { + "description": "SDI clock control register\n (SDIO_CLKCR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLKDIV": { + "description": "Clock divide factor", + "offset": 0, + "size": 8 + }, + "CLKEN": { + "description": "Clock enable bit", + "offset": 8, + "size": 1 + }, + "PWRSAV": { + "description": "Power saving configuration\n bit", + "offset": 9, + "size": 1 + }, + "BYPASS": { + "description": "Clock divider bypass enable\n bit", + "offset": 10, + "size": 1 + }, + "WIDBUS": { + "description": "Wide bus mode enable bit", + "offset": 11, + "size": 2 + }, + "NEGEDGE": { + "description": "SDIO_CK dephasing selection\n bit", + "offset": 13, + "size": 1 + }, + "HWFC_EN": { + "description": "HW Flow Control enable", + "offset": 14, + "size": 1 + } + } + } + }, + "ARG": { + "description": "Bits 31:0 = : Command argument", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMDARG": { + "description": "Command argument", + "offset": 0, + "size": 32 + } + } + } + }, + "CMD": { + "description": "SDIO command register\n (SDIO_CMD)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMDINDEX": { + "description": "CMDINDEX", + "offset": 0, + "size": 6 + }, + "WAITRESP": { + "description": "WAITRESP", + "offset": 6, + "size": 2 + }, + "WAITINT": { + "description": "WAITINT", + "offset": 8, + "size": 1 + }, + "WAITPEND": { + "description": "WAITPEND", + "offset": 9, + "size": 1 + }, + "CPSMEN": { + "description": "CPSMEN", + "offset": 10, + "size": 1 + }, + "SDIOSuspend": { + "description": "SDIOSuspend", + "offset": 11, + "size": 1 + }, + "ENCMDcompl": { + "description": "ENCMDcompl", + "offset": 12, + "size": 1 + }, + "nIEN": { + "description": "nIEN", + "offset": 13, + "size": 1 + }, + "CE_ATACMD": { + "description": "CE_ATACMD", + "offset": 14, + "size": 1 + } + } + } + }, + "RESPCMD": { + "description": "SDIO command register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESPCMD": { + "description": "RESPCMD", + "offset": 0, + "size": 6 + } + } + } + }, + "RESPI1": { + "description": "Bits 31:0 = CARDSTATUS1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS1": { + "description": "CARDSTATUS1", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP2": { + "description": "Bits 31:0 = CARDSTATUS2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS2": { + "description": "CARDSTATUS2", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP3": { + "description": "Bits 31:0 = CARDSTATUS3", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS3": { + "description": "CARDSTATUS3", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP4": { + "description": "Bits 31:0 = CARDSTATUS4", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS4": { + "description": "CARDSTATUS4", + "offset": 0, + "size": 32 + } + } + } + }, + "DTIMER": { + "description": "Bits 31:0 = DATATIME: Data timeout\n period", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATATIME": { + "description": "Data timeout period", + "offset": 0, + "size": 32 + } + } + } + }, + "DLEN": { + "description": "Bits 24:0 = DATALENGTH: Data length\n value", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATALENGTH": { + "description": "Data length value", + "offset": 0, + "size": 25 + } + } + } + }, + "DCTRL": { + "description": "SDIO data control register\n (SDIO_DCTRL)", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DTEN": { + "description": "DTEN", + "offset": 0, + "size": 1 + }, + "DTDIR": { + "description": "DTDIR", + "offset": 1, + "size": 1 + }, + "DTMODE": { + "description": "DTMODE", + "offset": 2, + "size": 1 + }, + "DMAEN": { + "description": "DMAEN", + "offset": 3, + "size": 1 + }, + "DBLOCKSIZE": { + "description": "DBLOCKSIZE", + "offset": 4, + "size": 4 + }, + "PWSTART": { + "description": "PWSTART", + "offset": 8, + "size": 1 + }, + "PWSTOP": { + "description": "PWSTOP", + "offset": 9, + "size": 1 + }, + "RWMOD": { + "description": "RWMOD", + "offset": 10, + "size": 1 + }, + "SDIOEN": { + "description": "SDIOEN", + "offset": 11, + "size": 1 + } + } + } + }, + "DCOUNT": { + "description": "Bits 24:0 = DATACOUNT: Data count\n value", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATACOUNT": { + "description": "Data count value", + "offset": 0, + "size": 25 + } + } + } + }, + "STA": { + "description": "SDIO status register\n (SDIO_STA)", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CCRCFAIL": { + "description": "CCRCFAIL", + "offset": 0, + "size": 1 + }, + "DCRCFAIL": { + "description": "DCRCFAIL", + "offset": 1, + "size": 1 + }, + "CTIMEOUT": { + "description": "CTIMEOUT", + "offset": 2, + "size": 1 + }, + "DTIMEOUT": { + "description": "DTIMEOUT", + "offset": 3, + "size": 1 + }, + "TXUNDERR": { + "description": "TXUNDERR", + "offset": 4, + "size": 1 + }, + "RXOVERR": { + "description": "RXOVERR", + "offset": 5, + "size": 1 + }, + "CMDREND": { + "description": "CMDREND", + "offset": 6, + "size": 1 + }, + "CMDSENT": { + "description": "CMDSENT", + "offset": 7, + "size": 1 + }, + "DATAEND": { + "description": "DATAEND", + "offset": 8, + "size": 1 + }, + "STBITERR": { + "description": "STBITERR", + "offset": 9, + "size": 1 + }, + "DBCKEND": { + "description": "DBCKEND", + "offset": 10, + "size": 1 + }, + "CMDACT": { + "description": "CMDACT", + "offset": 11, + "size": 1 + }, + "TXACT": { + "description": "TXACT", + "offset": 12, + "size": 1 + }, + "RXACT": { + "description": "RXACT", + "offset": 13, + "size": 1 + }, + "TXFIFOHE": { + "description": "TXFIFOHE", + "offset": 14, + "size": 1 + }, + "RXFIFOHF": { + "description": "RXFIFOHF", + "offset": 15, + "size": 1 + }, + "TXFIFOF": { + "description": "TXFIFOF", + "offset": 16, + "size": 1 + }, + "RXFIFOF": { + "description": "RXFIFOF", + "offset": 17, + "size": 1 + }, + "TXFIFOE": { + "description": "TXFIFOE", + "offset": 18, + "size": 1 + }, + "RXFIFOE": { + "description": "RXFIFOE", + "offset": 19, + "size": 1 + }, + "TXDAVL": { + "description": "TXDAVL", + "offset": 20, + "size": 1 + }, + "RXDAVL": { + "description": "RXDAVL", + "offset": 21, + "size": 1 + }, + "SDIOIT": { + "description": "SDIOIT", + "offset": 22, + "size": 1 + }, + "CEATAEND": { + "description": "CEATAEND", + "offset": 23, + "size": 1 + } + } + } + }, + "ICR": { + "description": "SDIO interrupt clear register\n (SDIO_ICR)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCRCFAILC": { + "description": "CCRCFAILC", + "offset": 0, + "size": 1 + }, + "DCRCFAILC": { + "description": "DCRCFAILC", + "offset": 1, + "size": 1 + }, + "CTIMEOUTC": { + "description": "CTIMEOUTC", + "offset": 2, + "size": 1 + }, + "DTIMEOUTC": { + "description": "DTIMEOUTC", + "offset": 3, + "size": 1 + }, + "TXUNDERRC": { + "description": "TXUNDERRC", + "offset": 4, + "size": 1 + }, + "RXOVERRC": { + "description": "RXOVERRC", + "offset": 5, + "size": 1 + }, + "CMDRENDC": { + "description": "CMDRENDC", + "offset": 6, + "size": 1 + }, + "CMDSENTC": { + "description": "CMDSENTC", + "offset": 7, + "size": 1 + }, + "DATAENDC": { + "description": "DATAENDC", + "offset": 8, + "size": 1 + }, + "STBITERRC": { + "description": "STBITERRC", + "offset": 9, + "size": 1 + }, + "DBCKENDC": { + "description": "DBCKENDC", + "offset": 10, + "size": 1 + }, + "SDIOITC": { + "description": "SDIOITC", + "offset": 22, + "size": 1 + }, + "CEATAENDC": { + "description": "CEATAENDC", + "offset": 23, + "size": 1 + } + } + } + }, + "MASK": { + "description": "SDIO mask register (SDIO_MASK)", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCRCFAILIE": { + "description": "CCRCFAILIE", + "offset": 0, + "size": 1 + }, + "DCRCFAILIE": { + "description": "DCRCFAILIE", + "offset": 1, + "size": 1 + }, + "CTIMEOUTIE": { + "description": "CTIMEOUTIE", + "offset": 2, + "size": 1 + }, + "DTIMEOUTIE": { + "description": "DTIMEOUTIE", + "offset": 3, + "size": 1 + }, + "TXUNDERRIE": { + "description": "TXUNDERRIE", + "offset": 4, + "size": 1 + }, + "RXOVERRIE": { + "description": "RXOVERRIE", + "offset": 5, + "size": 1 + }, + "CMDRENDIE": { + "description": "CMDRENDIE", + "offset": 6, + "size": 1 + }, + "CMDSENTIE": { + "description": "CMDSENTIE", + "offset": 7, + "size": 1 + }, + "DATAENDIE": { + "description": "DATAENDIE", + "offset": 8, + "size": 1 + }, + "STBITERRIE": { + "description": "STBITERRIE", + "offset": 9, + "size": 1 + }, + "DBACKENDIE": { + "description": "DBACKENDIE", + "offset": 10, + "size": 1 + }, + "CMDACTIE": { + "description": "CMDACTIE", + "offset": 11, + "size": 1 + }, + "TXACTIE": { + "description": "TXACTIE", + "offset": 12, + "size": 1 + }, + "RXACTIE": { + "description": "RXACTIE", + "offset": 13, + "size": 1 + }, + "TXFIFOHEIE": { + "description": "TXFIFOHEIE", + "offset": 14, + "size": 1 + }, + "RXFIFOHFIE": { + "description": "RXFIFOHFIE", + "offset": 15, + "size": 1 + }, + "TXFIFOFIE": { + "description": "TXFIFOFIE", + "offset": 16, + "size": 1 + }, + "RXFIFOFIE": { + "description": "RXFIFOFIE", + "offset": 17, + "size": 1 + }, + "TXFIFOEIE": { + "description": "TXFIFOEIE", + "offset": 18, + "size": 1 + }, + "RXFIFOEIE": { + "description": "RXFIFOEIE", + "offset": 19, + "size": 1 + }, + "TXDAVLIE": { + "description": "TXDAVLIE", + "offset": 20, + "size": 1 + }, + "RXDAVLIE": { + "description": "RXDAVLIE", + "offset": 21, + "size": 1 + }, + "SDIOITIE": { + "description": "SDIOITIE", + "offset": 22, + "size": 1 + }, + "CEATENDIE": { + "description": "CEATENDIE", + "offset": 23, + "size": 1 + } + } + } + }, + "FIFOCNT": { + "description": "Bits 23:0 = FIFOCOUNT: Remaining number of\n words to be written to or read from the\n FIFO", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FIF0COUNT": { + "description": "FIF0COUNT", + "offset": 0, + "size": 24 + } + } + } + }, + "FIFO": { + "description": "bits 31:0 = FIFOData: Receive and transmit\n FIFO data", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FIFOData": { + "description": "FIFOData", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "RTC": { + "description": "Real time clock", + "children": { + "registers": { + "CRH": { + "description": "RTC Control Register High", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SECIE": { + "description": "Second interrupt Enable", + "offset": 0, + "size": 1 + }, + "ALRIE": { + "description": "Alarm interrupt Enable", + "offset": 1, + "size": 1 + }, + "OWIE": { + "description": "Overflow interrupt Enable", + "offset": 2, + "size": 1 + } + } + } + }, + "CRL": { + "description": "RTC Control Register Low", + "offset": 4, + "size": 32, + "reset_value": 32, + "reset_mask": 4294967295, + "children": { + "fields": { + "SECF": { + "description": "Second Flag", + "offset": 0, + "size": 1 + }, + "ALRF": { + "description": "Alarm Flag", + "offset": 1, + "size": 1 + }, + "OWF": { + "description": "Overflow Flag", + "offset": 2, + "size": 1 + }, + "RSF": { + "description": "Registers Synchronized\n Flag", + "offset": 3, + "size": 1 + }, + "CNF": { + "description": "Configuration Flag", + "offset": 4, + "size": 1 + }, + "RTOFF": { + "description": "RTC operation OFF", + "offset": 5, + "size": 1, + "access": "read-only" + } + } + } + }, + "PRLH": { + "description": "RTC Prescaler Load Register\n High", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "PRLH": { + "description": "RTC Prescaler Load Register\n High", + "offset": 0, + "size": 4 + } + } + } + }, + "PRLL": { + "description": "RTC Prescaler Load Register\n Low", + "offset": 12, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "PRLL": { + "description": "RTC Prescaler Divider Register\n Low", + "offset": 0, + "size": 16 + } + } + } + }, + "DIVH": { + "description": "RTC Prescaler Divider Register\n High", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DIVH": { + "description": "RTC prescaler divider register\n high", + "offset": 0, + "size": 4 + } + } + } + }, + "DIVL": { + "description": "RTC Prescaler Divider Register\n Low", + "offset": 20, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DIVL": { + "description": "RTC prescaler divider register\n Low", + "offset": 0, + "size": 16 + } + } + } + }, + "CNTH": { + "description": "RTC Counter Register High", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNTH": { + "description": "RTC counter register high", + "offset": 0, + "size": 16 + } + } + } + }, + "CNTL": { + "description": "RTC Counter Register Low", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNTL": { + "description": "RTC counter register Low", + "offset": 0, + "size": 16 + } + } + } + }, + "ALRH": { + "description": "RTC Alarm Register High", + "offset": 32, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ALRH": { + "description": "RTC alarm register high", + "offset": 0, + "size": 16 + } + } + } + }, + "ALRL": { + "description": "RTC Alarm Register Low", + "offset": 36, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ALRL": { + "description": "RTC alarm register low", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "BKP": { + "description": "Backup registers", + "children": { + "registers": { + "DR1": { + "description": "Backup data register (BKP_DR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D1": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR2": { + "description": "Backup data register (BKP_DR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D2": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR3": { + "description": "Backup data register (BKP_DR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D3": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR4": { + "description": "Backup data register (BKP_DR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D4": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR5": { + "description": "Backup data register (BKP_DR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D5": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR6": { + "description": "Backup data register (BKP_DR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D6": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR7": { + "description": "Backup data register (BKP_DR)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D7": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR8": { + "description": "Backup data register (BKP_DR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D8": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR9": { + "description": "Backup data register (BKP_DR)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D9": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR10": { + "description": "Backup data register (BKP_DR)", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D10": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR11": { + "description": "Backup data register (BKP_DR)", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR11": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR12": { + "description": "Backup data register (BKP_DR)", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR12": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR13": { + "description": "Backup data register (BKP_DR)", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR13": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR14": { + "description": "Backup data register (BKP_DR)", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D14": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR15": { + "description": "Backup data register (BKP_DR)", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D15": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR16": { + "description": "Backup data register (BKP_DR)", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D16": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR17": { + "description": "Backup data register (BKP_DR)", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D17": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR18": { + "description": "Backup data register (BKP_DR)", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D18": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR19": { + "description": "Backup data register (BKP_DR)", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D19": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR20": { + "description": "Backup data register (BKP_DR)", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D20": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR21": { + "description": "Backup data register (BKP_DR)", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D21": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR22": { + "description": "Backup data register (BKP_DR)", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D22": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR23": { + "description": "Backup data register (BKP_DR)", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D23": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR24": { + "description": "Backup data register (BKP_DR)", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D24": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR25": { + "description": "Backup data register (BKP_DR)", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D25": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR26": { + "description": "Backup data register (BKP_DR)", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D26": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR27": { + "description": "Backup data register (BKP_DR)", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D27": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR28": { + "description": "Backup data register (BKP_DR)", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D28": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR29": { + "description": "Backup data register (BKP_DR)", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D29": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR30": { + "description": "Backup data register (BKP_DR)", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D30": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR31": { + "description": "Backup data register (BKP_DR)", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D31": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR32": { + "description": "Backup data register (BKP_DR)", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D32": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR33": { + "description": "Backup data register (BKP_DR)", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D33": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR34": { + "description": "Backup data register (BKP_DR)", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D34": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR35": { + "description": "Backup data register (BKP_DR)", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D35": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR36": { + "description": "Backup data register (BKP_DR)", + "offset": 160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D36": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR37": { + "description": "Backup data register (BKP_DR)", + "offset": 164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D37": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR38": { + "description": "Backup data register (BKP_DR)", + "offset": 168, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D38": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR39": { + "description": "Backup data register (BKP_DR)", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D39": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR40": { + "description": "Backup data register (BKP_DR)", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D40": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR41": { + "description": "Backup data register (BKP_DR)", + "offset": 180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D41": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR42": { + "description": "Backup data register (BKP_DR)", + "offset": 184, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "D42": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "RTCCR": { + "description": "RTC clock calibration register\n (BKP_RTCCR)", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CAL": { + "description": "Calibration value", + "offset": 0, + "size": 7 + }, + "CCO": { + "description": "Calibration Clock Output", + "offset": 7, + "size": 1 + }, + "ASOE": { + "description": "Alarm or second output\n enable", + "offset": 8, + "size": 1 + }, + "ASOS": { + "description": "Alarm or second output\n selection", + "offset": 9, + "size": 1 + } + } + } + }, + "CR": { + "description": "Backup control register\n (BKP_CR)", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TPE": { + "description": "Tamper pin enable", + "offset": 0, + "size": 1 + }, + "TPAL": { + "description": "Tamper pin active level", + "offset": 1, + "size": 1 + } + } + } + }, + "CSR": { + "description": "BKP_CSR control/status register\n (BKP_CSR)", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTE": { + "description": "Clear Tamper event", + "offset": 0, + "size": 1, + "access": "write-only" + }, + "CTI": { + "description": "Clear Tamper Interrupt", + "offset": 1, + "size": 1, + "access": "write-only" + }, + "TPIE": { + "description": "Tamper Pin interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEF": { + "description": "Tamper Event Flag", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "TIF": { + "description": "Tamper Interrupt Flag", + "offset": 9, + "size": 1, + "access": "read-only" + } + } + } + } + } + } + }, + "IWDG": { + "description": "Independent watchdog", + "children": { + "registers": { + "KR": { + "description": "Key register (IWDG_KR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Key value", + "offset": 0, + "size": 16 + } + } + } + }, + "PR": { + "description": "Prescaler register (IWDG_PR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR": { + "description": "Prescaler divider", + "offset": 0, + "size": 3 + } + } + } + }, + "RLR": { + "description": "Reload register (IWDG_RLR)", + "offset": 8, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Watchdog counter reload\n value", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "Status register (IWDG_SR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PVU": { + "description": "Watchdog prescaler value\n update", + "offset": 0, + "size": 1 + }, + "RVU": { + "description": "Watchdog counter reload value\n update", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "WWDG": { + "description": "Window watchdog", + "children": { + "registers": { + "CR": { + "description": "Control register (WWDG_CR)", + "offset": 0, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "T": { + "description": "7-bit counter (MSB to LSB)", + "offset": 0, + "size": 7 + }, + "WDGA": { + "description": "Activation bit", + "offset": 7, + "size": 1 + } + } + } + }, + "CFR": { + "description": "Configuration register\n (WWDG_CFR)", + "offset": 4, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "W": { + "description": "7-bit window value", + "offset": 0, + "size": 7 + }, + "WDGTB": { + "description": "Timer Base", + "offset": 7, + "size": 2 + }, + "EWI": { + "description": "Early Wakeup Interrupt", + "offset": 9, + "size": 1 + } + } + } + }, + "SR": { + "description": "Status register (WWDG_SR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWI": { + "description": "Early Wakeup Interrupt", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "TIM1": { + "description": "Advanced timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OIS4": { + "description": "Output Idle state 4", + "offset": 14, + "size": 1 + }, + "OIS3N": { + "description": "Output Idle state 3", + "offset": 13, + "size": 1 + }, + "OIS3": { + "description": "Output Idle state 3", + "offset": 12, + "size": 1 + }, + "OIS2N": { + "description": "Output Idle state 2", + "offset": 11, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output Compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output Compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC4CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3NE": { + "description": "Capture/Compare 3 complementary output\n enable", + "offset": 10, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2NE": { + "description": "Capture/Compare 2 complementary output\n enable", + "offset": 6, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "ETHERNET_PTP": { + "description": "Ethernet: Precision time protocol", + "children": { + "registers": { + "PTPTSCR": { + "description": "Ethernet PTP time stamp control register\n (ETH_PTPTSCR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSE": { + "description": "Time stamp enable", + "offset": 0, + "size": 1 + }, + "TSFCU": { + "description": "Time stamp fine or coarse\n update", + "offset": 1, + "size": 1 + }, + "TSSTI": { + "description": "Time stamp system time\n initialize", + "offset": 2, + "size": 1 + }, + "TSSTU": { + "description": "Time stamp system time\n update", + "offset": 3, + "size": 1 + }, + "TSITE": { + "description": "Time stamp interrupt trigger\n enable", + "offset": 4, + "size": 1 + }, + "TSARU": { + "description": "Time stamp addend register\n update", + "offset": 5, + "size": 1 + } + } + } + }, + "PTPSSIR": { + "description": "Ethernet PTP subsecond increment\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STSSI": { + "description": "System time subsecond\n increment", + "offset": 0, + "size": 8 + } + } + } + }, + "PTPTSHR": { + "description": "Ethernet PTP time stamp high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STS": { + "description": "System time second", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLR": { + "description": "Ethernet PTP time stamp low register\n (ETH_PTPTSLR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STSS": { + "description": "System time subseconds", + "offset": 0, + "size": 31 + }, + "STPNS": { + "description": "System time positive or negative\n sign", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSHUR": { + "description": "Ethernet PTP time stamp high update\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUS": { + "description": "Time stamp update second", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLUR": { + "description": "Ethernet PTP time stamp low update register\n (ETH_PTPTSLUR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUSS": { + "description": "Time stamp update\n subseconds", + "offset": 0, + "size": 31 + }, + "TSUPNS": { + "description": "Time stamp update positive or negative\n sign", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSAR": { + "description": "Ethernet PTP time stamp addend\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSA": { + "description": "Time stamp addend", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTHR": { + "description": "Ethernet PTP target time high\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSH": { + "description": "Target time stamp high", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTLR": { + "description": "Ethernet PTP target time low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSL": { + "description": "Target time stamp low", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "TIM2": { + "description": "General purpose timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PSC": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "ETHERNET_MAC": { + "description": "Ethernet: media access control", + "children": { + "registers": { + "MACCR": { + "description": "Ethernet MAC configuration register\n (ETH_MACCR)", + "offset": 0, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "DC": { + "description": "Deferral check", + "offset": 4, + "size": 1 + }, + "BL": { + "description": "Back-off limit", + "offset": 5, + "size": 2 + }, + "APCS": { + "description": "Automatic pad/CRC\n stripping", + "offset": 7, + "size": 1 + }, + "RD": { + "description": "Retry disable", + "offset": 9, + "size": 1 + }, + "IPCO": { + "description": "IPv4 checksum offload", + "offset": 10, + "size": 1 + }, + "DM": { + "description": "Duplex mode", + "offset": 11, + "size": 1 + }, + "LM": { + "description": "Loopback mode", + "offset": 12, + "size": 1 + }, + "ROD": { + "description": "Receive own disable", + "offset": 13, + "size": 1 + }, + "FES": { + "description": "Fast Ethernet speed", + "offset": 14, + "size": 1 + }, + "CSD": { + "description": "Carrier sense disable", + "offset": 16, + "size": 1 + }, + "IFG": { + "description": "Interframe gap", + "offset": 17, + "size": 3 + }, + "JD": { + "description": "Jabber disable", + "offset": 22, + "size": 1 + }, + "WD": { + "description": "Watchdog disable", + "offset": 23, + "size": 1 + } + } + } + }, + "MACFFR": { + "description": "Ethernet MAC frame filter register\n (ETH_MACCFFR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "Promiscuous mode", + "offset": 0, + "size": 1 + }, + "HU": { + "description": "Hash unicast", + "offset": 1, + "size": 1 + }, + "HM": { + "description": "Hash multicast", + "offset": 2, + "size": 1 + }, + "DAIF": { + "description": "Destination address inverse\n filtering", + "offset": 3, + "size": 1 + }, + "PAM": { + "description": "Pass all multicast", + "offset": 4, + "size": 1 + }, + "BFD": { + "description": "Broadcast frames disable", + "offset": 5, + "size": 1 + }, + "PCF": { + "description": "Pass control frames", + "offset": 6, + "size": 2 + }, + "SAIF": { + "description": "Source address inverse\n filtering", + "offset": 8, + "size": 1 + }, + "SAF": { + "description": "Source address filter", + "offset": 9, + "size": 1 + }, + "HPF": { + "description": "Hash or perfect filter", + "offset": 10, + "size": 1 + }, + "RA": { + "description": "Receive all", + "offset": 31, + "size": 1 + } + } + } + }, + "MACHTHR": { + "description": "Ethernet MAC hash table high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTH": { + "description": "Hash table high", + "offset": 0, + "size": 32 + } + } + } + }, + "MACHTLR": { + "description": "Ethernet MAC hash table low\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTL": { + "description": "Hash table low", + "offset": 0, + "size": 32 + } + } + } + }, + "MACMIIAR": { + "description": "Ethernet MAC MII address register\n (ETH_MACMIIAR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MB": { + "description": "MII busy", + "offset": 0, + "size": 1 + }, + "MW": { + "description": "MII write", + "offset": 1, + "size": 1 + }, + "CR": { + "description": "Clock range", + "offset": 2, + "size": 3 + }, + "MR": { + "description": "MII register", + "offset": 6, + "size": 5 + }, + "PA": { + "description": "PHY address", + "offset": 11, + "size": 5 + } + } + } + }, + "MACMIIDR": { + "description": "Ethernet MAC MII data register\n (ETH_MACMIIDR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MD": { + "description": "MII data", + "offset": 0, + "size": 16 + } + } + } + }, + "MACFCR": { + "description": "Ethernet MAC flow control register\n (ETH_MACFCR)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FCB_BPA": { + "description": "Flow control busy/back pressure\n activate", + "offset": 0, + "size": 1 + }, + "TFCE": { + "description": "Transmit flow control\n enable", + "offset": 1, + "size": 1 + }, + "RFCE": { + "description": "Receive flow control\n enable", + "offset": 2, + "size": 1 + }, + "UPFD": { + "description": "Unicast pause frame detect", + "offset": 3, + "size": 1 + }, + "PLT": { + "description": "Pause low threshold", + "offset": 4, + "size": 2 + }, + "ZQPD": { + "description": "Zero-quanta pause disable", + "offset": 7, + "size": 1 + }, + "PT": { + "description": "Pass control frames", + "offset": 16, + "size": 16 + } + } + } + }, + "MACVLANTR": { + "description": "Ethernet MAC VLAN tag register\n (ETH_MACVLANTR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VLANTI": { + "description": "VLAN tag identifier (for receive\n frames)", + "offset": 0, + "size": 16 + }, + "VLANTC": { + "description": "12-bit VLAN tag comparison", + "offset": 16, + "size": 1 + } + } + } + }, + "MACRWUFFR": { + "description": "Ethernet MAC remote wakeup frame filter\n register (ETH_MACRWUFFR)", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "MACPMTCSR": { + "description": "Ethernet MAC PMT control and status register\n (ETH_MACPMTCSR)", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PD": { + "description": "Power down", + "offset": 0, + "size": 1 + }, + "MPE": { + "description": "Magic Packet enable", + "offset": 1, + "size": 1 + }, + "WFE": { + "description": "Wakeup frame enable", + "offset": 2, + "size": 1 + }, + "MPR": { + "description": "Magic packet received", + "offset": 5, + "size": 1 + }, + "WFR": { + "description": "Wakeup frame received", + "offset": 6, + "size": 1 + }, + "GU": { + "description": "Global unicast", + "offset": 9, + "size": 1 + }, + "WFFRPR": { + "description": "Wakeup frame filter register pointer\n reset", + "offset": 31, + "size": 1 + } + } + } + }, + "MACSR": { + "description": "Ethernet MAC interrupt status register\n (ETH_MACSR)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTS": { + "description": "PMT status", + "offset": 3, + "size": 1 + }, + "MMCS": { + "description": "MMC status", + "offset": 4, + "size": 1 + }, + "MMCRS": { + "description": "MMC receive status", + "offset": 5, + "size": 1 + }, + "MMCTS": { + "description": "MMC transmit status", + "offset": 6, + "size": 1 + }, + "TSTS": { + "description": "Time stamp trigger status", + "offset": 9, + "size": 1 + } + } + } + }, + "MACIMR": { + "description": "Ethernet MAC interrupt mask register\n (ETH_MACIMR)", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTIM": { + "description": "PMT interrupt mask", + "offset": 3, + "size": 1 + }, + "TSTIM": { + "description": "Time stamp trigger interrupt\n mask", + "offset": 9, + "size": 1 + } + } + } + }, + "MACA0HR": { + "description": "Ethernet MAC address 0 high register\n (ETH_MACA0HR)", + "offset": 64, + "size": 32, + "reset_value": 1114111, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0H": { + "description": "MAC address0 high", + "offset": 0, + "size": 16 + }, + "MO": { + "description": "Always 1", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "MACA0LR": { + "description": "Ethernet MAC address 0 low\n register", + "offset": 68, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0L": { + "description": "MAC address0 low", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA1HR": { + "description": "Ethernet MAC address 1 high register\n (ETH_MACA1HR)", + "offset": 72, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1H": { + "description": "MAC address1 high", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "Mask byte control", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "Source address", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "Address enable", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA1LR": { + "description": "Ethernet MAC address1 low\n register", + "offset": 76, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1L": { + "description": "MAC address1 low", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA2HR": { + "description": "Ethernet MAC address 2 high register\n (ETH_MACA2HR)", + "offset": 80, + "size": 32, + "reset_value": 80, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETH_MACA2HR": { + "description": "Ethernet MAC address 2 high\n register", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "Mask byte control", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "Source address", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "Address enable", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA2LR": { + "description": "Ethernet MAC address 2 low\n register", + "offset": 84, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA2L": { + "description": "MAC address2 low", + "offset": 0, + "size": 31 + } + } + } + }, + "MACA3HR": { + "description": "Ethernet MAC address 3 high register\n (ETH_MACA3HR)", + "offset": 88, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA3H": { + "description": "MAC address3 high", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "Mask byte control", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "Source address", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "Address enable", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA3LR": { + "description": "Ethernet MAC address 3 low\n register", + "offset": 92, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MBCA3L": { + "description": "MAC address3 low", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "ETHERNET_MMC": { + "description": "Ethernet: MAC management counters", + "children": { + "registers": { + "MMCCR": { + "description": "Ethernet MMC control register\n (ETH_MMCCR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CR": { + "description": "Counter reset", + "offset": 0, + "size": 1 + }, + "CSR": { + "description": "Counter stop rollover", + "offset": 1, + "size": 1 + }, + "ROR": { + "description": "Reset on read", + "offset": 2, + "size": 1 + }, + "MCF": { + "description": "MMC counter freeze", + "offset": 31, + "size": 1 + } + } + } + }, + "MMCRIR": { + "description": "Ethernet MMC receive interrupt register\n (ETH_MMCRIR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCES": { + "description": "Received frames CRC error\n status", + "offset": 5, + "size": 1 + }, + "RFAES": { + "description": "Received frames alignment error\n status", + "offset": 6, + "size": 1 + }, + "RGUFS": { + "description": "Received Good Unicast Frames\n Status", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIR": { + "description": "Ethernet MMC transmit interrupt register\n (ETH_MMCTIR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TGFSCS": { + "description": "Transmitted good frames single collision\n status", + "offset": 14, + "size": 1 + }, + "TGFMSCS": { + "description": "Transmitted good frames more single\n collision status", + "offset": 15, + "size": 1 + }, + "TGFS": { + "description": "Transmitted good frames\n status", + "offset": 21, + "size": 1 + } + } + } + }, + "MMCRIMR": { + "description": "Ethernet MMC receive interrupt mask register\n (ETH_MMCRIMR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCEM": { + "description": "Received frame CRC error\n mask", + "offset": 5, + "size": 1 + }, + "RFAEM": { + "description": "Received frames alignment error\n mask", + "offset": 6, + "size": 1 + }, + "RGUFM": { + "description": "Received good unicast frames\n mask", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIMR": { + "description": "Ethernet MMC transmit interrupt mask\n register (ETH_MMCTIMR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TGFSCM": { + "description": "Transmitted good frames single collision\n mask", + "offset": 14, + "size": 1 + }, + "TGFMSCM": { + "description": "Transmitted good frames more single\n collision mask", + "offset": 15, + "size": 1 + }, + "TGFM": { + "description": "Transmitted good frames\n mask", + "offset": 21, + "size": 1 + } + } + } + }, + "MMCTGFSCCR": { + "description": "Ethernet MMC transmitted good frames after a\n single collision counter", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFSCC": { + "description": "Transmitted good frames after a single\n collision counter", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFMSCCR": { + "description": "Ethernet MMC transmitted good frames after\n more than a single collision", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFMSCC": { + "description": "Transmitted good frames after more than\n a single collision counter", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFCR": { + "description": "Ethernet MMC transmitted good frames counter\n register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFC": { + "description": "Transmitted good frames\n counter", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFCECR": { + "description": "Ethernet MMC received frames with CRC error\n counter register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFCFC": { + "description": "Received frames with CRC error\n counter", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFAECR": { + "description": "Ethernet MMC received frames with alignment\n error counter register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFAEC": { + "description": "Received frames with alignment error\n counter", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRGUFCR": { + "description": "MMC received good unicast frames counter\n register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RGUFC": { + "description": "Received good unicast frames\n counter", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_PCGCCTL": { + "description": "OTG_FS power and clock gating control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPPCLK": { + "description": "Stop PHY clock", + "offset": 0, + "size": 1 + }, + "GATEHCLK": { + "description": "Gate HCLK", + "offset": 1, + "size": 1 + }, + "PHYSUSP": { + "description": "PHY Suspended", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "TIM9": { + "description": "General purpose timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PSC": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_HCFG": { + "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSLSPCS": { + "description": "FS/LS PHY clock select", + "offset": 0, + "size": 2 + }, + "FSLSS": { + "description": "FS- and LS-only support", + "offset": 2, + "size": 1, + "access": "read-only" + } + } + } + }, + "HFIR": { + "description": "OTG_FS Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 60000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRIVL": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HFNUM": { + "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)", + "offset": 8, + "size": 32, + "reset_value": 16383, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FTREM": { + "description": "Frame time remaining", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_HPTXSTS": { + "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)", + "offset": 16, + "size": 32, + "reset_value": 524544, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFSAVL": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16 + }, + "PTXQSAV": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXQTOP": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "HAINT": { + "description": "OTG_FS Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HAINT": { + "description": "Channel interrupts", + "offset": 0, + "size": 16 + } + } + } + }, + "HAINTMSK": { + "description": "OTG_FS host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HAINTM": { + "description": "Channel interrupt mask", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HPRT": { + "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCSTS": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCDET": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PENA": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PENCHNG": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "POCA": { + "description": "Port overcurrent active", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "POCCHNG": { + "description": "Port overcurrent change", + "offset": 5, + "size": 1 + }, + "PRES": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSUSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLSTS": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PPWR": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PTCTL": { + "description": "Port test control", + "offset": 13, + "size": 4 + }, + "PSPD": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "FS_HCCHAR0": { + "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR1": { + "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR2": { + "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR3": { + "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR4": { + "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR5": { + "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR6": { + "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR7": { + "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCINT0": { + "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT1": { + "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT2": { + "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT3": { + "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT4": { + "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT5": { + "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT6": { + "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT7": { + "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK0": { + "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK1": { + "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK2": { + "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK3": { + "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK4": { + "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK5": { + "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK6": { + "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK7": { + "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCTSIZ0": { + "description": "OTG_FS host channel-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ1": { + "description": "OTG_FS host channel-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ2": { + "description": "OTG_FS host channel-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ3": { + "description": "OTG_FS host channel-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ4": { + "description": "OTG_FS host channel-x transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ5": { + "description": "OTG_FS host channel-5 transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ6": { + "description": "OTG_FS host channel-6 transfer size\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ7": { + "description": "OTG_FS host channel-7 transfer size\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "TIM10": { + "description": "General purpose timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_GOTGCTL": { + "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRQSCS": { + "description": "Session request success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRQ": { + "description": "Session request", + "offset": 1, + "size": 1 + }, + "HNGSCS": { + "description": "Host negotiation success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPRQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HSHNPEN": { + "description": "Host set HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "CIDSTS": { + "description": "Connector ID status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DBCT": { + "description": "Long/short debounce time", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASVLD": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSVLD": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GOTGINT": { + "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEDET": { + "description": "Session end detected", + "offset": 2, + "size": 1 + }, + "SRSSCHG": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNSSCHG": { + "description": "Host negotiation success status\n change", + "offset": 9, + "size": 1 + }, + "HNGDET": { + "description": "Host negotiation detected", + "offset": 17, + "size": 1 + }, + "ADTOCHG": { + "description": "A-device timeout change", + "offset": 18, + "size": 1 + }, + "DBCDNE": { + "description": "Debounce done", + "offset": 19, + "size": 1 + } + } + } + }, + "FS_GAHBCFG": { + "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINT": { + "description": "Global interrupt mask", + "offset": 0, + "size": 1 + }, + "TXFELVL": { + "description": "TxFIFO empty level", + "offset": 7, + "size": 1 + }, + "PTXFELVL": { + "description": "Periodic TxFIFO empty\n level", + "offset": 8, + "size": 1 + } + } + } + }, + "FS_GUSBCFG": { + "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)", + "offset": 12, + "size": 32, + "reset_value": 2560, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOCAL": { + "description": "FS timeout calibration", + "offset": 0, + "size": 3 + }, + "PHYSEL": { + "description": "Full Speed serial transceiver\n select", + "offset": 6, + "size": 1, + "access": "write-only" + }, + "SRPCAP": { + "description": "SRP-capable", + "offset": 8, + "size": 1 + }, + "HNPCAP": { + "description": "HNP-capable", + "offset": 9, + "size": 1 + }, + "TRDT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "FHMOD": { + "description": "Force host mode", + "offset": 29, + "size": 1 + }, + "FDMOD": { + "description": "Force device mode", + "offset": 30, + "size": 1 + }, + "CTXPKT": { + "description": "Corrupt Tx packet", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRSTCTL": { + "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)", + "offset": 16, + "size": 32, + "reset_value": 536870912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "FCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFFLSH": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFFLSH": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + }, + "AHBIDL": { + "description": "AHB master idle", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GINTSTS": { + "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)", + "offset": 20, + "size": 32, + "reset_value": 67108896, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMOD": { + "description": "Current mode of operation", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MMIS": { + "description": "Mode mismatch interrupt", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFLVL": { + "description": "RxFIFO non-empty", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFE": { + "description": "Non-periodic TxFIFO empty", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GINAKEFF": { + "description": "Global IN non-periodic NAK\n effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "GOUTNAKEFF": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESUSP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "USBSUSP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMDNE": { + "description": "Enumeration done", + "offset": 13, + "size": 1 + }, + "ISOODRP": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPF": { + "description": "End of periodic frame\n interrupt", + "offset": 15, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoint interrupt", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPINT": { + "description": "OUT endpoint interrupt", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "IISOIXFR": { + "description": "Incomplete isochronous IN\n transfer", + "offset": 20, + "size": 1 + }, + "IPXFR_INCOMPISOOUT": { + "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)", + "offset": 21, + "size": 1 + }, + "HPRTINT": { + "description": "Host port interrupt", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCINT": { + "description": "Host channels interrupt", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFE": { + "description": "Periodic TxFIFO empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CIDSCHG": { + "description": "Connector ID status change", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected\n interrupt", + "offset": 29, + "size": 1 + }, + "SRQINT": { + "description": "Session request/new session detected\n interrupt", + "offset": 30, + "size": 1 + }, + "WKUPINT": { + "description": "Resume/remote wakeup detected\n interrupt", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GINTMSK": { + "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMISM": { + "description": "Mode mismatch interrupt\n mask", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt mask", + "offset": 2, + "size": 1 + }, + "SOFM": { + "description": "Start of frame mask", + "offset": 3, + "size": 1 + }, + "RXFLVLM": { + "description": "Receive FIFO non-empty\n mask", + "offset": 4, + "size": 1 + }, + "NPTXFEM": { + "description": "Non-periodic TxFIFO empty\n mask", + "offset": 5, + "size": 1 + }, + "GINAKEFFM": { + "description": "Global non-periodic IN NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "GONAKEFFM": { + "description": "Global OUT NAK effective\n mask", + "offset": 7, + "size": 1 + }, + "ESUSPM": { + "description": "Early suspend mask", + "offset": 10, + "size": 1 + }, + "USBSUSPM": { + "description": "USB suspend mask", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset mask", + "offset": 12, + "size": 1 + }, + "ENUMDNEM": { + "description": "Enumeration done mask", + "offset": 13, + "size": 1 + }, + "ISOODRPM": { + "description": "Isochronous OUT packet dropped interrupt\n mask", + "offset": 14, + "size": 1 + }, + "EOPFM": { + "description": "End of periodic frame interrupt\n mask", + "offset": 15, + "size": 1 + }, + "EPMISM": { + "description": "Endpoint mismatch interrupt\n mask", + "offset": 17, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoints interrupt\n mask", + "offset": 18, + "size": 1 + }, + "OEPINT": { + "description": "OUT endpoints interrupt\n mask", + "offset": 19, + "size": 1 + }, + "IISOIXFRM": { + "description": "Incomplete isochronous IN transfer\n mask", + "offset": 20, + "size": 1 + }, + "IPXFRM_IISOOXFRM": { + "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)", + "offset": 21, + "size": 1 + }, + "PRTIM": { + "description": "Host port interrupt mask", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIM": { + "description": "Host channels interrupt\n mask", + "offset": 25, + "size": 1 + }, + "PTXFEM": { + "description": "Periodic TxFIFO empty mask", + "offset": 26, + "size": 1 + }, + "CIDSCHGM": { + "description": "Connector ID status change\n mask", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected interrupt\n mask", + "offset": 29, + "size": 1 + }, + "SRQIM": { + "description": "Session request/new session detected\n interrupt mask", + "offset": 30, + "size": 1 + }, + "WUIM": { + "description": "Resume/remote wakeup detected interrupt\n mask", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRXSTSR_Device": { + "description": "OTG_FS Receive status debug read(Device\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXSTSR_Host": { + "description": "OTG_FS Receive status debug read(Host\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXFSIZ": { + "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "RxFIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Device": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX0FSA": { + "description": "Endpoint 0 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "TX0FD": { + "description": "Endpoint 0 TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Host": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "NPTXFSA": { + "description": "Non-periodic transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "NPTXFD": { + "description": "Non-periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXSTS": { + "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFSAV": { + "description": "Non-periodic TxFIFO space\n available", + "offset": 0, + "size": 16 + }, + "NPTQXSAV": { + "description": "Non-periodic transmit request queue\n space available", + "offset": 16, + "size": 8 + }, + "NPTXQTOP": { + "description": "Top of the non-periodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "FS_GCCFG": { + "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRDWN": { + "description": "Power down", + "offset": 16, + "size": 1 + }, + "VBUSASEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 18, + "size": 1 + }, + "VBUSBSEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 19, + "size": 1 + }, + "SOFOUTEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + } + } + } + }, + "FS_CID": { + "description": "core ID register", + "offset": 60, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRODUCT_ID": { + "description": "Product ID field", + "offset": 0, + "size": 32 + } + } + } + }, + "FS_HPTXFSIZ": { + "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXSA": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "PTXFSIZ": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF1": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO2 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF2": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO3 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF3": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)", + "offset": 268, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO4 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + } + } + } + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_DCFG": { + "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)", + "offset": 0, + "size": 32, + "reset_value": 35651584, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSPD": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOHSK": { + "description": "Non-zero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAD": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "PFIVL": { + "description": "Periodic frame interval", + "offset": 11, + "size": 2 + } + } + } + }, + "FS_DCTL": { + "description": "OTG_FS device control register\n (OTG_FS_DCTL)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWUSIG": { + "description": "Remote wakeup signaling", + "offset": 0, + "size": 1 + }, + "SDIS": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINSTS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONSTS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "TCTL": { + "description": "Test control", + "offset": 4, + "size": 3 + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1 + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1 + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1 + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1 + }, + "POPRGDNE": { + "description": "Power-on programming done", + "offset": 11, + "size": 1 + } + } + } + }, + "FS_DSTS": { + "description": "OTG_FS device status register\n (OTG_FS_DSTS)", + "offset": 8, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SUSPSTS": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ENUMSPD": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "EERR": { + "description": "Erratic error", + "offset": 3, + "size": 1 + }, + "FNSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "FS_DIEPMSK": { + "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (Non-isochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + } + } + } + }, + "FS_DOEPMSK": { + "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "STUPM": { + "description": "SETUP phase done mask", + "offset": 3, + "size": 1 + }, + "OTEPDM": { + "description": "OUT token received when endpoint\n disabled mask", + "offset": 4, + "size": 1 + } + } + } + }, + "FS_DAINT": { + "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPINT": { + "description": "IN endpoint interrupt bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DAINTMSK": { + "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPM": { + "description": "IN EP interrupt mask bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "DVBUSDIS": { + "description": "OTG_FS device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "DVBUSPULSE": { + "description": "OTG_FS device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSP": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "DIEPEMPMSK": { + "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXFEM": { + "description": "IN EP Tx FIFO empty interrupt mask\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_DIEPCTL0": { + "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 2 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "DIEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM_SD1PID": { + "description": "SODDFRM/SD1PID", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL0": { + "description": "device endpoint-0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "DOEPCTL1": { + "description": "device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL2": { + "description": "device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL3": { + "description": "device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPINT0": { + "description": "device endpoint-x interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT0": { + "description": "device endpoint-0 interrupt\n register", + "offset": 776, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 808, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 840, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 872, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPTSIZ0": { + "description": "device endpoint-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DOEPTSIZ0": { + "description": "device OUT endpoint-0 transfer size\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STUPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DIEPTSIZ1": { + "description": "device endpoint-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ2": { + "description": "device endpoint-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ3": { + "description": "device endpoint-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DTXFSTS0": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS1": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS2": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS3": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DOEPTSIZ1": { + "description": "device OUT endpoint-1 transfer size\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ2": { + "description": "device OUT endpoint-2 transfer size\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ3": { + "description": "device OUT endpoint-3 transfer size\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + } + } + } + }, + "USB": { + "description": "Universal serial bus full-speed device\n interface", + "children": { + "registers": { + "EP0R": { + "description": "endpoint 0 register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP1R": { + "description": "endpoint 1 register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP2R": { + "description": "endpoint 2 register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP3R": { + "description": "endpoint 3 register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP4R": { + "description": "endpoint 4 register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP5R": { + "description": "endpoint 5 register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP6R": { + "description": "endpoint 6 register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "EP7R": { + "description": "endpoint 7 register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1 + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "CNTR": { + "description": "control register", + "offset": 64, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRES": { + "description": "Force USB Reset", + "offset": 0, + "size": 1 + }, + "PDWN": { + "description": "Power down", + "offset": 1, + "size": 1 + }, + "LPMODE": { + "description": "Low-power mode", + "offset": 2, + "size": 1 + }, + "FSUSP": { + "description": "Force suspend", + "offset": 3, + "size": 1 + }, + "RESUME": { + "description": "Resume request", + "offset": 4, + "size": 1 + }, + "ESOFM": { + "description": "Expected start of frame interrupt\n mask", + "offset": 8, + "size": 1 + }, + "SOFM": { + "description": "Start of frame interrupt\n mask", + "offset": 9, + "size": 1 + }, + "RESETM": { + "description": "USB reset interrupt mask", + "offset": 10, + "size": 1 + }, + "SUSPM": { + "description": "Suspend mode interrupt\n mask", + "offset": 11, + "size": 1 + }, + "WKUPM": { + "description": "Wakeup interrupt mask", + "offset": 12, + "size": 1 + }, + "ERRM": { + "description": "Error interrupt mask", + "offset": 13, + "size": 1 + }, + "PMAOVRM": { + "description": "Packet memory area over / underrun\n interrupt mask", + "offset": 14, + "size": 1 + }, + "CTRM": { + "description": "Correct transfer interrupt\n mask", + "offset": 15, + "size": 1 + } + } + } + }, + "ISTR": { + "description": "interrupt status register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EP_ID": { + "description": "Endpoint Identifier", + "offset": 0, + "size": 4 + }, + "DIR": { + "description": "Direction of transaction", + "offset": 4, + "size": 1 + }, + "ESOF": { + "description": "Expected start frame", + "offset": 8, + "size": 1 + }, + "SOF": { + "description": "start of frame", + "offset": 9, + "size": 1 + }, + "RESET": { + "description": "reset request", + "offset": 10, + "size": 1 + }, + "SUSP": { + "description": "Suspend mode request", + "offset": 11, + "size": 1 + }, + "WKUP": { + "description": "Wakeup", + "offset": 12, + "size": 1 + }, + "ERR": { + "description": "Error", + "offset": 13, + "size": 1 + }, + "PMAOVR": { + "description": "Packet memory area over /\n underrun", + "offset": 14, + "size": 1 + }, + "CTR": { + "description": "Correct transfer", + "offset": 15, + "size": 1 + } + } + } + }, + "FNR": { + "description": "frame number register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FN": { + "description": "Frame number", + "offset": 0, + "size": 11 + }, + "LSOF": { + "description": "Lost SOF", + "offset": 11, + "size": 2 + }, + "LCK": { + "description": "Locked", + "offset": 13, + "size": 1 + }, + "RXDM": { + "description": "Receive data - line status", + "offset": 14, + "size": 1 + }, + "RXDP": { + "description": "Receive data + line status", + "offset": 15, + "size": 1 + } + } + } + }, + "DADDR": { + "description": "device address", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD": { + "description": "Device address", + "offset": 0, + "size": 7 + }, + "EF": { + "description": "Enable function", + "offset": 7, + "size": 1 + } + } + } + }, + "BTABLE": { + "description": "Buffer table address", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTABLE": { + "description": "Buffer table", + "offset": 3, + "size": 13 + } + } + } + } + } + } + }, + "TIM6": { + "description": "Basic timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "FLASH": { + "description": "FLASH", + "children": { + "registers": { + "ACR": { + "description": "Flash access control register", + "offset": 0, + "size": 32, + "reset_value": 48, + "reset_mask": 4294967295, + "children": { + "fields": { + "LATENCY": { + "description": "Latency", + "offset": 0, + "size": 3 + }, + "HLFCYA": { + "description": "Flash half cycle access\n enable", + "offset": 3, + "size": 1 + }, + "PRFTBE": { + "description": "Prefetch buffer enable", + "offset": 4, + "size": 1 + }, + "PRFTBS": { + "description": "Prefetch buffer status", + "offset": 5, + "size": 1, + "access": "read-only" + } + } + } + }, + "KEYR": { + "description": "Flash key register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "FPEC key", + "offset": 0, + "size": 32 + } + } + } + }, + "OPTKEYR": { + "description": "Flash option key register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "OPTKEY": { + "description": "Option byte key", + "offset": 0, + "size": 32 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOP": { + "description": "End of operation", + "offset": 5, + "size": 1 + }, + "WRPRTERR": { + "description": "Write protection error", + "offset": 4, + "size": 1 + }, + "PGERR": { + "description": "Programming error", + "offset": 2, + "size": 1 + }, + "BSY": { + "description": "Busy", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 16, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "PG": { + "description": "Programming", + "offset": 0, + "size": 1 + }, + "PER": { + "description": "Page Erase", + "offset": 1, + "size": 1 + }, + "MER": { + "description": "Mass Erase", + "offset": 2, + "size": 1 + }, + "OPTPG": { + "description": "Option byte programming", + "offset": 4, + "size": 1 + }, + "OPTER": { + "description": "Option byte erase", + "offset": 5, + "size": 1 + }, + "STRT": { + "description": "Start", + "offset": 6, + "size": 1 + }, + "LOCK": { + "description": "Lock", + "offset": 7, + "size": 1 + }, + "OPTWRE": { + "description": "Option bytes write enable", + "offset": 9, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 10, + "size": 1 + }, + "EOPIE": { + "description": "End of operation interrupt\n enable", + "offset": 12, + "size": 1 + } + } + } + }, + "AR": { + "description": "Flash address register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "FAR": { + "description": "Flash Address", + "offset": 0, + "size": 32 + } + } + } + }, + "OBR": { + "description": "Option byte register", + "offset": 28, + "size": 32, + "reset_value": 67108860, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OPTERR": { + "description": "Option byte error", + "offset": 0, + "size": 1 + }, + "RDPRT": { + "description": "Read protection", + "offset": 1, + "size": 1 + }, + "WDG_SW": { + "description": "WDG_SW", + "offset": 2, + "size": 1 + }, + "nRST_STOP": { + "description": "nRST_STOP", + "offset": 3, + "size": 1 + }, + "nRST_STDBY": { + "description": "nRST_STDBY", + "offset": 4, + "size": 1 + }, + "Data0": { + "description": "Data0", + "offset": 10, + "size": 8 + }, + "Data1": { + "description": "Data1", + "offset": 18, + "size": 8 + } + } + } + }, + "WRPR": { + "description": "Write protection register", + "offset": 32, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WRP": { + "description": "Write protect", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "I2C1": { + "description": "Inter integrated circuit", + "children": { + "registers": { + "CR1": { + "description": "Control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWRST": { + "description": "Software reset", + "offset": 15, + "size": 1 + }, + "ALERT": { + "description": "SMBus alert", + "offset": 13, + "size": 1 + }, + "PEC": { + "description": "Packet error checking", + "offset": 12, + "size": 1 + }, + "POS": { + "description": "Acknowledge/PEC Position (for data\n reception)", + "offset": 11, + "size": 1 + }, + "ACK": { + "description": "Acknowledge enable", + "offset": 10, + "size": 1 + }, + "STOP": { + "description": "Stop generation", + "offset": 9, + "size": 1 + }, + "START": { + "description": "Start generation", + "offset": 8, + "size": 1 + }, + "NOSTRETCH": { + "description": "Clock stretching disable (Slave\n mode)", + "offset": 7, + "size": 1 + }, + "ENGC": { + "description": "General call enable", + "offset": 6, + "size": 1 + }, + "ENPEC": { + "description": "PEC enable", + "offset": 5, + "size": 1 + }, + "ENARP": { + "description": "ARP enable", + "offset": 4, + "size": 1 + }, + "SMBTYPE": { + "description": "SMBus type", + "offset": 3, + "size": 1 + }, + "SMBUS": { + "description": "SMBus mode", + "offset": 1, + "size": 1 + }, + "PE": { + "description": "Peripheral enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LAST": { + "description": "DMA last transfer", + "offset": 12, + "size": 1 + }, + "DMAEN": { + "description": "DMA requests enable", + "offset": 11, + "size": 1 + }, + "ITBUFEN": { + "description": "Buffer interrupt enable", + "offset": 10, + "size": 1 + }, + "ITEVTEN": { + "description": "Event interrupt enable", + "offset": 9, + "size": 1 + }, + "ITERREN": { + "description": "Error interrupt enable", + "offset": 8, + "size": 1 + }, + "FREQ": { + "description": "Peripheral clock frequency", + "offset": 0, + "size": 6 + } + } + } + }, + "OAR1": { + "description": "Own address register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDMODE": { + "description": "Addressing mode (slave\n mode)", + "offset": 15, + "size": 1 + }, + "ADD10": { + "description": "Interface address", + "offset": 8, + "size": 2 + }, + "ADD7": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ADD0": { + "description": "Interface address", + "offset": 0, + "size": 1 + } + } + } + }, + "OAR2": { + "description": "Own address register 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD2": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ENDUAL": { + "description": "Dual addressing mode\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "8-bit data register", + "offset": 0, + "size": 8 + } + } + } + }, + "SR1": { + "description": "Status register 1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMBALERT": { + "description": "SMBus alert", + "offset": 15, + "size": 1 + }, + "TIMEOUT": { + "description": "Timeout or Tlow error", + "offset": 14, + "size": 1 + }, + "PECERR": { + "description": "PEC Error in reception", + "offset": 12, + "size": 1 + }, + "OVR": { + "description": "Overrun/Underrun", + "offset": 11, + "size": 1 + }, + "AF": { + "description": "Acknowledge failure", + "offset": 10, + "size": 1 + }, + "ARLO": { + "description": "Arbitration lost (master\n mode)", + "offset": 9, + "size": 1 + }, + "BERR": { + "description": "Bus error", + "offset": 8, + "size": 1 + }, + "TxE": { + "description": "Data register empty\n (transmitters)", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "RxNE": { + "description": "Data register not empty\n (receivers)", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "STOPF": { + "description": "Stop detection (slave\n mode)", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ADD10": { + "description": "10-bit header sent (Master\n mode)", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "BTF": { + "description": "Byte transfer finished", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ADDR": { + "description": "Address sent (master mode)/matched\n (slave mode)", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "SB": { + "description": "Start bit (Master mode)", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "SR2": { + "description": "Status register 2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PEC": { + "description": "acket error checking\n register", + "offset": 8, + "size": 8 + }, + "DUALF": { + "description": "Dual flag (Slave mode)", + "offset": 7, + "size": 1 + }, + "SMBHOST": { + "description": "SMBus host header (Slave\n mode)", + "offset": 6, + "size": 1 + }, + "SMBDEFAULT": { + "description": "SMBus device default address (Slave\n mode)", + "offset": 5, + "size": 1 + }, + "GENCALL": { + "description": "General call address (Slave\n mode)", + "offset": 4, + "size": 1 + }, + "TRA": { + "description": "Transmitter/receiver", + "offset": 2, + "size": 1 + }, + "BUSY": { + "description": "Bus busy", + "offset": 1, + "size": 1 + }, + "MSL": { + "description": "Master/slave", + "offset": 0, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Clock control register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "F_S": { + "description": "I2C master mode selection", + "offset": 15, + "size": 1 + }, + "DUTY": { + "description": "Fast mode duty cycle", + "offset": 14, + "size": 1 + }, + "CCR": { + "description": "Clock control register in Fast/Standard\n mode (Master mode)", + "offset": 0, + "size": 12 + } + } + } + }, + "TRISE": { + "description": "TRISE register", + "offset": 32, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRISE": { + "description": "Maximum rise time in Fast/Standard mode\n (Master mode)", + "offset": 0, + "size": 6 + } + } + } + } + } + } + }, + "CRC": { + "description": "CRC calculation unit", + "children": { + "registers": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data Register", + "offset": 0, + "size": 32 + } + } + } + }, + "IDR": { + "description": "Independent Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IDR": { + "description": "Independent Data register", + "offset": 0, + "size": 8 + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "RESET": { + "description": "Reset bit", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "SPI1": { + "description": "Serial peripheral interface", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BIDIMODE": { + "description": "Bidirectional data mode\n enable", + "offset": 15, + "size": 1 + }, + "BIDIOE": { + "description": "Output enable in bidirectional\n mode", + "offset": 14, + "size": 1 + }, + "CRCEN": { + "description": "Hardware CRC calculation\n enable", + "offset": 13, + "size": 1 + }, + "CRCNEXT": { + "description": "CRC transfer next", + "offset": 12, + "size": 1 + }, + "DFF": { + "description": "Data frame format", + "offset": 11, + "size": 1 + }, + "RXONLY": { + "description": "Receive only", + "offset": 10, + "size": 1 + }, + "SSM": { + "description": "Software slave management", + "offset": 9, + "size": 1 + }, + "SSI": { + "description": "Internal slave select", + "offset": 8, + "size": 1 + }, + "LSBFIRST": { + "description": "Frame format", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI enable", + "offset": 6, + "size": 1 + }, + "BR": { + "description": "Baud rate control", + "offset": 3, + "size": 3 + }, + "MSTR": { + "description": "Master selection", + "offset": 2, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 1, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXEIE": { + "description": "Tx buffer empty interrupt\n enable", + "offset": 7, + "size": 1 + }, + "RXNEIE": { + "description": "RX buffer not empty interrupt\n enable", + "offset": 6, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 5, + "size": 1 + }, + "SSOE": { + "description": "SS output enable", + "offset": 2, + "size": 1 + }, + "TXDMAEN": { + "description": "Tx buffer DMA enable", + "offset": 1, + "size": 1 + }, + "RXDMAEN": { + "description": "Rx buffer DMA enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 8, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "BSY": { + "description": "Busy flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "OVR": { + "description": "Overrun flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "MODF": { + "description": "Mode fault", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "CRCERR": { + "description": "CRC error flag", + "offset": 4, + "size": 1 + }, + "UDR": { + "description": "Underrun flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "CHSIDE": { + "description": "Channel side", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "TXE": { + "description": "Transmit buffer empty", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "Receive buffer not empty", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 16 + } + } + } + }, + "CRCPR": { + "description": "CRC polynomial register", + "offset": 16, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial register", + "offset": 0, + "size": 16 + } + } + } + }, + "RXCRCR": { + "description": "RX CRC register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RxCRC": { + "description": "Rx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "TXCRCR": { + "description": "TX CRC register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TxCRC": { + "description": "Tx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "I2SCFGR": { + "description": "I2S configuration register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "I2SMOD": { + "description": "I2S mode selection", + "offset": 11, + "size": 1 + }, + "I2SE": { + "description": "I2S Enable", + "offset": 10, + "size": 1 + }, + "I2SCFG": { + "description": "I2S configuration mode", + "offset": 8, + "size": 2 + }, + "PCMSYNC": { + "description": "PCM frame synchronization", + "offset": 7, + "size": 1 + }, + "I2SSTD": { + "description": "I2S standard selection", + "offset": 4, + "size": 2 + }, + "CKPOL": { + "description": "Steady state clock\n polarity", + "offset": 3, + "size": 1 + }, + "DATLEN": { + "description": "Data length to be\n transferred", + "offset": 1, + "size": 2 + }, + "CHLEN": { + "description": "Channel length (number of bits per audio\n channel)", + "offset": 0, + "size": 1 + } + } + } + }, + "I2SPR": { + "description": "I2S prescaler register", + "offset": 32, + "size": 32, + "reset_value": 10, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKOE": { + "description": "Master clock output enable", + "offset": 9, + "size": 1 + }, + "ODD": { + "description": "Odd factor for the\n prescaler", + "offset": 8, + "size": 1 + }, + "I2SDIV": { + "description": "I2S Linear prescaler", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "UART5": { + "description": "Universal asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "UART4_SR", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PE": { + "description": "PE", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "FE", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "NE": { + "description": "NE", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "ORE", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "IDLE": { + "description": "IDLE", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "RXNE", + "offset": 5, + "size": 1 + }, + "TC": { + "description": "TC", + "offset": 6, + "size": 1 + }, + "TXE": { + "description": "TXE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "LBD": { + "description": "LBD", + "offset": 8, + "size": 1 + } + } + } + }, + "DR": { + "description": "UART4_DR", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "DR", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "UART4_BRR", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Fraction": { + "description": "DIV_Fraction", + "offset": 0, + "size": 4 + }, + "DIV_Mantissa": { + "description": "DIV_Mantissa", + "offset": 4, + "size": 12 + } + } + } + }, + "CR1": { + "description": "UART4_CR1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SBK": { + "description": "SBK", + "offset": 0, + "size": 1 + }, + "RWU": { + "description": "RWU", + "offset": 1, + "size": 1 + }, + "RE": { + "description": "RE", + "offset": 2, + "size": 1 + }, + "TE": { + "description": "TE", + "offset": 3, + "size": 1 + }, + "IDLEIE": { + "description": "IDLEIE", + "offset": 4, + "size": 1 + }, + "RXNEIE": { + "description": "RXNEIE", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "TCIE", + "offset": 6, + "size": 1 + }, + "TXEIE": { + "description": "TXEIE", + "offset": 7, + "size": 1 + }, + "PEIE": { + "description": "PEIE", + "offset": 8, + "size": 1 + }, + "PS": { + "description": "PS", + "offset": 9, + "size": 1 + }, + "PCE": { + "description": "PCE", + "offset": 10, + "size": 1 + }, + "WAKE": { + "description": "WAKE", + "offset": 11, + "size": 1 + }, + "M": { + "description": "M", + "offset": 12, + "size": 1 + }, + "UE": { + "description": "UE", + "offset": 13, + "size": 1 + } + } + } + }, + "CR2": { + "description": "UART4_CR2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD": { + "description": "ADD", + "offset": 0, + "size": 4 + }, + "LBDL": { + "description": "LBDL", + "offset": 5, + "size": 1 + }, + "LBDIE": { + "description": "LBDIE", + "offset": 6, + "size": 1 + }, + "STOP": { + "description": "STOP", + "offset": 12, + "size": 2 + }, + "LINEN": { + "description": "LINEN", + "offset": 14, + "size": 1 + } + } + } + }, + "CR3": { + "description": "UART4_CR3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + } + } + } + } + } + } + }, + "UART4": { + "description": "Universal asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "UART4_SR", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "NE": { + "description": "Noise error flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + } + } + } + }, + "DR": { + "description": "UART4_DR", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "DR", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "UART4_BRR", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Fraction": { + "description": "DIV_Fraction", + "offset": 0, + "size": 4 + }, + "DIV_Mantissa": { + "description": "DIV_Mantissa", + "offset": 4, + "size": 12 + } + } + } + }, + "CR1": { + "description": "UART4_CR1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + } + } + } + }, + "CR2": { + "description": "UART4_CR2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + } + } + } + }, + "CR3": { + "description": "UART4_CR3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + } + } + } + } + } + } + }, + "USART1": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "Status register", + "offset": 0, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "CTS flag", + "offset": 9, + "size": 1 + }, + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NE": { + "description": "Noise error flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "CR1": { + "description": "Control register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "CLKEN": { + "description": "Clock enable", + "offset": 11, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 10, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 9, + "size": 1 + }, + "LBCL": { + "description": "Last bit clock pulse", + "offset": 8, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTSIE": { + "description": "CTS interrupt enable", + "offset": 10, + "size": 1 + }, + "CTSE": { + "description": "CTS enable", + "offset": 9, + "size": 1 + }, + "RTSE": { + "description": "RTS enable", + "offset": 8, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "SCEN": { + "description": "Smartcard mode enable", + "offset": 5, + "size": 1 + }, + "NACK": { + "description": "Smartcard NACK enable", + "offset": 4, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GTPR": { + "description": "Guard time and prescaler\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GT": { + "description": "Guard time value", + "offset": 8, + "size": 8 + }, + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "DBG": { + "description": "Debug support", + "children": { + "registers": { + "IDCODE": { + "description": "DBGMCU_IDCODE", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEV_ID": { + "description": "DEV_ID", + "offset": 0, + "size": 12 + }, + "REV_ID": { + "description": "REV_ID", + "offset": 16, + "size": 16 + } + } + } + }, + "CR": { + "description": "DBGMCU_CR", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_SLEEP": { + "description": "DBG_SLEEP", + "offset": 0, + "size": 1 + }, + "DBG_STOP": { + "description": "DBG_STOP", + "offset": 1, + "size": 1 + }, + "DBG_STANDBY": { + "description": "DBG_STANDBY", + "offset": 2, + "size": 1 + }, + "TRACE_IOEN": { + "description": "TRACE_IOEN", + "offset": 5, + "size": 1 + }, + "TRACE_MODE": { + "description": "TRACE_MODE", + "offset": 6, + "size": 2 + }, + "DBG_IWDG_STOP": { + "description": "DBG_IWDG_STOP", + "offset": 8, + "size": 1 + }, + "DBG_WWDG_STOP": { + "description": "DBG_WWDG_STOP", + "offset": 9, + "size": 1 + }, + "DBG_TIM1_STOP": { + "description": "DBG_TIM1_STOP", + "offset": 10, + "size": 1 + }, + "DBG_TIM2_STOP": { + "description": "DBG_TIM2_STOP", + "offset": 11, + "size": 1 + }, + "DBG_TIM3_STOP": { + "description": "DBG_TIM3_STOP", + "offset": 12, + "size": 1 + }, + "DBG_TIM4_STOP": { + "description": "DBG_TIM4_STOP", + "offset": 13, + "size": 1 + }, + "DBG_CAN1_STOP": { + "description": "DBG_CAN1_STOP", + "offset": 14, + "size": 1 + }, + "DBG_I2C1_SMBUS_TIMEOUT": { + "description": "DBG_I2C1_SMBUS_TIMEOUT", + "offset": 15, + "size": 1 + }, + "DBG_I2C2_SMBUS_TIMEOUT": { + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "offset": 16, + "size": 1 + }, + "DBG_TIM8_STOP": { + "description": "DBG_TIM8_STOP", + "offset": 17, + "size": 1 + }, + "DBG_TIM5_STOP": { + "description": "DBG_TIM5_STOP", + "offset": 18, + "size": 1 + }, + "DBG_TIM6_STOP": { + "description": "DBG_TIM6_STOP", + "offset": 19, + "size": 1 + }, + "DBG_TIM7_STOP": { + "description": "DBG_TIM7_STOP", + "offset": 20, + "size": 1 + }, + "DBG_CAN2_STOP": { + "description": "DBG_CAN2_STOP", + "offset": 21, + "size": 1 + } + } + } + } + } + } + }, + "DAC": { + "description": "Digital to analog converter", + "children": { + "registers": { + "CR": { + "description": "Control register (DAC_CR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN1": { + "description": "DAC channel1 enable", + "offset": 0, + "size": 1 + }, + "BOFF1": { + "description": "DAC channel1 output buffer\n disable", + "offset": 1, + "size": 1 + }, + "TEN1": { + "description": "DAC channel1 trigger\n enable", + "offset": 2, + "size": 1 + }, + "TSEL1": { + "description": "DAC channel1 trigger\n selection", + "offset": 3, + "size": 3 + }, + "WAVE1": { + "description": "DAC channel1 noise/triangle wave\n generation enable", + "offset": 6, + "size": 2 + }, + "MAMP1": { + "description": "DAC channel1 mask/amplitude\n selector", + "offset": 8, + "size": 4 + }, + "DMAEN1": { + "description": "DAC channel1 DMA enable", + "offset": 12, + "size": 1 + }, + "EN2": { + "description": "DAC channel2 enable", + "offset": 16, + "size": 1 + }, + "BOFF2": { + "description": "DAC channel2 output buffer\n disable", + "offset": 17, + "size": 1 + }, + "TEN2": { + "description": "DAC channel2 trigger\n enable", + "offset": 18, + "size": 1 + }, + "TSEL2": { + "description": "DAC channel2 trigger\n selection", + "offset": 19, + "size": 3 + }, + "WAVE2": { + "description": "DAC channel2 noise/triangle wave\n generation enable", + "offset": 22, + "size": 2 + }, + "MAMP2": { + "description": "DAC channel2 mask/amplitude\n selector", + "offset": 24, + "size": 4 + }, + "DMAEN2": { + "description": "DAC channel2 DMA enable", + "offset": 28, + "size": 1 + } + } + } + }, + "SWTRIGR": { + "description": "DAC software trigger register\n (DAC_SWTRIGR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SWTRIG1": { + "description": "DAC channel1 software\n trigger", + "offset": 0, + "size": 1 + }, + "SWTRIG2": { + "description": "DAC channel2 software\n trigger", + "offset": 1, + "size": 1 + } + } + } + }, + "DHR12R1": { + "description": "DAC channel1 12-bit right-aligned data\n holding register(DAC_DHR12R1)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L1": { + "description": "DAC channel1 12-bit left aligned data\n holding register (DAC_DHR12L1)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R1": { + "description": "DAC channel1 8-bit right aligned data\n holding register (DAC_DHR8R1)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12R2": { + "description": "DAC channel2 12-bit right aligned data\n holding register (DAC_DHR12R2)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L2": { + "description": "DAC channel2 12-bit left aligned data\n holding register (DAC_DHR12L2)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R2": { + "description": "DAC channel2 8-bit right-aligned data\n holding register (DAC_DHR8R2)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12RD": { + "description": "Dual DAC 12-bit right-aligned data holding\n register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12\n Reserved", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + }, + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 16, + "size": 12 + } + } + } + }, + "DHR12LD": { + "description": "DUAL DAC 12-bit left aligned data holding\n register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0\n Reserved", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + }, + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 20, + "size": 12 + } + } + } + }, + "DHR8RD": { + "description": "DUAL DAC 8-bit right aligned data holding\n register (DAC_DHR8RD), Bits 31:16 Reserved", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + }, + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 8, + "size": 8 + } + } + } + }, + "DOR1": { + "description": "DAC channel1 data output register\n (DAC_DOR1)", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC1DOR": { + "description": "DAC channel1 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "DOR2": { + "description": "DAC channel2 data output register\n (DAC_DOR2)", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC2DOR": { + "description": "DAC channel2 data output", + "offset": 0, + "size": 12 + } + } + } + } + } + } + }, + "ADC1": { + "description": "Analog to digital converter", + "children": { + "registers": { + "SR": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STRT": { + "description": "Regular channel start flag", + "offset": 4, + "size": 1 + }, + "JSTRT": { + "description": "Injected channel start\n flag", + "offset": 3, + "size": 1 + }, + "JEOC": { + "description": "Injected channel end of\n conversion", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "Regular channel end of\n conversion", + "offset": 1, + "size": 1 + }, + "AWD": { + "description": "Analog watchdog flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CR1": { + "description": "control register 1", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AWDEN": { + "description": "Analog watchdog enable on regular\n channels", + "offset": 23, + "size": 1 + }, + "JAWDEN": { + "description": "Analog watchdog enable on injected\n channels", + "offset": 22, + "size": 1 + }, + "DUALMOD": { + "description": "Dual mode selection", + "offset": 16, + "size": 4 + }, + "DISCNUM": { + "description": "Discontinuous mode channel\n count", + "offset": 13, + "size": 3 + }, + "JDISCEN": { + "description": "Discontinuous mode on injected\n channels", + "offset": 12, + "size": 1 + }, + "DISCEN": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "JAUTO": { + "description": "Automatic injected group\n conversion", + "offset": 10, + "size": 1 + }, + "AWDSGL": { + "description": "Enable the watchdog on a single channel\n in scan mode", + "offset": 9, + "size": 1 + }, + "SCAN": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "JEOCIE": { + "description": "Interrupt enable for injected\n channels", + "offset": 7, + "size": 1 + }, + "AWDIE": { + "description": "Analog watchdog interrupt\n enable", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "AWDCH": { + "description": "Analog watchdog channel select\n bits", + "offset": 0, + "size": 5 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSVREFE": { + "description": "Temperature sensor and VREFINT\n enable", + "offset": 23, + "size": 1 + }, + "SWSTART": { + "description": "Start conversion of regular\n channels", + "offset": 22, + "size": 1 + }, + "JSWSTART": { + "description": "Start conversion of injected\n channels", + "offset": 21, + "size": 1 + }, + "EXTTRIG": { + "description": "External trigger conversion mode for\n regular channels", + "offset": 20, + "size": 1 + }, + "EXTSEL": { + "description": "External event select for regular\n group", + "offset": 17, + "size": 3 + }, + "JEXTTRIG": { + "description": "External trigger conversion mode for\n injected channels", + "offset": 15, + "size": 1 + }, + "JEXTSEL": { + "description": "External event select for injected\n group", + "offset": 12, + "size": 3 + }, + "ALIGN": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "DMA": { + "description": "Direct memory access mode", + "offset": 8, + "size": 1 + }, + "RSTCAL": { + "description": "Reset calibration", + "offset": 3, + "size": 1 + }, + "CAL": { + "description": "A/D calibration", + "offset": 2, + "size": 1 + }, + "CONT": { + "description": "Continuous conversion", + "offset": 1, + "size": 1 + }, + "ADON": { + "description": "A/D converter ON / OFF", + "offset": 0, + "size": 1 + } + } + } + }, + "SMPR1": { + "description": "sample time register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP10": { + "description": "Channel 10 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SMP11": { + "description": "Channel 11 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SMP12": { + "description": "Channel 12 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SMP13": { + "description": "Channel 13 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SMP14": { + "description": "Channel 14 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SMP15": { + "description": "Channel 15 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SMP16": { + "description": "Channel 16 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SMP17": { + "description": "Channel 17 sample time\n selection", + "offset": 21, + "size": 3 + } + } + } + }, + "SMPR2": { + "description": "sample time register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP0": { + "description": "Channel 0 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SMP1": { + "description": "Channel 1 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SMP2": { + "description": "Channel 2 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SMP3": { + "description": "Channel 3 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SMP4": { + "description": "Channel 4 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SMP5": { + "description": "Channel 5 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SMP6": { + "description": "Channel 6 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SMP7": { + "description": "Channel 7 sample time\n selection", + "offset": 21, + "size": 3 + }, + "SMP8": { + "description": "Channel 8 sample time\n selection", + "offset": 24, + "size": 3 + }, + "SMP9": { + "description": "Channel 9 sample time\n selection", + "offset": 27, + "size": 3 + } + } + } + }, + "JOFR1": { + "description": "injected channel data offset register\n x", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET1": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR2": { + "description": "injected channel data offset register\n x", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET2": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR3": { + "description": "injected channel data offset register\n x", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET3": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR4": { + "description": "injected channel data offset register\n x", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET4": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "HTR": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "LTR": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "SQR1": { + "description": "regular sequence register 1", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "L": { + "description": "Regular channel sequence\n length", + "offset": 20, + "size": 4 + }, + "SQ16": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ15": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ14": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ13": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR2": { + "description": "regular sequence register 2", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ12": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ11": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ10": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ9": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ8": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ7": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR3": { + "description": "regular sequence register 3", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ6": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ5": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ4": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ3": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ2": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ1": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JSQR": { + "description": "injected sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JL": { + "description": "Injected sequence length", + "offset": 20, + "size": 2 + }, + "JSQ4": { + "description": "4th conversion in injected\n sequence", + "offset": 15, + "size": 5 + }, + "JSQ3": { + "description": "3rd conversion in injected\n sequence", + "offset": 10, + "size": 5 + }, + "JSQ2": { + "description": "2nd conversion in injected\n sequence", + "offset": 5, + "size": 5 + }, + "JSQ1": { + "description": "1st conversion in injected\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JDR1": { + "description": "injected data register x", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR2": { + "description": "injected data register x", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR3": { + "description": "injected data register x", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR4": { + "description": "injected data register x", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA": { + "description": "Regular data", + "offset": 0, + "size": 16 + }, + "ADC2DATA": { + "description": "ADC2 data", + "offset": 16, + "size": 16 + } + } + } + } + } + } + }, + "ADC2": { + "description": "Analog to digital converter", + "children": { + "registers": { + "SR": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STRT": { + "description": "Regular channel start flag", + "offset": 4, + "size": 1 + }, + "JSTRT": { + "description": "Injected channel start\n flag", + "offset": 3, + "size": 1 + }, + "JEOC": { + "description": "Injected channel end of\n conversion", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "Regular channel end of\n conversion", + "offset": 1, + "size": 1 + }, + "AWD": { + "description": "Analog watchdog flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CR1": { + "description": "control register 1", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AWDEN": { + "description": "Analog watchdog enable on regular\n channels", + "offset": 23, + "size": 1 + }, + "JAWDEN": { + "description": "Analog watchdog enable on injected\n channels", + "offset": 22, + "size": 1 + }, + "DISCNUM": { + "description": "Discontinuous mode channel\n count", + "offset": 13, + "size": 3 + }, + "JDISCEN": { + "description": "Discontinuous mode on injected\n channels", + "offset": 12, + "size": 1 + }, + "DISCEN": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "JAUTO": { + "description": "Automatic injected group\n conversion", + "offset": 10, + "size": 1 + }, + "AWDSGL": { + "description": "Enable the watchdog on a single channel\n in scan mode", + "offset": 9, + "size": 1 + }, + "SCAN": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "JEOCIE": { + "description": "Interrupt enable for injected\n channels", + "offset": 7, + "size": 1 + }, + "AWDIE": { + "description": "Analog watchdog interrupt\n enable", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "AWDCH": { + "description": "Analog watchdog channel select\n bits", + "offset": 0, + "size": 5 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSVREFE": { + "description": "Temperature sensor and VREFINT\n enable", + "offset": 23, + "size": 1 + }, + "SWSTART": { + "description": "Start conversion of regular\n channels", + "offset": 22, + "size": 1 + }, + "JSWSTART": { + "description": "Start conversion of injected\n channels", + "offset": 21, + "size": 1 + }, + "EXTTRIG": { + "description": "External trigger conversion mode for\n regular channels", + "offset": 20, + "size": 1 + }, + "EXTSEL": { + "description": "External event select for regular\n group", + "offset": 17, + "size": 3 + }, + "JEXTTRIG": { + "description": "External trigger conversion mode for\n injected channels", + "offset": 15, + "size": 1 + }, + "JEXTSEL": { + "description": "External event select for injected\n group", + "offset": 12, + "size": 3 + }, + "ALIGN": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "DMA": { + "description": "Direct memory access mode", + "offset": 8, + "size": 1 + }, + "RSTCAL": { + "description": "Reset calibration", + "offset": 3, + "size": 1 + }, + "CAL": { + "description": "A/D calibration", + "offset": 2, + "size": 1 + }, + "CONT": { + "description": "Continuous conversion", + "offset": 1, + "size": 1 + }, + "ADON": { + "description": "A/D converter ON / OFF", + "offset": 0, + "size": 1 + } + } + } + }, + "SMPR1": { + "description": "sample time register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP10": { + "description": "Channel 10 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SMP11": { + "description": "Channel 11 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SMP12": { + "description": "Channel 12 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SMP13": { + "description": "Channel 13 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SMP14": { + "description": "Channel 14 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SMP15": { + "description": "Channel 15 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SMP16": { + "description": "Channel 16 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SMP17": { + "description": "Channel 17 sample time\n selection", + "offset": 21, + "size": 3 + } + } + } + }, + "SMPR2": { + "description": "sample time register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP0": { + "description": "Channel 0 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SMP1": { + "description": "Channel 1 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SMP2": { + "description": "Channel 2 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SMP3": { + "description": "Channel 3 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SMP4": { + "description": "Channel 4 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SMP5": { + "description": "Channel 5 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SMP6": { + "description": "Channel 6 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SMP7": { + "description": "Channel 7 sample time\n selection", + "offset": 21, + "size": 3 + }, + "SMP8": { + "description": "Channel 8 sample time\n selection", + "offset": 24, + "size": 3 + }, + "SMP9": { + "description": "Channel 9 sample time\n selection", + "offset": 27, + "size": 3 + } + } + } + }, + "JOFR1": { + "description": "injected channel data offset register\n x", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET1": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR2": { + "description": "injected channel data offset register\n x", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET2": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR3": { + "description": "injected channel data offset register\n x", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET3": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR4": { + "description": "injected channel data offset register\n x", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET4": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "HTR": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "LTR": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "SQR1": { + "description": "regular sequence register 1", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "L": { + "description": "Regular channel sequence\n length", + "offset": 20, + "size": 4 + }, + "SQ16": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ15": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ14": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ13": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR2": { + "description": "regular sequence register 2", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ12": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ11": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ10": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ9": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ8": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ7": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR3": { + "description": "regular sequence register 3", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ6": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ5": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ4": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ3": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ2": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ1": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JSQR": { + "description": "injected sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JL": { + "description": "Injected sequence length", + "offset": 20, + "size": 2 + }, + "JSQ4": { + "description": "4th conversion in injected\n sequence", + "offset": 15, + "size": 5 + }, + "JSQ3": { + "description": "3rd conversion in injected\n sequence", + "offset": 10, + "size": 5 + }, + "JSQ2": { + "description": "2nd conversion in injected\n sequence", + "offset": 5, + "size": 5 + }, + "JSQ1": { + "description": "1st conversion in injected\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JDR1": { + "description": "injected data register x", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR2": { + "description": "injected data register x", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR3": { + "description": "injected data register x", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR4": { + "description": "injected data register x", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA": { + "description": "Regular data", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "CAN1": { + "description": "Controller area network", + "children": { + "registers": { + "CAN_MCR": { + "description": "CAN_MCR", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBF": { + "description": "DBF", + "offset": 16, + "size": 1 + }, + "RESET": { + "description": "RESET", + "offset": 15, + "size": 1 + }, + "TTCM": { + "description": "TTCM", + "offset": 7, + "size": 1 + }, + "ABOM": { + "description": "ABOM", + "offset": 6, + "size": 1 + }, + "AWUM": { + "description": "AWUM", + "offset": 5, + "size": 1 + }, + "NART": { + "description": "NART", + "offset": 4, + "size": 1 + }, + "RFLM": { + "description": "RFLM", + "offset": 3, + "size": 1 + }, + "TXFP": { + "description": "TXFP", + "offset": 2, + "size": 1 + }, + "SLEEP": { + "description": "SLEEP", + "offset": 1, + "size": 1 + }, + "INRQ": { + "description": "INRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_MSR": { + "description": "CAN_MSR", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RX": { + "description": "RX", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "SAMP": { + "description": "SAMP", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "RXM": { + "description": "RXM", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "TXM": { + "description": "TXM", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "SLAKI": { + "description": "SLAKI", + "offset": 4, + "size": 1 + }, + "WKUI": { + "description": "WKUI", + "offset": 3, + "size": 1 + }, + "ERRI": { + "description": "ERRI", + "offset": 2, + "size": 1 + }, + "SLAK": { + "description": "SLAK", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "INAK": { + "description": "INAK", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "CAN_TSR": { + "description": "CAN_TSR", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOW2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 31, + "size": 1, + "access": "read-only" + }, + "LOW1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOW0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "TME2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TME1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "TME0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CODE": { + "description": "CODE", + "offset": 24, + "size": 2, + "access": "read-only" + }, + "ABRQ2": { + "description": "ABRQ2", + "offset": 23, + "size": 1 + }, + "TERR2": { + "description": "TERR2", + "offset": 19, + "size": 1 + }, + "ALST2": { + "description": "ALST2", + "offset": 18, + "size": 1 + }, + "TXOK2": { + "description": "TXOK2", + "offset": 17, + "size": 1 + }, + "RQCP2": { + "description": "RQCP2", + "offset": 16, + "size": 1 + }, + "ABRQ1": { + "description": "ABRQ1", + "offset": 15, + "size": 1 + }, + "TERR1": { + "description": "TERR1", + "offset": 11, + "size": 1 + }, + "ALST1": { + "description": "ALST1", + "offset": 10, + "size": 1 + }, + "TXOK1": { + "description": "TXOK1", + "offset": 9, + "size": 1 + }, + "RQCP1": { + "description": "RQCP1", + "offset": 8, + "size": 1 + }, + "ABRQ0": { + "description": "ABRQ0", + "offset": 7, + "size": 1 + }, + "TERR0": { + "description": "TERR0", + "offset": 3, + "size": 1 + }, + "ALST0": { + "description": "ALST0", + "offset": 2, + "size": 1 + }, + "TXOK0": { + "description": "TXOK0", + "offset": 1, + "size": 1 + }, + "RQCP0": { + "description": "RQCP0", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_RF0R": { + "description": "CAN_RF0R", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM0": { + "description": "RFOM0", + "offset": 5, + "size": 1 + }, + "FOVR0": { + "description": "FOVR0", + "offset": 4, + "size": 1 + }, + "FULL0": { + "description": "FULL0", + "offset": 3, + "size": 1 + }, + "FMP0": { + "description": "FMP0", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "CAN_RF1R": { + "description": "CAN_RF1R", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM1": { + "description": "RFOM1", + "offset": 5, + "size": 1 + }, + "FOVR1": { + "description": "FOVR1", + "offset": 4, + "size": 1 + }, + "FULL1": { + "description": "FULL1", + "offset": 3, + "size": 1 + }, + "FMP1": { + "description": "FMP1", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "CAN_IER": { + "description": "CAN_IER", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLKIE": { + "description": "SLKIE", + "offset": 17, + "size": 1 + }, + "WKUIE": { + "description": "WKUIE", + "offset": 16, + "size": 1 + }, + "ERRIE": { + "description": "ERRIE", + "offset": 15, + "size": 1 + }, + "LECIE": { + "description": "LECIE", + "offset": 11, + "size": 1 + }, + "BOFIE": { + "description": "BOFIE", + "offset": 10, + "size": 1 + }, + "EPVIE": { + "description": "EPVIE", + "offset": 9, + "size": 1 + }, + "EWGIE": { + "description": "EWGIE", + "offset": 8, + "size": 1 + }, + "FOVIE1": { + "description": "FOVIE1", + "offset": 6, + "size": 1 + }, + "FFIE1": { + "description": "FFIE1", + "offset": 5, + "size": 1 + }, + "FMPIE1": { + "description": "FMPIE1", + "offset": 4, + "size": 1 + }, + "FOVIE0": { + "description": "FOVIE0", + "offset": 3, + "size": 1 + }, + "FFIE0": { + "description": "FFIE0", + "offset": 2, + "size": 1 + }, + "FMPIE0": { + "description": "FMPIE0", + "offset": 1, + "size": 1 + }, + "TMEIE": { + "description": "TMEIE", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_ESR": { + "description": "CAN_ESR", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REC": { + "description": "REC", + "offset": 24, + "size": 8, + "access": "read-only" + }, + "TEC": { + "description": "TEC", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "LEC": { + "description": "LEC", + "offset": 4, + "size": 3 + }, + "BOFF": { + "description": "BOFF", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "EPVF": { + "description": "EPVF", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "EWGF": { + "description": "EWGF", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "CAN_BTR": { + "description": "CAN_BTR", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SILM": { + "description": "SILM", + "offset": 31, + "size": 1 + }, + "LBKM": { + "description": "LBKM", + "offset": 30, + "size": 1 + }, + "SJW": { + "description": "SJW", + "offset": 24, + "size": 2 + }, + "TS2": { + "description": "TS2", + "offset": 20, + "size": 3 + }, + "TS1": { + "description": "TS1", + "offset": 16, + "size": 4 + }, + "BRP": { + "description": "BRP", + "offset": 0, + "size": 10 + } + } + } + }, + "CAN_TI0R": { + "description": "CAN_TI0R", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_TDT0R": { + "description": "CAN_TDT0R", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "CAN_TDL0R": { + "description": "CAN_TDL0R", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_TDH0R": { + "description": "CAN_TDH0R", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_TI1R": { + "description": "CAN_TI1R", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_TDT1R": { + "description": "CAN_TDT1R", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "CAN_TDL1R": { + "description": "CAN_TDL1R", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_TDH1R": { + "description": "CAN_TDH1R", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_TI2R": { + "description": "CAN_TI2R", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "CAN_TDT2R": { + "description": "CAN_TDT2R", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "CAN_TDL2R": { + "description": "CAN_TDL2R", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_TDH2R": { + "description": "CAN_TDH2R", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_RI0R": { + "description": "CAN_RI0R", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + } + } + } + }, + "CAN_RDT0R": { + "description": "CAN_RDT0R", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "FMI": { + "description": "FMI", + "offset": 8, + "size": 8 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "CAN_RDL0R": { + "description": "CAN_RDL0R", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "CAN_RDH0R": { + "description": "CAN_RDH0R", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + 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17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R2": { + "description": "Filter bank 2 register 2", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R1": { + "description": "Filter bank 3 register 1", + "offset": 600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R2": { + "description": "Filter bank 3 register 2", + "offset": 604, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R1": { + "description": "Filter bank 4 register 1", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R2": { + "description": "Filter bank 4 register 2", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R1": { + "description": "Filter bank 5 register 1", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R2": { + "description": "Filter bank 5 register 2", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R1": { + "description": "Filter bank 6 register 1", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R2": { + "description": "Filter bank 6 register 2", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R1": { + "description": "Filter bank 7 register 1", + "offset": 632, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + 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"description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R2": { + "description": "Filter bank 7 register 2", + "offset": 636, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R1": { + "description": "Filter bank 8 register 1", + "offset": 640, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R2": { + "description": "Filter bank 8 register 2", + "offset": 644, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R1": { + "description": "Filter bank 9 register 1", + "offset": 648, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R2": { + "description": "Filter bank 9 register 2", + "offset": 652, + "size": 32, + "reset_value": 0, + "reset_mask": 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"offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R1": { + "description": "Filter bank 10 register 1", + "offset": 656, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R2": { + "description": "Filter bank 10 register 2", + "offset": 660, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R1": { + "description": "Filter bank 11 register 1", + "offset": 664, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R2": { + "description": "Filter bank 11 register 2", + "offset": 668, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R1": { + "description": "Filter bank 4 register 1", + "offset": 672, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R2": { + "description": "Filter bank 12 register 2", + "offset": 676, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R1": { + "description": "Filter bank 13 register 1", + "offset": 680, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R2": { + "description": "Filter bank 13 register 2", + "offset": 684, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + } + } + } + } + } + }, + "devices": { + "STM32F103": { + "arch": "cortex_m3", + "description": "STM32F103", + "properties": { + "cpu.nvic_prio_bits": "4", + "cpu.mpu": "false", + "cpu.fpu": "false", + "cpu.revision": "r1p1", + "cpu.vendor_systick_config": "false", + "cpu.endian": "little", + "cpu.name": "CM3" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "FSMC": { + "index": 48, + "description": "FSMC global interrupt" + }, + "PVD": { + "index": 1, + "description": "PVD through EXTI line detection\n interrupt" + }, + "RCC": { + "index": 5, + "description": "RCC global interrupt" + }, + "TAMPER": { + "index": 2, + "description": "Tamper interrupt" + }, + "DMA1_Channel1": { + "index": 11, + "description": "DMA1 Channel1 global interrupt" + }, + "DMA2_Channel1": { + "index": 56, + "description": "DMA2 Channel1 global interrupt" + }, + "SDIO": { + "index": 49, + "description": "SDIO global interrupt" + }, + "RTC": { + "index": 3, + "description": "RTC global interrupt" + }, + "WWDG": { + "index": 0, + "description": "Window Watchdog interrupt" + }, + "TIM1_BRK": { + "index": 24, + "description": "TIM1 Break interrupt" + }, + "TIM8_BRK": { + "index": 43, + "description": "TIM8 Break interrupt" + }, + "TIM2": { + "index": 28, + "description": "TIM2 global interrupt" + }, + "TIM3": { + "index": 29, + "description": "TIM3 global interrupt" + }, + "TIM4": { + "index": 30, + "description": "TIM4 global interrupt" + }, + "TIM5": { + "index": 50, + "description": "TIM5 global interrupt" + }, + "TIM1_UP": { + "index": 25, + "description": "TIM1 Update interrupt" + }, + "TIM1_TRG_COM": { + "index": 26, + "description": "TIM1 Trigger and Commutation\n interrupts" + }, + "TIM6": { + "index": 54, + "description": "TIM6 global interrupt" + }, + "TIM7": { + "index": 55, + "description": "TIM7 global interrupt" + }, + "I2C1_EV": { + "index": 31, + "description": "I2C1 event interrupt" + }, + "I2C2_EV": { + "index": 33, + "description": "I2C2 event interrupt" + }, + "SPI1": { + "index": 35, + "description": "SPI1 global interrupt" + }, + "SPI2": { + "index": 36, + "description": "SPI2 global interrupt" + }, + "SPI3": { + "index": 51, + "description": "SPI3 global interrupt" + }, + "USART1": { + "index": 37, + "description": "USART1 global interrupt" + }, + "USART2": { + "index": 38, + "description": "USART2 global interrupt" + }, + "USART3": { + "index": 39, + "description": "USART3 global interrupt" + }, + "ADC1_2": { + "index": 18, + "description": "ADC1 and ADC2 global interrupt" + }, + "ADC3": { + "index": 47, + "description": "ADC3 global interrupt" + }, + "CAN_RX1": { + "index": 21, + "description": "CAN RX1 interrupt" + }, + "UART4": { + "index": 52, + "description": "UART4 global interrupt" + }, + "UART5": { + "index": 53, + "description": "UART5 global interrupt" + }, + "FLASH": { + "index": 4, + "description": "Flash global interrupt" + }, + "USB_HP_CAN_TX": { + "index": 19, + "description": "USB High Priority or CAN TX\n interrupts" + } + }, + "peripheral_instances": { + "FSMC": { + "description": "Flexible static memory controller", + "offset": 2684354560, + "type": "types.peripherals.FSMC" + }, + "PWR": { + "description": "Power control", + "offset": 1073770496, + "type": "types.peripherals.PWR" + }, + "RCC": { + "description": "Reset and clock control", + "offset": 1073876992, + "type": "types.peripherals.RCC" + }, + "GPIOA": { + "description": "General purpose I/O", + "offset": 1073809408, + "type": "types.peripherals.GPIOA" + }, + "GPIOB": { + "offset": 1073810432, + "type": "types.peripherals.GPIOA" + }, + "GPIOC": { + "offset": 1073811456, + "type": "types.peripherals.GPIOA" + }, + "GPIOD": { + "offset": 1073812480, + "type": "types.peripherals.GPIOA" + }, + "GPIOE": { + "offset": 1073813504, + "type": "types.peripherals.GPIOA" + }, + "GPIOF": { + "offset": 1073814528, + "type": "types.peripherals.GPIOA" + }, + "GPIOG": { + "offset": 1073815552, + "type": "types.peripherals.GPIOA" + }, + "AFIO": { + "description": "Alternate function I/O", + "offset": 1073807360, + "type": "types.peripherals.AFIO" + }, + "EXTI": { + "description": "EXTI", + "offset": 1073808384, + "type": "types.peripherals.EXTI" + }, + "DMA1": { + "description": "DMA controller", + "offset": 1073872896, + "type": "types.peripherals.DMA1" + }, + "DMA2": { + "offset": 1073873920, + "type": "types.peripherals.DMA1" + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "offset": 1073840128, + "type": "types.peripherals.SDIO" + }, + "RTC": { + "description": "Real time clock", + "offset": 1073752064, + "type": "types.peripherals.RTC" + }, + "BKP": { + "description": "Backup registers", + "offset": 1073769472, + "type": "types.peripherals.BKP" + }, + "IWDG": { + "description": "Independent watchdog", + "offset": 1073754112, + "type": "types.peripherals.IWDG" + }, + "WWDG": { + "description": "Window watchdog", + "offset": 1073753088, + "type": "types.peripherals.WWDG" + }, + "TIM1": { + "description": "Advanced timer", + "offset": 1073818624, + "type": "types.peripherals.TIM1" + }, + "TIM8": { + "offset": 1073820672, + "type": "types.peripherals.TIM1" + }, + "TIM2": { + "description": "General purpose timer", + "offset": 1073741824, + "type": "types.peripherals.TIM2" + }, + "TIM3": { + "offset": 1073742848, + "type": "types.peripherals.TIM2" + }, + "TIM4": { + "offset": 1073743872, + "type": "types.peripherals.TIM2" + }, + "TIM5": { + "offset": 1073744896, + "type": "types.peripherals.TIM2" + }, + "TIM9": { + "description": "General purpose timer", + "offset": 1073826816, + "type": "types.peripherals.TIM9" + }, + "TIM12": { + "offset": 1073747968, + "type": "types.peripherals.TIM9" + }, + "TIM10": { + "description": "General purpose timer", + "offset": 1073827840, + "type": "types.peripherals.TIM10" + }, + "TIM11": { + "offset": 1073828864, + "type": "types.peripherals.TIM10" + }, + "TIM13": { + "offset": 1073748992, + "type": "types.peripherals.TIM10" + }, + "TIM14": { + "offset": 1073750016, + "type": "types.peripherals.TIM10" + }, + "TIM6": { + "description": "Basic timer", + "offset": 1073745920, + "type": "types.peripherals.TIM6" + }, + "TIM7": { + "offset": 1073746944, + "type": "types.peripherals.TIM6" + }, + "I2C1": { + "description": "Inter integrated circuit", + "offset": 1073763328, + "type": "types.peripherals.I2C1" + }, + "I2C2": { + "offset": 1073764352, + "type": "types.peripherals.I2C1" + }, + "SPI1": { + "description": "Serial peripheral interface", + "offset": 1073819648, + "type": "types.peripherals.SPI1" + }, + "SPI2": { + "offset": 1073756160, + "type": "types.peripherals.SPI1" + }, + "SPI3": { + "offset": 1073757184, + "type": "types.peripherals.SPI1" + }, + "USART1": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073821696, + "type": "types.peripherals.USART1" + }, + "USART2": { + "offset": 1073759232, + "type": "types.peripherals.USART1" + }, + "USART3": { + "offset": 1073760256, + "type": "types.peripherals.USART1" + }, + "ADC1": { + "description": "Analog to digital converter", + "offset": 1073816576, + "type": "types.peripherals.ADC1" + }, + "ADC2": { + "description": "Analog to digital converter", + "offset": 1073817600, + "type": "types.peripherals.ADC2" + }, + "ADC3": { + "offset": 1073822720, + "type": "types.peripherals.ADC2" + }, + "CAN1": { + "description": "Controller area network", + "offset": 1073767424, + "type": "types.peripherals.CAN1" + }, + "CAN2": { + "offset": 1073768448, + "type": "types.peripherals.CAN1" + }, + "DAC": { + "description": "Digital to analog converter", + "offset": 1073771520, + "type": "types.peripherals.DAC" + }, + "DBG": { + "description": "Debug support", + "offset": 3758366720, + "type": "types.peripherals.DBG" + }, + "UART4": { + "description": "Universal asynchronous receiver\n transmitter", + "offset": 1073761280, + "type": "types.peripherals.UART4" + }, + "UART5": { + "description": "Universal asynchronous receiver\n transmitter", + "offset": 1073762304, + "type": "types.peripherals.UART5" + }, + "CRC": { + "description": "CRC calculation unit", + "offset": 1073885184, + "type": "types.peripherals.CRC" + }, + "FLASH": { + "description": "FLASH", + "offset": 1073881088, + "type": "types.peripherals.FLASH" + }, + "USB": { + "description": "Universal serial bus full-speed device\n interface", + "offset": 1073765376, + "type": "types.peripherals.USB" + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "offset": 1342179328, + "type": "types.peripherals.OTG_FS_DEVICE" + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "offset": 1342177280, + "type": "types.peripherals.OTG_FS_GLOBAL" + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "offset": 1342178304, + "type": "types.peripherals.OTG_FS_HOST" + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "offset": 1342180864, + "type": "types.peripherals.OTG_FS_PWRCLK" + }, + "ETHERNET_MMC": { + "description": "Ethernet: MAC management counters", + "offset": 1073905920, + "type": "types.peripherals.ETHERNET_MMC" + }, + "ETHERNET_MAC": { + "description": "Ethernet: media access control", + "offset": 1073905664, + "type": "types.peripherals.ETHERNET_MAC" + }, + "ETHERNET_PTP": { + "description": "Ethernet: Precision time protocol", + "offset": 1073907456, + "type": "types.peripherals.ETHERNET_PTP" + }, + "ETHERNET_DMA": { + "description": "Ethernet: DMA controller operation", + "offset": 1073909760, + "type": "types.peripherals.ETHERNET_DMA" + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "offset": 3758153984, + "type": "types.peripherals.NVIC" + }, + "MPU": { + "description": "Memory protection unit", + "offset": 3758157200, + "type": "types.peripherals.MPU" + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "offset": 3758153736, + "type": "types.peripherals.SCB_ACTRL" + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "offset": 3758157568, + "type": "types.peripherals.NVIC_STIR" + }, + "SCB": { + "description": "System control block", + "offset": 3758157056, + "type": "types.peripherals.SCB" + }, + "STK": { + "description": "SysTick timer", + "offset": 3758153744, + "type": "types.peripherals.STK" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/STM32F103.zig b/src/chips/STM32F103.zig new file mode 100644 index 0000000..f29fded --- /dev/null +++ b/src/chips/STM32F103.zig @@ -0,0 +1,10854 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// STM32F103 + pub const STM32F103 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "4"; + pub const @"cpu.mpu" = "false"; + pub const @"cpu.fpu" = "false"; + pub const @"cpu.revision" = "r1p1"; + pub const @"cpu.vendor_systick_config" = "false"; + pub const @"cpu.endian" = "little"; + pub const @"cpu.name" = "CM3"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + /// Window Watchdog interrupt + WWDG: Handler = unhandled, + /// PVD through EXTI line detection interrupt + PVD: Handler = unhandled, + /// Tamper interrupt + TAMPER: Handler = unhandled, + /// RTC global interrupt + RTC: Handler = unhandled, + /// Flash global interrupt + FLASH: Handler = unhandled, + /// RCC global interrupt + RCC: Handler = unhandled, + reserved20: [5]u32 = undefined, + /// DMA1 Channel1 global interrupt + DMA1_Channel1: Handler = unhandled, + reserved26: [6]u32 = undefined, + /// ADC1 and ADC2 global interrupt + ADC1_2: Handler = unhandled, + /// USB High Priority or CAN TX interrupts + USB_HP_CAN_TX: Handler = unhandled, + reserved34: [1]u32 = undefined, + /// CAN RX1 interrupt + CAN_RX1: Handler = unhandled, + reserved36: [2]u32 = undefined, + /// TIM1 Break interrupt + TIM1_BRK: Handler = unhandled, + /// TIM1 Update interrupt + TIM1_UP: Handler = unhandled, + /// TIM1 Trigger and Commutation interrupts + TIM1_TRG_COM: Handler = unhandled, + reserved41: [1]u32 = undefined, + /// TIM2 global interrupt + TIM2: Handler = unhandled, + /// TIM3 global interrupt + TIM3: Handler = unhandled, + /// TIM4 global interrupt + TIM4: Handler = unhandled, + /// I2C1 event interrupt + I2C1_EV: Handler = unhandled, + reserved46: [1]u32 = undefined, + /// I2C2 event interrupt + I2C2_EV: Handler = unhandled, + reserved48: [1]u32 = undefined, + /// SPI1 global interrupt + SPI1: Handler = unhandled, + /// SPI2 global interrupt + SPI2: Handler = unhandled, + /// USART1 global interrupt + USART1: Handler = unhandled, + /// USART2 global interrupt + USART2: Handler = unhandled, + /// USART3 global interrupt + USART3: Handler = unhandled, + reserved54: [3]u32 = undefined, + /// TIM8 Break interrupt + TIM8_BRK: Handler = unhandled, + reserved58: [3]u32 = undefined, + /// ADC3 global interrupt + ADC3: Handler = unhandled, + /// FSMC global interrupt + FSMC: Handler = unhandled, + /// SDIO global interrupt + SDIO: Handler = unhandled, + /// TIM5 global interrupt + TIM5: Handler = unhandled, + /// SPI3 global interrupt + SPI3: Handler = unhandled, + /// UART4 global interrupt + UART4: Handler = unhandled, + /// UART5 global interrupt + UART5: Handler = unhandled, + /// TIM6 global interrupt + TIM6: Handler = unhandled, + /// TIM7 global interrupt + TIM7: Handler = unhandled, + /// DMA2 Channel1 global interrupt + DMA2_Channel1: Handler = unhandled, + }; + + pub const peripherals = struct { + /// General purpose timer + pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000); + /// General purpose timer + pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400); + /// General purpose timer + pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800); + /// General purpose timer + pub const TIM5 = @ptrCast(*volatile types.TIM2, 0x40000c00); + /// Basic timer + pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000); + /// Basic timer + pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400); + /// General purpose timer + pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800); + /// General purpose timer + pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00); + /// General purpose timer + pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000); + /// Real time clock + pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800); + /// Window watchdog + pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00); + /// Independent watchdog + pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000); + /// Serial peripheral interface + pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800); + /// Serial peripheral interface + pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00); + /// Universal synchronous asynchronous receiver transmitter + pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800); + /// Universal asynchronous receiver transmitter + pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00); + /// Universal asynchronous receiver transmitter + pub const UART5 = @ptrCast(*volatile types.UART5, 0x40005000); + /// Inter integrated circuit + pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400); + /// Inter integrated circuit + pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800); + /// Universal serial bus full-speed device interface + pub const USB = @ptrCast(*volatile types.USB, 0x40005c00); + /// Controller area network + pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400); + /// Controller area network + pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800); + /// Backup registers + pub const BKP = @ptrCast(*volatile types.BKP, 0x40006c00); + /// Power control + pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000); + /// Digital to analog converter + pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400); + /// Alternate function I/O + pub const AFIO = @ptrCast(*volatile types.AFIO, 0x40010000); + /// EXTI + pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400); + /// General purpose I/O + pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40010800); + /// General purpose I/O + pub const GPIOB = @ptrCast(*volatile types.GPIOA, 0x40010c00); + /// General purpose I/O + pub const GPIOC = @ptrCast(*volatile types.GPIOA, 0x40011000); + /// General purpose I/O + pub const GPIOD = @ptrCast(*volatile types.GPIOA, 0x40011400); + /// General purpose I/O + pub const GPIOE = @ptrCast(*volatile types.GPIOA, 0x40011800); + /// General purpose I/O + pub const GPIOF = @ptrCast(*volatile types.GPIOA, 0x40011c00); + /// General purpose I/O + pub const GPIOG = @ptrCast(*volatile types.GPIOA, 0x40012000); + /// Analog to digital converter + pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012400); + /// Analog to digital converter + pub const ADC2 = @ptrCast(*volatile types.ADC2, 0x40012800); + /// Advanced timer + pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00); + /// Serial peripheral interface + pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000); + /// Advanced timer + pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40013400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800); + /// Analog to digital converter + pub const ADC3 = @ptrCast(*volatile types.ADC2, 0x40013c00); + /// General purpose timer + pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014c00); + /// General purpose timer + pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40015000); + /// General purpose timer + pub const TIM11 = @ptrCast(*volatile types.TIM10, 0x40015400); + /// Secure digital input/output interface + pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40018000); + /// DMA controller + pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000); + /// DMA controller + pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400); + /// Reset and clock control + pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000); + /// FLASH + pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40022000); + /// CRC calculation unit + pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000); + /// Ethernet: media access control + pub const ETHERNET_MAC = @ptrCast(*volatile types.ETHERNET_MAC, 0x40028000); + /// Ethernet: MAC management counters + pub const ETHERNET_MMC = @ptrCast(*volatile types.ETHERNET_MMC, 0x40028100); + /// Ethernet: Precision time protocol + pub const ETHERNET_PTP = @ptrCast(*volatile types.ETHERNET_PTP, 0x40028700); + /// Ethernet: DMA controller operation + pub const ETHERNET_DMA = @ptrCast(*volatile types.ETHERNET_DMA, 0x40029000); + /// USB on the go full speed + pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000); + /// USB on the go full speed + pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400); + /// USB on the go full speed + pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800); + /// USB on the go full speed + pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00); + /// Flexible static memory controller + pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000); + /// System control block ACTLR + pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008); + /// SysTick timer + pub const STK = @ptrCast(*volatile types.STK, 0xe000e010); + /// Nested Vectored Interrupt Controller + pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100); + /// System control block + pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00); + /// Memory protection unit + pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90); + /// Nested vectored interrupt controller + pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00); + /// Debug support + pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000); + }; + }; +}; + +pub const types = struct { + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved11: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 1 + BTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2 + BCR2: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 2 + BTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 3 + BCR3: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 3 + BTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 4 + BCR4: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 4 + BTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved96: [64]u8, + /// PC Card/NAND Flash control register 2 + PCR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 2 + PMEM2: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 2 + PATT2: mmio.Mmio(packed struct(u32) { + /// Attribute memory x setup time + ATTSETx: u8, + /// Attribute memory x wait time + ATTWAITx: u8, + /// Attribute memory x hold time + ATTHOLDx: u8, + /// Attribute memory x databus HiZ time + ATTHIZx: u8, + }), + reserved116: [4]u8, + /// ECC result register 2 + ECCR2: mmio.Mmio(packed struct(u32) { + /// ECC result + ECCx: u32, + }), + reserved128: [8]u8, + /// PC Card/NAND Flash control register 3 + PCR3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 3 + SR3: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 3 + PMEM3: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 3 + PATT3: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved148: [4]u8, + /// ECC result register 3 + ECCR3: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved160: [8]u8, + /// PC Card/NAND Flash control register 4 + PCR4: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 4 + SR4: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 4 + PMEM4: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 4 + PATT4: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1 + BWTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved268: [4]u8, + /// SRAM/NOR-Flash write timing registers 2 + BWTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved276: [4]u8, + /// SRAM/NOR-Flash write timing registers 3 + BWTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved284: [4]u8, + /// SRAM/NOR-Flash write timing registers 4 + BWTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + }; + + /// Power control + pub const PWR = extern struct { + /// Power control register (PWR_CR) + CR: mmio.Mmio(packed struct(u32) { + /// Low Power Deep Sleep + LPDS: u1, + /// Power Down Deep Sleep + PDDS: u1, + /// Clear Wake-up Flag + CWUF: u1, + /// Clear STANDBY Flag + CSBF: u1, + /// Power Voltage Detector Enable + PVDE: u1, + /// PVD Level Selection + PLS: u3, + /// Disable Backup Domain write protection + DBP: u1, + padding: u23, + }), + /// Power control register (PWR_CR) + CSR: mmio.Mmio(packed struct(u32) { + /// Wake-Up Flag + WUF: u1, + /// STANDBY Flag + SBF: u1, + /// PVD Output + PVDO: u1, + reserved8: u5, + /// Enable WKUP pin + EWUP: u1, + padding: u23, + }), + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler (APB1) + PPRE1: u3, + /// APB High speed prescaler (APB2) + PPRE2: u3, + /// ADC prescaler + ADCPRE: u2, + /// PLL entry clock source + PLLSRC: u1, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB OTG FS prescaler + OTGFSPRE: u1, + reserved24: u1, + /// Microcontroller clock output + MCO: u3, + padding: u5, + }), + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O reset + AFIORST: u1, + reserved2: u1, + /// IO port A reset + IOPARST: u1, + /// IO port B reset + IOPBRST: u1, + /// IO port C reset + IOPCRST: u1, + /// IO port D reset + IOPDRST: u1, + /// IO port E reset + IOPERST: u1, + /// IO port F reset + IOPFRST: u1, + /// IO port G reset + IOPGRST: u1, + /// ADC 1 interface reset + ADC1RST: u1, + /// ADC 2 interface reset + ADC2RST: u1, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + /// ADC 3 interface reset + ADC3RST: u1, + reserved19: u3, + /// TIM9 timer reset + TIM9RST: u1, + /// TIM10 timer reset + TIM10RST: u1, + /// TIM11 timer reset + TIM11RST: u1, + padding: u10, + }), + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 4 reset + TIM4RST: u1, + /// Timer 5 reset + TIM5RST: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + /// Timer 12 reset + TIM12RST: u1, + /// Timer 13 reset + TIM13RST: u1, + /// Timer 14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART 3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + reserved27: u1, + /// Backup interface reset + BKPRST: u1, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + padding: u2, + }), + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLITF clock enable + FLITFEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved8: u1, + /// FSMC clock enable + FSMCEN: u1, + reserved10: u1, + /// SDIO clock enable + SDIOEN: u1, + padding: u21, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O clock enable + AFIOEN: u1, + reserved2: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// ADC 1 interface clock enable + ADC1EN: u1, + /// ADC 2 interface clock enable + ADC2EN: u1, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + /// ADC3 interface clock enable + ADC3EN: u1, + reserved19: u3, + /// TIM9 Timer clock enable + TIM9EN: u1, + /// TIM10 Timer clock enable + TIM10EN: u1, + /// TIM11 Timer clock enable + TIM11EN: u1, + padding: u10, + }), + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + /// Timer 5 clock enable + TIM5EN: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + /// Timer 12 clock enable + TIM12EN: u1, + /// Timer 13 clock enable + TIM13EN: u1, + /// Timer 14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// UART 4 clock enable + UART4EN: u1, + /// UART 5 clock enable + UART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + reserved27: u1, + /// Backup interface clock enable + BKPEN: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, + }), + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL: u2, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + reserved26: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + }; + + /// General purpose I/O + pub const GPIOA = extern struct { + /// Port configuration register low (GPIOn_CRL) + CRL: mmio.Mmio(packed struct(u32) { + /// Port n.0 mode bits + MODE0: u2, + /// Port n.0 configuration bits + CNF0: u2, + /// Port n.1 mode bits + MODE1: u2, + /// Port n.1 configuration bits + CNF1: u2, + /// Port n.2 mode bits + MODE2: u2, + /// Port n.2 configuration bits + CNF2: u2, + /// Port n.3 mode bits + MODE3: u2, + /// Port n.3 configuration bits + CNF3: u2, + /// Port n.4 mode bits + MODE4: u2, + /// Port n.4 configuration bits + CNF4: u2, + /// Port n.5 mode bits + MODE5: u2, + /// Port n.5 configuration bits + CNF5: u2, + /// Port n.6 mode bits + MODE6: u2, + /// Port n.6 configuration bits + CNF6: u2, + /// Port n.7 mode bits + MODE7: u2, + /// Port n.7 configuration bits + CNF7: u2, + }), + /// Port configuration register high (GPIOn_CRL) + CRH: mmio.Mmio(packed struct(u32) { + /// Port n.8 mode bits + MODE8: u2, + /// Port n.8 configuration bits + CNF8: u2, + /// Port n.9 mode bits + MODE9: u2, + /// Port n.9 configuration bits + CNF9: u2, + /// Port n.10 mode bits + MODE10: u2, + /// Port n.10 configuration bits + CNF10: u2, + /// Port n.11 mode bits + MODE11: u2, + /// Port n.11 configuration bits + CNF11: u2, + /// Port n.12 mode bits + MODE12: u2, + /// Port n.12 configuration bits + CNF12: u2, + /// Port n.13 mode bits + MODE13: u2, + /// Port n.13 configuration bits + CNF13: u2, + /// Port n.14 mode bits + MODE14: u2, + /// Port n.14 configuration bits + CNF14: u2, + /// Port n.15 mode bits + MODE15: u2, + /// Port n.15 configuration bits + CNF15: u2, + }), + /// Port input data register (GPIOn_IDR) + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data + IDR0: u1, + /// Port input data + IDR1: u1, + /// Port input data + IDR2: u1, + /// Port input data + IDR3: u1, + /// Port input data + IDR4: u1, + /// Port input data + IDR5: u1, + /// Port input data + IDR6: u1, + /// Port input data + IDR7: u1, + /// Port input data + IDR8: u1, + /// Port input data + IDR9: u1, + /// Port input data + IDR10: u1, + /// Port input data + IDR11: u1, + /// Port input data + IDR12: u1, + /// Port input data + IDR13: u1, + /// Port input data + IDR14: u1, + /// Port input data + IDR15: u1, + padding: u16, + }), + /// Port output data register (GPIOn_ODR) + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data + ODR0: u1, + /// Port output data + ODR1: u1, + /// Port output data + ODR2: u1, + /// Port output data + ODR3: u1, + /// Port output data + ODR4: u1, + /// Port output data + ODR5: u1, + /// Port output data + ODR6: u1, + /// Port output data + ODR7: u1, + /// Port output data + ODR8: u1, + /// Port output data + ODR9: u1, + /// Port output data + ODR10: u1, + /// Port output data + ODR11: u1, + /// Port output data + ODR12: u1, + /// Port output data + ODR13: u1, + /// Port output data + ODR14: u1, + /// Port output data + ODR15: u1, + padding: u16, + }), + /// Port bit set/reset register (GPIOn_BSRR) + BSRR: mmio.Mmio(packed struct(u32) { + /// Set bit 0 + BS0: u1, + /// Set bit 1 + BS1: u1, + /// Set bit 1 + BS2: u1, + /// Set bit 3 + BS3: u1, + /// Set bit 4 + BS4: u1, + /// Set bit 5 + BS5: u1, + /// Set bit 6 + BS6: u1, + /// Set bit 7 + BS7: u1, + /// Set bit 8 + BS8: u1, + /// Set bit 9 + BS9: u1, + /// Set bit 10 + BS10: u1, + /// Set bit 11 + BS11: u1, + /// Set bit 12 + BS12: u1, + /// Set bit 13 + BS13: u1, + /// Set bit 14 + BS14: u1, + /// Set bit 15 + BS15: u1, + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 2 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + }), + /// Port bit reset register (GPIOn_BRR) + BRR: mmio.Mmio(packed struct(u32) { + /// Reset bit 0 + BR0: u1, + /// Reset bit 1 + BR1: u1, + /// Reset bit 1 + BR2: u1, + /// Reset bit 3 + BR3: u1, + /// Reset bit 4 + BR4: u1, + /// Reset bit 5 + BR5: u1, + /// Reset bit 6 + BR6: u1, + /// Reset bit 7 + BR7: u1, + /// Reset bit 8 + BR8: u1, + /// Reset bit 9 + BR9: u1, + /// Reset bit 10 + BR10: u1, + /// Reset bit 11 + BR11: u1, + /// Reset bit 12 + BR12: u1, + /// Reset bit 13 + BR13: u1, + /// Reset bit 14 + BR14: u1, + /// Reset bit 15 + BR15: u1, + padding: u16, + }), + /// Port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port A Lock bit 0 + LCK0: u1, + /// Port A Lock bit 1 + LCK1: u1, + /// Port A Lock bit 2 + LCK2: u1, + /// Port A Lock bit 3 + LCK3: u1, + /// Port A Lock bit 4 + LCK4: u1, + /// Port A Lock bit 5 + LCK5: u1, + /// Port A Lock bit 6 + LCK6: u1, + /// Port A Lock bit 7 + LCK7: u1, + /// Port A Lock bit 8 + LCK8: u1, + /// Port A Lock bit 9 + LCK9: u1, + /// Port A Lock bit 10 + LCK10: u1, + /// Port A Lock bit 11 + LCK11: u1, + /// Port A Lock bit 12 + LCK12: u1, + /// Port A Lock bit 13 + LCK13: u1, + /// Port A Lock bit 14 + LCK14: u1, + /// Port A Lock bit 15 + LCK15: u1, + /// Lock key + LCKK: u1, + padding: u15, + }), + }; + + /// SysTick timer + pub const STK = extern struct { + /// SysTick control and status register + CTRL: mmio.Mmio(packed struct(u32) { + /// Counter enable + ENABLE: u1, + /// SysTick exception request enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved16: u13, + /// COUNTFLAG + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick reload value register + LOAD_: mmio.Mmio(packed struct(u32) { + /// RELOAD value + RELOAD: u24, + padding: u8, + }), + /// SysTick current value register + VAL: mmio.Mmio(packed struct(u32) { + /// Current counter value + CURRENT: u24, + padding: u8, + }), + /// SysTick calibration value register + CALIB: mmio.Mmio(packed struct(u32) { + /// Calibration value + TENMS: u24, + padding: u8, + }), + }; + + /// System control block + pub const SCB = extern struct { + /// CPUID base register + CPUID: mmio.Mmio(packed struct(u32) { + /// Revision number + Revision: u4, + /// Part number of the processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), + /// Interrupt control and state register + ICSR: mmio.Mmio(packed struct(u32) { + /// Active vector + VECTACTIVE: u9, + reserved11: u2, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved22: u3, + /// Interrupt pending flag + ISRPENDING: u1, + reserved25: u2, + /// SysTick exception clear-pending bit + PENDSTCLR: u1, + /// SysTick exception set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved31: u2, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), + /// Vector table offset register + VTOR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// Vector table base offset field + TBLOFF: u21, + padding: u2, + }), + /// Application interrupt and reset control register + AIRCR: mmio.Mmio(packed struct(u32) { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved8: u5, + /// PRIGROUP + PRIGROUP: u3, + reserved15: u4, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), + /// System control register + SCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved4: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding: u27, + }), + /// Configuration and control register + CCR: mmio.Mmio(packed struct(u32) { + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved3: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved8: u3, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding: u22, + }), + /// System handler priority registers + SHPR1: mmio.Mmio(packed struct(u32) { + /// Priority of system handler 4 + PRI_4: u8, + /// Priority of system handler 5 + PRI_5: u8, + /// Priority of system handler 6 + PRI_6: u8, + padding: u8, + }), + /// System handler priority registers + SHPR2: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// Priority of system handler 11 + PRI_11: u8, + }), + /// System handler priority registers + SHPR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Priority of system handler 14 + PRI_14: u8, + /// Priority of system handler 15 + PRI_15: u8, + }), + /// System handler control and state register + SHCRS: mmio.Mmio(packed struct(u32) { + /// Memory management fault exception active bit + MEMFAULTACT: u1, + /// Bus fault exception active bit + BUSFAULTACT: u1, + reserved3: u1, + /// Usage fault exception active bit + USGFAULTACT: u1, + reserved7: u3, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved10: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// Usage fault exception pending bit + USGFAULTPENDED: u1, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding: u13, + }), + /// Configurable fault status register + CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) { + /// IACCVIOL + IACCVIOL: u1, + /// DACCVIOL + DACCVIOL: u1, + reserved3: u1, + /// MUNSTKERR + MUNSTKERR: u1, + /// MSTKERR + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved7: u1, + /// MMARVALID + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception entry + STKERR: u1, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1, + reserved15: u1, + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1, + /// Undefined instruction usage fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage fault + INVPC: u1, + /// No coprocessor usage fault. + NOCP: u1, + reserved24: u4, + /// Unaligned access usage fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding: u6, + }), + /// Hard fault status register + HFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved30: u28, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), + reserved52: [4]u8, + /// Memory management fault address register + MMFAR: mmio.Mmio(packed struct(u32) { + /// Memory management fault address + MMFAR: u32, + }), + /// Bus fault address register + BFAR: mmio.Mmio(packed struct(u32) { + /// Bus fault address + BFAR: u32, + }), + }; + + /// Nested vectored interrupt controller + pub const NVIC_STIR = extern struct { + /// Software trigger interrupt register + STIR: mmio.Mmio(packed struct(u32) { + /// Software generated interrupt ID + INTID: u9, + padding: u23, + }), + }; + + /// System control block ACTLR + pub const SCB_ACTRL = extern struct { + /// Auxiliary control register + ACTRL: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// DISFOLD + DISFOLD: u1, + reserved10: u7, + /// FPEXCODIS + FPEXCODIS: u1, + /// DISRAMODE + DISRAMODE: u1, + /// DISITMATBFLUSH + DISITMATBFLUSH: u1, + padding: u19, + }), + }; + + /// Memory protection unit + pub const MPU = extern struct { + /// MPU type register + MPU_TYPER: mmio.Mmio(packed struct(u32) { + /// Separate flag + SEPARATE: u1, + reserved8: u7, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction regions + IREGION: u8, + padding: u8, + }), + /// MPU control register + MPU_CTRL: mmio.Mmio(packed struct(u32) { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1, + padding: u29, + }), + /// MPU region number register + MPU_RNR: mmio.Mmio(packed struct(u32) { + /// MPU region + REGION: u8, + padding: u24, + }), + /// MPU region base address register + MPU_RBAR: mmio.Mmio(packed struct(u32) { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), + /// MPU region attribute and size register + MPU_RASR: mmio.Mmio(packed struct(u32) { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection region + SIZE: u5, + reserved8: u2, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved24: u2, + /// Access permission + AP: u3, + reserved28: u1, + /// Instruction access disable bit + XN: u1, + padding: u3, + }), + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = extern struct { + /// Interrupt Set-Enable Register + ISER0: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER1: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + reserved128: [120]u8, + /// Interrupt Clear-Enable Register + ICER0: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER1: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + reserved256: [120]u8, + /// Interrupt Set-Pending Register + ISPR0: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR1: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + reserved384: [120]u8, + /// Interrupt Clear-Pending Register + ICPR0: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR1: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + reserved512: [120]u8, + /// Interrupt Active Bit Register + IABR0: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR1: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + reserved768: [248]u8, + /// Interrupt Priority Register + IPR0: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR1: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR2: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR3: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR4: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR5: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR6: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR7: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR8: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR9: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR10: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR11: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR12: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR13: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR14: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + }; + + /// Alternate function I/O + pub const AFIO = extern struct { + /// Event Control Register (AFIO_EVCR) + EVCR: mmio.Mmio(packed struct(u32) { + /// Pin selection + PIN: u4, + /// Port selection + PORT: u3, + /// Event Output Enable + EVOE: u1, + padding: u24, + }), + /// AF remap and debug I/O configuration register (AFIO_MAPR) + MAPR: mmio.Mmio(packed struct(u32) { + /// SPI1 remapping + SPI1_REMAP: u1, + /// I2C1 remapping + I2C1_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u1, + /// USART3 remapping + USART3_REMAP: u2, + /// TIM1 remapping + TIM1_REMAP: u2, + /// TIM2 remapping + TIM2_REMAP: u2, + /// TIM3 remapping + TIM3_REMAP: u2, + /// TIM4 remapping + TIM4_REMAP: u1, + /// CAN1 remapping + CAN_REMAP: u2, + /// Port D0/Port D1 mapping on OSCIN/OSCOUT + PD01_REMAP: u1, + /// Set and cleared by software + TIM5CH4_IREMAP: u1, + /// ADC 1 External trigger injected conversion remapping + ADC1_ETRGINJ_REMAP: u1, + /// ADC 1 external trigger regular conversion remapping + ADC1_ETRGREG_REMAP: u1, + /// ADC 2 external trigger injected conversion remapping + ADC2_ETRGINJ_REMAP: u1, + /// ADC 2 external trigger regular conversion remapping + ADC2_ETRGREG_REMAP: u1, + reserved24: u3, + /// Serial wire JTAG configuration + SWJ_CFG: u3, + padding: u5, + }), + /// External interrupt configuration register 1 (AFIO_EXTICR1) + EXTICR1: mmio.Mmio(packed struct(u32) { + /// EXTI0 configuration + EXTI0: u4, + /// EXTI1 configuration + EXTI1: u4, + /// EXTI2 configuration + EXTI2: u4, + /// EXTI3 configuration + EXTI3: u4, + padding: u16, + }), + /// External interrupt configuration register 2 (AFIO_EXTICR2) + EXTICR2: mmio.Mmio(packed struct(u32) { + /// EXTI4 configuration + EXTI4: u4, + /// EXTI5 configuration + EXTI5: u4, + /// EXTI6 configuration + EXTI6: u4, + /// EXTI7 configuration + EXTI7: u4, + padding: u16, + }), + /// External interrupt configuration register 3 (AFIO_EXTICR3) + EXTICR3: mmio.Mmio(packed struct(u32) { + /// EXTI8 configuration + EXTI8: u4, + /// EXTI9 configuration + EXTI9: u4, + /// EXTI10 configuration + EXTI10: u4, + /// EXTI11 configuration + EXTI11: u4, + padding: u16, + }), + /// External interrupt configuration register 4 (AFIO_EXTICR4) + EXTICR4: mmio.Mmio(packed struct(u32) { + /// EXTI12 configuration + EXTI12: u4, + /// EXTI13 configuration + EXTI13: u4, + /// EXTI14 configuration + EXTI14: u4, + /// EXTI15 configuration + EXTI15: u4, + padding: u16, + }), + reserved28: [4]u8, + /// AF remap and debug I/O configuration register + MAPR2: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// TIM9 remapping + TIM9_REMAP: u1, + /// TIM10 remapping + TIM10_REMAP: u1, + /// TIM11 remapping + TIM11_REMAP: u1, + /// TIM13 remapping + TIM13_REMAP: u1, + /// TIM14 remapping + TIM14_REMAP: u1, + /// NADV connect/disconnect + FSMC_NADV: u1, + padding: u21, + }), + }; + + /// EXTI + pub const EXTI = extern struct { + /// Interrupt mask register (EXTI_IMR) + IMR: mmio.Mmio(packed struct(u32) { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + padding: u13, + }), + /// Event mask register (EXTI_EMR) + EMR: mmio.Mmio(packed struct(u32) { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + padding: u13, + }), + /// Rising Trigger selection register (EXTI_RTSR) + RTSR: mmio.Mmio(packed struct(u32) { + /// Rising trigger event configuration of line 0 + TR0: u1, + /// Rising trigger event configuration of line 1 + TR1: u1, + /// Rising trigger event configuration of line 2 + TR2: u1, + /// Rising trigger event configuration of line 3 + TR3: u1, + /// Rising trigger event configuration of line 4 + TR4: u1, + /// Rising trigger event configuration of line 5 + TR5: u1, + /// Rising trigger event configuration of line 6 + TR6: u1, + /// Rising trigger event configuration of line 7 + TR7: u1, + /// Rising trigger event configuration of line 8 + TR8: u1, + /// Rising trigger event configuration of line 9 + TR9: u1, + /// Rising trigger event configuration of line 10 + TR10: u1, + /// Rising trigger event configuration of line 11 + TR11: u1, + /// Rising trigger event configuration of line 12 + TR12: u1, + /// Rising trigger event configuration of line 13 + TR13: u1, + /// Rising trigger event configuration of line 14 + TR14: u1, + /// Rising trigger event configuration of line 15 + TR15: u1, + /// Rising trigger event configuration of line 16 + TR16: u1, + /// Rising trigger event configuration of line 17 + TR17: u1, + /// Rising trigger event configuration of line 18 + TR18: u1, + padding: u13, + }), + /// Falling Trigger selection register (EXTI_FTSR) + FTSR: mmio.Mmio(packed struct(u32) { + /// Falling trigger event configuration of line 0 + TR0: u1, + /// Falling trigger event configuration of line 1 + TR1: u1, + /// Falling trigger event configuration of line 2 + TR2: u1, + /// Falling trigger event configuration of line 3 + TR3: u1, + /// Falling trigger event configuration of line 4 + TR4: u1, + /// Falling trigger event configuration of line 5 + TR5: u1, + /// Falling trigger event configuration of line 6 + TR6: u1, + /// Falling trigger event configuration of line 7 + TR7: u1, + /// Falling trigger event configuration of line 8 + TR8: u1, + /// Falling trigger event configuration of line 9 + TR9: u1, + /// Falling trigger event configuration of line 10 + TR10: u1, + /// Falling trigger event configuration of line 11 + TR11: u1, + /// Falling trigger event configuration of line 12 + TR12: u1, + /// Falling trigger event configuration of line 13 + TR13: u1, + /// Falling trigger event configuration of line 14 + TR14: u1, + /// Falling trigger event configuration of line 15 + TR15: u1, + /// Falling trigger event configuration of line 16 + TR16: u1, + /// Falling trigger event configuration of line 17 + TR17: u1, + /// Falling trigger event configuration of line 18 + TR18: u1, + padding: u13, + }), + /// Software interrupt event register (EXTI_SWIER) + SWIER: mmio.Mmio(packed struct(u32) { + /// Software Interrupt on line 0 + SWIER0: u1, + /// Software Interrupt on line 1 + SWIER1: u1, + /// Software Interrupt on line 2 + SWIER2: u1, + /// Software Interrupt on line 3 + SWIER3: u1, + /// Software Interrupt on line 4 + SWIER4: u1, + /// Software Interrupt on line 5 + SWIER5: u1, + /// Software Interrupt on line 6 + SWIER6: u1, + /// Software Interrupt on line 7 + SWIER7: u1, + /// Software Interrupt on line 8 + SWIER8: u1, + /// Software Interrupt on line 9 + SWIER9: u1, + /// Software Interrupt on line 10 + SWIER10: u1, + /// Software Interrupt on line 11 + SWIER11: u1, + /// Software Interrupt on line 12 + SWIER12: u1, + /// Software Interrupt on line 13 + SWIER13: u1, + /// Software Interrupt on line 14 + SWIER14: u1, + /// Software Interrupt on line 15 + SWIER15: u1, + /// Software Interrupt on line 16 + SWIER16: u1, + /// Software Interrupt on line 17 + SWIER17: u1, + /// Software Interrupt on line 18 + SWIER18: u1, + padding: u13, + }), + /// Pending register (EXTI_PR) + PR: mmio.Mmio(packed struct(u32) { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + padding: u13, + }), + }; + + /// DMA controller + pub const DMA1 = extern struct { + /// DMA interrupt status register (DMA_ISR) + ISR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF1: u1, + /// Channel 1 Transfer Complete flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1, + /// Channel 1 Transfer Error flag + TEIF1: u1, + /// Channel 2 Global interrupt flag + GIF2: u1, + /// Channel 2 Transfer Complete flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1, + /// Channel 2 Transfer Error flag + TEIF2: u1, + /// Channel 3 Global interrupt flag + GIF3: u1, + /// Channel 3 Transfer Complete flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1, + /// Channel 3 Transfer Error flag + TEIF3: u1, + /// Channel 4 Global interrupt flag + GIF4: u1, + /// Channel 4 Transfer Complete flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1, + /// Channel 4 Transfer Error flag + TEIF4: u1, + /// Channel 5 Global interrupt flag + GIF5: u1, + /// Channel 5 Transfer Complete flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1, + /// Channel 5 Transfer Error flag + TEIF5: u1, + /// Channel 6 Global interrupt flag + GIF6: u1, + /// Channel 6 Transfer Complete flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1, + /// Channel 6 Transfer Error flag + TEIF6: u1, + /// Channel 7 Global interrupt flag + GIF7: u1, + /// Channel 7 Transfer Complete flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1, + /// Channel 7 Transfer Error flag + TEIF7: u1, + padding: u4, + }), + /// DMA interrupt flag clear register (DMA_IFCR) + IFCR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt clear + CGIF1: u1, + /// Channel 1 Transfer Complete clear + CTCIF1: u1, + /// Channel 1 Half Transfer clear + CHTIF1: u1, + /// Channel 1 Transfer Error clear + CTEIF1: u1, + /// Channel 2 Global interrupt clear + CGIF2: u1, + /// Channel 2 Transfer Complete clear + CTCIF2: u1, + /// Channel 2 Half Transfer clear + CHTIF2: u1, + /// Channel 2 Transfer Error clear + CTEIF2: u1, + /// Channel 3 Global interrupt clear + CGIF3: u1, + /// Channel 3 Transfer Complete clear + CTCIF3: u1, + /// Channel 3 Half Transfer clear + CHTIF3: u1, + /// Channel 3 Transfer Error clear + CTEIF3: u1, + /// Channel 4 Global interrupt clear + CGIF4: u1, + /// Channel 4 Transfer Complete clear + CTCIF4: u1, + /// Channel 4 Half Transfer clear + CHTIF4: u1, + /// Channel 4 Transfer Error clear + CTEIF4: u1, + /// Channel 5 Global interrupt clear + CGIF5: u1, + /// Channel 5 Transfer Complete clear + CTCIF5: u1, + /// Channel 5 Half Transfer clear + CHTIF5: u1, + /// Channel 5 Transfer Error clear + CTEIF5: u1, + /// Channel 6 Global interrupt clear + CGIF6: u1, + /// Channel 6 Transfer Complete clear + CTCIF6: u1, + /// Channel 6 Half Transfer clear + CHTIF6: u1, + /// Channel 6 Transfer Error clear + CTEIF6: u1, + /// Channel 7 Global interrupt clear + CGIF7: u1, + /// Channel 7 Transfer Complete clear + CTCIF7: u1, + /// Channel 7 Half Transfer clear + CHTIF7: u1, + /// Channel 7 Transfer Error clear + CTEIF7: u1, + padding: u4, + }), + /// DMA channel configuration register (DMA_CCR) + CCR1: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 1 number of data register + CNDTR1: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 1 peripheral address register + CPAR1: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 1 memory address register + CMAR1: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved28: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR2: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 2 number of data register + CNDTR2: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 2 peripheral address register + CPAR2: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 2 memory address register + CMAR2: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved48: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR3: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 3 number of data register + CNDTR3: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 3 peripheral address register + CPAR3: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 3 memory address register + CMAR3: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved68: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR4: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 4 number of data register + CNDTR4: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 4 peripheral address register + CPAR4: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 4 memory address register + CMAR4: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved88: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR5: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 5 number of data register + CNDTR5: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 5 peripheral address register + CPAR5: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 5 memory address register + CMAR5: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved108: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR6: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 6 number of data register + CNDTR6: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 6 peripheral address register + CPAR6: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 6 memory address register + CMAR6: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved128: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR7: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 7 number of data register + CNDTR7: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 7 peripheral address register + CPAR7: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 7 memory address register + CMAR7: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + }; + + /// Ethernet: DMA controller operation + pub const ETHERNET_DMA = extern struct { + /// Ethernet DMA bus mode register + DMABMR: mmio.Mmio(packed struct(u32) { + /// Software reset + SR: u1, + /// DMA Arbitration + DA: u1, + /// Descriptor skip length + DSL: u5, + reserved8: u1, + /// Programmable burst length + PBL: u6, + /// Rx Tx priority ratio + RTPR: u2, + /// Fixed burst + FB: u1, + /// Rx DMA PBL + RDP: u6, + /// Use separate PBL + USP: u1, + /// 4xPBL mode + FPM: u1, + /// Address-aligned beats + AAB: u1, + padding: u6, + }), + /// Ethernet DMA transmit poll demand register + DMATPDR: mmio.Mmio(packed struct(u32) { + /// Transmit poll demand + TPD: u32, + }), + /// EHERNET DMA receive poll demand register + DMARPDR: mmio.Mmio(packed struct(u32) { + /// Receive poll demand + RPD: u32, + }), + /// Ethernet DMA receive descriptor list address register + DMARDLAR: mmio.Mmio(packed struct(u32) { + /// Start of receive list + SRL: u32, + }), + /// Ethernet DMA transmit descriptor list address register + DMATDLAR: mmio.Mmio(packed struct(u32) { + /// Start of transmit list + STL: u32, + }), + /// Ethernet DMA status register + DMASR: mmio.Mmio(packed struct(u32) { + /// Transmit status + TS: u1, + /// Transmit process stopped status + TPSS: u1, + /// Transmit buffer unavailable status + TBUS: u1, + /// Transmit jabber timeout status + TJTS: u1, + /// Receive overflow status + ROS: u1, + /// Transmit underflow status + TUS: u1, + /// Receive status + RS: u1, + /// Receive buffer unavailable status + RBUS: u1, + /// Receive process stopped status + RPSS: u1, + /// Receive watchdog timeout status + PWTS: u1, + /// Early transmit status + ETS: u1, + reserved13: u2, + /// Fatal bus error status + FBES: u1, + /// Early receive status + ERS: u1, + /// Abnormal interrupt summary + AIS: u1, + /// Normal interrupt summary + NIS: u1, + /// Receive process state + RPS: u3, + /// Transmit process state + TPS: u3, + /// Error bits status + EBS: u3, + reserved27: u1, + /// MMC status + MMCS: u1, + /// PMT status + PMTS: u1, + /// Time stamp trigger status + TSTS: u1, + padding: u2, + }), + /// Ethernet DMA operation mode register + DMAOMR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved6: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved13: u5, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved20: u3, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved24: u2, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding: u5, + }), + /// Ethernet DMA interrupt enable register + DMAIER: mmio.Mmio(packed struct(u32) { + /// Transmit interrupt enable + TIE: u1, + /// Transmit process stopped interrupt enable + TPSIE: u1, + /// Transmit buffer unavailable interrupt enable + TBUIE: u1, + /// Transmit jabber timeout interrupt enable + TJTIE: u1, + /// Overflow interrupt enable + ROIE: u1, + /// Underflow interrupt enable + TUIE: u1, + /// Receive interrupt enable + RIE: u1, + /// Receive buffer unavailable interrupt enable + RBUIE: u1, + /// Receive process stopped interrupt enable + RPSIE: u1, + /// receive watchdog timeout interrupt enable + RWTIE: u1, + /// Early transmit interrupt enable + ETIE: u1, + reserved13: u2, + /// Fatal bus error interrupt enable + FBEIE: u1, + /// Early receive interrupt enable + ERIE: u1, + /// Abnormal interrupt summary enable + AISE: u1, + /// Normal interrupt summary enable + NISE: u1, + padding: u15, + }), + /// Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR: mmio.Mmio(packed struct(u32) { + /// Missed frames by the controller + MFC: u16, + /// Overflow bit for missed frame counter + OMFC: u1, + /// Missed frames by the application + MFA: u11, + /// Overflow bit for FIFO overflow counter + OFOC: u1, + padding: u3, + }), + reserved72: [36]u8, + /// Ethernet DMA current host transmit descriptor register + DMACHTDR: mmio.Mmio(packed struct(u32) { + /// Host transmit descriptor address pointer + HTDAP: u32, + }), + /// Ethernet DMA current host receive descriptor register + DMACHRDR: mmio.Mmio(packed struct(u32) { + /// Host receive descriptor address pointer + HRDAP: u32, + }), + /// Ethernet DMA current host transmit buffer address register + DMACHTBAR: mmio.Mmio(packed struct(u32) { + /// Host transmit buffer address pointer + HTBAP: u32, + }), + /// Ethernet DMA current host receive buffer address register + DMACHRBAR: mmio.Mmio(packed struct(u32) { + /// Host receive buffer address pointer + HRBAP: u32, + }), + }; + + /// Secure digital input/output interface + pub const SDIO = extern struct { + /// Bits 1:0 = PWRCTRL: Power supply control bits + POWER: mmio.Mmio(packed struct(u32) { + /// PWRCTRL + PWRCTRL: u2, + padding: u30, + }), + /// SDI clock control register (SDIO_CLKCR) + CLKCR: mmio.Mmio(packed struct(u32) { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration bit + PWRSAV: u1, + /// Clock divider bypass enable bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding: u17, + }), + /// Bits 31:0 = : Command argument + ARG: mmio.Mmio(packed struct(u32) { + /// Command argument + CMDARG: u32, + }), + /// SDIO command register (SDIO_CMD) + CMD: mmio.Mmio(packed struct(u32) { + /// CMDINDEX + CMDINDEX: u6, + /// WAITRESP + WAITRESP: u2, + /// WAITINT + WAITINT: u1, + /// WAITPEND + WAITPEND: u1, + /// CPSMEN + CPSMEN: u1, + /// SDIOSuspend + SDIOSuspend: u1, + /// ENCMDcompl + ENCMDcompl: u1, + /// nIEN + nIEN: u1, + /// CE_ATACMD + CE_ATACMD: u1, + padding: u17, + }), + /// SDIO command register + RESPCMD: mmio.Mmio(packed struct(u32) { + /// RESPCMD + RESPCMD: u6, + padding: u26, + }), + /// Bits 31:0 = CARDSTATUS1 + RESPI1: mmio.Mmio(packed struct(u32) { + /// CARDSTATUS1 + CARDSTATUS1: u32, + }), + /// Bits 31:0 = CARDSTATUS2 + RESP2: mmio.Mmio(packed struct(u32) { + /// CARDSTATUS2 + CARDSTATUS2: u32, + }), + /// Bits 31:0 = CARDSTATUS3 + RESP3: mmio.Mmio(packed struct(u32) { + /// CARDSTATUS3 + CARDSTATUS3: u32, + }), + /// Bits 31:0 = CARDSTATUS4 + RESP4: mmio.Mmio(packed struct(u32) { + /// CARDSTATUS4 + CARDSTATUS4: u32, + }), + /// Bits 31:0 = DATATIME: Data timeout period + DTIMER: mmio.Mmio(packed struct(u32) { + /// Data timeout period + DATATIME: u32, + }), + /// Bits 24:0 = DATALENGTH: Data length value + DLEN: mmio.Mmio(packed struct(u32) { + /// Data length value + DATALENGTH: u25, + padding: u7, + }), + /// SDIO data control register (SDIO_DCTRL) + DCTRL: mmio.Mmio(packed struct(u32) { + /// DTEN + DTEN: u1, + /// DTDIR + DTDIR: u1, + /// DTMODE + DTMODE: u1, + /// DMAEN + DMAEN: u1, + /// DBLOCKSIZE + DBLOCKSIZE: u4, + /// PWSTART + PWSTART: u1, + /// PWSTOP + PWSTOP: u1, + /// RWMOD + RWMOD: u1, + /// SDIOEN + SDIOEN: u1, + padding: u20, + }), + /// Bits 24:0 = DATACOUNT: Data count value + DCOUNT: mmio.Mmio(packed struct(u32) { + /// Data count value + DATACOUNT: u25, + padding: u7, + }), + /// SDIO status register (SDIO_STA) + STA: mmio.Mmio(packed struct(u32) { + /// CCRCFAIL + CCRCFAIL: u1, + /// DCRCFAIL + DCRCFAIL: u1, + /// CTIMEOUT + CTIMEOUT: u1, + /// DTIMEOUT + DTIMEOUT: u1, + /// TXUNDERR + TXUNDERR: u1, + /// RXOVERR + RXOVERR: u1, + /// CMDREND + CMDREND: u1, + /// CMDSENT + CMDSENT: u1, + /// DATAEND + DATAEND: u1, + /// STBITERR + STBITERR: u1, + /// DBCKEND + DBCKEND: u1, + /// CMDACT + CMDACT: u1, + /// TXACT + TXACT: u1, + /// RXACT + RXACT: u1, + /// TXFIFOHE + TXFIFOHE: u1, + /// RXFIFOHF + RXFIFOHF: u1, + /// TXFIFOF + TXFIFOF: u1, + /// RXFIFOF + RXFIFOF: u1, + /// TXFIFOE + TXFIFOE: u1, + /// RXFIFOE + RXFIFOE: u1, + /// TXDAVL + TXDAVL: u1, + /// RXDAVL + RXDAVL: u1, + /// SDIOIT + SDIOIT: u1, + /// CEATAEND + CEATAEND: u1, + padding: u8, + }), + /// SDIO interrupt clear register (SDIO_ICR) + ICR: mmio.Mmio(packed struct(u32) { + /// CCRCFAILC + CCRCFAILC: u1, + /// DCRCFAILC + DCRCFAILC: u1, + /// CTIMEOUTC + CTIMEOUTC: u1, + /// DTIMEOUTC + DTIMEOUTC: u1, + /// TXUNDERRC + TXUNDERRC: u1, + /// RXOVERRC + RXOVERRC: u1, + /// CMDRENDC + CMDRENDC: u1, + /// CMDSENTC + CMDSENTC: u1, + /// DATAENDC + DATAENDC: u1, + /// STBITERRC + STBITERRC: u1, + /// DBCKENDC + DBCKENDC: u1, + reserved22: u11, + /// SDIOITC + SDIOITC: u1, + /// CEATAENDC + CEATAENDC: u1, + padding: u8, + }), + /// SDIO mask register (SDIO_MASK) + MASK: mmio.Mmio(packed struct(u32) { + /// CCRCFAILIE + CCRCFAILIE: u1, + /// DCRCFAILIE + DCRCFAILIE: u1, + /// CTIMEOUTIE + CTIMEOUTIE: u1, + /// DTIMEOUTIE + DTIMEOUTIE: u1, + /// TXUNDERRIE + TXUNDERRIE: u1, + /// RXOVERRIE + RXOVERRIE: u1, + /// CMDRENDIE + CMDRENDIE: u1, + /// CMDSENTIE + CMDSENTIE: u1, + /// DATAENDIE + DATAENDIE: u1, + /// STBITERRIE + STBITERRIE: u1, + /// DBACKENDIE + DBACKENDIE: u1, + /// CMDACTIE + CMDACTIE: u1, + /// TXACTIE + TXACTIE: u1, + /// RXACTIE + RXACTIE: u1, + /// TXFIFOHEIE + TXFIFOHEIE: u1, + /// RXFIFOHFIE + RXFIFOHFIE: u1, + /// TXFIFOFIE + TXFIFOFIE: u1, + /// RXFIFOFIE + RXFIFOFIE: u1, + /// TXFIFOEIE + TXFIFOEIE: u1, + /// RXFIFOEIE + RXFIFOEIE: u1, + /// TXDAVLIE + TXDAVLIE: u1, + /// RXDAVLIE + RXDAVLIE: u1, + /// SDIOITIE + SDIOITIE: u1, + /// CEATENDIE + CEATENDIE: u1, + padding: u8, + }), + reserved72: [8]u8, + /// Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO + FIFOCNT: mmio.Mmio(packed struct(u32) { + /// FIF0COUNT + FIF0COUNT: u24, + padding: u8, + }), + reserved128: [52]u8, + /// bits 31:0 = FIFOData: Receive and transmit FIFO data + FIFO: mmio.Mmio(packed struct(u32) { + /// FIFOData + FIFOData: u32, + }), + }; + + /// Real time clock + pub const RTC = extern struct { + /// RTC Control Register High + CRH: mmio.Mmio(packed struct(u32) { + /// Second interrupt Enable + SECIE: u1, + /// Alarm interrupt Enable + ALRIE: u1, + /// Overflow interrupt Enable + OWIE: u1, + padding: u29, + }), + /// RTC Control Register Low + CRL: mmio.Mmio(packed struct(u32) { + /// Second Flag + SECF: u1, + /// Alarm Flag + ALRF: u1, + /// Overflow Flag + OWF: u1, + /// Registers Synchronized Flag + RSF: u1, + /// Configuration Flag + CNF: u1, + /// RTC operation OFF + RTOFF: u1, + padding: u26, + }), + /// RTC Prescaler Load Register High + PRLH: mmio.Mmio(packed struct(u32) { + /// RTC Prescaler Load Register High + PRLH: u4, + padding: u28, + }), + /// RTC Prescaler Load Register Low + PRLL: mmio.Mmio(packed struct(u32) { + /// RTC Prescaler Divider Register Low + PRLL: u16, + padding: u16, + }), + /// RTC Prescaler Divider Register High + DIVH: mmio.Mmio(packed struct(u32) { + /// RTC prescaler divider register high + DIVH: u4, + padding: u28, + }), + /// RTC Prescaler Divider Register Low + DIVL: mmio.Mmio(packed struct(u32) { + /// RTC prescaler divider register Low + DIVL: u16, + padding: u16, + }), + /// RTC Counter Register High + CNTH: mmio.Mmio(packed struct(u32) { + /// RTC counter register high + CNTH: u16, + padding: u16, + }), + /// RTC Counter Register Low + CNTL: mmio.Mmio(packed struct(u32) { + /// RTC counter register Low + CNTL: u16, + padding: u16, + }), + /// RTC Alarm Register High + ALRH: mmio.Mmio(packed struct(u32) { + /// RTC alarm register high + ALRH: u16, + padding: u16, + }), + /// RTC Alarm Register Low + ALRL: mmio.Mmio(packed struct(u32) { + /// RTC alarm register low + ALRL: u16, + padding: u16, + }), + }; + + /// Backup registers + pub const BKP = extern struct { + /// Backup data register (BKP_DR) + DR1: mmio.Mmio(packed struct(u32) { + /// Backup data + D1: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR2: mmio.Mmio(packed struct(u32) { + /// Backup data + D2: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR3: mmio.Mmio(packed struct(u32) { + /// Backup data + D3: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR4: mmio.Mmio(packed struct(u32) { + /// Backup data + D4: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR5: mmio.Mmio(packed struct(u32) { + /// Backup data + D5: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR6: mmio.Mmio(packed struct(u32) { + /// Backup data + D6: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR7: mmio.Mmio(packed struct(u32) { + /// Backup data + D7: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR8: mmio.Mmio(packed struct(u32) { + /// Backup data + D8: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR9: mmio.Mmio(packed struct(u32) { + /// Backup data + D9: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR10: mmio.Mmio(packed struct(u32) { + /// Backup data + D10: u16, + padding: u16, + }), + /// RTC clock calibration register (BKP_RTCCR) + RTCCR: mmio.Mmio(packed struct(u32) { + /// Calibration value + CAL: u7, + /// Calibration Clock Output + CCO: u1, + /// Alarm or second output enable + ASOE: u1, + /// Alarm or second output selection + ASOS: u1, + padding: u22, + }), + /// Backup control register (BKP_CR) + CR: mmio.Mmio(packed struct(u32) { + /// Tamper pin enable + TPE: u1, + /// Tamper pin active level + TPAL: u1, + padding: u30, + }), + /// BKP_CSR control/status register (BKP_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Clear Tamper event + CTE: u1, + /// Clear Tamper Interrupt + CTI: u1, + /// Tamper Pin interrupt enable + TPIE: u1, + reserved8: u5, + /// Tamper Event Flag + TEF: u1, + /// Tamper Interrupt Flag + TIF: u1, + padding: u22, + }), + reserved60: [8]u8, + /// Backup data register (BKP_DR) + DR11: mmio.Mmio(packed struct(u32) { + /// Backup data + DR11: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR12: mmio.Mmio(packed struct(u32) { + /// Backup data + DR12: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR13: mmio.Mmio(packed struct(u32) { + /// Backup data + DR13: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR14: mmio.Mmio(packed struct(u32) { + /// Backup data + D14: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR15: mmio.Mmio(packed struct(u32) { + /// Backup data + D15: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR16: mmio.Mmio(packed struct(u32) { + /// Backup data + D16: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR17: mmio.Mmio(packed struct(u32) { + /// Backup data + D17: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR18: mmio.Mmio(packed struct(u32) { + /// Backup data + D18: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR19: mmio.Mmio(packed struct(u32) { + /// Backup data + D19: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR20: mmio.Mmio(packed struct(u32) { + /// Backup data + D20: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR21: mmio.Mmio(packed struct(u32) { + /// Backup data + D21: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR22: mmio.Mmio(packed struct(u32) { + /// Backup data + D22: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR23: mmio.Mmio(packed struct(u32) { + /// Backup data + D23: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR24: mmio.Mmio(packed struct(u32) { + /// Backup data + D24: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR25: mmio.Mmio(packed struct(u32) { + /// Backup data + D25: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR26: mmio.Mmio(packed struct(u32) { + /// Backup data + D26: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR27: mmio.Mmio(packed struct(u32) { + /// Backup data + D27: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR28: mmio.Mmio(packed struct(u32) { + /// Backup data + D28: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR29: mmio.Mmio(packed struct(u32) { + /// Backup data + D29: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR30: mmio.Mmio(packed struct(u32) { + /// Backup data + D30: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR31: mmio.Mmio(packed struct(u32) { + /// Backup data + D31: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR32: mmio.Mmio(packed struct(u32) { + /// Backup data + D32: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR33: mmio.Mmio(packed struct(u32) { + /// Backup data + D33: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR34: mmio.Mmio(packed struct(u32) { + /// Backup data + D34: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR35: mmio.Mmio(packed struct(u32) { + /// Backup data + D35: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR36: mmio.Mmio(packed struct(u32) { + /// Backup data + D36: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR37: mmio.Mmio(packed struct(u32) { + /// Backup data + D37: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR38: mmio.Mmio(packed struct(u32) { + /// Backup data + D38: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR39: mmio.Mmio(packed struct(u32) { + /// Backup data + D39: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR40: mmio.Mmio(packed struct(u32) { + /// Backup data + D40: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR41: mmio.Mmio(packed struct(u32) { + /// Backup data + D41: u16, + padding: u16, + }), + /// Backup data register (BKP_DR) + DR42: mmio.Mmio(packed struct(u32) { + /// Backup data + D42: u16, + padding: u16, + }), + }; + + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register (IWDG_KR) + KR: mmio.Mmio(packed struct(u32) { + /// Key value + KEY: u16, + padding: u16, + }), + /// Prescaler register (IWDG_PR) + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: u3, + padding: u29, + }), + /// Reload register (IWDG_RLR) + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register (IWDG_SR) + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + padding: u30, + }), + }; + + /// Window watchdog + pub const WWDG = extern struct { + /// Control register (WWDG_CR) + CR: mmio.Mmio(packed struct(u32) { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding: u24, + }), + /// Configuration register (WWDG_CFR) + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + /// Timer Base + WDGTB: u2, + /// Early Wakeup Interrupt + EWI: u1, + padding: u22, + }), + /// Status register (WWDG_SR) + SR: mmio.Mmio(packed struct(u32) { + /// Early Wakeup Interrupt + EWI: u1, + padding: u31, + }), + }; + + /// Advanced timer + pub const TIM1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding: u17, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear enable + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + OC4CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output enable + CC2NE: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output enable + CC3NE: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + padding: u18, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR4: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding: u16, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Ethernet: Precision time protocol + pub const ETHERNET_PTP = extern struct { + /// Ethernet PTP time stamp control register (ETH_PTPTSCR) + PTPTSCR: mmio.Mmio(packed struct(u32) { + /// Time stamp enable + TSE: u1, + /// Time stamp fine or coarse update + TSFCU: u1, + /// Time stamp system time initialize + TSSTI: u1, + /// Time stamp system time update + TSSTU: u1, + /// Time stamp interrupt trigger enable + TSITE: u1, + /// Time stamp addend register update + TSARU: u1, + padding: u26, + }), + /// Ethernet PTP subsecond increment register + PTPSSIR: mmio.Mmio(packed struct(u32) { + /// System time subsecond increment + STSSI: u8, + padding: u24, + }), + /// Ethernet PTP time stamp high register + PTPTSHR: mmio.Mmio(packed struct(u32) { + /// System time second + STS: u32, + }), + /// Ethernet PTP time stamp low register (ETH_PTPTSLR) + PTPTSLR: mmio.Mmio(packed struct(u32) { + /// System time subseconds + STSS: u31, + /// System time positive or negative sign + STPNS: u1, + }), + /// Ethernet PTP time stamp high update register + PTPTSHUR: mmio.Mmio(packed struct(u32) { + /// Time stamp update second + TSUS: u32, + }), + /// Ethernet PTP time stamp low update register (ETH_PTPTSLUR) + PTPTSLUR: mmio.Mmio(packed struct(u32) { + /// Time stamp update subseconds + TSUSS: u31, + /// Time stamp update positive or negative sign + TSUPNS: u1, + }), + /// Ethernet PTP time stamp addend register + PTPTSAR: mmio.Mmio(packed struct(u32) { + /// Time stamp addend + TSA: u32, + }), + /// Ethernet PTP target time high register + PTPTTHR: mmio.Mmio(packed struct(u32) { + /// Target time stamp high + TTSH: u32, + }), + /// Ethernet PTP target time low register + PTPTTLR: mmio.Mmio(packed struct(u32) { + /// Target time stamp low + TTSL: u32, + }), + }; + + /// General purpose timer + pub const TIM2 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output compare 1 fast enable + OC1FE: u1, + /// Output compare 1 preload enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output compare 2 fast enable + OC2FE: u1, + /// Output compare 2 preload enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear enable + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved4: u2, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved8: u2, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved12: u2, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + padding: u18, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR4: u16, + padding: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Ethernet: media access control + pub const ETHERNET_MAC = extern struct { + /// Ethernet MAC configuration register (ETH_MACCR) + MACCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// Deferral check + DC: u1, + /// Back-off limit + BL: u2, + /// Automatic pad/CRC stripping + APCS: u1, + reserved9: u1, + /// Retry disable + RD: u1, + /// IPv4 checksum offload + IPCO: u1, + /// Duplex mode + DM: u1, + /// Loopback mode + LM: u1, + /// Receive own disable + ROD: u1, + /// Fast Ethernet speed + FES: u1, + reserved16: u1, + /// Carrier sense disable + CSD: u1, + /// Interframe gap + IFG: u3, + reserved22: u2, + /// Jabber disable + JD: u1, + /// Watchdog disable + WD: u1, + padding: u8, + }), + /// Ethernet MAC frame filter register (ETH_MACCFFR) + MACFFR: mmio.Mmio(packed struct(u32) { + /// Promiscuous mode + PM: u1, + /// Hash unicast + HU: u1, + /// Hash multicast + HM: u1, + /// Destination address inverse filtering + DAIF: u1, + /// Pass all multicast + PAM: u1, + /// Broadcast frames disable + BFD: u1, + /// Pass control frames + PCF: u2, + /// Source address inverse filtering + SAIF: u1, + /// Source address filter + SAF: u1, + /// Hash or perfect filter + HPF: u1, + reserved31: u20, + /// Receive all + RA: u1, + }), + /// Ethernet MAC hash table high register + MACHTHR: mmio.Mmio(packed struct(u32) { + /// Hash table high + HTH: u32, + }), + /// Ethernet MAC hash table low register + MACHTLR: mmio.Mmio(packed struct(u32) { + /// Hash table low + HTL: u32, + }), + /// Ethernet MAC MII address register (ETH_MACMIIAR) + MACMIIAR: mmio.Mmio(packed struct(u32) { + /// MII busy + MB: u1, + /// MII write + MW: u1, + /// Clock range + CR: u3, + reserved6: u1, + /// MII register + MR: u5, + /// PHY address + PA: u5, + padding: u16, + }), + /// Ethernet MAC MII data register (ETH_MACMIIDR) + MACMIIDR: mmio.Mmio(packed struct(u32) { + /// MII data + MD: u16, + padding: u16, + }), + /// Ethernet MAC flow control register (ETH_MACFCR) + MACFCR: mmio.Mmio(packed struct(u32) { + /// Flow control busy/back pressure activate + FCB_BPA: u1, + /// Transmit flow control enable + TFCE: u1, + /// Receive flow control enable + RFCE: u1, + /// Unicast pause frame detect + UPFD: u1, + /// Pause low threshold + PLT: u2, + reserved7: u1, + /// Zero-quanta pause disable + ZQPD: u1, + reserved16: u8, + /// Pass control frames + PT: u16, + }), + /// Ethernet MAC VLAN tag register (ETH_MACVLANTR) + MACVLANTR: mmio.Mmio(packed struct(u32) { + /// VLAN tag identifier (for receive frames) + VLANTI: u16, + /// 12-bit VLAN tag comparison + VLANTC: u1, + padding: u15, + }), + reserved40: [8]u8, + /// Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) + MACRWUFFR: u32, + /// Ethernet MAC PMT control and status register (ETH_MACPMTCSR) + MACPMTCSR: mmio.Mmio(packed struct(u32) { + /// Power down + PD: u1, + /// Magic Packet enable + MPE: u1, + /// Wakeup frame enable + WFE: u1, + reserved5: u2, + /// Magic packet received + MPR: u1, + /// Wakeup frame received + WFR: u1, + reserved9: u2, + /// Global unicast + GU: u1, + reserved31: u21, + /// Wakeup frame filter register pointer reset + WFFRPR: u1, + }), + reserved56: [8]u8, + /// Ethernet MAC interrupt status register (ETH_MACSR) + MACSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT status + PMTS: u1, + /// MMC status + MMCS: u1, + /// MMC receive status + MMCRS: u1, + /// MMC transmit status + MMCTS: u1, + reserved9: u2, + /// Time stamp trigger status + TSTS: u1, + padding: u22, + }), + /// Ethernet MAC interrupt mask register (ETH_MACIMR) + MACIMR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMT interrupt mask + PMTIM: u1, + reserved9: u5, + /// Time stamp trigger interrupt mask + TSTIM: u1, + padding: u22, + }), + /// Ethernet MAC address 0 high register (ETH_MACA0HR) + MACA0HR: mmio.Mmio(packed struct(u32) { + /// MAC address0 high + MACA0H: u16, + reserved31: u15, + /// Always 1 + MO: u1, + }), + /// Ethernet MAC address 0 low register + MACA0LR: mmio.Mmio(packed struct(u32) { + /// MAC address0 low + MACA0L: u32, + }), + /// Ethernet MAC address 1 high register (ETH_MACA1HR) + MACA1HR: mmio.Mmio(packed struct(u32) { + /// MAC address1 high + MACA1H: u16, + reserved24: u8, + /// Mask byte control + MBC: u6, + /// Source address + SA: u1, + /// Address enable + AE: u1, + }), + /// Ethernet MAC address1 low register + MACA1LR: mmio.Mmio(packed struct(u32) { + /// MAC address1 low + MACA1L: u32, + }), + /// Ethernet MAC address 2 high register (ETH_MACA2HR) + MACA2HR: mmio.Mmio(packed struct(u32) { + /// Ethernet MAC address 2 high register + ETH_MACA2HR: u16, + reserved24: u8, + /// Mask byte control + MBC: u6, + /// Source address + SA: u1, + /// Address enable + AE: u1, + }), + /// Ethernet MAC address 2 low register + MACA2LR: mmio.Mmio(packed struct(u32) { + /// MAC address2 low + MACA2L: u31, + padding: u1, + }), + /// Ethernet MAC address 3 high register (ETH_MACA3HR) + MACA3HR: mmio.Mmio(packed struct(u32) { + /// MAC address3 high + MACA3H: u16, + reserved24: u8, + /// Mask byte control + MBC: u6, + /// Source address + SA: u1, + /// Address enable + AE: u1, + }), + /// Ethernet MAC address 3 low register + MACA3LR: mmio.Mmio(packed struct(u32) { + /// MAC address3 low + MBCA3L: u32, + }), + }; + + /// Ethernet: MAC management counters + pub const ETHERNET_MMC = extern struct { + /// Ethernet MMC control register (ETH_MMCCR) + MMCCR: mmio.Mmio(packed struct(u32) { + /// Counter reset + CR: u1, + /// Counter stop rollover + CSR: u1, + /// Reset on read + ROR: u1, + reserved31: u28, + /// MMC counter freeze + MCF: u1, + }), + /// Ethernet MMC receive interrupt register (ETH_MMCRIR) + MMCRIR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frames CRC error status + RFCES: u1, + /// Received frames alignment error status + RFAES: u1, + reserved17: u10, + /// Received Good Unicast Frames Status + RGUFS: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt register (ETH_MMCTIR) + MMCTIR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision status + TGFSCS: u1, + /// Transmitted good frames more single collision status + TGFMSCS: u1, + reserved21: u5, + /// Transmitted good frames status + TGFS: u1, + padding: u10, + }), + /// Ethernet MMC receive interrupt mask register (ETH_MMCRIMR) + MMCRIMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// Received frame CRC error mask + RFCEM: u1, + /// Received frames alignment error mask + RFAEM: u1, + reserved17: u10, + /// Received good unicast frames mask + RGUFM: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR) + MMCTIMR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// Transmitted good frames single collision mask + TGFSCM: u1, + /// Transmitted good frames more single collision mask + TGFMSCM: u1, + reserved21: u5, + /// Transmitted good frames mask + TGFM: u1, + padding: u10, + }), + reserved76: [56]u8, + /// Ethernet MMC transmitted good frames after a single collision counter + MMCTGFSCCR: mmio.Mmio(packed struct(u32) { + /// Transmitted good frames after a single collision counter + TGFSCC: u32, + }), + /// Ethernet MMC transmitted good frames after more than a single collision + MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { + /// Transmitted good frames after more than a single collision counter + TGFMSCC: u32, + }), + reserved104: [20]u8, + /// Ethernet MMC transmitted good frames counter register + MMCTGFCR: mmio.Mmio(packed struct(u32) { + /// Transmitted good frames counter + TGFC: u32, + }), + reserved148: [40]u8, + /// Ethernet MMC received frames with CRC error counter register + MMCRFCECR: mmio.Mmio(packed struct(u32) { + /// Received frames with CRC error counter + RFCFC: u32, + }), + /// Ethernet MMC received frames with alignment error counter register + MMCRFAECR: mmio.Mmio(packed struct(u32) { + /// Received frames with alignment error counter + RFAEC: u32, + }), + reserved196: [40]u8, + /// MMC received good unicast frames counter register + MMCRGUFCR: mmio.Mmio(packed struct(u32) { + /// Received good unicast frames counter + RGUFC: u32, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = extern struct { + /// OTG_FS power and clock gating control register + FS_PCGCCTL: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY Suspended + PHYSUSP: u1, + padding: u27, + }), + }; + + /// General purpose timer + pub const TIM9 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding: u24, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + reserved6: u3, + /// Trigger interrupt enable + TIE: u1, + padding: u25, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + reserved6: u3, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + padding: u21, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + reserved6: u3, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved8: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding: u17, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + padding: u24, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = extern struct { + /// OTG_FS host configuration register (OTG_FS_HCFG) + FS_HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, + }), + /// OTG_FS Host frame interval register + HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, + }), + /// OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + FS_HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), + reserved16: [4]u8, + /// OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + FS_HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, + }), + /// OTG_FS Host all channels interrupt register + HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, + }), + /// OTG_FS host all channels interrupt mask register + HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, + }), + reserved64: [36]u8, + /// OTG_FS host port control and status register (OTG_FS_HPRT) + FS_HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, + }), + reserved256: [188]u8, + /// OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + FS_HCCHAR0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved264: [4]u8, + /// OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + FS_HCINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + FS_HCINTMSK0: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-0 transfer size register + FS_HCTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved288: [12]u8, + /// OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) + FS_HCCHAR1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved296: [4]u8, + /// OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) + FS_HCINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) + FS_HCINTMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-1 transfer size register + FS_HCTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved320: [12]u8, + /// OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) + FS_HCCHAR2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved328: [4]u8, + /// OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) + FS_HCINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) + FS_HCINTMSK2: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-2 transfer size register + FS_HCTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved352: [12]u8, + /// OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) + FS_HCCHAR3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved360: [4]u8, + /// OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) + FS_HCINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) + FS_HCINTMSK3: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-3 transfer size register + FS_HCTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved384: [12]u8, + /// OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) + FS_HCCHAR4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved392: [4]u8, + /// OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) + FS_HCINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) + FS_HCINTMSK4: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-x transfer size register + FS_HCTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved416: [12]u8, + /// OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) + FS_HCCHAR5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved424: [4]u8, + /// OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) + FS_HCINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) + FS_HCINTMSK5: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-5 transfer size register + FS_HCTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved448: [12]u8, + /// OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) + FS_HCCHAR6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved456: [4]u8, + /// OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) + FS_HCINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) + FS_HCINTMSK6: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-6 transfer size register + FS_HCTSIZ6: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved480: [12]u8, + /// OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) + FS_HCCHAR7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved488: [4]u8, + /// OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) + FS_HCINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) + FS_HCINTMSK7: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-7 transfer size register + FS_HCTSIZ7: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + }; + + /// General purpose timer + pub const TIM10 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved7: u4, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved9: u7, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + padding: u30, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + reserved3: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding: u25, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = extern struct { + /// OTG_FS control and status register (OTG_FS_GOTGCTL) + FS_GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved8: u6, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, + }), + /// OTG_FS interrupt register (OTG_FS_GOTGINT) + FS_GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding: u12, + }), + /// OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + FS_GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + reserved7: u6, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, + }), + /// OTG_FS USB configuration register (OTG_FS_GUSBCFG) + FS_GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// Full Speed serial transceiver select + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved29: u15, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), + /// OTG_FS reset register (OTG_FS_GRSTCTL) + FS_GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved31: u20, + /// AHB master idle + AHBIDL: u1, + }), + /// OTG_FS core interrupt register (OTG_FS_GINTSTS) + FS_GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + IPXFR_INCOMPISOOUT: u1, + reserved24: u2, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUPINT: u1, + }), + /// OTG_FS interrupt mask register (OTG_FS_GINTMSK) + FS_GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM: u1, + reserved24: u2, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved28: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, + }), + /// OTG_FS Receive status debug read(Device mode) + FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding: u7, + }), + reserved36: [4]u8, + /// OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + FS_GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, + }), + /// OTG_FS non-periodic transmit FIFO size register (Device mode) + FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint 0 transmit RAM start address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), + /// OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + FS_GNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Non-periodic TxFIFO space available + NPTXFSAV: u16, + /// Non-periodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request queue + NPTXQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// OTG_FS general core configuration register (OTG_FS_GCCFG) + FS_GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + reserved18: u1, + /// Enable the VBUS sensing device + VBUSASEN: u1, + /// Enable the VBUS sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding: u11, + }), + /// core ID register + FS_CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, + }), + reserved256: [192]u8, + /// OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + FS_DIEPTXF1: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO2 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + FS_DIEPTXF2: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO3 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + FS_DIEPTXF3: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO4 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = extern struct { + /// OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding: u19, + }), + /// OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, + }), + /// OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + FS_DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (Non-isochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + padding: u25, + }), + /// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + FS_DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + padding: u27, + }), + /// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + /// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + reserved40: [8]u8, + /// OTG_FS device VBUS discharge time register + DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, + }), + /// OTG_FS device VBUS pulsing time register + DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + reserved52: [4]u8, + /// OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + reserved256: [200]u8, + /// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + FS_DIEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u2, + reserved15: u13, + /// USB active endpoint + USBAEP: u1, + reserved17: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved264: [4]u8, + /// device endpoint-x interrupt register + DIEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved272: [4]u8, + /// device endpoint-0 transfer size register + DIEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u2, + padding: u11, + }), + reserved280: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved288: [4]u8, + /// OTG device endpoint-1 control register + DIEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved296: [4]u8, + /// device endpoint-1 interrupt register + DIEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved304: [4]u8, + /// device endpoint-1 transfer size register + DIEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved312: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved320: [4]u8, + /// OTG device endpoint-2 control register + DIEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved328: [4]u8, + /// device endpoint-2 interrupt register + DIEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved336: [4]u8, + /// device endpoint-2 transfer size register + DIEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved344: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved352: [4]u8, + /// OTG device endpoint-3 control register + DIEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved360: [4]u8, + /// device endpoint-3 interrupt register + DIEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved368: [4]u8, + /// device endpoint-3 transfer size register + DIEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved376: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved768: [388]u8, + /// device endpoint-0 control register + DOEPCTL0: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u2, + reserved15: u13, + /// USBAEP + USBAEP: u1, + reserved17: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved30: u2, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved776: [4]u8, + /// device endpoint-0 interrupt register + DOEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved784: [4]u8, + /// device OUT endpoint-0 transfer size register + DOEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u1, + reserved29: u9, + /// SETUP packet count + STUPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// device endpoint-1 control register + DOEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved808: [4]u8, + /// device endpoint-1 interrupt register + DOEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved816: [4]u8, + /// device OUT endpoint-1 transfer size register + DOEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved832: [12]u8, + /// device endpoint-2 control register + DOEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved840: [4]u8, + /// device endpoint-2 interrupt register + DOEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved848: [4]u8, + /// device OUT endpoint-2 transfer size register + DOEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved864: [12]u8, + /// device endpoint-3 control register + DOEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved872: [4]u8, + /// device endpoint-3 interrupt register + DOEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved880: [4]u8, + /// device OUT endpoint-3 transfer size register + DOEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + }; + + /// Universal serial bus full-speed device interface + pub const USB = extern struct { + /// endpoint 0 register + EP0R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 1 register + EP1R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 2 register + EP2R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 3 register + EP3R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 4 register + EP4R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 5 register + EP5R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 6 register + EP6R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 7 register + EP7R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + reserved64: [32]u8, + /// control register + CNTR: mmio.Mmio(packed struct(u32) { + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved8: u3, + /// Expected start of frame interrupt mask + ESOFM: u1, + /// Start of frame interrupt mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt mask + CTRM: u1, + padding: u16, + }), + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved8: u3, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding: u16, + }), + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding: u16, + }), + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// Device address + ADD: u7, + /// Enable function + EF: u1, + padding: u24, + }), + /// Buffer table address + BTABLE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Buffer table + BTABLE: u13, + padding: u16, + }), + }; + + /// Basic timer + pub const TIM6 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + padding: u24, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: u3, + /// Flash half cycle access enable + HLFCYA: u1, + /// Prefetch buffer enable + PRFTBE: u1, + /// Prefetch buffer status + PRFTBS: u1, + padding: u26, + }), + /// Flash key register + KEYR: mmio.Mmio(packed struct(u32) { + /// FPEC key + KEY: u32, + }), + /// Flash option key register + OPTKEYR: mmio.Mmio(packed struct(u32) { + /// Option byte key + OPTKEY: u32, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Busy + BSY: u1, + reserved2: u1, + /// Programming error + PGERR: u1, + reserved4: u1, + /// Write protection error + WRPRTERR: u1, + /// End of operation + EOP: u1, + padding: u26, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page Erase + PER: u1, + /// Mass Erase + MER: u1, + reserved4: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved9: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable + EOPIE: u1, + padding: u19, + }), + /// Flash address register + AR: mmio.Mmio(packed struct(u32) { + /// Flash Address + FAR: u32, + }), + reserved28: [4]u8, + /// Option byte register + OBR: mmio.Mmio(packed struct(u32) { + /// Option byte error + OPTERR: u1, + /// Read protection + RDPRT: u1, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved10: u5, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + padding: u6, + }), + /// Write protection register + WRPR: mmio.Mmio(packed struct(u32) { + /// Write protect + WRP: u32, + }), + }; + + /// Inter integrated circuit + pub const I2C1 = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved3: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Software reset + SWRST: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Peripheral clock frequency + FREQ: u6, + reserved8: u2, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding: u19, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved15: u5, + /// Addressing mode (slave mode) + ADDMODE: u1, + padding: u16, + }), + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + /// Dual addressing mode enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding: u24, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// 8-bit data register + DR: u8, + padding: u24, + }), + /// Status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master mode) + ADD10: u1, + /// Stop detection (slave mode) + STOPF: u1, + reserved6: u1, + /// Data register not empty (receivers) + RxNE: u1, + /// Data register empty (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved14: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding: u16, + }), + /// Status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved4: u1, + /// General call address (Slave mode) + GENCALL: u1, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking register + PEC: u8, + padding: u16, + }), + /// Clock control register + CCR: mmio.Mmio(packed struct(u32) { + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12, + reserved14: u2, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding: u16, + }), + /// TRISE register + TRISE: mmio.Mmio(packed struct(u32) { + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6, + padding: u26, + }), + }; + + /// CRC calculation unit + pub const CRC = extern struct { + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data Register + DR: u32, + }), + /// Independent Data register + IDR: mmio.Mmio(packed struct(u32) { + /// Independent Data register + IDR: u8, + padding: u24, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Reset bit + RESET: u1, + padding: u31, + }), + }; + + /// Serial peripheral interface + pub const SPI1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Output enable in bidirectional mode + BIDIOE: u1, + /// Bidirectional data mode enable + BIDIMODE: u1, + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved5: u2, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + padding: u24, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + padding: u24, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, + padding: u16, + }), + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, + }), + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, + }), + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, + }), + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: u1, + /// Data length to be transferred + DATLEN: u2, + /// Steady state clock polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding: u22, + }), + }; + + /// Universal asynchronous receiver transmitter + pub const UART5 = extern struct { + /// UART4_SR + SR: mmio.Mmio(packed struct(u32) { + /// PE + PE: u1, + /// FE + FE: u1, + /// NE + NE: u1, + /// ORE + ORE: u1, + /// IDLE + IDLE: u1, + /// RXNE + RXNE: u1, + /// TC + TC: u1, + /// TXE + TXE: u1, + /// LBD + LBD: u1, + padding: u23, + }), + /// UART4_DR + DR: mmio.Mmio(packed struct(u32) { + /// DR + DR: u9, + padding: u23, + }), + /// UART4_BRR + BRR: mmio.Mmio(packed struct(u32) { + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding: u16, + }), + /// UART4_CR1 + CR1: mmio.Mmio(packed struct(u32) { + /// SBK + SBK: u1, + /// RWU + RWU: u1, + /// RE + RE: u1, + /// TE + TE: u1, + /// IDLEIE + IDLEIE: u1, + /// RXNEIE + RXNEIE: u1, + /// TCIE + TCIE: u1, + /// TXEIE + TXEIE: u1, + /// PEIE + PEIE: u1, + /// PS + PS: u1, + /// PCE + PCE: u1, + /// WAKE + WAKE: u1, + /// M + M: u1, + /// UE + UE: u1, + padding: u18, + }), + /// UART4_CR2 + CR2: mmio.Mmio(packed struct(u32) { + /// ADD + ADD: u4, + reserved5: u1, + /// LBDL + LBDL: u1, + /// LBDIE + LBDIE: u1, + reserved12: u5, + /// STOP + STOP: u2, + /// LINEN + LINEN: u1, + padding: u17, + }), + /// UART4_CR3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved7: u3, + /// DMA enable transmitter + DMAT: u1, + padding: u24, + }), + }; + + /// Universal asynchronous receiver transmitter + pub const UART4 = extern struct { + /// UART4_SR + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding: u23, + }), + /// UART4_DR + DR: mmio.Mmio(packed struct(u32) { + /// DR + DR: u9, + padding: u23, + }), + /// UART4_BRR + BRR: mmio.Mmio(packed struct(u32) { + /// DIV_Fraction + DIV_Fraction: u4, + /// DIV_Mantissa + DIV_Mantissa: u12, + padding: u16, + }), + /// UART4_CR1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding: u18, + }), + /// UART4_CR2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// UART4_CR3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved6: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + padding: u24, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise error flag + NE: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + padding: u18, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + padding: u21, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + }; + + /// Debug support + pub const DBG = extern struct { + /// DBGMCU_IDCODE + IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, + }), + /// DBGMCU_CR + CR: mmio.Mmio(packed struct(u32) { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + /// DBG_IWDG_STOP + DBG_IWDG_STOP: u1, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_TIM1_STOP + DBG_TIM1_STOP: u1, + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3_STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT: u1, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_TIM8_STOP + DBG_TIM8_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding: u10, + }), + }; + + /// Digital to analog converter + pub const DAC = extern struct { + /// Control register (DAC_CR) + CR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer disable + BOFF1: u1, + /// DAC channel1 trigger enable + TEN1: u1, + /// DAC channel1 trigger selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + reserved16: u3, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer disable + BOFF2: u1, + /// DAC channel2 trigger enable + TEN2: u1, + /// DAC channel2 trigger selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + padding: u3, + }), + /// DAC software trigger register (DAC_SWTRIGR) + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 software trigger + SWTRIG1: u1, + /// DAC channel2 software trigger + SWTRIG2: u1, + padding: u30, + }), + /// DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1) + DHR12R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + padding: u20, + }), + /// DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) + DHR12L1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + padding: u16, + }), + /// DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) + DHR8R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + padding: u24, + }), + /// DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) + DHR12R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u20, + }), + /// DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) + DHR12L2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + padding: u16, + }), + /// DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) + DHR8R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u24, + }), + /// Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved + DHR12RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + reserved16: u4, + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u4, + }), + /// DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + reserved20: u4, + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + }), + /// DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved + DHR8RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u16, + }), + /// DAC channel1 data output register (DAC_DOR1) + DOR1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 data output + DACC1DOR: u12, + padding: u20, + }), + /// DAC channel2 data output register (DAC_DOR2) + DOR2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 data output + DACC2DOR: u12, + padding: u20, + }), + }; + + /// Analog to digital converter + pub const ADC1 = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding: u27, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + /// Dual mode selection + DUALMOD: u4, + reserved22: u2, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + padding: u8, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved8: u4, + /// Direct memory access mode + DMA: u1, + reserved11: u2, + /// Data alignment + ALIGN: u1, + /// External event select for injected group + JEXTSEL: u3, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1, + reserved17: u1, + /// External event select for regular group + EXTSEL: u3, + /// External trigger conversion mode for regular channels + EXTTRIG: u1, + /// Start conversion of injected channels + JSWSTART: u1, + /// Start conversion of regular channels + SWSTART: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Channel 10 sample time selection + SMP10: u3, + /// Channel 11 sample time selection + SMP11: u3, + /// Channel 12 sample time selection + SMP12: u3, + /// Channel 13 sample time selection + SMP13: u3, + /// Channel 14 sample time selection + SMP14: u3, + /// Channel 15 sample time selection + SMP15: u3, + /// Channel 16 sample time selection + SMP16: u3, + /// Channel 17 sample time selection + SMP17: u3, + padding: u8, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Channel 0 sample time selection + SMP0: u3, + /// Channel 1 sample time selection + SMP1: u3, + /// Channel 2 sample time selection + SMP2: u3, + /// Channel 3 sample time selection + SMP3: u3, + /// Channel 4 sample time selection + SMP4: u3, + /// Channel 5 sample time selection + SMP5: u3, + /// Channel 6 sample time selection + SMP6: u3, + /// Channel 7 sample time selection + SMP7: u3, + /// Channel 8 sample time selection + SMP8: u3, + /// Channel 9 sample time selection + SMP9: u3, + padding: u2, + }), + /// injected channel data offset register x + JOFR1: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR2: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR3: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR4: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ13: u5, + /// 14th conversion in regular sequence + SQ14: u5, + /// 15th conversion in regular sequence + SQ15: u5, + /// 16th conversion in regular sequence + SQ16: u5, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ7: u5, + /// 8th conversion in regular sequence + SQ8: u5, + /// 9th conversion in regular sequence + SQ9: u5, + /// 10th conversion in regular sequence + SQ10: u5, + /// 11th conversion in regular sequence + SQ11: u5, + /// 12th conversion in regular sequence + SQ12: u5, + padding: u2, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ1: u5, + /// 2nd conversion in regular sequence + SQ2: u5, + /// 3rd conversion in regular sequence + SQ3: u5, + /// 4th conversion in regular sequence + SQ4: u5, + /// 5th conversion in regular sequence + SQ5: u5, + /// 6th conversion in regular sequence + SQ6: u5, + padding: u2, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + /// ADC2 data + ADC2DATA: u16, + }), + }; + + /// Analog to digital converter + pub const ADC2 = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + padding: u27, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + reserved22: u6, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + padding: u8, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + /// A/D calibration + CAL: u1, + /// Reset calibration + RSTCAL: u1, + reserved8: u4, + /// Direct memory access mode + DMA: u1, + reserved11: u2, + /// Data alignment + ALIGN: u1, + /// External event select for injected group + JEXTSEL: u3, + /// External trigger conversion mode for injected channels + JEXTTRIG: u1, + reserved17: u1, + /// External event select for regular group + EXTSEL: u3, + /// External trigger conversion mode for regular channels + EXTTRIG: u1, + /// Start conversion of injected channels + JSWSTART: u1, + /// Start conversion of regular channels + SWSTART: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Channel 10 sample time selection + SMP10: u3, + /// Channel 11 sample time selection + SMP11: u3, + /// Channel 12 sample time selection + SMP12: u3, + /// Channel 13 sample time selection + SMP13: u3, + /// Channel 14 sample time selection + SMP14: u3, + /// Channel 15 sample time selection + SMP15: u3, + /// Channel 16 sample time selection + SMP16: u3, + /// Channel 17 sample time selection + SMP17: u3, + padding: u8, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Channel 0 sample time selection + SMP0: u3, + /// Channel 1 sample time selection + SMP1: u3, + /// Channel 2 sample time selection + SMP2: u3, + /// Channel 3 sample time selection + SMP3: u3, + /// Channel 4 sample time selection + SMP4: u3, + /// Channel 5 sample time selection + SMP5: u3, + /// Channel 6 sample time selection + SMP6: u3, + /// Channel 7 sample time selection + SMP7: u3, + /// Channel 8 sample time selection + SMP8: u3, + /// Channel 9 sample time selection + SMP9: u3, + padding: u2, + }), + /// injected channel data offset register x + JOFR1: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR2: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR3: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR4: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ13: u5, + /// 14th conversion in regular sequence + SQ14: u5, + /// 15th conversion in regular sequence + SQ15: u5, + /// 16th conversion in regular sequence + SQ16: u5, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ7: u5, + /// 8th conversion in regular sequence + SQ8: u5, + /// 9th conversion in regular sequence + SQ9: u5, + /// 10th conversion in regular sequence + SQ10: u5, + /// 11th conversion in regular sequence + SQ11: u5, + /// 12th conversion in regular sequence + SQ12: u5, + padding: u2, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ1: u5, + /// 2nd conversion in regular sequence + SQ2: u5, + /// 3rd conversion in regular sequence + SQ3: u5, + /// 4th conversion in regular sequence + SQ4: u5, + /// 5th conversion in regular sequence + SQ5: u5, + /// 6th conversion in regular sequence + SQ6: u5, + padding: u2, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + padding: u16, + }), + }; + + /// Controller area network + pub const CAN1 = extern struct { + /// CAN_MCR + CAN_MCR: mmio.Mmio(packed struct(u32) { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved15: u7, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding: u15, + }), + /// CAN_MSR + CAN_MSR: mmio.Mmio(packed struct(u32) { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved8: u3, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding: u20, + }), + /// CAN_TSR + CAN_TSR: mmio.Mmio(packed struct(u32) { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved7: u3, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved15: u3, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved23: u3, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox 0 + TME0: u1, + /// Lowest priority flag for mailbox 1 + TME1: u1, + /// Lowest priority flag for mailbox 2 + TME2: u1, + /// Lowest priority flag for mailbox 0 + LOW0: u1, + /// Lowest priority flag for mailbox 1 + LOW1: u1, + /// Lowest priority flag for mailbox 2 + LOW2: u1, + }), + /// CAN_RF0R + CAN_RF0R: mmio.Mmio(packed struct(u32) { + /// FMP0 + FMP0: u2, + reserved3: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding: u26, + }), + /// CAN_RF1R + CAN_RF1R: mmio.Mmio(packed struct(u32) { + /// FMP1 + FMP1: u2, + reserved3: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding: u26, + }), + /// CAN_IER + CAN_IER: mmio.Mmio(packed struct(u32) { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved8: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved15: u3, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding: u14, + }), + /// CAN_ESR + CAN_ESR: mmio.Mmio(packed struct(u32) { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved4: u1, + /// LEC + LEC: u3, + reserved16: u9, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), + /// CAN_BTR + CAN_BTR: mmio.Mmio(packed struct(u32) { + /// BRP + BRP: u10, + reserved16: u6, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved24: u1, + /// SJW + SJW: u2, + reserved30: u4, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), + reserved384: [352]u8, + /// CAN_TI0R + CAN_TI0R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// CAN_TDT0R + CAN_TDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// CAN_TDL0R + CAN_TDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// CAN_TDH0R + CAN_TDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// CAN_TI1R + CAN_TI1R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// CAN_TDT1R + CAN_TDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// CAN_TDL1R + CAN_TDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// CAN_TDH1R + CAN_TDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// CAN_TI2R + CAN_TI2R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// CAN_TDT2R + CAN_TDT2R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// CAN_TDL2R + CAN_TDL2R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// CAN_TDH2R + CAN_TDH2R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// CAN_RI0R + CAN_RI0R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// CAN_RDT0R + CAN_RDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// CAN_RDL0R + CAN_RDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// CAN_RDH0R + CAN_RDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// CAN_RI1R + CAN_RI1R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// CAN_RDT1R + CAN_RDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// CAN_RDL1R + CAN_RDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// CAN_RDH1R + CAN_RDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + reserved512: [48]u8, + /// CAN_FMR + CAN_FMR: mmio.Mmio(packed struct(u32) { + /// FINIT + FINIT: u1, + padding: u31, + }), + /// CAN_FM1R + CAN_FM1R: mmio.Mmio(packed struct(u32) { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + padding: u18, + }), + reserved524: [4]u8, + /// CAN_FS1R + CAN_FS1R: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + padding: u18, + }), + reserved532: [4]u8, + /// CAN_FFA1R + CAN_FFA1R: mmio.Mmio(packed struct(u32) { + /// Filter FIFO assignment for filter 0 + FFA0: u1, + /// Filter FIFO assignment for filter 1 + FFA1: u1, + /// Filter FIFO assignment for filter 2 + FFA2: u1, + /// Filter FIFO assignment for filter 3 + FFA3: u1, + /// Filter FIFO assignment for filter 4 + FFA4: u1, + /// Filter FIFO assignment for filter 5 + FFA5: u1, + /// Filter FIFO assignment for filter 6 + FFA6: u1, + /// Filter FIFO assignment for filter 7 + FFA7: u1, + /// Filter FIFO assignment for filter 8 + FFA8: u1, + /// Filter FIFO assignment for filter 9 + FFA9: u1, + /// Filter FIFO assignment for filter 10 + FFA10: u1, + /// Filter FIFO assignment for filter 11 + FFA11: u1, + /// Filter FIFO assignment for filter 12 + FFA12: u1, + /// Filter FIFO assignment for filter 13 + FFA13: u1, + padding: u18, + }), + reserved540: [4]u8, + /// CAN_FA1R + CAN_FA1R: mmio.Mmio(packed struct(u32) { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + padding: u18, + }), + reserved576: [32]u8, + /// Filter bank 0 register 1 + F0R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 0 register 2 + F0R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 1 + F1R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 2 + F1R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 1 + F2R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 2 + F2R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 1 + F3R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 2 + F3R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F4R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 2 + F4R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 1 + F5R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 2 + F5R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 1 + F6R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 2 + F6R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 1 + F7R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 2 + F7R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 1 + F8R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 2 + F8R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 1 + F9R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 2 + F9R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 1 + F10R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 2 + F10R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 1 + F11R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 2 + F11R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F12R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 12 register 2 + F12R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 1 + F13R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 2 + F13R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + }; +}; diff --git a/src/chips/STM32F303.json b/src/chips/STM32F303.json new file mode 100644 index 0000000..6468498 --- /dev/null +++ b/src/chips/STM32F303.json @@ -0,0 +1,33184 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "GPIOA": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 671088640, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 603979776, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Lok Key", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + }, + "BRR": { + "description": "Port bit reset register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR0": { + "description": "Port x Reset bit y", + "offset": 0, + "size": 1 + }, + "BR1": { + "description": "Port x Reset bit y", + "offset": 1, + "size": 1 + }, + "BR2": { + "description": "Port x Reset bit y", + "offset": 2, + "size": 1 + }, + "BR3": { + "description": "Port x Reset bit y", + "offset": 3, + "size": 1 + }, + "BR4": { + "description": "Port x Reset bit y", + "offset": 4, + "size": 1 + }, + "BR5": { + "description": "Port x Reset bit y", + "offset": 5, + "size": 1 + }, + "BR6": { + "description": "Port x Reset bit y", + "offset": 6, + "size": 1 + }, + "BR7": { + "description": "Port x Reset bit y", + "offset": 7, + "size": 1 + }, + "BR8": { + "description": "Port x Reset bit y", + "offset": 8, + "size": 1 + }, + "BR9": { + "description": "Port x Reset bit y", + "offset": 9, + "size": 1 + }, + "BR10": { + "description": "Port x Reset bit y", + "offset": 10, + "size": 1 + }, + "BR11": { + "description": "Port x Reset bit y", + "offset": 11, + "size": 1 + }, + "BR12": { + "description": "Port x Reset bit y", + "offset": 12, + "size": 1 + }, + "BR13": { + "description": "Port x Reset bit y", + "offset": 13, + "size": 1 + }, + "BR14": { + "description": "Port x Reset bit y", + "offset": 14, + "size": 1 + }, + "BR15": { + "description": "Port x Reset bit y", + "offset": 15, + "size": 1 + } + } + } + } + } + } + }, + "GPIOB": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bit\n 15", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bit\n 14", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bit\n 13", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bit\n 12", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bit\n 11", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bit\n 10", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bit 9", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bit 8", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bit 7", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bit 6", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bit 5", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bit 4", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bit 3", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bit 2", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bit 1", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bit 0", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Lok Key", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + }, + "BRR": { + "description": "Port bit reset register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR0": { + "description": "Port x Reset bit y", + "offset": 0, + "size": 1 + }, + "BR1": { + "description": "Port x Reset bit y", + "offset": 1, + "size": 1 + }, + "BR2": { + "description": "Port x Reset bit y", + "offset": 2, + "size": 1 + }, + "BR3": { + "description": "Port x Reset bit y", + "offset": 3, + "size": 1 + }, + "BR4": { + "description": "Port x Reset bit y", + "offset": 4, + "size": 1 + }, + "BR5": { + "description": "Port x Reset bit y", + "offset": 5, + "size": 1 + }, + "BR6": { + "description": "Port x Reset bit y", + "offset": 6, + "size": 1 + }, + "BR7": { + "description": "Port x Reset bit y", + "offset": 7, + "size": 1 + }, + "BR8": { + "description": "Port x Reset bit y", + "offset": 8, + "size": 1 + }, + "BR9": { + "description": "Port x Reset bit y", + "offset": 9, + "size": 1 + }, + "BR10": { + "description": "Port x Reset bit y", + "offset": 10, + "size": 1 + }, + "BR11": { + "description": "Port x Reset bit y", + "offset": 11, + "size": 1 + }, + "BR12": { + "description": "Port x Reset bit y", + "offset": 12, + "size": 1 + }, + "BR13": { + "description": "Port x Reset bit y", + "offset": 13, + "size": 1 + }, + "BR14": { + "description": "Port x Reset bit y", + "offset": 14, + "size": 1 + }, + "BR15": { + "description": "Port x Reset bit y", + "offset": 15, + "size": 1 + } + } + } + } + } + } + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "children": { + "registers": { + "ACTRL": { + "description": "Auxiliary control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DISMCYCINT": { + "description": "DISMCYCINT", + "offset": 0, + "size": 1 + }, + "DISDEFWBUF": { + "description": "DISDEFWBUF", + "offset": 1, + "size": 1 + }, + "DISFOLD": { + "description": "DISFOLD", + "offset": 2, + "size": 1 + }, + "DISFPCA": { + "description": "DISFPCA", + "offset": 8, + "size": 1 + }, + "DISOOFP": { + "description": "DISOOFP", + "offset": 9, + "size": 1 + } + } + } + } + } + } + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "children": { + "registers": { + "CPACR": { + "description": "Coprocessor access control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CP": { + "description": "CP", + "offset": 20, + "size": 4 + } + } + } + } + } + } + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "children": { + "registers": { + "STIR": { + "description": "Software trigger interrupt\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTID": { + "description": "Software generated interrupt\n ID", + "offset": 0, + "size": 9 + } + } + } + } + } + } + }, + "SCB": { + "description": "System control block", + "children": { + "registers": { + "CPUID": { + "description": "CPUID base register", + "offset": 0, + "size": 32, + "reset_value": 1091551809, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Revision": { + "description": "Revision number", + "offset": 0, + "size": 4 + }, + "PartNo": { + "description": "Part number of the\n processor", + "offset": 4, + "size": 12 + }, + "Constant": { + "description": "Reads as 0xF", + "offset": 16, + "size": 4 + }, + "Variant": { + "description": "Variant number", + "offset": 20, + "size": 4 + }, + "Implementer": { + "description": "Implementer code", + "offset": 24, + "size": 8 + } + } + } + }, + "ICSR": { + "description": "Interrupt control and state\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTACTIVE": { + "description": "Active vector", + "offset": 0, + "size": 9 + }, + "RETTOBASE": { + "description": "Return to base level", + "offset": 11, + "size": 1 + }, + "VECTPENDING": { + "description": "Pending vector", + "offset": 12, + "size": 7 + }, + "ISRPENDING": { + "description": "Interrupt pending flag", + "offset": 22, + "size": 1 + }, + "PENDSTCLR": { + "description": "SysTick exception clear-pending\n bit", + "offset": 25, + "size": 1 + }, + "PENDSTSET": { + "description": "SysTick exception set-pending\n bit", + "offset": 26, + "size": 1 + }, + "PENDSVCLR": { + "description": "PendSV clear-pending bit", + "offset": 27, + "size": 1 + }, + "PENDSVSET": { + "description": "PendSV set-pending bit", + "offset": 28, + "size": 1 + }, + "NMIPENDSET": { + "description": "NMI set-pending bit.", + "offset": 31, + "size": 1 + } + } + } + }, + "VTOR": { + "description": "Vector table offset register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TBLOFF": { + "description": "Vector table base offset\n field", + "offset": 9, + "size": 21 + } + } + } + }, + "AIRCR": { + "description": "Application interrupt and reset control\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTRESET": { + "description": "VECTRESET", + "offset": 0, + "size": 1 + }, + "VECTCLRACTIVE": { + "description": "VECTCLRACTIVE", + "offset": 1, + "size": 1 + }, + "SYSRESETREQ": { + "description": "SYSRESETREQ", + "offset": 2, + "size": 1 + }, + "PRIGROUP": { + "description": "PRIGROUP", + "offset": 8, + "size": 3 + }, + "ENDIANESS": { + "description": "ENDIANESS", + "offset": 15, + "size": 1 + }, + "VECTKEYSTAT": { + "description": "Register key", + "offset": 16, + "size": 16 + } + } + } + }, + "SCR": { + "description": "System control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEPONEXIT": { + "description": "SLEEPONEXIT", + "offset": 1, + "size": 1 + }, + "SLEEPDEEP": { + "description": "SLEEPDEEP", + "offset": 2, + "size": 1 + }, + "SEVEONPEND": { + "description": "Send Event on Pending bit", + "offset": 4, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Configuration and control\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONBASETHRDENA": { + "description": "Configures how the processor enters\n Thread mode", + "offset": 0, + "size": 1 + }, + "USERSETMPEND": { + "description": "USERSETMPEND", + "offset": 1, + "size": 1 + }, + "UNALIGN__TRP": { + "description": "UNALIGN_ TRP", + "offset": 3, + "size": 1 + }, + "DIV_0_TRP": { + "description": "DIV_0_TRP", + "offset": 4, + "size": 1 + }, + "BFHFNMIGN": { + "description": "BFHFNMIGN", + "offset": 8, + "size": 1 + }, + "STKALIGN": { + "description": "STKALIGN", + "offset": 9, + "size": 1 + } + } + } + }, + "SHPR1": { + "description": "System handler priority\n registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_4": { + "description": "Priority of system handler\n 4", + "offset": 0, + "size": 8 + }, + "PRI_5": { + "description": "Priority of system handler\n 5", + "offset": 8, + "size": 8 + }, + "PRI_6": { + "description": "Priority of system handler\n 6", + "offset": 16, + "size": 8 + } + } + } + }, + "SHPR2": { + "description": "System handler priority\n registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_11": { + "description": "Priority of system handler\n 11", + "offset": 24, + "size": 8 + } + } + } + }, + "SHPR3": { + "description": "System handler priority\n registers", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_14": { + "description": "Priority of system handler\n 14", + "offset": 16, + "size": 8 + }, + "PRI_15": { + "description": "Priority of system handler\n 15", + "offset": 24, + "size": 8 + } + } + } + }, + "SHCRS": { + "description": "System handler control and state\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMFAULTACT": { + "description": "Memory management fault exception active\n bit", + "offset": 0, + "size": 1 + }, + "BUSFAULTACT": { + "description": "Bus fault exception active\n bit", + "offset": 1, + "size": 1 + }, + "USGFAULTACT": { + "description": "Usage fault exception active\n bit", + "offset": 3, + "size": 1 + }, + "SVCALLACT": { + "description": "SVC call active bit", + "offset": 7, + "size": 1 + }, + "MONITORACT": { + "description": "Debug monitor active bit", + "offset": 8, + "size": 1 + }, + "PENDSVACT": { + "description": "PendSV exception active\n bit", + "offset": 10, + "size": 1 + }, + "SYSTICKACT": { + "description": "SysTick exception active\n bit", + "offset": 11, + "size": 1 + }, + "USGFAULTPENDED": { + "description": "Usage fault exception pending\n bit", + "offset": 12, + "size": 1 + }, + "MEMFAULTPENDED": { + "description": "Memory management fault exception\n pending bit", + "offset": 13, + "size": 1 + }, + "BUSFAULTPENDED": { + "description": "Bus fault exception pending\n bit", + "offset": 14, + "size": 1 + }, + "SVCALLPENDED": { + "description": "SVC call pending bit", + "offset": 15, + "size": 1 + }, + "MEMFAULTENA": { + "description": "Memory management fault enable\n bit", + "offset": 16, + "size": 1 + }, + "BUSFAULTENA": { + "description": "Bus fault enable bit", + "offset": 17, + "size": 1 + }, + "USGFAULTENA": { + "description": "Usage fault enable bit", + "offset": 18, + "size": 1 + } + } + } + }, + "CFSR_UFSR_BFSR_MMFSR": { + "description": "Configurable fault status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IACCVIOL": { + "description": "Instruction access violation\n flag", + "offset": 1, + "size": 1 + }, + "MUNSTKERR": { + "description": "Memory manager fault on unstacking for a\n return from exception", + "offset": 3, + "size": 1 + }, + "MSTKERR": { + "description": "Memory manager fault on stacking for\n exception entry.", + "offset": 4, + "size": 1 + }, + "MLSPERR": { + "description": "MLSPERR", + "offset": 5, + "size": 1 + }, + "MMARVALID": { + "description": "Memory Management Fault Address Register\n (MMAR) valid flag", + "offset": 7, + "size": 1 + }, + "IBUSERR": { + "description": "Instruction bus error", + "offset": 8, + "size": 1 + }, + "PRECISERR": { + "description": "Precise data bus error", + "offset": 9, + "size": 1 + }, + "IMPRECISERR": { + "description": "Imprecise data bus error", + "offset": 10, + "size": 1 + }, + "UNSTKERR": { + "description": "Bus fault on unstacking for a return\n from exception", + "offset": 11, + "size": 1 + }, + "STKERR": { + "description": "Bus fault on stacking for exception\n entry", + "offset": 12, + "size": 1 + }, + "LSPERR": { + "description": "Bus fault on floating-point lazy state\n preservation", + "offset": 13, + "size": 1 + }, + "BFARVALID": { + "description": "Bus Fault Address Register (BFAR) valid\n flag", + "offset": 15, + "size": 1 + }, + "UNDEFINSTR": { + "description": "Undefined instruction usage\n fault", + "offset": 16, + "size": 1 + }, + "INVSTATE": { + "description": "Invalid state usage fault", + "offset": 17, + "size": 1 + }, + "INVPC": { + "description": "Invalid PC load usage\n fault", + "offset": 18, + "size": 1 + }, + "NOCP": { + "description": "No coprocessor usage\n fault.", + "offset": 19, + "size": 1 + }, + "UNALIGNED": { + "description": "Unaligned access usage\n fault", + "offset": 24, + "size": 1 + }, + "DIVBYZERO": { + "description": "Divide by zero usage fault", + "offset": 25, + "size": 1 + } + } + } + }, + "HFSR": { + "description": "Hard fault status register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTTBL": { + "description": "Vector table hard fault", + "offset": 1, + "size": 1 + }, + "FORCED": { + "description": "Forced hard fault", + "offset": 30, + "size": 1 + }, + "DEBUG_VT": { + "description": "Reserved for Debug use", + "offset": 31, + "size": 1 + } + } + } + }, + "MMFAR": { + "description": "Memory management fault address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMFAR": { + "description": "Memory management fault\n address", + "offset": 0, + "size": 32 + } + } + } + }, + "BFAR": { + "description": "Bus fault address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BFAR": { + "description": "Bus fault address", + "offset": 0, + "size": 32 + } + } + } + }, + "AFSR": { + "description": "Auxiliary fault status\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IMPDEF": { + "description": "Implementation defined", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "STK": { + "description": "SysTick timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "TICKINT": { + "description": "SysTick exception request\n enable", + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "description": "Clock source selection", + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "description": "COUNTFLAG", + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick reload value register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RELOAD": { + "description": "RELOAD value", + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick current value register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CURRENT": { + "description": "Current counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick calibration value\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TENMS": { + "description": "Calibration value", + "offset": 0, + "size": 24 + }, + "SKEW": { + "description": "SKEW flag: Indicates whether the TENMS\n value is exact", + "offset": 30, + "size": 1 + }, + "NOREF": { + "description": "NOREF flag. Reads as zero", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "MPU": { + "description": "Memory protection unit", + "children": { + "registers": { + "MPU_TYPER": { + "description": "MPU type register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEPARATE": { + "description": "Separate flag", + "offset": 0, + "size": 1 + }, + "DREGION": { + "description": "Number of MPU data regions", + "offset": 8, + "size": 8 + }, + "IREGION": { + "description": "Number of MPU instruction\n regions", + "offset": 16, + "size": 8 + } + } + } + }, + "MPU_CTRL": { + "description": "MPU control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ENABLE": { + "description": "Enables the MPU", + "offset": 0, + "size": 1 + }, + "HFNMIENA": { + "description": "Enables the operation of MPU during hard\n fault", + "offset": 1, + "size": 1 + }, + "PRIVDEFENA": { + "description": "Enable priviliged software access to\n default memory map", + "offset": 2, + "size": 1 + } + } + } + }, + "MPU_RNR": { + "description": "MPU region number register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region", + "offset": 0, + "size": 8 + } + } + } + }, + "MPU_RBAR": { + "description": "MPU region base address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region field", + "offset": 0, + "size": 4 + }, + "VALID": { + "description": "MPU region number valid", + "offset": 4, + "size": 1 + }, + "ADDR": { + "description": "Region base address field", + "offset": 5, + "size": 27 + } + } + } + }, + "MPU_RASR": { + "description": "MPU region attribute and size\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Region enable bit.", + "offset": 0, + "size": 1 + }, + "SIZE": { + "description": "Size of the MPU protection\n region", + "offset": 1, + "size": 5 + }, + "SRD": { + "description": "Subregion disable bits", + "offset": 8, + "size": 8 + }, + "B": { + "description": "memory attribute", + "offset": 16, + "size": 1 + }, + "C": { + "description": "memory attribute", + "offset": 17, + "size": 1 + }, + "S": { + "description": "Shareable memory attribute", + "offset": 18, + "size": 1 + }, + "TEX": { + "description": "memory attribute", + "offset": 19, + "size": 3 + }, + "AP": { + "description": "Access permission", + "offset": 24, + "size": 3 + }, + "XN": { + "description": "Instruction access disable\n bit", + "offset": 28, + "size": 1 + } + } + } + } + } + } + }, + "TSC": { + "description": "Touch sensing controller", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTPH": { + "description": "Charge transfer pulse high", + "offset": 28, + "size": 4 + }, + "CTPL": { + "description": "Charge transfer pulse low", + "offset": 24, + "size": 4 + }, + "SSD": { + "description": "Spread spectrum deviation", + "offset": 17, + "size": 7 + }, + "SSE": { + "description": "Spread spectrum enable", + "offset": 16, + "size": 1 + }, + "SSPSC": { + "description": "Spread spectrum prescaler", + "offset": 15, + "size": 1 + }, + "PGPSC": { + "description": "pulse generator prescaler", + "offset": 12, + "size": 3 + }, + "MCV": { + "description": "Max count value", + "offset": 5, + "size": 3 + }, + "IODEF": { + "description": "I/O Default mode", + "offset": 4, + "size": 1 + }, + "SYNCPOL": { + "description": "Synchronization pin\n polarity", + "offset": 3, + "size": 1 + }, + "AM": { + "description": "Acquisition mode", + "offset": 2, + "size": 1 + }, + "START": { + "description": "Start a new acquisition", + "offset": 1, + "size": 1 + }, + "TSCE": { + "description": "Touch sensing controller\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCEIE": { + "description": "Max count error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EOAIE": { + "description": "End of acquisition interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "interrupt clear register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCEIC": { + "description": "Max count error interrupt\n clear", + "offset": 1, + "size": 1 + }, + "EOAIC": { + "description": "End of acquisition interrupt\n clear", + "offset": 0, + "size": 1 + } + } + } + }, + "ISR": { + "description": "interrupt status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCEF": { + "description": "Max count error flag", + "offset": 1, + "size": 1 + }, + "EOAF": { + "description": "End of acquisition flag", + "offset": 0, + "size": 1 + } + } + } + }, + "IOHCR": { + "description": "I/O hysteresis control\n register", + "offset": 16, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "G1_IO1": { + "description": "G1_IO1 Schmitt trigger hysteresis\n mode", + "offset": 0, + "size": 1 + }, + "G1_IO2": { + "description": "G1_IO2 Schmitt trigger hysteresis\n mode", + "offset": 1, + "size": 1 + }, + "G1_IO3": { + "description": "G1_IO3 Schmitt trigger hysteresis\n mode", + "offset": 2, + "size": 1 + }, + "G1_IO4": { + "description": "G1_IO4 Schmitt trigger hysteresis\n mode", + "offset": 3, + "size": 1 + }, + "G2_IO1": { + "description": "G2_IO1 Schmitt trigger hysteresis\n mode", + "offset": 4, + "size": 1 + }, + "G2_IO2": { + "description": "G2_IO2 Schmitt trigger hysteresis\n mode", + "offset": 5, + "size": 1 + }, + "G2_IO3": { + "description": "G2_IO3 Schmitt trigger hysteresis\n mode", + "offset": 6, + "size": 1 + }, + "G2_IO4": { + "description": "G2_IO4 Schmitt trigger hysteresis\n mode", + "offset": 7, + "size": 1 + }, + "G3_IO1": { + "description": "G3_IO1 Schmitt trigger hysteresis\n mode", + "offset": 8, + "size": 1 + }, + "G3_IO2": { + "description": "G3_IO2 Schmitt trigger hysteresis\n mode", + "offset": 9, + "size": 1 + }, + "G3_IO3": { + "description": "G3_IO3 Schmitt trigger hysteresis\n mode", + "offset": 10, + "size": 1 + }, + "G3_IO4": { + "description": "G3_IO4 Schmitt trigger hysteresis\n mode", + "offset": 11, + "size": 1 + }, + "G4_IO1": { + "description": "G4_IO1 Schmitt trigger hysteresis\n mode", + "offset": 12, + "size": 1 + }, + "G4_IO2": { + "description": "G4_IO2 Schmitt trigger hysteresis\n mode", + "offset": 13, + "size": 1 + }, + "G4_IO3": { + "description": "G4_IO3 Schmitt trigger hysteresis\n mode", + "offset": 14, + "size": 1 + }, + "G4_IO4": { + "description": "G4_IO4 Schmitt trigger hysteresis\n mode", + "offset": 15, + "size": 1 + }, + "G5_IO1": { + "description": "G5_IO1 Schmitt trigger hysteresis\n mode", + "offset": 16, + "size": 1 + }, + "G5_IO2": { + "description": "G5_IO2 Schmitt trigger hysteresis\n mode", + "offset": 17, + "size": 1 + }, + "G5_IO3": { + "description": "G5_IO3 Schmitt trigger hysteresis\n mode", + "offset": 18, + "size": 1 + }, + "G5_IO4": { + "description": "G5_IO4 Schmitt trigger hysteresis\n mode", + "offset": 19, + "size": 1 + }, + "G6_IO1": { + "description": "G6_IO1 Schmitt trigger hysteresis\n mode", + "offset": 20, + "size": 1 + }, + "G6_IO2": { + "description": "G6_IO2 Schmitt trigger hysteresis\n mode", + "offset": 21, + "size": 1 + }, + "G6_IO3": { + "description": "G6_IO3 Schmitt trigger hysteresis\n mode", + "offset": 22, + "size": 1 + }, + "G6_IO4": { + "description": "G6_IO4 Schmitt trigger hysteresis\n mode", + "offset": 23, + "size": 1 + }, + "G7_IO1": { + "description": "G7_IO1 Schmitt trigger hysteresis\n mode", + "offset": 24, + "size": 1 + }, + "G7_IO2": { + "description": "G7_IO2 Schmitt trigger hysteresis\n mode", + "offset": 25, + "size": 1 + }, + "G7_IO3": { + "description": "G7_IO3 Schmitt trigger hysteresis\n mode", + "offset": 26, + "size": 1 + }, + "G7_IO4": { + "description": "G7_IO4 Schmitt trigger hysteresis\n mode", + "offset": 27, + "size": 1 + }, + "G8_IO1": { + "description": "G8_IO1 Schmitt trigger hysteresis\n mode", + "offset": 28, + "size": 1 + }, + "G8_IO2": { + "description": "G8_IO2 Schmitt trigger hysteresis\n mode", + "offset": 29, + "size": 1 + }, + "G8_IO3": { + "description": "G8_IO3 Schmitt trigger hysteresis\n mode", + "offset": 30, + "size": 1 + }, + "G8_IO4": { + "description": "G8_IO4 Schmitt trigger hysteresis\n mode", + "offset": 31, + "size": 1 + } + } + } + }, + "IOASCR": { + "description": "I/O analog switch control\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "G1_IO1": { + "description": "G1_IO1 analog switch\n enable", + "offset": 0, + "size": 1 + }, + "G1_IO2": { + "description": "G1_IO2 analog switch\n enable", + "offset": 1, + "size": 1 + }, + "G1_IO3": { + "description": "G1_IO3 analog switch\n enable", + "offset": 2, + "size": 1 + }, + "G1_IO4": { + "description": "G1_IO4 analog switch\n enable", + "offset": 3, + "size": 1 + }, + "G2_IO1": { + "description": "G2_IO1 analog switch\n enable", + "offset": 4, + "size": 1 + }, + "G2_IO2": { + "description": "G2_IO2 analog switch\n enable", + "offset": 5, + "size": 1 + }, + "G2_IO3": { + "description": "G2_IO3 analog switch\n enable", + "offset": 6, + "size": 1 + }, + "G2_IO4": { + "description": "G2_IO4 analog switch\n enable", + "offset": 7, + "size": 1 + }, + "G3_IO1": { + "description": "G3_IO1 analog switch\n enable", + "offset": 8, + "size": 1 + }, + "G3_IO2": { + "description": "G3_IO2 analog switch\n enable", + "offset": 9, + "size": 1 + }, + "G3_IO3": { + "description": "G3_IO3 analog switch\n enable", + "offset": 10, + "size": 1 + }, + "G3_IO4": { + "description": "G3_IO4 analog switch\n enable", + "offset": 11, + "size": 1 + }, + "G4_IO1": { + "description": "G4_IO1 analog switch\n enable", + "offset": 12, + "size": 1 + }, + "G4_IO2": { + "description": "G4_IO2 analog switch\n enable", + "offset": 13, + "size": 1 + }, + "G4_IO3": { + "description": "G4_IO3 analog switch\n enable", + "offset": 14, + "size": 1 + }, + "G4_IO4": { + "description": "G4_IO4 analog switch\n enable", + "offset": 15, + "size": 1 + }, + "G5_IO1": { + "description": "G5_IO1 analog switch\n enable", + "offset": 16, + "size": 1 + }, + "G5_IO2": { + "description": "G5_IO2 analog switch\n enable", + "offset": 17, + "size": 1 + }, + "G5_IO3": { + "description": "G5_IO3 analog switch\n enable", + "offset": 18, + "size": 1 + }, + "G5_IO4": { + "description": "G5_IO4 analog switch\n enable", + "offset": 19, + "size": 1 + }, + "G6_IO1": { + "description": "G6_IO1 analog switch\n enable", + "offset": 20, + "size": 1 + }, + "G6_IO2": { + "description": "G6_IO2 analog switch\n enable", + "offset": 21, + "size": 1 + }, + "G6_IO3": { + "description": "G6_IO3 analog switch\n enable", + "offset": 22, + "size": 1 + }, + "G6_IO4": { + "description": "G6_IO4 analog switch\n enable", + "offset": 23, + "size": 1 + }, + "G7_IO1": { + "description": "G7_IO1 analog switch\n enable", + "offset": 24, + "size": 1 + }, + "G7_IO2": { + "description": "G7_IO2 analog switch\n enable", + "offset": 25, + "size": 1 + }, + "G7_IO3": { + "description": "G7_IO3 analog switch\n enable", + "offset": 26, + "size": 1 + }, + "G7_IO4": { + "description": "G7_IO4 analog switch\n enable", + "offset": 27, + "size": 1 + }, + "G8_IO1": { + "description": "G8_IO1 analog switch\n enable", + "offset": 28, + "size": 1 + }, + "G8_IO2": { + "description": "G8_IO2 analog switch\n enable", + "offset": 29, + "size": 1 + }, + "G8_IO3": { + "description": "G8_IO3 analog switch\n enable", + "offset": 30, + "size": 1 + }, + "G8_IO4": { + "description": "G8_IO4 analog switch\n enable", + "offset": 31, + "size": 1 + } + } + } + }, + "IOSCR": { + "description": "I/O sampling control register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "G1_IO1": { + "description": "G1_IO1 sampling mode", + "offset": 0, + "size": 1 + }, + "G1_IO2": { + "description": "G1_IO2 sampling mode", + "offset": 1, + "size": 1 + }, + "G1_IO3": { + "description": "G1_IO3 sampling mode", + "offset": 2, + "size": 1 + }, + "G1_IO4": { + "description": "G1_IO4 sampling mode", + "offset": 3, + "size": 1 + }, + "G2_IO1": { + "description": "G2_IO1 sampling mode", + "offset": 4, + "size": 1 + }, + "G2_IO2": { + "description": "G2_IO2 sampling mode", + "offset": 5, + "size": 1 + }, + "G2_IO3": { + "description": "G2_IO3 sampling mode", + "offset": 6, + "size": 1 + }, + "G2_IO4": { + "description": "G2_IO4 sampling mode", + "offset": 7, + "size": 1 + }, + "G3_IO1": { + "description": "G3_IO1 sampling mode", + "offset": 8, + "size": 1 + }, + "G3_IO2": { + "description": "G3_IO2 sampling mode", + "offset": 9, + "size": 1 + }, + "G3_IO3": { + "description": "G3_IO3 sampling mode", + "offset": 10, + "size": 1 + }, + "G3_IO4": { + "description": "G3_IO4 sampling mode", + "offset": 11, + "size": 1 + }, + "G4_IO1": { + "description": "G4_IO1 sampling mode", + "offset": 12, + "size": 1 + }, + "G4_IO2": { + "description": "G4_IO2 sampling mode", + "offset": 13, + "size": 1 + }, + "G4_IO3": { + "description": "G4_IO3 sampling mode", + "offset": 14, + "size": 1 + }, + "G4_IO4": { + "description": "G4_IO4 sampling mode", + "offset": 15, + "size": 1 + }, + "G5_IO1": { + "description": "G5_IO1 sampling mode", + "offset": 16, + "size": 1 + }, + "G5_IO2": { + "description": "G5_IO2 sampling mode", + "offset": 17, + "size": 1 + }, + "G5_IO3": { + "description": "G5_IO3 sampling mode", + "offset": 18, + "size": 1 + }, + "G5_IO4": { + "description": "G5_IO4 sampling mode", + "offset": 19, + "size": 1 + }, + "G6_IO1": { + "description": "G6_IO1 sampling mode", + "offset": 20, + "size": 1 + }, + "G6_IO2": { + "description": "G6_IO2 sampling mode", + "offset": 21, + "size": 1 + }, + "G6_IO3": { + "description": "G6_IO3 sampling mode", + "offset": 22, + "size": 1 + }, + "G6_IO4": { + "description": "G6_IO4 sampling mode", + "offset": 23, + "size": 1 + }, + "G7_IO1": { + "description": "G7_IO1 sampling mode", + "offset": 24, + "size": 1 + }, + "G7_IO2": { + "description": "G7_IO2 sampling mode", + "offset": 25, + "size": 1 + }, + "G7_IO3": { + "description": "G7_IO3 sampling mode", + "offset": 26, + "size": 1 + }, + "G7_IO4": { + "description": "G7_IO4 sampling mode", + "offset": 27, + "size": 1 + }, + "G8_IO1": { + "description": "G8_IO1 sampling mode", + "offset": 28, + "size": 1 + }, + "G8_IO2": { + "description": "G8_IO2 sampling mode", + "offset": 29, + "size": 1 + }, + "G8_IO3": { + "description": "G8_IO3 sampling mode", + "offset": 30, + "size": 1 + }, + "G8_IO4": { + "description": "G8_IO4 sampling mode", + "offset": 31, + "size": 1 + } + } + } + }, + "IOCCR": { + "description": "I/O channel control register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "G1_IO1": { + "description": "G1_IO1 channel mode", + "offset": 0, + "size": 1 + }, + "G1_IO2": { + "description": "G1_IO2 channel mode", + "offset": 1, + "size": 1 + }, + "G1_IO3": { + "description": "G1_IO3 channel mode", + "offset": 2, + "size": 1 + }, + "G1_IO4": { + "description": "G1_IO4 channel mode", + "offset": 3, + "size": 1 + }, + "G2_IO1": { + "description": "G2_IO1 channel mode", + "offset": 4, + "size": 1 + }, + "G2_IO2": { + "description": "G2_IO2 channel mode", + "offset": 5, + "size": 1 + }, + "G2_IO3": { + "description": "G2_IO3 channel mode", + "offset": 6, + "size": 1 + }, + "G2_IO4": { + "description": "G2_IO4 channel mode", + "offset": 7, + "size": 1 + }, + "G3_IO1": { + "description": "G3_IO1 channel mode", + "offset": 8, + "size": 1 + }, + "G3_IO2": { + "description": "G3_IO2 channel mode", + "offset": 9, + "size": 1 + }, + "G3_IO3": { + "description": "G3_IO3 channel mode", + "offset": 10, + "size": 1 + }, + "G3_IO4": { + "description": "G3_IO4 channel mode", + "offset": 11, + "size": 1 + }, + "G4_IO1": { + "description": "G4_IO1 channel mode", + "offset": 12, + "size": 1 + }, + "G4_IO2": { + "description": "G4_IO2 channel mode", + "offset": 13, + "size": 1 + }, + "G4_IO3": { + "description": "G4_IO3 channel mode", + "offset": 14, + "size": 1 + }, + "G4_IO4": { + "description": "G4_IO4 channel mode", + "offset": 15, + "size": 1 + }, + "G5_IO1": { + "description": "G5_IO1 channel mode", + "offset": 16, + "size": 1 + }, + "G5_IO2": { + "description": "G5_IO2 channel mode", + "offset": 17, + "size": 1 + }, + "G5_IO3": { + "description": "G5_IO3 channel mode", + "offset": 18, + "size": 1 + }, + "G5_IO4": { + "description": "G5_IO4 channel mode", + "offset": 19, + "size": 1 + }, + "G6_IO1": { + "description": "G6_IO1 channel mode", + "offset": 20, + "size": 1 + }, + "G6_IO2": { + "description": "G6_IO2 channel mode", + "offset": 21, + "size": 1 + }, + "G6_IO3": { + "description": "G6_IO3 channel mode", + "offset": 22, + "size": 1 + }, + "G6_IO4": { + "description": "G6_IO4 channel mode", + "offset": 23, + "size": 1 + }, + "G7_IO1": { + "description": "G7_IO1 channel mode", + "offset": 24, + "size": 1 + }, + "G7_IO2": { + "description": "G7_IO2 channel mode", + "offset": 25, + "size": 1 + }, + "G7_IO3": { + "description": "G7_IO3 channel mode", + "offset": 26, + "size": 1 + }, + "G7_IO4": { + "description": "G7_IO4 channel mode", + "offset": 27, + "size": 1 + }, + "G8_IO1": { + "description": "G8_IO1 channel mode", + "offset": 28, + "size": 1 + }, + "G8_IO2": { + "description": "G8_IO2 channel mode", + "offset": 29, + "size": 1 + }, + "G8_IO3": { + "description": "G8_IO3 channel mode", + "offset": 30, + "size": 1 + }, + "G8_IO4": { + "description": "G8_IO4 channel mode", + "offset": 31, + "size": 1 + } + } + } + }, + "IOGCSR": { + "description": "I/O group control status\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "G8S": { + "description": "Analog I/O group x status", + "offset": 23, + "size": 1 + }, + "G7S": { + "description": "Analog I/O group x status", + "offset": 22, + "size": 1 + }, + "G6S": { + "description": "Analog I/O group x status", + "offset": 21, + "size": 1, + "access": "read-only" + }, + "G5S": { + "description": "Analog I/O group x status", + "offset": 20, + "size": 1, + "access": "read-only" + }, + "G4S": { + "description": "Analog I/O group x status", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "G3S": { + "description": "Analog I/O group x status", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "G2S": { + "description": "Analog I/O group x status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "G1S": { + "description": "Analog I/O group x status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "G8E": { + "description": "Analog I/O group x enable", + "offset": 7, + "size": 1 + }, + "G7E": { + "description": "Analog I/O group x enable", + "offset": 6, + "size": 1 + }, + "G6E": { + "description": "Analog I/O group x enable", + "offset": 5, + "size": 1 + }, + "G5E": { + "description": "Analog I/O group x enable", + "offset": 4, + "size": 1 + }, + "G4E": { + "description": "Analog I/O group x enable", + "offset": 3, + "size": 1 + }, + "G3E": { + "description": "Analog I/O group x enable", + "offset": 2, + "size": 1 + }, + "G2E": { + "description": "Analog I/O group x enable", + "offset": 1, + "size": 1 + }, + "G1E": { + "description": "Analog I/O group x enable", + "offset": 0, + "size": 1 + } + } + } + }, + "IOG1CR": { + "description": "I/O group x counter register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG2CR": { + "description": "I/O group x counter register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG3CR": { + "description": "I/O group x counter register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG4CR": { + "description": "I/O group x counter register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG5CR": { + "description": "I/O group x counter register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG6CR": { + "description": "I/O group x counter register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG7CR": { + "description": "I/O group x counter register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + }, + "IOG8CR": { + "description": "I/O group x counter register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNT": { + "description": "Counter value", + "offset": 0, + "size": 14 + } + } + } + } + } + } + }, + "CRC": { + "description": "cyclic redundancy check calculation\n unit", + "children": { + "registers": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data register bits", + "offset": 0, + "size": 32 + } + } + } + }, + "IDR": { + "description": "Independent data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IDR": { + "description": "General-purpose 8-bit data register\n bits", + "offset": 0, + "size": 8 + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RESET": { + "description": "reset bit", + "offset": 0, + "size": 1 + }, + "POLYSIZE": { + "description": "Polynomial size", + "offset": 3, + "size": 2 + }, + "REV_IN": { + "description": "Reverse input data", + "offset": 5, + "size": 2 + }, + "REV_OUT": { + "description": "Reverse output data", + "offset": 7, + "size": 1 + } + } + } + }, + "INIT": { + "description": "Initial CRC value", + "offset": 16, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "INIT": { + "description": "Programmable initial CRC\n value", + "offset": 0, + "size": 32 + } + } + } + }, + "POL": { + "description": "CRC polynomial", + "offset": 20, + "size": 32, + "reset_value": 79764919, + "reset_mask": 4294967295, + "children": { + "fields": { + "POL": { + "description": "Programmable polynomial", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "Flash": { + "description": "Flash", + "children": { + "registers": { + "ACR": { + "description": "Flash access control register", + "offset": 0, + "size": 32, + "reset_value": 48, + "reset_mask": 4294967295, + "children": { + "fields": { + "LATENCY": { + "description": "LATENCY", + "offset": 0, + "size": 3 + }, + "PRFTBE": { + "description": "PRFTBE", + "offset": 4, + "size": 1 + }, + "PRFTBS": { + "description": "PRFTBS", + "offset": 5, + "size": 1, + "access": "read-only" + } + } + } + }, + "KEYR": { + "description": "Flash key register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "FKEYR": { + "description": "Flash Key", + "offset": 0, + "size": 32 + } + } + } + }, + "OPTKEYR": { + "description": "Flash option key register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "OPTKEYR": { + "description": "Option byte key", + "offset": 0, + "size": 32 + } + } + } + }, + "SR": { + "description": "Flash status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOP": { + "description": "End of operation", + "offset": 5, + "size": 1 + }, + "WRPRT": { + "description": "Write protection error", + "offset": 4, + "size": 1 + }, + "PGERR": { + "description": "Programming error", + "offset": 2, + "size": 1 + }, + "BSY": { + "description": "Busy", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "CR": { + "description": "Flash control register", + "offset": 16, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "FORCE_OPTLOAD": { + "description": "Force option byte loading", + "offset": 13, + "size": 1 + }, + "EOPIE": { + "description": "End of operation interrupt\n enable", + "offset": 12, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 10, + "size": 1 + }, + "OPTWRE": { + "description": "Option bytes write enable", + "offset": 9, + "size": 1 + }, + "LOCK": { + "description": "Lock", + "offset": 7, + "size": 1 + }, + "STRT": { + "description": "Start", + "offset": 6, + "size": 1 + }, + "OPTER": { + "description": "Option byte erase", + "offset": 5, + "size": 1 + }, + "OPTPG": { + "description": "Option byte programming", + "offset": 4, + "size": 1 + }, + "MER": { + "description": "Mass erase", + "offset": 2, + "size": 1 + }, + "PER": { + "description": "Page erase", + "offset": 1, + "size": 1 + }, + "PG": { + "description": "Programming", + "offset": 0, + "size": 1 + } + } + } + }, + "AR": { + "description": "Flash address register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "FAR": { + "description": "Flash address", + "offset": 0, + "size": 32 + } + } + } + }, + "OBR": { + "description": "Option byte register", + "offset": 28, + "size": 32, + "reset_value": 4294967042, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OPTERR": { + "description": "Option byte error", + "offset": 0, + "size": 1 + }, + "LEVEL1_PROT": { + "description": "Level 1 protection status", + "offset": 1, + "size": 1 + }, + "LEVEL2_PROT": { + "description": "Level 2 protection status", + "offset": 2, + "size": 1 + }, + "WDG_SW": { + "description": "WDG_SW", + "offset": 8, + "size": 1 + }, + "nRST_STOP": { + "description": "nRST_STOP", + "offset": 9, + "size": 1 + }, + "nRST_STDBY": { + "description": "nRST_STDBY", + "offset": 10, + "size": 1 + }, + "BOOT1": { + "description": "BOOT1", + "offset": 12, + "size": 1 + }, + "VDDA_MONITOR": { + "description": "VDDA_MONITOR", + "offset": 13, + "size": 1 + }, + "SRAM_PARITY_CHECK": { + "description": "SRAM_PARITY_CHECK", + "offset": 14, + "size": 1 + }, + "Data0": { + "description": "Data0", + "offset": 16, + "size": 8 + }, + "Data1": { + "description": "Data1", + "offset": 24, + "size": 8 + } + } + } + }, + "WRPR": { + "description": "Write protection register", + "offset": 32, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WRP": { + "description": "Write protect", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "RCC": { + "description": "Reset and clock control", + "children": { + "registers": { + "CR": { + "description": "Clock control register", + "offset": 0, + "size": 32, + "reset_value": 131, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSION": { + "description": "Internal High Speed clock\n enable", + "offset": 0, + "size": 1 + }, + "HSIRDY": { + "description": "Internal High Speed clock ready\n flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSITRIM": { + "description": "Internal High Speed clock\n trimming", + "offset": 3, + "size": 5 + }, + "HSICAL": { + "description": "Internal High Speed clock\n Calibration", + "offset": 8, + "size": 8, + "access": "read-only" + }, + "HSEON": { + "description": "External High Speed clock\n enable", + "offset": 16, + "size": 1 + }, + "HSERDY": { + "description": "External High Speed clock ready\n flag", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "HSEBYP": { + "description": "External High Speed clock\n Bypass", + "offset": 18, + "size": 1 + }, + "CSSON": { + "description": "Clock Security System\n enable", + "offset": 19, + "size": 1 + }, + "PLLON": { + "description": "PLL enable", + "offset": 24, + "size": 1 + }, + "PLLRDY": { + "description": "PLL clock ready flag", + "offset": 25, + "size": 1, + "access": "read-only" + } + } + } + }, + "CFGR": { + "description": "Clock configuration register\n (RCC_CFGR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SW": { + "description": "System clock Switch", + "offset": 0, + "size": 2 + }, + "SWS": { + "description": "System Clock Switch Status", + "offset": 2, + "size": 2, + "access": "read-only" + }, + "HPRE": { + "description": "AHB prescaler", + "offset": 4, + "size": 4 + }, + "PPRE1": { + "description": "APB Low speed prescaler\n (APB1)", + "offset": 8, + "size": 3 + }, + "PPRE2": { + "description": "APB high speed prescaler\n (APB2)", + "offset": 11, + "size": 3 + }, + "PLLSRC": { + "description": "PLL entry clock source", + "offset": 15, + "size": 2 + }, + "PLLXTPRE": { + "description": "HSE divider for PLL entry", + "offset": 17, + "size": 1 + }, + "PLLMUL": { + "description": "PLL Multiplication Factor", + "offset": 18, + "size": 4 + }, + "USBPRES": { + "description": "USB prescaler", + "offset": 22, + "size": 1 + }, + "MCO": { + "description": "Microcontroller clock\n output", + "offset": 24, + "size": 3 + }, + "MCOF": { + "description": "Microcontroller Clock Output\n Flag", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "I2SSRC": { + "description": "I2S external clock source\n selection", + "offset": 23, + "size": 1 + } + } + } + }, + "CIR": { + "description": "Clock interrupt register\n (RCC_CIR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSIRDYF": { + "description": "LSI Ready Interrupt flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "LSERDYF": { + "description": "LSE Ready Interrupt flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSIRDYF": { + "description": "HSI Ready Interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "HSERDYF": { + "description": "HSE Ready Interrupt flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "PLLRDYF": { + "description": "PLL Ready Interrupt flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "CSSF": { + "description": "Clock Security System Interrupt\n flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "LSIRDYIE": { + "description": "LSI Ready Interrupt Enable", + "offset": 8, + "size": 1 + }, + "LSERDYIE": { + "description": "LSE Ready Interrupt Enable", + "offset": 9, + "size": 1 + }, + "HSIRDYIE": { + "description": "HSI Ready Interrupt Enable", + "offset": 10, + "size": 1 + }, + "HSERDYIE": { + "description": "HSE Ready Interrupt Enable", + "offset": 11, + "size": 1 + }, + "PLLRDYIE": { + "description": "PLL Ready Interrupt Enable", + "offset": 12, + "size": 1 + }, + "LSIRDYC": { + "description": "LSI Ready Interrupt Clear", + "offset": 16, + "size": 1, + "access": "write-only" + }, + "LSERDYC": { + "description": "LSE Ready Interrupt Clear", + "offset": 17, + "size": 1, + "access": "write-only" + }, + "HSIRDYC": { + "description": "HSI Ready Interrupt Clear", + "offset": 18, + "size": 1, + "access": "write-only" + }, + "HSERDYC": { + "description": "HSE Ready Interrupt Clear", + "offset": 19, + "size": 1, + "access": "write-only" + }, + "PLLRDYC": { + "description": "PLL Ready Interrupt Clear", + "offset": 20, + "size": 1, + "access": "write-only" + }, + "CSSC": { + "description": "Clock security system interrupt\n clear", + "offset": 23, + "size": 1, + "access": "write-only" + } + } + } + }, + "APB2RSTR": { + "description": "APB2 peripheral reset register\n (RCC_APB2RSTR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SYSCFGRST": { + "description": "SYSCFG and COMP reset", + "offset": 0, + "size": 1 + }, + "TIM1RST": { + "description": "TIM1 timer reset", + "offset": 11, + "size": 1 + }, + "SPI1RST": { + "description": "SPI 1 reset", + "offset": 12, + "size": 1 + }, + "TIM8RST": { + "description": "TIM8 timer reset", + "offset": 13, + "size": 1 + }, + "USART1RST": { + "description": "USART1 reset", + "offset": 14, + "size": 1 + }, + "TIM15RST": { + "description": "TIM15 timer reset", + "offset": 16, + "size": 1 + }, + "TIM16RST": { + "description": "TIM16 timer reset", + "offset": 17, + "size": 1 + }, + "TIM17RST": { + "description": "TIM17 timer reset", + "offset": 18, + "size": 1 + } + } + } + }, + "APB1RSTR": { + "description": "APB1 peripheral reset register\n (RCC_APB1RSTR)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2RST": { + "description": "Timer 2 reset", + "offset": 0, + "size": 1 + }, + "TIM3RST": { + "description": "Timer 3 reset", + "offset": 1, + "size": 1 + }, + "TIM4RST": { + "description": "Timer 14 reset", + "offset": 2, + "size": 1 + }, + "TIM6RST": { + "description": "Timer 6 reset", + "offset": 4, + "size": 1 + }, + "TIM7RST": { + "description": "Timer 7 reset", + "offset": 5, + "size": 1 + }, + "WWDGRST": { + "description": "Window watchdog reset", + "offset": 11, + "size": 1 + }, + "SPI2RST": { + "description": "SPI2 reset", + "offset": 14, + "size": 1 + }, + "SPI3RST": { + "description": "SPI3 reset", + "offset": 15, + "size": 1 + }, + "USART2RST": { + "description": "USART 2 reset", + "offset": 17, + "size": 1 + }, + "USART3RST": { + "description": "USART3 reset", + "offset": 18, + "size": 1 + }, + "UART4RST": { + "description": "UART 4 reset", + "offset": 19, + "size": 1 + }, + "UART5RST": { + "description": "UART 5 reset", + "offset": 20, + "size": 1 + }, + "I2C1RST": { + "description": "I2C1 reset", + "offset": 21, + "size": 1 + }, + "I2C2RST": { + "description": "I2C2 reset", + "offset": 22, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 23, + "size": 1 + }, + "CANRST": { + "description": "CAN reset", + "offset": 25, + "size": 1 + }, + "PWRRST": { + "description": "Power interface reset", + "offset": 28, + "size": 1 + }, + "DACRST": { + "description": "DAC interface reset", + "offset": 29, + "size": 1 + }, + "I2C3RST": { + "description": "I2C3 reset", + "offset": 30, + "size": 1 + } + } + } + }, + "AHBENR": { + "description": "AHB Peripheral Clock enable register\n (RCC_AHBENR)", + "offset": 20, + "size": 32, + "reset_value": 20, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAEN": { + "description": "DMA1 clock enable", + "offset": 0, + "size": 1 + }, + "DMA2EN": { + "description": "DMA2 clock enable", + "offset": 1, + "size": 1 + }, + "SRAMEN": { + "description": "SRAM interface clock\n enable", + "offset": 2, + "size": 1 + }, + "FLITFEN": { + "description": "FLITF clock enable", + "offset": 4, + "size": 1 + }, + "FMCEN": { + "description": "FMC clock enable", + "offset": 5, + "size": 1 + }, + "CRCEN": { + "description": "CRC clock enable", + "offset": 6, + "size": 1 + }, + "IOPHEN": { + "description": "IO port H clock enable", + "offset": 16, + "size": 1 + }, + "IOPAEN": { + "description": "I/O port A clock enable", + "offset": 17, + "size": 1 + }, + "IOPBEN": { + "description": "I/O port B clock enable", + "offset": 18, + "size": 1 + }, + "IOPCEN": { + "description": "I/O port C clock enable", + "offset": 19, + "size": 1 + }, + "IOPDEN": { + "description": "I/O port D clock enable", + "offset": 20, + "size": 1 + }, + "IOPEEN": { + "description": "I/O port E clock enable", + "offset": 21, + "size": 1 + }, + "IOPFEN": { + "description": "I/O port F clock enable", + "offset": 22, + "size": 1 + }, + "IOPGEN": { + "description": "I/O port G clock enable", + "offset": 23, + "size": 1 + }, + "TSCEN": { + "description": "Touch sensing controller clock\n enable", + "offset": 24, + "size": 1 + }, + "ADC12EN": { + "description": "ADC1 and ADC2 clock enable", + "offset": 28, + "size": 1 + }, + "ADC34EN": { + "description": "ADC3 and ADC4 clock enable", + "offset": 29, + "size": 1 + } + } + } + }, + "APB2ENR": { + "description": "APB2 peripheral clock enable register\n (RCC_APB2ENR)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SYSCFGEN": { + "description": "SYSCFG clock enable", + "offset": 0, + "size": 1 + }, + "TIM1EN": { + "description": "TIM1 Timer clock enable", + "offset": 11, + "size": 1 + }, + "SPI1EN": { + "description": "SPI 1 clock enable", + "offset": 12, + "size": 1 + }, + "TIM8EN": { + "description": "TIM8 Timer clock enable", + "offset": 13, + "size": 1 + }, + "USART1EN": { + "description": "USART1 clock enable", + "offset": 14, + "size": 1 + }, + "TIM15EN": { + "description": "TIM15 timer clock enable", + "offset": 16, + "size": 1 + }, + "TIM16EN": { + "description": "TIM16 timer clock enable", + "offset": 17, + "size": 1 + }, + "TIM17EN": { + "description": "TIM17 timer clock enable", + "offset": 18, + "size": 1 + } + } + } + }, + "APB1ENR": { + "description": "APB1 peripheral clock enable register\n (RCC_APB1ENR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2EN": { + "description": "Timer 2 clock enable", + "offset": 0, + "size": 1 + }, + "TIM3EN": { + "description": "Timer 3 clock enable", + "offset": 1, + "size": 1 + }, + "TIM4EN": { + "description": "Timer 4 clock enable", + "offset": 2, + "size": 1 + }, + "TIM6EN": { + "description": "Timer 6 clock enable", + "offset": 4, + "size": 1 + }, + "TIM7EN": { + "description": "Timer 7 clock enable", + "offset": 5, + "size": 1 + }, + "WWDGEN": { + "description": "Window watchdog clock\n enable", + "offset": 11, + "size": 1 + }, + "SPI2EN": { + "description": "SPI 2 clock enable", + "offset": 14, + "size": 1 + }, + "SPI3EN": { + "description": "SPI 3 clock enable", + "offset": 15, + "size": 1 + }, + "USART2EN": { + "description": "USART 2 clock enable", + "offset": 17, + "size": 1 + }, + "USART3EN": { + "description": "USART 3 clock enable", + "offset": 18, + "size": 1 + }, + "USART4EN": { + "description": "USART 4 clock enable", + "offset": 19, + "size": 1 + }, + "USART5EN": { + "description": "USART 5 clock enable", + "offset": 20, + "size": 1 + }, + "I2C1EN": { + "description": "I2C 1 clock enable", + "offset": 21, + "size": 1 + }, + "I2C2EN": { + "description": "I2C 2 clock enable", + "offset": 22, + "size": 1 + }, + "USBEN": { + "description": "USB clock enable", + "offset": 23, + "size": 1 + }, + "CANEN": { + "description": "CAN clock enable", + "offset": 25, + "size": 1 + }, + "DAC2EN": { + "description": "DAC2 interface clock\n enable", + "offset": 26, + "size": 1 + }, + "PWREN": { + "description": "Power interface clock\n enable", + "offset": 28, + "size": 1 + }, + "DACEN": { + "description": "DAC interface clock enable", + "offset": 29, + "size": 1 + }, + "I2C3EN": { + "description": "I2C3 clock enable", + "offset": 30, + "size": 1 + } + } + } + }, + "BDCR": { + "description": "Backup domain control register\n (RCC_BDCR)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSEON": { + "description": "External Low Speed oscillator\n enable", + "offset": 0, + "size": 1 + }, + "LSERDY": { + "description": "External Low Speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSEBYP": { + "description": "External Low Speed oscillator\n bypass", + "offset": 2, + "size": 1 + }, + "LSEDRV": { + "description": "LSE oscillator drive\n capability", + "offset": 3, + "size": 2 + }, + "RTCSEL": { + "description": "RTC clock source selection", + "offset": 8, + "size": 2 + }, + "RTCEN": { + "description": "RTC clock enable", + "offset": 15, + "size": 1 + }, + "BDRST": { + "description": "Backup domain software\n reset", + "offset": 16, + "size": 1 + } + } + } + }, + "CSR": { + "description": "Control/status register\n (RCC_CSR)", + "offset": 36, + "size": 32, + "reset_value": 201326592, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSION": { + "description": "Internal low speed oscillator\n enable", + "offset": 0, + "size": 1 + }, + "LSIRDY": { + "description": "Internal low speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RMVF": { + "description": "Remove reset flag", + "offset": 24, + "size": 1 + }, + "OBLRSTF": { + "description": "Option byte loader reset\n flag", + "offset": 25, + "size": 1 + }, + "PINRSTF": { + "description": "PIN reset flag", + "offset": 26, + "size": 1 + }, + "PORRSTF": { + "description": "POR/PDR reset flag", + "offset": 27, + "size": 1 + }, + "SFTRSTF": { + "description": "Software reset flag", + "offset": 28, + "size": 1 + }, + "IWDGRSTF": { + "description": "Independent watchdog reset\n flag", + "offset": 29, + "size": 1 + }, + "WWDGRSTF": { + "description": "Window watchdog reset flag", + "offset": 30, + "size": 1 + }, + "LPWRRSTF": { + "description": "Low-power reset flag", + "offset": 31, + "size": 1 + } + } + } + }, + "AHBRSTR": { + "description": "AHB peripheral reset register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FMCRST": { + "description": "FMC reset", + "offset": 5, + "size": 1 + }, + "IOPHRST": { + "description": "I/O port H reset", + "offset": 16, + "size": 1 + }, + "IOPARST": { + "description": "I/O port A reset", + "offset": 17, + "size": 1 + }, + "IOPBRST": { + "description": "I/O port B reset", + "offset": 18, + "size": 1 + }, + "IOPCRST": { + "description": "I/O port C reset", + "offset": 19, + "size": 1 + }, + "IOPDRST": { + "description": "I/O port D reset", + "offset": 20, + "size": 1 + }, + "IOPERST": { + "description": "I/O port E reset", + "offset": 21, + "size": 1 + }, + "IOPFRST": { + "description": "I/O port F reset", + "offset": 22, + "size": 1 + }, + "IOPGRST": { + "description": "Touch sensing controller\n reset", + "offset": 23, + "size": 1 + }, + "TSCRST": { + "description": "Touch sensing controller\n reset", + "offset": 24, + "size": 1 + }, + "ADC12RST": { + "description": "ADC1 and ADC2 reset", + "offset": 28, + "size": 1 + }, + "ADC34RST": { + "description": "ADC3 and ADC4 reset", + "offset": 29, + "size": 1 + } + } + } + }, + "CFGR2": { + "description": "Clock configuration register 2", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PREDIV": { + "description": "PREDIV division factor", + "offset": 0, + "size": 4 + }, + "ADC12PRES": { + "description": "ADC1 and ADC2 prescaler", + "offset": 4, + "size": 5 + }, + "ADC34PRES": { + "description": "ADC3 and ADC4 prescaler", + "offset": 9, + "size": 5 + } + } + } + }, + "CFGR3": { + "description": "Clock configuration register 3", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "USART1SW": { + "description": "USART1 clock source\n selection", + "offset": 0, + "size": 2 + }, + "I2C1SW": { + "description": "I2C1 clock source\n selection", + "offset": 4, + "size": 1 + }, + "I2C2SW": { + "description": "I2C2 clock source\n selection", + "offset": 5, + "size": 1 + }, + "I2C3SW": { + "description": "I2C3 clock source\n selection", + "offset": 6, + "size": 1 + }, + "USART2SW": { + "description": "USART2 clock source\n selection", + "offset": 16, + "size": 2 + }, + "USART3SW": { + "description": "USART3 clock source\n selection", + "offset": 18, + "size": 2 + }, + "TIM1SW": { + "description": "Timer1 clock source\n selection", + "offset": 8, + "size": 1 + }, + "TIM8SW": { + "description": "Timer8 clock source\n selection", + "offset": 9, + "size": 1 + }, + "UART4SW": { + "description": "UART4 clock source\n selection", + "offset": 20, + "size": 2 + }, + "UART5SW": { + "description": "UART5 clock source\n selection", + "offset": 22, + "size": 2 + } + } + } + } + } + } + }, + "DMA1": { + "description": "DMA controller 1", + "children": { + "registers": { + "ISR": { + "description": "DMA interrupt status register\n (DMA_ISR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "GIF1": { + "description": "Channel 1 Global interrupt\n flag", + "offset": 0, + "size": 1 + }, + "TCIF1": { + "description": "Channel 1 Transfer Complete\n flag", + "offset": 1, + "size": 1 + }, + "HTIF1": { + "description": "Channel 1 Half Transfer Complete\n flag", + "offset": 2, + "size": 1 + }, + "TEIF1": { + "description": "Channel 1 Transfer Error\n flag", + "offset": 3, + "size": 1 + }, + "GIF2": { + "description": "Channel 2 Global interrupt\n flag", + "offset": 4, + "size": 1 + }, + "TCIF2": { + "description": "Channel 2 Transfer Complete\n flag", + "offset": 5, + "size": 1 + }, + "HTIF2": { + "description": "Channel 2 Half Transfer Complete\n flag", + "offset": 6, + "size": 1 + }, + "TEIF2": { + "description": "Channel 2 Transfer Error\n flag", + "offset": 7, + "size": 1 + }, + "GIF3": { + "description": "Channel 3 Global interrupt\n flag", + "offset": 8, + "size": 1 + }, + "TCIF3": { + "description": "Channel 3 Transfer Complete\n flag", + "offset": 9, + "size": 1 + }, + "HTIF3": { + "description": "Channel 3 Half Transfer Complete\n flag", + "offset": 10, + "size": 1 + }, + "TEIF3": { + "description": "Channel 3 Transfer Error\n flag", + "offset": 11, + "size": 1 + }, + "GIF4": { + "description": "Channel 4 Global interrupt\n flag", + "offset": 12, + "size": 1 + }, + "TCIF4": { + "description": "Channel 4 Transfer Complete\n flag", + "offset": 13, + "size": 1 + }, + "HTIF4": { + "description": "Channel 4 Half Transfer Complete\n flag", + "offset": 14, + "size": 1 + }, + "TEIF4": { + "description": "Channel 4 Transfer Error\n flag", + "offset": 15, + "size": 1 + }, + "GIF5": { + "description": "Channel 5 Global interrupt\n flag", + "offset": 16, + "size": 1 + }, + "TCIF5": { + "description": "Channel 5 Transfer Complete\n flag", + "offset": 17, + "size": 1 + }, + "HTIF5": { + "description": "Channel 5 Half Transfer Complete\n flag", + "offset": 18, + "size": 1 + }, + "TEIF5": { + "description": "Channel 5 Transfer Error\n flag", + "offset": 19, + "size": 1 + }, + "GIF6": { + "description": "Channel 6 Global interrupt\n flag", + "offset": 20, + "size": 1 + }, + "TCIF6": { + "description": "Channel 6 Transfer Complete\n flag", + "offset": 21, + "size": 1 + }, + "HTIF6": { + "description": "Channel 6 Half Transfer Complete\n flag", + "offset": 22, + "size": 1 + }, + "TEIF6": { + "description": "Channel 6 Transfer Error\n flag", + "offset": 23, + "size": 1 + }, + "GIF7": { + "description": "Channel 7 Global interrupt\n flag", + "offset": 24, + "size": 1 + }, + "TCIF7": { + "description": "Channel 7 Transfer Complete\n flag", + "offset": 25, + "size": 1 + }, + "HTIF7": { + "description": "Channel 7 Half Transfer Complete\n flag", + "offset": 26, + "size": 1 + }, + "TEIF7": { + "description": "Channel 7 Transfer Error\n flag", + "offset": 27, + "size": 1 + } + } + } + }, + "IFCR": { + "description": "DMA interrupt flag clear register\n (DMA_IFCR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CGIF1": { + "description": "Channel 1 Global interrupt\n clear", + "offset": 0, + "size": 1 + }, + "CTCIF1": { + "description": "Channel 1 Transfer Complete\n clear", + "offset": 1, + "size": 1 + }, + "CHTIF1": { + "description": "Channel 1 Half Transfer\n clear", + "offset": 2, + "size": 1 + }, + "CTEIF1": { + "description": "Channel 1 Transfer Error\n clear", + "offset": 3, + "size": 1 + }, + "CGIF2": { + "description": "Channel 2 Global interrupt\n clear", + "offset": 4, + "size": 1 + }, + "CTCIF2": { + "description": "Channel 2 Transfer Complete\n clear", + "offset": 5, + "size": 1 + }, + "CHTIF2": { + "description": "Channel 2 Half Transfer\n clear", + "offset": 6, + "size": 1 + }, + "CTEIF2": { + "description": "Channel 2 Transfer Error\n clear", + "offset": 7, + "size": 1 + }, + "CGIF3": { + "description": "Channel 3 Global interrupt\n clear", + "offset": 8, + "size": 1 + }, + "CTCIF3": { + "description": "Channel 3 Transfer Complete\n clear", + "offset": 9, + "size": 1 + }, + "CHTIF3": { + "description": "Channel 3 Half Transfer\n clear", + "offset": 10, + "size": 1 + }, + "CTEIF3": { + "description": "Channel 3 Transfer Error\n clear", + "offset": 11, + "size": 1 + }, + "CGIF4": { + "description": "Channel 4 Global interrupt\n clear", + "offset": 12, + "size": 1 + }, + "CTCIF4": { + "description": "Channel 4 Transfer Complete\n clear", + "offset": 13, + "size": 1 + }, + "CHTIF4": { + "description": "Channel 4 Half Transfer\n clear", + "offset": 14, + "size": 1 + }, + "CTEIF4": { + "description": "Channel 4 Transfer Error\n clear", + "offset": 15, + "size": 1 + }, + "CGIF5": { + "description": "Channel 5 Global interrupt\n clear", + "offset": 16, + "size": 1 + }, + "CTCIF5": { + "description": "Channel 5 Transfer Complete\n clear", + "offset": 17, + "size": 1 + }, + "CHTIF5": { + "description": "Channel 5 Half Transfer\n clear", + "offset": 18, + "size": 1 + }, + "CTEIF5": { + "description": "Channel 5 Transfer Error\n clear", + "offset": 19, + "size": 1 + }, + "CGIF6": { + "description": "Channel 6 Global interrupt\n clear", + "offset": 20, + "size": 1 + }, + "CTCIF6": { + "description": "Channel 6 Transfer Complete\n clear", + "offset": 21, + "size": 1 + }, + "CHTIF6": { + "description": "Channel 6 Half Transfer\n clear", + "offset": 22, + "size": 1 + }, + "CTEIF6": { + "description": "Channel 6 Transfer Error\n clear", + "offset": 23, + "size": 1 + }, + "CGIF7": { + "description": "Channel 7 Global interrupt\n clear", + "offset": 24, + "size": 1 + }, + "CTCIF7": { + "description": "Channel 7 Transfer Complete\n clear", + "offset": 25, + "size": 1 + }, + "CHTIF7": { + "description": "Channel 7 Half Transfer\n clear", + "offset": 26, + "size": 1 + }, + "CTEIF7": { + "description": "Channel 7 Transfer Error\n clear", + "offset": 27, + "size": 1 + } + } + } + }, + "CCR1": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR1": { + "description": "DMA channel 1 number of data\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR1": { + "description": "DMA channel 1 peripheral address\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR1": { + "description": "DMA channel 1 memory address\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR2": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR2": { + "description": "DMA channel 2 number of data\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR2": { + "description": "DMA channel 2 peripheral address\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR2": { + "description": "DMA channel 2 memory address\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR3": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR3": { + "description": "DMA channel 3 number of data\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR3": { + "description": "DMA channel 3 peripheral address\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR3": { + "description": "DMA channel 3 memory address\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR4": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR4": { + "description": "DMA channel 4 number of data\n register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR4": { + "description": "DMA channel 4 peripheral address\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR4": { + "description": "DMA channel 4 memory address\n register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR5": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR5": { + "description": "DMA channel 5 number of data\n register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR5": { + "description": "DMA channel 5 peripheral address\n register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR5": { + "description": "DMA channel 5 memory address\n register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR6": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR6": { + "description": "DMA channel 6 number of data\n register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR6": { + "description": "DMA channel 6 peripheral address\n register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR6": { + "description": "DMA channel 6 memory address\n register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "CCR7": { + "description": "DMA channel configuration register\n (DMA_CCR)", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 1, + "size": 1 + }, + "HTIE": { + "description": "Half Transfer interrupt\n enable", + "offset": 2, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 4, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 5, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 6, + "size": 1 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 7, + "size": 1 + }, + "PSIZE": { + "description": "Peripheral size", + "offset": 8, + "size": 2 + }, + "MSIZE": { + "description": "Memory size", + "offset": 10, + "size": 2 + }, + "PL": { + "description": "Channel Priority level", + "offset": 12, + "size": 2 + }, + "MEM2MEM": { + "description": "Memory to memory mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CNDTR7": { + "description": "DMA channel 7 number of data\n register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data to transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "CPAR7": { + "description": "DMA channel 7 peripheral address\n register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "CMAR7": { + "description": "DMA channel 7 memory address\n register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "FPU": { + "description": "Floting point unit", + "children": { + "registers": { + "FPCCR": { + "description": "Floating-point context control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSPACT": { + "description": "LSPACT", + "offset": 0, + "size": 1 + }, + "USER": { + "description": "USER", + "offset": 1, + "size": 1 + }, + "THREAD": { + "description": "THREAD", + "offset": 3, + "size": 1 + }, + "HFRDY": { + "description": "HFRDY", + "offset": 4, + "size": 1 + }, + "MMRDY": { + "description": "MMRDY", + "offset": 5, + "size": 1 + }, + "BFRDY": { + "description": "BFRDY", + "offset": 6, + "size": 1 + }, + "MONRDY": { + "description": "MONRDY", + "offset": 8, + "size": 1 + }, + "LSPEN": { + "description": "LSPEN", + "offset": 30, + "size": 1 + }, + "ASPEN": { + "description": "ASPEN", + "offset": 31, + "size": 1 + } + } + } + }, + "FPCAR": { + "description": "Floating-point context address\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Location of unpopulated\n floating-point", + "offset": 3, + "size": 29 + } + } + } + }, + "FPSCR": { + "description": "Floating-point status control\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOC": { + "description": "Invalid operation cumulative exception\n bit", + "offset": 0, + "size": 1 + }, + "DZC": { + "description": "Division by zero cumulative exception\n bit.", + "offset": 1, + "size": 1 + }, + "OFC": { + "description": "Overflow cumulative exception\n bit", + "offset": 2, + "size": 1 + }, + "UFC": { + "description": "Underflow cumulative exception\n bit", + "offset": 3, + "size": 1 + }, + "IXC": { + "description": "Inexact cumulative exception\n bit", + "offset": 4, + "size": 1 + }, + "IDC": { + "description": "Input denormal cumulative exception\n bit.", + "offset": 7, + "size": 1 + }, + "RMode": { + "description": "Rounding Mode control\n field", + "offset": 22, + "size": 2 + }, + "FZ": { + "description": "Flush-to-zero mode control\n bit:", + "offset": 24, + "size": 1 + }, + "DN": { + "description": "Default NaN mode control\n bit", + "offset": 25, + "size": 1 + }, + "AHP": { + "description": "Alternative half-precision control\n bit", + "offset": 26, + "size": 1 + }, + "V": { + "description": "Overflow condition code\n flag", + "offset": 28, + "size": 1 + }, + "C": { + "description": "Carry condition code flag", + "offset": 29, + "size": 1 + }, + "Z": { + "description": "Zero condition code flag", + "offset": 30, + "size": 1 + }, + "N": { + "description": "Negative condition code\n flag", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "TIM2": { + "description": "General purpose timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + }, + "OCCS": { + "description": "OCREF clear selection", + "offset": 3, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "SMS_3": { + "description": "Slave mode selection bit3", + "offset": 16, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1FE": { + "description": "Output compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC1PE": { + "description": "Output compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1M": { + "description": "Output compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1CE": { + "description": "Output compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC2FE": { + "description": "Output compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "OC2PE": { + "description": "Output compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2M": { + "description": "Output compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2CE": { + "description": "Output compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC1M_3": { + "description": "Output compare 1 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC2M_3": { + "description": "Output compare 2 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PSC": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "O24CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC3M_3": { + "description": "Output compare 3 mode bit3", + "offset": 16, + "size": 1 + }, + "OC4M_3": { + "description": "Output compare 4 mode bit3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 15, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNTL": { + "description": "Low counter value", + "offset": 0, + "size": 16 + }, + "CNTH": { + "description": "High counter value", + "offset": 16, + "size": 15 + }, + "CNT_or_UIFCPY": { + "description": "if IUFREMAP=0 than CNT with read write\n access else UIFCPY with read only\n access", + "offset": 31, + "size": 1 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARRL": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + }, + "ARRH": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + }, + "CCR1H": { + "description": "High Capture/Compare 1 value (on\n TIM2)", + "offset": 16, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + }, + "CCR2H": { + "description": "High Capture/Compare 2 value (on\n TIM2)", + "offset": 16, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + }, + "CCR3H": { + "description": "High Capture/Compare value (on\n TIM2)", + "offset": 16, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + }, + "CCR4H": { + "description": "High Capture/Compare value (on\n TIM2)", + "offset": 16, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "children": { + "registers": { + "ISER0": { + "description": "Interrupt Set-Enable Register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER1": { + "description": "Interrupt Set-Enable Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER2": { + "description": "Interrupt Set-Enable Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER0": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER1": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER2": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR0": { + "description": "Interrupt Set-Pending Register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR1": { + "description": "Interrupt Set-Pending Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR2": { + "description": "Interrupt Set-Pending Register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR0": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR1": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR2": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR0": { + "description": "Interrupt Active Bit Register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR1": { + "description": "Interrupt Active Bit Register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR2": { + "description": "Interrupt Active Bit Register", + "offset": 520, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IPR0": { + "description": "Interrupt Priority Register", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR1": { + "description": "Interrupt Priority Register", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR2": { + "description": "Interrupt Priority Register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR3": { + "description": "Interrupt Priority Register", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR4": { + "description": "Interrupt Priority Register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR5": { + "description": "Interrupt Priority Register", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR6": { + "description": "Interrupt Priority Register", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR7": { + "description": "Interrupt Priority Register", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR8": { + "description": "Interrupt Priority Register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR9": { + "description": "Interrupt Priority Register", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR10": { + "description": "Interrupt Priority Register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR11": { + "description": "Interrupt Priority Register", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR12": { + "description": "Interrupt Priority Register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR13": { + "description": "Interrupt Priority Register", + "offset": 820, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR14": { + "description": "Interrupt Priority Register", + "offset": 824, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR15": { + "description": "Interrupt Priority Register", + "offset": 828, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR16": { + "description": "Interrupt Priority Register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR17": { + "description": "Interrupt Priority Register", + "offset": 836, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": 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+ "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR3": { + "description": "FIFO status and interrupt register\n 3", + "offset": 132, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM3": { + "description": "Common memory space timing register\n 3", + "offset": 136, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT3": { + "description": "Attribute memory space timing register\n 3", + "offset": 140, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR3": { + "description": "ECC result register 3", + "offset": 148, + "size": 32, + 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register\n 4", + "offset": 164, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM4": { + "description": "Common memory space timing register\n 4", + "offset": 168, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT4": { + "description": "Attribute memory space timing register\n 4", + "offset": 172, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PIO4": { + "description": "I/O space timing register 4", + "offset": 176, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOHIZx": { + "description": "IOHIZx", + "offset": 24, + "size": 8 + }, + "IOHOLDx": { + "description": "IOHOLDx", + "offset": 16, + "size": 8 + }, + "IOWAITx": { + "description": "IOWAITx", + "offset": 8, + "size": 8 + }, + "IOSETx": { + "description": "IOSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "BWTR1": { + "description": "SRAM/NOR-Flash write timing registers\n 1", + "offset": 260, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "Bus turnaround phase\n duration", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR2": { + "description": "SRAM/NOR-Flash write timing registers\n 2", + "offset": 268, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "Bus turnaround phase\n duration", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR3": { + "description": "SRAM/NOR-Flash write timing registers\n 3", + "offset": 276, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "Bus turnaround phase\n duration", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR4": { + "description": "SRAM/NOR-Flash write timing registers\n 4", + "offset": 284, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "Bus turnaround phase\n duration", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "TIM15": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "SMS_3": { + "description": "Slave mode selection bit 3", + "offset": 16, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC1M_3": { + "description": "Output Compare 1 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC2M_3": { + "description": "Output Compare 2 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PSC": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + }, + "BKF": { + "description": "Break filter", + "offset": 16, + "size": 4 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "TIM16": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1M_3": { + "description": "Output Compare 1 mode", + "offset": 16, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF Copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "BKF": { + "description": "Break filter", + "offset": 16, + "size": 4 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + } + } + } + }, + "TIM17": { + "description": "General purpose timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1M_3": { + "description": "Output Compare 1 mode", + "offset": 16, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PSC": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF Copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "BKF": { + "description": "Break filter", + "offset": 16, + "size": 4 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "USART1": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "CR1": { + "description": "Control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOBIE": { + "description": "End of Block interrupt\n enable", + "offset": 27, + "size": 1 + }, + "RTOIE": { + "description": "Receiver timeout interrupt\n enable", + "offset": 26, + "size": 1 + }, + "DEAT": { + "description": "Driver Enable assertion\n time", + "offset": 21, + "size": 5 + }, + "DEDT": { + "description": "Driver Enable deassertion\n time", + "offset": 16, + "size": 5 + }, + "OVER8": { + "description": "Oversampling mode", + "offset": 15, + "size": 1 + }, + "CMIE": { + "description": "Character match interrupt\n enable", + "offset": 14, + "size": 1 + }, + "MME": { + "description": "Mute mode enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Receiver wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "UESM": { + "description": "USART enable in Stop mode", + "offset": 1, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD4": { + "description": "Address of the USART node", + "offset": 28, + "size": 4 + }, + "ADD0": { + "description": "Address of the USART node", + "offset": 24, + "size": 4 + }, + "RTOEN": { + "description": "Receiver timeout enable", + "offset": 23, + "size": 1 + }, + "ABRMOD": { + "description": "Auto baud rate mode", + "offset": 21, + "size": 2 + }, + "ABREN": { + "description": "Auto baud rate enable", + "offset": 20, + "size": 1 + }, + "MSBFIRST": { + "description": "Most significant bit first", + "offset": 19, + "size": 1 + }, + "DATAINV": { + "description": "Binary data inversion", + "offset": 18, + "size": 1 + }, + "TXINV": { + "description": "TX pin active level\n inversion", + "offset": 17, + "size": 1 + }, + "RXINV": { + "description": "RX pin active level\n inversion", + "offset": 16, + "size": 1 + }, + "SWAP": { + "description": "Swap TX/RX pins", + "offset": 15, + "size": 1 + }, + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "CLKEN": { + "description": "Clock enable", + "offset": 11, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 10, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 9, + "size": 1 + }, + "LBCL": { + "description": "Last bit clock pulse", + "offset": 8, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "LIN break detection length", + "offset": 5, + "size": 1 + }, + "ADDM7": { + "description": "7-bit Address Detection/4-bit Address\n Detection", + "offset": 4, + "size": 1 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUFIE": { + "description": "Wakeup from Stop mode interrupt\n enable", + "offset": 22, + "size": 1 + }, + "WUS": { + "description": "Wakeup from Stop mode interrupt flag\n selection", + "offset": 20, + "size": 2 + }, + "SCARCNT": { + "description": "Smartcard auto-retry count", + "offset": 17, + "size": 3 + }, + "DEP": { + "description": "Driver enable polarity\n selection", + "offset": 15, + "size": 1 + }, + "DEM": { + "description": "Driver enable mode", + "offset": 14, + "size": 1 + }, + "DDRE": { + "description": "DMA Disable on Reception\n Error", + "offset": 13, + "size": 1 + }, + "OVRDIS": { + "description": "Overrun Disable", + "offset": 12, + "size": 1 + }, + "ONEBIT": { + "description": "One sample bit method\n enable", + "offset": 11, + "size": 1 + }, + "CTSIE": { + "description": "CTS interrupt enable", + "offset": 10, + "size": 1 + }, + "CTSE": { + "description": "CTS enable", + "offset": 9, + "size": 1 + }, + "RTSE": { + "description": "RTS enable", + "offset": 8, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "SCEN": { + "description": "Smartcard mode enable", + "offset": 5, + "size": 1 + }, + "NACK": { + "description": "Smartcard NACK enable", + "offset": 4, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "GTPR": { + "description": "Guard time and prescaler\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GT": { + "description": "Guard time value", + "offset": 8, + "size": 8 + }, + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + }, + "RTOR": { + "description": "Receiver timeout register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BLEN": { + "description": "Block Length", + "offset": 24, + "size": 8 + }, + "RTO": { + "description": "Receiver timeout value", + "offset": 0, + "size": 24 + } + } + } + }, + "RQR": { + "description": "Request register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFRQ": { + "description": "Transmit data flush\n request", + "offset": 4, + "size": 1 + }, + "RXFRQ": { + "description": "Receive data flush request", + "offset": 3, + "size": 1 + }, + "MMRQ": { + "description": "Mute mode request", + "offset": 2, + "size": 1 + }, + "SBKRQ": { + "description": "Send break request", + "offset": 1, + "size": 1 + }, + "ABRRQ": { + "description": "Auto baud rate request", + "offset": 0, + "size": 1 + } + } + } + }, + "ISR": { + "description": "Interrupt & status\n register", + "offset": 28, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "REACK": { + "description": "Receive enable acknowledge\n flag", + "offset": 22, + "size": 1 + }, + "TEACK": { + "description": "Transmit enable acknowledge\n flag", + "offset": 21, + "size": 1 + }, + "WUF": { + "description": "Wakeup from Stop mode flag", + "offset": 20, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup from Mute\n mode", + "offset": 19, + "size": 1 + }, + "SBKF": { + "description": "Send break flag", + "offset": 18, + "size": 1 + }, + "CMF": { + "description": "character match flag", + "offset": 17, + "size": 1 + }, + "BUSY": { + "description": "Busy flag", + "offset": 16, + "size": 1 + }, + "ABRF": { + "description": "Auto baud rate flag", + "offset": 15, + "size": 1 + }, + "ABRE": { + "description": "Auto baud rate error", + "offset": 14, + "size": 1 + }, + "EOBF": { + "description": "End of block flag", + "offset": 12, + "size": 1 + }, + "RTOF": { + "description": "Receiver timeout", + "offset": 11, + "size": 1 + }, + "CTS": { + "description": "CTS flag", + "offset": 10, + "size": 1 + }, + "CTSIF": { + "description": "CTS interrupt flag", + "offset": 9, + "size": 1 + }, + "LBDF": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1 + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "Idle line detected", + "offset": 4, + "size": 1 + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1 + }, + "NF": { + "description": "Noise detected flag", + "offset": 2, + "size": 1 + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1 + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "Interrupt flag clear register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUCF": { + "description": "Wakeup from Stop mode clear\n flag", + "offset": 20, + "size": 1 + }, + "CMCF": { + "description": "Character match clear flag", + "offset": 17, + "size": 1 + }, + "EOBCF": { + "description": "End of timeout clear flag", + "offset": 12, + "size": 1 + }, + "RTOCF": { + "description": "Receiver timeout clear\n flag", + "offset": 11, + "size": 1 + }, + "CTSCF": { + "description": "CTS clear flag", + "offset": 9, + "size": 1 + }, + "LBDCF": { + "description": "LIN break detection clear\n flag", + "offset": 8, + "size": 1 + }, + "TCCF": { + "description": "Transmission complete clear\n flag", + "offset": 6, + "size": 1 + }, + "IDLECF": { + "description": "Idle line detected clear\n flag", + "offset": 4, + "size": 1 + }, + "ORECF": { + "description": "Overrun error clear flag", + "offset": 3, + "size": 1 + }, + "NCF": { + "description": "Noise detected clear flag", + "offset": 2, + "size": 1 + }, + "FECF": { + "description": "Framing error clear flag", + "offset": 1, + "size": 1 + }, + "PECF": { + "description": "Parity error clear flag", + "offset": 0, + "size": 1 + } + } + } + }, + "RDR": { + "description": "Receive data register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RDR": { + "description": "Receive data value", + "offset": 0, + "size": 9 + } + } + } + }, + "TDR": { + "description": "Transmit data register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDR": { + "description": "Transmit data value", + "offset": 0, + "size": 9 + } + } + } + } + } + } + }, + "SYSCFG_COMP_OPAMP": { + "description": "System configuration controller _Comparator and\n Operational amplifier", + "children": { + "registers": { + "SYSCFG_CFGR1": { + "description": "configuration register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEM_MODE": { + "description": "Memory mapping selection\n bits", + "offset": 0, + "size": 2 + }, + "USB_IT_RMP": { + "description": "USB interrupt remap", + "offset": 5, + "size": 1 + }, + "TIM1_ITR_RMP": { + "description": "Timer 1 ITR3 selection", + "offset": 6, + "size": 1 + }, + "DAC_TRIG_RMP": { + "description": "DAC trigger remap (when TSEL =\n 001)", + "offset": 7, + "size": 1 + }, + "ADC24_DMA_RMP": { + "description": "ADC24 DMA remapping bit", + "offset": 8, + "size": 1 + }, + "TIM16_DMA_RMP": { + "description": "TIM16 DMA request remapping\n bit", + "offset": 11, + "size": 1 + }, + "TIM17_DMA_RMP": { + "description": "TIM17 DMA request remapping\n bit", + "offset": 12, + "size": 1 + }, + "TIM6_DAC1_DMA_RMP": { + "description": "TIM6 and DAC1 DMA request remapping\n bit", + "offset": 13, + "size": 1 + }, + "TIM7_DAC2_DMA_RMP": { + "description": "TIM7 and DAC2 DMA request remapping\n bit", + "offset": 14, + "size": 1 + }, + "I2C_PB6_FM": { + "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", + "offset": 16, + "size": 1 + }, + "I2C_PB7_FM": { + "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", + "offset": 17, + "size": 1 + }, + "I2C_PB8_FM": { + "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", + "offset": 18, + "size": 1 + }, + "I2C_PB9_FM": { + "description": "Fast Mode Plus (FM+) driving capability\n activation bits.", + "offset": 19, + "size": 1 + }, + "I2C1_FM": { + "description": "I2C1 Fast Mode Plus", + "offset": 20, + "size": 1 + }, + "I2C2_FM": { + "description": "I2C2 Fast Mode Plus", + "offset": 21, + "size": 1 + }, + "ENCODER_MODE": { + "description": "Encoder mode", + "offset": 22, + "size": 2 + }, + "FPU_IT": { + "description": "Interrupt enable bits from\n FPU", + "offset": 26, + "size": 6 + } + } + } + }, + "SYSCFG_EXTICR1": { + "description": "external interrupt configuration register\n 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI3": { + "description": "EXTI 3 configuration bits", + "offset": 12, + "size": 4 + }, + "EXTI2": { + "description": "EXTI 2 configuration bits", + "offset": 8, + "size": 4 + }, + "EXTI1": { + "description": "EXTI 1 configuration bits", + "offset": 4, + "size": 4 + }, + "EXTI0": { + "description": "EXTI 0 configuration bits", + "offset": 0, + "size": 4 + } + } + } + }, + "SYSCFG_EXTICR2": { + "description": "external interrupt configuration register\n 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI7": { + "description": "EXTI 7 configuration bits", + "offset": 12, + "size": 4 + }, + "EXTI6": { + "description": "EXTI 6 configuration bits", + "offset": 8, + "size": 4 + }, + "EXTI5": { + "description": "EXTI 5 configuration bits", + "offset": 4, + "size": 4 + }, + "EXTI4": { + "description": "EXTI 4 configuration bits", + "offset": 0, + "size": 4 + } + } + } + }, + "SYSCFG_EXTICR3": { + "description": "external interrupt configuration register\n 3", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI11": { + "description": "EXTI 11 configuration bits", + "offset": 12, + "size": 4 + }, + "EXTI10": { + "description": "EXTI 10 configuration bits", + "offset": 8, + "size": 4 + }, + "EXTI9": { + "description": "EXTI 9 configuration bits", + "offset": 4, + "size": 4 + }, + "EXTI8": { + "description": "EXTI 8 configuration bits", + "offset": 0, + "size": 4 + } + } + } + }, + "SYSCFG_EXTICR4": { + "description": "external interrupt configuration register\n 4", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI15": { + "description": "EXTI 15 configuration bits", + "offset": 12, + "size": 4 + }, + "EXTI14": { + "description": "EXTI 14 configuration bits", + "offset": 8, + "size": 4 + }, + "EXTI13": { + "description": "EXTI 13 configuration bits", + "offset": 4, + "size": 4 + }, + "EXTI12": { + "description": "EXTI 12 configuration bits", + "offset": 0, + "size": 4 + } + } + } + }, + "SYSCFG_CFGR2": { + "description": "configuration register 2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOCUP_LOCK": { + "description": "Cortex-M0 LOCKUP bit enable\n bit", + "offset": 0, + "size": 1 + }, + "SRAM_PARITY_LOCK": { + "description": "SRAM parity lock bit", + "offset": 1, + "size": 1 + }, + "PVD_LOCK": { + "description": "PVD lock enable bit", + "offset": 2, + "size": 1 + }, + "BYP_ADD_PAR": { + "description": "Bypass address bit 29 in parity\n calculation", + "offset": 4, + "size": 1 + }, + "SRAM_PEF": { + "description": "SRAM parity flag", + "offset": 8, + "size": 1 + } + } + } + }, + "SYSCFG_RCR": { + "description": "CCM SRAM protection register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PAGE0_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 0, + "size": 1 + }, + "PAGE1_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 1, + "size": 1 + }, + "PAGE2_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 2, + "size": 1 + }, + "PAGE3_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 3, + "size": 1 + }, + "PAGE4_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 4, + "size": 1 + }, + "PAGE5_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 5, + "size": 1 + }, + "PAGE6_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 6, + "size": 1 + }, + "PAGE7_WP": { + "description": "CCM SRAM page write protection\n bit", + "offset": 7, + "size": 1 + } + } + } + }, + "COMP1_CSR": { + "description": "control and status register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP1EN": { + "description": "Comparator 1 enable", + "offset": 0, + "size": 1 + }, + "COMP1_INP_DAC": { + "description": "COMP1_INP_DAC", + "offset": 1, + "size": 1 + }, + "COMP1MODE": { + "description": "Comparator 1 mode", + "offset": 2, + "size": 2 + }, + "COMP1INSEL": { + "description": "Comparator 1 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP1_OUT_SEL": { + "description": "Comparator 1 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP1POL": { + "description": "Comparator 1 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP1HYST": { + "description": "Comparator 1 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP1_BLANKING": { + "description": "Comparator 1 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP1OUT": { + "description": "Comparator 1 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP1LOCK": { + "description": "Comparator 1 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP2_CSR": { + "description": "control and status register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP2EN": { + "description": "Comparator 2 enable", + "offset": 0, + "size": 1 + }, + "COMP2MODE": { + "description": "Comparator 2 mode", + "offset": 2, + "size": 2 + }, + "COMP2INSEL": { + "description": "Comparator 2 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP2INPSEL": { + "description": "Comparator 2 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COMP2INMSEL": { + "description": "Comparator 1inverting input\n selection", + "offset": 9, + "size": 1 + }, + "COMP2_OUT_SEL": { + "description": "Comparator 2 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP2POL": { + "description": "Comparator 2 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP2HYST": { + "description": "Comparator 2 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP2_BLANKING": { + "description": "Comparator 2 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP2LOCK": { + "description": "Comparator 2 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP3_CSR": { + "description": "control and status register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP3EN": { + "description": "Comparator 3 enable", + "offset": 0, + "size": 1 + }, + "COMP3MODE": { + "description": "Comparator 3 mode", + "offset": 2, + "size": 2 + }, + "COMP3INSEL": { + "description": "Comparator 3 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP3INPSEL": { + "description": "Comparator 3 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COMP3_OUT_SEL": { + "description": "Comparator 3 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP3POL": { + "description": "Comparator 3 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP3HYST": { + "description": "Comparator 3 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP3_BLANKING": { + "description": "Comparator 3 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP3OUT": { + "description": "Comparator 3 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP3LOCK": { + "description": "Comparator 3 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP4_CSR": { + "description": "control and status register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP4EN": { + "description": "Comparator 4 enable", + "offset": 0, + "size": 1 + }, + "COMP4MODE": { + "description": "Comparator 4 mode", + "offset": 2, + "size": 2 + }, + "COMP4INSEL": { + "description": "Comparator 4 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP4INPSEL": { + "description": "Comparator 4 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COM4WINMODE": { + "description": "Comparator 4 window mode", + "offset": 9, + "size": 1 + }, + "COMP4_OUT_SEL": { + "description": "Comparator 4 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP4POL": { + "description": "Comparator 4 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP4HYST": { + "description": "Comparator 4 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP4_BLANKING": { + "description": "Comparator 4 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP4OUT": { + "description": "Comparator 4 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP4LOCK": { + "description": "Comparator 4 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP5_CSR": { + "description": "control and status register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP5EN": { + "description": "Comparator 5 enable", + "offset": 0, + "size": 1 + }, + "COMP5MODE": { + "description": "Comparator 5 mode", + "offset": 2, + "size": 2 + }, + "COMP5INSEL": { + "description": "Comparator 5 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP5INPSEL": { + "description": "Comparator 5 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COMP5_OUT_SEL": { + "description": "Comparator 5 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP5POL": { + "description": "Comparator 5 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP5HYST": { + "description": "Comparator 5 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP5_BLANKING": { + "description": "Comparator 5 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP5OUT": { + "description": "Comparator51 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP5LOCK": { + "description": "Comparator 5 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP6_CSR": { + "description": "control and status register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP6EN": { + "description": "Comparator 6 enable", + "offset": 0, + "size": 1 + }, + "COMP6MODE": { + "description": "Comparator 6 mode", + "offset": 2, + "size": 2 + }, + "COMP6INSEL": { + "description": "Comparator 6 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP6INPSEL": { + "description": "Comparator 6 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COM6WINMODE": { + "description": "Comparator 6 window mode", + "offset": 9, + "size": 1 + }, + "COMP6_OUT_SEL": { + "description": "Comparator 6 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP6POL": { + "description": "Comparator 6 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP6HYST": { + "description": "Comparator 6 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP6_BLANKING": { + "description": "Comparator 6 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP6OUT": { + "description": "Comparator 6 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP6LOCK": { + "description": "Comparator 6 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "COMP7_CSR": { + "description": "control and status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP7EN": { + "description": "Comparator 7 enable", + "offset": 0, + "size": 1 + }, + "COMP7MODE": { + "description": "Comparator 7 mode", + "offset": 2, + "size": 2 + }, + "COMP7INSEL": { + "description": "Comparator 7 inverting input\n selection", + "offset": 4, + "size": 3 + }, + "COMP7INPSEL": { + "description": "Comparator 7 non inverted input\n selection", + "offset": 7, + "size": 1 + }, + "COMP7_OUT_SEL": { + "description": "Comparator 7 output\n selection", + "offset": 10, + "size": 4 + }, + "COMP7POL": { + "description": "Comparator 7 output\n polarity", + "offset": 15, + "size": 1 + }, + "COMP7HYST": { + "description": "Comparator 7 hysteresis", + "offset": 16, + "size": 2 + }, + "COMP7_BLANKING": { + "description": "Comparator 7 blanking\n source", + "offset": 18, + "size": 3 + }, + "COMP7OUT": { + "description": "Comparator 7 output", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "COMP7LOCK": { + "description": "Comparator 7 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPAMP1_CSR": { + "description": "control register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPAMP1_EN": { + "description": "OPAMP1 enable", + "offset": 0, + "size": 1 + }, + "FORCE_VP": { + "description": "FORCE_VP", + "offset": 1, + "size": 1 + }, + "VP_SEL": { + "description": "OPAMP1 Non inverting input\n selection", + "offset": 2, + "size": 2 + }, + "VM_SEL": { + "description": "OPAMP1 inverting input\n selection", + "offset": 5, + "size": 2 + }, + "TCM_EN": { + "description": "Timer controlled Mux mode\n enable", + "offset": 7, + "size": 1 + }, + "VMS_SEL": { + "description": "OPAMP1 inverting input secondary\n selection", + "offset": 8, + "size": 1 + }, + "VPS_SEL": { + "description": "OPAMP1 Non inverting input secondary\n selection", + "offset": 9, + "size": 2 + }, + "CALON": { + "description": "Calibration mode enable", + "offset": 11, + "size": 1 + }, + "CALSEL": { + "description": "Calibration selection", + "offset": 12, + "size": 2 + }, + "PGA_GAIN": { + "description": "Gain in PGA mode", + "offset": 14, + "size": 4 + }, + "USER_TRIM": { + "description": "User trimming enable", + "offset": 18, + "size": 1 + }, + "TRIMOFFSETP": { + "description": "Offset trimming value\n (PMOS)", + "offset": 19, + "size": 5 + }, + "TRIMOFFSETN": { + "description": "Offset trimming value\n (NMOS)", + "offset": 24, + "size": 5 + }, + "TSTREF": { + "description": "TSTREF", + "offset": 29, + "size": 1 + }, + "OUTCAL": { + "description": "OPAMP 1 ouput status flag", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOCK": { + "description": "OPAMP 1 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPAMP2_CSR": { + "description": "control register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPAMP2EN": { + "description": "OPAMP2 enable", + "offset": 0, + "size": 1 + }, + "FORCE_VP": { + "description": "FORCE_VP", + "offset": 1, + "size": 1 + }, + "VP_SEL": { + "description": "OPAMP2 Non inverting input\n selection", + "offset": 2, + "size": 2 + }, + "VM_SEL": { + "description": "OPAMP2 inverting input\n selection", + "offset": 5, + "size": 2 + }, + "TCM_EN": { + "description": "Timer controlled Mux mode\n enable", + "offset": 7, + "size": 1 + }, + "VMS_SEL": { + "description": "OPAMP2 inverting input secondary\n selection", + "offset": 8, + "size": 1 + }, + "VPS_SEL": { + "description": "OPAMP2 Non inverting input secondary\n selection", + "offset": 9, + "size": 2 + }, + "CALON": { + "description": "Calibration mode enable", + "offset": 11, + "size": 1 + }, + "CAL_SEL": { + "description": "Calibration selection", + "offset": 12, + "size": 2 + }, + "PGA_GAIN": { + "description": "Gain in PGA mode", + "offset": 14, + "size": 4 + }, + "USER_TRIM": { + "description": "User trimming enable", + "offset": 18, + "size": 1 + }, + "TRIMOFFSETP": { + "description": "Offset trimming value\n (PMOS)", + "offset": 19, + "size": 5 + }, + "TRIMOFFSETN": { + "description": "Offset trimming value\n (NMOS)", + "offset": 24, + "size": 5 + }, + "TSTREF": { + "description": "TSTREF", + "offset": 29, + "size": 1 + }, + "OUTCAL": { + "description": "OPAMP 2 ouput status flag", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOCK": { + "description": "OPAMP 2 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPAMP3_CSR": { + "description": "control register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPAMP3EN": { + "description": "OPAMP3 enable", + "offset": 0, + "size": 1 + }, + "FORCE_VP": { + "description": "FORCE_VP", + "offset": 1, + "size": 1 + }, + "VP_SEL": { + "description": "OPAMP3 Non inverting input\n selection", + "offset": 2, + "size": 2 + }, + "VM_SEL": { + "description": "OPAMP3 inverting input\n selection", + "offset": 5, + "size": 2 + }, + "TCM_EN": { + "description": "Timer controlled Mux mode\n enable", + "offset": 7, + "size": 1 + }, + "VMS_SEL": { + "description": "OPAMP3 inverting input secondary\n selection", + "offset": 8, + "size": 1 + }, + "VPS_SEL": { + "description": "OPAMP3 Non inverting input secondary\n selection", + "offset": 9, + "size": 2 + }, + "CALON": { + "description": "Calibration mode enable", + "offset": 11, + "size": 1 + }, + "CALSEL": { + "description": "Calibration selection", + "offset": 12, + "size": 2 + }, + "PGA_GAIN": { + "description": "Gain in PGA mode", + "offset": 14, + "size": 4 + }, + "USER_TRIM": { + "description": "User trimming enable", + "offset": 18, + "size": 1 + }, + "TRIMOFFSETP": { + "description": "Offset trimming value\n (PMOS)", + "offset": 19, + "size": 5 + }, + "TRIMOFFSETN": { + "description": "Offset trimming value\n (NMOS)", + "offset": 24, + "size": 5 + }, + "TSTREF": { + "description": "TSTREF", + "offset": 29, + "size": 1 + }, + "OUTCAL": { + "description": "OPAMP 3 ouput status flag", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOCK": { + "description": "OPAMP 3 lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPAMP4_CSR": { + "description": "control register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPAMP4EN": { + "description": "OPAMP4 enable", + "offset": 0, + "size": 1 + }, + "FORCE_VP": { + "description": "FORCE_VP", + "offset": 1, + "size": 1 + }, + "VP_SEL": { + "description": "OPAMP4 Non inverting input\n selection", + "offset": 2, + "size": 2 + }, + "VM_SEL": { + "description": "OPAMP4 inverting input\n selection", + "offset": 5, + "size": 2 + }, + "TCM_EN": { + "description": "Timer controlled Mux mode\n enable", + "offset": 7, + "size": 1 + }, + "VMS_SEL": { + "description": "OPAMP4 inverting input secondary\n selection", + "offset": 8, + "size": 1 + }, + "VPS_SEL": { + "description": "OPAMP4 Non inverting input secondary\n selection", + "offset": 9, + "size": 2 + }, + "CALON": { + "description": "Calibration mode enable", + "offset": 11, + "size": 1 + }, + "CALSEL": { + "description": "Calibration selection", + "offset": 12, + "size": 2 + }, + "PGA_GAIN": { + "description": "Gain in PGA mode", + "offset": 14, + "size": 4 + }, + "USER_TRIM": { + "description": "User trimming enable", + "offset": 18, + "size": 1 + }, + "TRIMOFFSETP": { + "description": "Offset trimming value\n (PMOS)", + "offset": 19, + "size": 5 + }, + "TRIMOFFSETN": { + "description": "Offset trimming value\n (NMOS)", + "offset": 24, + "size": 5 + }, + "TSTREF": { + "description": "TSTREF", + "offset": 29, + "size": 1 + }, + "OUTCAL": { + "description": "OPAMP 4 ouput status flag", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOCK": { + "description": "OPAMP 4 lock", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "IWDG": { + "description": "Independent watchdog", + "children": { + "registers": { + "KR": { + "description": "Key register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Key value", + "offset": 0, + "size": 16 + } + } + } + }, + "PR": { + "description": "Prescaler register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR": { + "description": "Prescaler divider", + "offset": 0, + "size": 3 + } + } + } + }, + "RLR": { + "description": "Reload register", + "offset": 8, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Watchdog counter reload\n value", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PVU": { + "description": "Watchdog prescaler value\n update", + "offset": 0, + "size": 1 + }, + "RVU": { + "description": "Watchdog counter reload value\n update", + "offset": 1, + "size": 1 + }, + "WVU": { + "description": "Watchdog counter window value\n update", + "offset": 2, + "size": 1 + } + } + } + }, + "WINR": { + "description": "Window register", + "offset": 16, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "WIN": { + "description": "Watchdog counter window\n value", + "offset": 0, + "size": 12 + } + } + } + } + } + } + }, + "ADC1_2": { + "description": "Analog-to-Digital Converter", + "children": { + "registers": { + "CSR": { + "description": "ADC Common status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ADDRDY_MST": { + "description": "ADDRDY_MST", + "offset": 0, + "size": 1 + }, + "EOSMP_MST": { + "description": "EOSMP_MST", + "offset": 1, + "size": 1 + }, + "EOC_MST": { + "description": "EOC_MST", + "offset": 2, + "size": 1 + }, + "EOS_MST": { + "description": "EOS_MST", + "offset": 3, + "size": 1 + }, + "OVR_MST": { + "description": "OVR_MST", + "offset": 4, + "size": 1 + }, + "JEOC_MST": { + "description": "JEOC_MST", + "offset": 5, + "size": 1 + }, + "JEOS_MST": { + "description": "JEOS_MST", + "offset": 6, + "size": 1 + }, + "AWD1_MST": { + "description": "AWD1_MST", + "offset": 7, + "size": 1 + }, + "AWD2_MST": { + "description": "AWD2_MST", + "offset": 8, + "size": 1 + }, + "AWD3_MST": { + "description": "AWD3_MST", + "offset": 9, + "size": 1 + }, + "JQOVF_MST": { + "description": "JQOVF_MST", + "offset": 10, + "size": 1 + }, + "ADRDY_SLV": { + "description": "ADRDY_SLV", + "offset": 16, + "size": 1 + }, + "EOSMP_SLV": { + "description": "EOSMP_SLV", + "offset": 17, + "size": 1 + }, + "EOC_SLV": { + "description": "End of regular conversion of the slave\n ADC", + "offset": 18, + "size": 1 + }, + "EOS_SLV": { + "description": "End of regular sequence flag of the\n slave ADC", + "offset": 19, + "size": 1 + }, + "OVR_SLV": { + "description": "Overrun flag of the slave\n ADC", + "offset": 20, + "size": 1 + }, + "JEOC_SLV": { + "description": "End of injected conversion flag of the\n slave ADC", + "offset": 21, + "size": 1 + }, + "JEOS_SLV": { + "description": "End of injected sequence flag of the\n slave ADC", + "offset": 22, + "size": 1 + }, + "AWD1_SLV": { + "description": "Analog watchdog 1 flag of the slave\n ADC", + "offset": 23, + "size": 1 + }, + "AWD2_SLV": { + "description": "Analog watchdog 2 flag of the slave\n ADC", + "offset": 24, + "size": 1 + }, + "AWD3_SLV": { + "description": "Analog watchdog 3 flag of the slave\n ADC", + "offset": 25, + "size": 1 + }, + "JQOVF_SLV": { + "description": "Injected Context Queue Overflow flag of\n the slave ADC", + "offset": 26, + "size": 1 + } + } + } + }, + "CCR": { + "description": "ADC common control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MULT": { + "description": "Multi ADC mode selection", + "offset": 0, + "size": 5 + }, + "DELAY": { + "description": "Delay between 2 sampling\n phases", + "offset": 8, + "size": 4 + }, + "DMACFG": { + "description": "DMA configuration (for multi-ADC\n mode)", + "offset": 13, + "size": 1 + }, + "MDMA": { + "description": "Direct memory access mode for multi ADC\n mode", + "offset": 14, + "size": 2 + }, + "CKMODE": { + "description": "ADC clock mode", + "offset": 16, + "size": 2 + }, + "VREFEN": { + "description": "VREFINT enable", + "offset": 22, + "size": 1 + }, + "TSEN": { + "description": "Temperature sensor enable", + "offset": 23, + "size": 1 + }, + "VBATEN": { + "description": "VBAT enable", + "offset": 24, + "size": 1 + } + } + } + }, + "CDR": { + "description": "ADC common regular data register for dual\n and triple modes", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RDATA_SLV": { + "description": "Regular data of the slave\n ADC", + "offset": 16, + "size": 16 + }, + "RDATA_MST": { + "description": "Regular data of the master\n ADC", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "WWDG": { + "description": "Window watchdog", + "children": { + "registers": { + "CR": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "T": { + "description": "7-bit counter", + "offset": 0, + "size": 7 + }, + "WDGA": { + "description": "Activation bit", + "offset": 7, + "size": 1 + } + } + } + }, + "CFR": { + "description": "Configuration register", + "offset": 4, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWI": { + "description": "Early wakeup interrupt", + "offset": 9, + "size": 1 + }, + "WDGTB": { + "description": "Timer base", + "offset": 7, + "size": 2 + }, + "W": { + "description": "7-bit window value", + "offset": 0, + "size": 7 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWIF": { + "description": "Early wakeup interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "SPI1": { + "description": "Serial peripheral interface/Inter-IC\n sound", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BIDIMODE": { + "description": "Bidirectional data mode\n enable", + "offset": 15, + "size": 1 + }, + "BIDIOE": { + "description": "Output enable in bidirectional\n mode", + "offset": 14, + "size": 1 + }, + "CRCEN": { + "description": "Hardware CRC calculation\n enable", + "offset": 13, + "size": 1 + }, + "CRCNEXT": { + "description": "CRC transfer next", + "offset": 12, + "size": 1 + }, + "CRCL": { + "description": "CRC length", + "offset": 11, + "size": 1 + }, + "RXONLY": { + "description": "Receive only", + "offset": 10, + "size": 1 + }, + "SSM": { + "description": "Software slave management", + "offset": 9, + "size": 1 + }, + "SSI": { + "description": "Internal slave select", + "offset": 8, + "size": 1 + }, + "LSBFIRST": { + "description": "Frame format", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI enable", + "offset": 6, + "size": 1 + }, + "BR": { + "description": "Baud rate control", + "offset": 3, + "size": 3 + }, + "MSTR": { + "description": "Master selection", + "offset": 2, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 1, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDMAEN": { + "description": "Rx buffer DMA enable", + "offset": 0, + "size": 1 + }, + "TXDMAEN": { + "description": "Tx buffer DMA enable", + "offset": 1, + "size": 1 + }, + "SSOE": { + "description": "SS output enable", + "offset": 2, + "size": 1 + }, + "NSSP": { + "description": "NSS pulse management", + "offset": 3, + "size": 1 + }, + "FRF": { + "description": "Frame format", + "offset": 4, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 5, + "size": 1 + }, + "RXNEIE": { + "description": "RX buffer not empty interrupt\n enable", + "offset": 6, + "size": 1 + }, + "TXEIE": { + "description": "Tx buffer empty interrupt\n enable", + "offset": 7, + "size": 1 + }, + "DS": { + "description": "Data size", + "offset": 8, + "size": 4 + }, + "FRXTH": { + "description": "FIFO reception threshold", + "offset": 12, + "size": 1 + }, + "LDMA_RX": { + "description": "Last DMA transfer for\n reception", + "offset": 13, + "size": 1 + }, + "LDMA_TX": { + "description": "Last DMA transfer for\n transmission", + "offset": 14, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 8, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXNE": { + "description": "Receive buffer not empty", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "TXE": { + "description": "Transmit buffer empty", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "CHSIDE": { + "description": "Channel side", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "UDR": { + "description": "Underrun flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "CRCERR": { + "description": "CRC error flag", + "offset": 4, + "size": 1 + }, + "MODF": { + "description": "Mode fault", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "OVR": { + "description": "Overrun flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "BSY": { + "description": "Busy flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TIFRFE": { + "description": "TI frame format error", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "FRLVL": { + "description": "FIFO reception level", + "offset": 9, + "size": 2, + "access": "read-only" + }, + "FTLVL": { + "description": "FIFO transmission level", + "offset": 11, + "size": 2, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 16 + } + } + } + }, + "CRCPR": { + "description": "CRC polynomial register", + "offset": 16, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial register", + "offset": 0, + "size": 16 + } + } + } + }, + "RXCRCR": { + "description": "RX CRC register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RxCRC": { + "description": "Rx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "TXCRCR": { + "description": "TX CRC register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TxCRC": { + "description": "Tx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "I2SCFGR": { + "description": "I2S configuration register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "I2SMOD": { + "description": "I2S mode selection", + "offset": 11, + "size": 1 + }, + "I2SE": { + "description": "I2S Enable", + "offset": 10, + "size": 1 + }, + "I2SCFG": { + "description": "I2S configuration mode", + "offset": 8, + "size": 2 + }, + "PCMSYNC": { + "description": "PCM frame synchronization", + "offset": 7, + "size": 1 + }, + "I2SSTD": { + "description": "I2S standard selection", + "offset": 4, + "size": 2 + }, + "CKPOL": { + "description": "Steady state clock\n polarity", + "offset": 3, + "size": 1 + }, + "DATLEN": { + "description": "Data length to be\n transferred", + "offset": 1, + "size": 2 + }, + "CHLEN": { + "description": "Channel length (number of bits per audio\n channel)", + "offset": 0, + "size": 1 + } + } + } + }, + "I2SPR": { + "description": "I2S prescaler register", + "offset": 32, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKOE": { + "description": "Master clock output enable", + "offset": 9, + "size": 1 + }, + "ODD": { + "description": "Odd factor for the\n prescaler", + "offset": 8, + "size": 1 + }, + "I2SDIV": { + "description": "I2S Linear prescaler", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "RTC": { + "description": "Real-time clock", + "children": { + "registers": { + "TR": { + "description": "time register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "DR": { + "description": "date register", + "offset": 4, + "size": 32, + "reset_value": 8449, + "reset_mask": 4294967295, + "children": { + "fields": { + "YT": { + "description": "Year tens in BCD format", + "offset": 20, + "size": 4 + }, + "YU": { + "description": "Year units in BCD format", + "offset": 16, + "size": 4 + }, + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "CR": { + "description": "control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WCKSEL": { + "description": "Wakeup clock selection", + "offset": 0, + "size": 3 + }, + "TSEDGE": { + "description": "Time-stamp event active\n edge", + "offset": 3, + "size": 1 + }, + "REFCKON": { + "description": "Reference clock detection enable (50 or\n 60 Hz)", + "offset": 4, + "size": 1 + }, + "BYPSHAD": { + "description": "Bypass the shadow\n registers", + "offset": 5, + "size": 1 + }, + "FMT": { + "description": "Hour format", + "offset": 6, + "size": 1 + }, + "ALRAE": { + "description": "Alarm A enable", + "offset": 8, + "size": 1 + }, + "ALRBE": { + "description": "Alarm B enable", + "offset": 9, + "size": 1 + }, + "WUTE": { + "description": "Wakeup timer enable", + "offset": 10, + "size": 1 + }, + "TSE": { + "description": "Time stamp enable", + "offset": 11, + "size": 1 + }, + "ALRAIE": { + "description": "Alarm A interrupt enable", + "offset": 12, + "size": 1 + }, + "ALRBIE": { + "description": "Alarm B interrupt enable", + "offset": 13, + "size": 1 + }, + "WUTIE": { + "description": "Wakeup timer interrupt\n enable", + "offset": 14, + "size": 1 + }, + "TSIE": { + "description": "Time-stamp interrupt\n enable", + "offset": 15, + "size": 1 + }, + "ADD1H": { + "description": "Add 1 hour (summer time\n change)", + "offset": 16, + "size": 1 + }, + "SUB1H": { + "description": "Subtract 1 hour (winter time\n change)", + "offset": 17, + "size": 1 + }, + "BKP": { + "description": "Backup", + "offset": 18, + "size": 1 + }, + "COSEL": { + "description": "Calibration output\n selection", + "offset": 19, + "size": 1 + }, + "POL": { + "description": "Output polarity", + "offset": 20, + "size": 1 + }, + "OSEL": { + "description": "Output selection", + "offset": 21, + "size": 2 + }, + "COE": { + "description": "Calibration output enable", + "offset": 23, + "size": 1 + } + } + } + }, + "ISR": { + "description": "initialization and status\n register", + "offset": 12, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALRAWF": { + "description": "Alarm A write flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "ALRBWF": { + "description": "Alarm B write flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "WUTWF": { + "description": "Wakeup timer write flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SHPF": { + "description": "Shift operation pending", + "offset": 3, + "size": 1 + }, + "INITS": { + "description": "Initialization status flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "RSF": { + "description": "Registers synchronization\n flag", + "offset": 5, + "size": 1 + }, + "INITF": { + "description": "Initialization flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "INIT": { + "description": "Initialization mode", + "offset": 7, + "size": 1 + }, + "ALRAF": { + "description": "Alarm A flag", + "offset": 8, + "size": 1 + }, + "ALRBF": { + "description": "Alarm B flag", + "offset": 9, + "size": 1 + }, + "WUTF": { + "description": "Wakeup timer flag", + "offset": 10, + "size": 1 + }, + "TSF": { + "description": "Time-stamp flag", + "offset": 11, + "size": 1 + }, + "TSOVF": { + "description": "Time-stamp overflow flag", + "offset": 12, + "size": 1 + }, + "TAMP1F": { + "description": "Tamper detection flag", + "offset": 13, + "size": 1 + }, + "TAMP2F": { + "description": "RTC_TAMP2 detection flag", + "offset": 14, + "size": 1 + }, + "TAMP3F": { + "description": "RTC_TAMP3 detection flag", + "offset": 15, + "size": 1 + }, + "RECALPF": { + "description": "Recalibration pending Flag", + "offset": 16, + "size": 1, + "access": "read-only" + } + } + } + }, + "PRER": { + "description": "prescaler register", + "offset": 16, + "size": 32, + "reset_value": 8323327, + "reset_mask": 4294967295, + "children": { + "fields": { + "PREDIV_A": { + "description": "Asynchronous prescaler\n factor", + "offset": 16, + "size": 7 + }, + "PREDIV_S": { + "description": "Synchronous prescaler\n factor", + "offset": 0, + "size": 15 + } + } + } + }, + "WUTR": { + "description": "wakeup timer register", + "offset": 20, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUT": { + "description": "Wakeup auto-reload value\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "ALRMAR": { + "description": "alarm A register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm A date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm A hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm A minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm A seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "ALRMBR": { + "description": "alarm B register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm B date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm B hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm B minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm B seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "WPR": { + "description": "write protection register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Write protection key", + "offset": 0, + "size": 8 + } + } + } + }, + "SSR": { + "description": "sub second register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "SHIFTR": { + "description": "shift control register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ADD1S": { + "description": "Add one second", + "offset": 31, + "size": 1 + }, + "SUBFS": { + "description": "Subtract a fraction of a\n second", + "offset": 0, + "size": 15 + } + } + } + }, + "TSTR": { + "description": "time stamp time register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + } + } + } + }, + "TSDR": { + "description": "time stamp date register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "TSSSR": { + "description": "timestamp sub second register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "CALR": { + "description": "calibration register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CALP": { + "description": "Increase frequency of RTC by 488.5\n ppm", + "offset": 15, + "size": 1 + }, + "CALW8": { + "description": "Use an 8-second calibration cycle\n period", + "offset": 14, + "size": 1 + }, + "CALW16": { + "description": "Use a 16-second calibration cycle\n period", + "offset": 13, + "size": 1 + }, + "CALM": { + "description": "Calibration minus", + "offset": 0, + "size": 9 + } + } + } + }, + "TAFCR": { + "description": "tamper and alternate function configuration\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TAMP1E": { + "description": "Tamper 1 detection enable", + "offset": 0, + "size": 1 + }, + "TAMP1TRG": { + "description": "Active level for tamper 1", + "offset": 1, + "size": 1 + }, + "TAMPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TAMP2E": { + "description": "Tamper 2 detection enable", + "offset": 3, + "size": 1 + }, + "TAMP2TRG": { + "description": "Active level for tamper 2", + "offset": 4, + "size": 1 + }, + "TAMP3E": { + "description": "Tamper 3 detection enable", + "offset": 5, + "size": 1 + }, + "TAMP3TRG": { + "description": "Active level for tamper 3", + "offset": 6, + "size": 1 + }, + "TAMPTS": { + "description": "Activate timestamp on tamper detection\n event", + "offset": 7, + "size": 1 + }, + "TAMPFREQ": { + "description": "Tamper sampling frequency", + "offset": 8, + "size": 3 + }, + "TAMPFLT": { + "description": "Tamper filter count", + "offset": 11, + "size": 2 + }, + "TAMPPRCH": { + "description": "Tamper precharge duration", + "offset": 13, + "size": 2 + }, + "TAMPPUDIS": { + "description": "TAMPER pull-up disable", + "offset": 15, + "size": 1 + }, + "PC13VALUE": { + "description": "PC13 value", + "offset": 18, + "size": 1 + }, + "PC13MODE": { + "description": "PC13 mode", + "offset": 19, + "size": 1 + }, + "PC14VALUE": { + "description": "PC14 value", + "offset": 20, + "size": 1 + }, + "PC14MODE": { + "description": "PC 14 mode", + "offset": 21, + "size": 1 + }, + "PC15VALUE": { + "description": "PC15 value", + "offset": 22, + "size": 1 + }, + "PC15MODE": { + "description": "PC15 mode", + "offset": 23, + "size": 1 + } + } + } + }, + "ALRMASSR": { + "description": "alarm A sub second register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "ALRMBSSR": { + "description": "alarm B sub second register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "BKP0R": { + "description": "backup register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP1R": { + "description": "backup register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP2R": { + "description": "backup register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP3R": { + "description": "backup register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP4R": { + "description": "backup register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP5R": { + "description": "backup register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP6R": { + "description": "backup register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP7R": { + "description": "backup register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP8R": { + "description": "backup register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP9R": { + "description": "backup register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP10R": { + "description": "backup register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP11R": { + "description": "backup register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP12R": { + "description": "backup register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP13R": { + "description": "backup register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP14R": { + "description": "backup register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP15R": { + "description": "backup register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP16R": { + "description": "backup register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP17R": { + "description": "backup register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP18R": { + "description": "backup register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP19R": { + "description": "backup register", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP20R": { + "description": "backup register", + "offset": 160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP21R": { + "description": "backup register", + "offset": 164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP22R": { + "description": "backup register", + "offset": 168, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP23R": { + "description": "backup register", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP24R": { + "description": "backup register", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP25R": { + "description": "backup register", + "offset": 180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP26R": { + "description": "backup register", + "offset": 184, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP27R": { + "description": "backup register", + "offset": 188, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP28R": { + "description": "backup register", + "offset": 192, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP29R": { + "description": "backup register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP30R": { + "description": "backup register", + "offset": 200, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP31R": { + "description": "backup register", + "offset": 204, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "TIM6": { + "description": "Basic timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Low counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF Copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "ADC1": { + "description": "Analog-to-Digital Converter", + "children": { + "registers": { + "ISR": { + "description": "interrupt and status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JQOVF": { + "description": "JQOVF", + "offset": 10, + "size": 1 + }, + "AWD3": { + "description": "AWD3", + "offset": 9, + "size": 1 + }, + "AWD2": { + "description": "AWD2", + "offset": 8, + "size": 1 + }, + "AWD1": { + "description": "AWD1", + "offset": 7, + "size": 1 + }, + "JEOS": { + "description": "JEOS", + "offset": 6, + "size": 1 + }, + "JEOC": { + "description": "JEOC", + "offset": 5, + "size": 1 + }, + "OVR": { + "description": "OVR", + "offset": 4, + "size": 1 + }, + "EOS": { + "description": "EOS", + "offset": 3, + "size": 1 + }, + "EOC": { + "description": "EOC", + "offset": 2, + "size": 1 + }, + "EOSMP": { + "description": "EOSMP", + "offset": 1, + "size": 1 + }, + "ADRDY": { + "description": "ADRDY", + "offset": 0, + "size": 1 + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JQOVFIE": { + "description": "JQOVFIE", + "offset": 10, + "size": 1 + }, + "AWD3IE": { + "description": "AWD3IE", + "offset": 9, + "size": 1 + }, + "AWD2IE": { + "description": "AWD2IE", + "offset": 8, + "size": 1 + }, + "AWD1IE": { + "description": "AWD1IE", + "offset": 7, + "size": 1 + }, + "JEOSIE": { + "description": "JEOSIE", + "offset": 6, + "size": 1 + }, + "JEOCIE": { + "description": "JEOCIE", + "offset": 5, + "size": 1 + }, + "OVRIE": { + "description": "OVRIE", + "offset": 4, + "size": 1 + }, + "EOSIE": { + "description": "EOSIE", + "offset": 3, + "size": 1 + }, + "EOCIE": { + "description": "EOCIE", + "offset": 2, + "size": 1 + }, + "EOSMPIE": { + "description": "EOSMPIE", + "offset": 1, + "size": 1 + }, + "ADRDYIE": { + "description": "ADRDYIE", + "offset": 0, + "size": 1 + } + } + } + }, + "CR": { + "description": "control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADCAL": { + "description": "ADCAL", + "offset": 31, + "size": 1 + }, + "ADCALDIF": { + "description": "ADCALDIF", + "offset": 30, + "size": 1 + }, + "DEEPPWD": { + "description": "DEEPPWD", + "offset": 29, + "size": 1 + }, + "ADVREGEN": { + "description": "ADVREGEN", + "offset": 28, + "size": 1 + }, + "JADSTP": { + "description": "JADSTP", + "offset": 5, + "size": 1 + }, + "ADSTP": { + "description": "ADSTP", + "offset": 4, + "size": 1 + }, + "JADSTART": { + "description": "JADSTART", + "offset": 3, + "size": 1 + }, + "ADSTART": { + "description": "ADSTART", + "offset": 2, + "size": 1 + }, + "ADDIS": { + "description": "ADDIS", + "offset": 1, + "size": 1 + }, + "ADEN": { + "description": "ADEN", + "offset": 0, + "size": 1 + } + } + } + }, + "CFGR": { + "description": "configuration register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AWDCH1CH": { + "description": "AWDCH1CH", + "offset": 26, + "size": 5 + }, + "JAUTO": { + "description": "JAUTO", + "offset": 25, + "size": 1 + }, + "JAWD1EN": { + "description": "JAWD1EN", + "offset": 24, + "size": 1 + }, + "AWD1EN": { + "description": "AWD1EN", + "offset": 23, + "size": 1 + }, + "AWD1SGL": { + "description": "AWD1SGL", + "offset": 22, + "size": 1 + }, + "JQM": { + "description": "JQM", + "offset": 21, + "size": 1 + }, + "JDISCEN": { + "description": "JDISCEN", + "offset": 20, + "size": 1 + }, + "DISCNUM": { + "description": "DISCNUM", + "offset": 17, + "size": 3 + }, + "DISCEN": { + "description": "DISCEN", + "offset": 16, + "size": 1 + }, + "AUTOFF": { + "description": "AUTOFF", + "offset": 15, + "size": 1 + }, + "AUTDLY": { + "description": "AUTDLY", + "offset": 14, + "size": 1 + }, + "CONT": { + "description": "CONT", + "offset": 13, + "size": 1 + }, + "OVRMOD": { + "description": "OVRMOD", + "offset": 12, + "size": 1 + }, + "EXTEN": { + "description": "EXTEN", + "offset": 10, + "size": 2 + }, + "EXTSEL": { + "description": "EXTSEL", + "offset": 6, + "size": 4 + }, + "ALIGN": { + "description": "ALIGN", + "offset": 5, + "size": 1 + }, + "RES": { + "description": "RES", + "offset": 3, + "size": 2 + }, + "DMACFG": { + "description": "DMACFG", + "offset": 1, + "size": 1 + }, + "DMAEN": { + "description": "DMAEN", + "offset": 0, + "size": 1 + } + } + } + }, + "SMPR1": { + "description": "sample time register 1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP9": { + "description": "SMP9", + "offset": 27, + "size": 3 + }, + "SMP8": { + "description": "SMP8", + "offset": 24, + "size": 3 + }, + "SMP7": { + "description": "SMP7", + "offset": 21, + "size": 3 + }, + "SMP6": { + "description": "SMP6", + "offset": 18, + "size": 3 + }, + "SMP5": { + "description": "SMP5", + "offset": 15, + "size": 3 + }, + "SMP4": { + "description": "SMP4", + "offset": 12, + "size": 3 + }, + "SMP3": { + "description": "SMP3", + "offset": 9, + "size": 3 + }, + "SMP2": { + "description": "SMP2", + "offset": 6, + "size": 3 + }, + "SMP1": { + "description": "SMP1", + "offset": 3, + "size": 3 + } + } + } + }, + "SMPR2": { + "description": "sample time register 2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMP18": { + "description": "SMP18", + "offset": 24, + "size": 3 + }, + "SMP17": { + "description": "SMP17", + "offset": 21, + "size": 3 + }, + "SMP16": { + "description": "SMP16", + "offset": 18, + "size": 3 + }, + "SMP15": { + "description": "SMP15", + "offset": 15, + "size": 3 + }, + "SMP14": { + "description": "SMP14", + "offset": 12, + "size": 3 + }, + "SMP13": { + "description": "SMP13", + "offset": 9, + "size": 3 + }, + "SMP12": { + "description": "SMP12", + "offset": 6, + "size": 3 + }, + "SMP11": { + "description": "SMP11", + "offset": 3, + "size": 3 + }, + "SMP10": { + "description": "SMP10", + "offset": 0, + "size": 3 + } + } + } + }, + "TR1": { + "description": "watchdog threshold register 1", + "offset": 32, + "size": 32, + "reset_value": 268369920, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT1": { + "description": "HT1", + "offset": 16, + "size": 12 + }, + "LT1": { + "description": "LT1", + "offset": 0, + "size": 12 + } + } + } + }, + "TR2": { + "description": "watchdog threshold register", + "offset": 36, + "size": 32, + "reset_value": 268369920, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT2": { + "description": "HT2", + "offset": 16, + "size": 8 + }, + "LT2": { + "description": "LT2", + "offset": 0, + "size": 8 + } + } + } + }, + "TR3": { + "description": "watchdog threshold register 3", + "offset": 40, + "size": 32, + "reset_value": 268369920, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT3": { + "description": "HT3", + "offset": 16, + "size": 8 + }, + "LT3": { + "description": "LT3", + "offset": 0, + "size": 8 + } + } + } + }, + "SQR1": { + "description": "regular sequence register 1", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ4": { + "description": "SQ4", + "offset": 24, + "size": 5 + }, + "SQ3": { + "description": "SQ3", + "offset": 18, + "size": 5 + }, + "SQ2": { + "description": "SQ2", + "offset": 12, + "size": 5 + }, + "SQ1": { + "description": "SQ1", + "offset": 6, + "size": 5 + }, + "L3": { + "description": "L3", + "offset": 0, + "size": 4 + } + } + } + }, + "SQR2": { + "description": "regular sequence register 2", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ9": { + "description": "SQ9", + "offset": 24, + "size": 5 + }, + "SQ8": { + "description": "SQ8", + "offset": 18, + "size": 5 + }, + "SQ7": { + "description": "SQ7", + "offset": 12, + "size": 5 + }, + "SQ6": { + "description": "SQ6", + "offset": 6, + "size": 5 + }, + "SQ5": { + "description": "SQ5", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR3": { + "description": "regular sequence register 3", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ14": { + "description": "SQ14", + "offset": 24, + "size": 5 + }, + "SQ13": { + "description": "SQ13", + "offset": 18, + "size": 5 + }, + "SQ12": { + "description": "SQ12", + "offset": 12, + "size": 5 + }, + "SQ11": { + "description": "SQ11", + "offset": 6, + "size": 5 + }, + "SQ10": { + "description": "SQ10", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR4": { + "description": "regular sequence register 4", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ16": { + "description": "SQ16", + "offset": 6, + "size": 5 + }, + "SQ15": { + "description": "SQ15", + "offset": 0, + "size": 5 + } + } + } + }, + "DR": { + "description": "regular Data Register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "regularDATA": { + "description": "regularDATA", + "offset": 0, + "size": 16 + } + } + } + }, + "JSQR": { + "description": "injected sequence register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JSQ4": { + "description": "JSQ4", + "offset": 26, + "size": 5 + }, + "JSQ3": { + "description": "JSQ3", + "offset": 20, + "size": 5 + }, + "JSQ2": { + "description": "JSQ2", + "offset": 14, + "size": 5 + }, + "JSQ1": { + "description": "JSQ1", + "offset": 8, + "size": 5 + }, + "JEXTEN": { + "description": "JEXTEN", + "offset": 6, + "size": 2 + }, + "JEXTSEL": { + "description": "JEXTSEL", + "offset": 2, + "size": 4 + }, + "JL": { + "description": "JL", + "offset": 0, + "size": 2 + } + } + } + }, + "OFR1": { + "description": "offset register 1", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OFFSET1_EN": { + "description": "OFFSET1_EN", + "offset": 31, + "size": 1 + }, + "OFFSET1_CH": { + "description": "OFFSET1_CH", + "offset": 26, + "size": 5 + }, + "OFFSET1": { + "description": "OFFSET1", + "offset": 0, + "size": 12 + } + } + } + }, + "OFR2": { + "description": "offset register 2", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OFFSET2_EN": { + "description": "OFFSET2_EN", + "offset": 31, + "size": 1 + }, + "OFFSET2_CH": { + "description": "OFFSET2_CH", + "offset": 26, + "size": 5 + }, + "OFFSET2": { + "description": "OFFSET2", + "offset": 0, + "size": 12 + } + } + } + }, + "OFR3": { + "description": "offset register 3", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OFFSET3_EN": { + "description": "OFFSET3_EN", + "offset": 31, + "size": 1 + }, + "OFFSET3_CH": { + "description": "OFFSET3_CH", + "offset": 26, + "size": 5 + }, + "OFFSET3": { + "description": "OFFSET3", + "offset": 0, + "size": 12 + } + } + } + }, + "OFR4": { + "description": "offset register 4", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OFFSET4_EN": { + "description": "OFFSET4_EN", + "offset": 31, + "size": 1 + }, + "OFFSET4_CH": { + "description": "OFFSET4_CH", + "offset": 26, + "size": 5 + }, + "OFFSET4": { + "description": "OFFSET4", + "offset": 0, + "size": 12 + } + } + } + }, + "JDR1": { + "description": "injected data register 1", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA1": { + "description": "JDATA1", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR2": { + "description": "injected data register 2", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA2": { + "description": "JDATA2", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR3": { + "description": "injected data register 3", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA3": { + "description": "JDATA3", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR4": { + "description": "injected data register 4", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA4": { + "description": "JDATA4", + "offset": 0, + "size": 16 + } + } + } + }, + "AWD2CR": { + "description": "Analog Watchdog 2 Configuration\n Register", + "offset": 160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AWD2CH": { + "description": "AWD2CH", + "offset": 1, + "size": 18 + } + } + } + }, + "AWD3CR": { + "description": "Analog Watchdog 3 Configuration\n Register", + "offset": 164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AWD3CH": { + "description": "AWD3CH", + "offset": 1, + "size": 18 + } + } + } + }, + "DIFSEL": { + "description": "Differential Mode Selection Register\n 2", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIFSEL_1_15": { + "description": "Differential mode for channels 15 to\n 1", + "offset": 1, + "size": 15 + }, + "DIFSEL_16_18": { + "description": "Differential mode for channels 18 to\n 16", + "offset": 16, + "size": 3, + "access": "read-only" + } + } + } + }, + "CALFACT": { + "description": "Calibration Factors", + "offset": 180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CALFACT_D": { + "description": "CALFACT_D", + "offset": 16, + "size": 7 + }, + "CALFACT_S": { + "description": "CALFACT_S", + "offset": 0, + "size": 7 + } + } + } + } + } + } + }, + "TIM8": { + "description": "Advanced-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + }, + "OIS2N": { + "description": "Output Idle state 2", + "offset": 11, + "size": 1 + }, + "OIS3": { + "description": "Output Idle state 3", + "offset": 12, + "size": 1 + }, + "OIS3N": { + "description": "Output Idle state 3", + "offset": 13, + "size": 1 + }, + "OIS4": { + "description": "Output Idle state 4", + "offset": 14, + "size": 1 + }, + "OIS5": { + "description": "Output Idle state 5", + "offset": 16, + "size": 1 + }, + "OIS6": { + "description": "Output Idle state 6", + "offset": 18, + "size": 1 + }, + "MMS2": { + "description": "Master mode selection 2", + "offset": 20, + "size": 4 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + }, + "OCCS": { + "description": "OCREF clear selection", + "offset": 3, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "SMS3": { + "description": "Slave mode selection bit 3", + "offset": 16, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "B2IF": { + "description": "Break 2 interrupt flag", + "offset": 8, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "C5IF": { + "description": "Capture/Compare 5 interrupt\n flag", + "offset": 16, + "size": 1 + }, + "C6IF": { + "description": "Capture/Compare 6 interrupt\n flag", + "offset": 17, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "B2G": { + "description": "Break 2 generation", + "offset": 8, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output Compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output Compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1M_3": { + "description": "Output Compare 1 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC2M_3": { + "description": "Output Compare 2 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC4CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + }, + "OC3M_3": { + "description": "Output Compare 3 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC4M_3": { + "description": "Output Compare 4 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2NE": { + "description": "Capture/Compare 2 complementary output\n enable", + "offset": 6, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3NE": { + "description": "Capture/Compare 3 complementary output\n enable", + "offset": 10, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC5E": { + "description": "Capture/Compare 5 output\n enable", + "offset": 16, + "size": 1 + }, + "CC5P": { + "description": "Capture/Compare 5 output\n Polarity", + "offset": 17, + "size": 1 + }, + "CC6E": { + "description": "Capture/Compare 6 output\n enable", + "offset": 20, + "size": 1 + }, + "CC6P": { + "description": "Capture/Compare 6 output\n Polarity", + "offset": 21, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare 3 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare 3 value", + "offset": 0, + "size": 16 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "BKF": { + "description": "Break filter", + "offset": 16, + "size": 4 + }, + "BK2F": { + "description": "Break 2 filter", + "offset": 20, + "size": 4 + }, + "BK2E": { + "description": "Break 2 enable", + "offset": 24, + "size": 1 + }, + "BK2P": { + "description": "Break 2 polarity", + "offset": 25, + "size": 1 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "CCMR3_Output": { + "description": "capture/compare mode register 3 (output\n mode)", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC5FE": { + "description": "Output compare 5 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC5PE": { + "description": "Output compare 5 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC5M": { + "description": "Output compare 5 mode", + "offset": 4, + "size": 3 + }, + "OC5CE": { + "description": "Output compare 5 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC6FE": { + "description": "Output compare 6 fast\n enable", + "offset": 10, + "size": 1 + }, + "OC6PE": { + "description": "Output compare 6 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC6M": { + "description": "Output compare 6 mode", + "offset": 12, + "size": 3 + }, + "OC6CE": { + "description": "Output compare 6 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC5M_3": { + "description": "Outout Compare 5 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC6M_3": { + "description": "Outout Compare 6 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCR5": { + "description": "capture/compare register 5", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR5": { + "description": "Capture/Compare 5 value", + "offset": 0, + "size": 16 + }, + "GC5C1": { + "description": "Group Channel 5 and Channel\n 1", + "offset": 29, + "size": 1 + }, + "GC5C2": { + "description": "Group Channel 5 and Channel\n 2", + "offset": 30, + "size": 1 + }, + "GC5C3": { + "description": "Group Channel 5 and Channel\n 3", + "offset": 31, + "size": 1 + } + } + } + }, + "CCR6": { + "description": "capture/compare register 6", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR6": { + "description": "Capture/Compare 6 value", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "option registers", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM8_ETR_ADC2_RMP": { + "description": "TIM8_ETR_ADC2 remapping\n capability", + "offset": 0, + "size": 2 + }, + "TIM8_ETR_ADC3_RMP": { + "description": "TIM8_ETR_ADC3 remapping\n capability", + "offset": 2, + "size": 2 + } + } + } + } + } + } + }, + "DAC": { + "description": "Digital-to-analog converter", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDRIE2": { + "description": "DAC channel2 DMA underrun interrupt\n enable", + "offset": 29, + "size": 1 + }, + "DMAEN2": { + "description": "DAC channel2 DMA enable", + "offset": 28, + "size": 1 + }, + "MAMP2": { + "description": "DAC channel2 mask/amplitude\n selector", + "offset": 24, + "size": 4 + }, + "WAVE2": { + "description": "DAC channel2 noise/triangle wave\n generation enable", + "offset": 22, + "size": 2 + }, + "TSEL2": { + "description": "DAC channel2 trigger\n selection", + "offset": 19, + "size": 3 + }, + "TEN2": { + "description": "DAC channel2 trigger\n enable", + "offset": 18, + "size": 1 + }, + "BOFF2": { + "description": "DAC channel2 output buffer\n disable", + "offset": 17, + "size": 1 + }, + "EN2": { + "description": "DAC channel2 enable", + "offset": 16, + "size": 1 + }, + "DMAUDRIE1": { + "description": "DAC channel1 DMA Underrun Interrupt\n enable", + "offset": 13, + "size": 1 + }, + "DMAEN1": { + "description": "DAC channel1 DMA enable", + "offset": 12, + "size": 1 + }, + "MAMP1": { + "description": "DAC channel1 mask/amplitude\n selector", + "offset": 8, + "size": 4 + }, + "WAVE1": { + "description": "DAC channel1 noise/triangle wave\n generation enable", + "offset": 6, + "size": 2 + }, + "TSEL1": { + "description": "DAC channel1 trigger\n selection", + "offset": 3, + "size": 3 + }, + "TEN1": { + "description": "DAC channel1 trigger\n enable", + "offset": 2, + "size": 1 + }, + "BOFF1": { + "description": "DAC channel1 output buffer\n disable", + "offset": 1, + "size": 1 + }, + "EN1": { + "description": "DAC channel1 enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SWTRIGR": { + "description": "software trigger register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SWTRIG2": { + "description": "DAC channel2 software\n trigger", + "offset": 1, + "size": 1 + }, + "SWTRIG1": { + "description": "DAC channel1 software\n trigger", + "offset": 0, + "size": 1 + } + } + } + }, + "DHR12R1": { + "description": "channel1 12-bit right-aligned data holding\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L1": { + "description": "channel1 12-bit left aligned data holding\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R1": { + "description": "channel1 8-bit right aligned data holding\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12R2": { + "description": "channel2 12-bit right aligned data holding\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L2": { + "description": "channel2 12-bit left aligned data holding\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R2": { + "description": "channel2 8-bit right-aligned data holding\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12RD": { + "description": "Dual DAC 12-bit right-aligned data holding\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 16, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12LD": { + "description": "DUAL DAC 12-bit left aligned data holding\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 20, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8RD": { + "description": "DUAL DAC 8-bit right aligned data holding\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 8, + "size": 8 + }, + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DOR1": { + "description": "channel1 data output register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC1DOR": { + "description": "DAC channel1 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "DOR2": { + "description": "channel2 data output register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC2DOR": { + "description": "DAC channel2 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDR2": { + "description": "DAC channel2 DMA underrun\n flag", + "offset": 29, + "size": 1 + }, + "DMAUDR1": { + "description": "DAC channel1 DMA underrun\n flag", + "offset": 13, + "size": 1 + } + } + } + } + } + } + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "children": { + "registers": { + "IMR1": { + "description": "Interrupt mask register", + "offset": 0, + "size": 32, + "reset_value": 528482304, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Interrupt Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Interrupt Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Interrupt Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Interrupt Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Interrupt Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Interrupt Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Interrupt Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Interrupt Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Interrupt Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Interrupt Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Interrupt Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Interrupt Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Interrupt Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Interrupt Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Interrupt Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Interrupt Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Interrupt Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Interrupt Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Interrupt Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Interrupt Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Interrupt Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Interrupt Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Interrupt Mask on line 22", + "offset": 22, + "size": 1 + }, + "MR23": { + "description": "Interrupt Mask on line 23", + "offset": 23, + "size": 1 + }, + "MR24": { + "description": "Interrupt Mask on line 24", + "offset": 24, + "size": 1 + }, + "MR25": { + "description": "Interrupt Mask on line 25", + "offset": 25, + "size": 1 + }, + "MR26": { + "description": "Interrupt Mask on line 26", + "offset": 26, + "size": 1 + }, + "MR27": { + "description": "Interrupt Mask on line 27", + "offset": 27, + "size": 1 + }, + "MR28": { + "description": "Interrupt Mask on line 28", + "offset": 28, + "size": 1 + }, + "MR29": { + "description": "Interrupt Mask on line 29", + "offset": 29, + "size": 1 + }, + "MR30": { + "description": "Interrupt Mask on line 30", + "offset": 30, + "size": 1 + }, + "MR31": { + "description": "Interrupt Mask on line 31", + "offset": 31, + "size": 1 + } + } + } + }, + "EMR1": { + "description": "Event mask register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Event Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Event Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Event Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Event Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Event Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Event Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Event Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Event Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Event Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Event Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Event Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Event Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Event Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Event Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Event Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Event Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Event Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Event Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Event Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Event Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Event Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Event Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Event Mask on line 22", + "offset": 22, + "size": 1 + }, + "MR23": { + "description": "Event Mask on line 23", + "offset": 23, + "size": 1 + }, + "MR24": { + "description": "Event Mask on line 24", + "offset": 24, + "size": 1 + }, + "MR25": { + "description": "Event Mask on line 25", + "offset": 25, + "size": 1 + }, + "MR26": { + "description": "Event Mask on line 26", + "offset": 26, + "size": 1 + }, + "MR27": { + "description": "Event Mask on line 27", + "offset": 27, + "size": 1 + }, + "MR28": { + "description": "Event Mask on line 28", + "offset": 28, + "size": 1 + }, + "MR29": { + "description": "Event Mask on line 29", + "offset": 29, + "size": 1 + }, + "MR30": { + "description": "Event Mask on line 30", + "offset": 30, + "size": 1 + }, + "MR31": { + "description": "Event Mask on line 31", + "offset": 31, + "size": 1 + } + } + } + }, + "RTSR1": { + "description": "Rising Trigger selection\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Rising trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Rising trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Rising trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Rising trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Rising trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Rising trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Rising trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Rising trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Rising trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Rising trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Rising trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Rising trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Rising trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Rising trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Rising trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Rising trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Rising trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Rising trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Rising trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Rising trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Rising trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Rising trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Rising trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + }, + "TR29": { + "description": "Rising trigger event configuration of\n line 29", + "offset": 29, + "size": 1 + }, + "TR30": { + "description": "Rising trigger event configuration of\n line 30", + "offset": 30, + "size": 1 + }, + "TR31": { + "description": "Rising trigger event configuration of\n line 31", + "offset": 31, + "size": 1 + } + } + } + }, + "FTSR1": { + "description": "Falling Trigger selection\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Falling trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Falling trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Falling trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Falling trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Falling trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Falling trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Falling trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Falling trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Falling trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Falling trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Falling trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Falling trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Falling trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Falling trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Falling trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Falling trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Falling trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Falling trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Falling trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Falling trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Falling trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Falling trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Falling trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + }, + "TR29": { + "description": "Falling trigger event configuration of\n line 29", + "offset": 29, + "size": 1 + }, + "TR30": { + "description": "Falling trigger event configuration of\n line 30.", + "offset": 30, + "size": 1 + }, + "TR31": { + "description": "Falling trigger event configuration of\n line 31", + "offset": 31, + "size": 1 + } + } + } + }, + "SWIER1": { + "description": "Software interrupt event\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIER0": { + "description": "Software Interrupt on line\n 0", + "offset": 0, + "size": 1 + }, + "SWIER1": { + "description": "Software Interrupt on line\n 1", + "offset": 1, + "size": 1 + }, + "SWIER2": { + "description": "Software Interrupt on line\n 2", + "offset": 2, + "size": 1 + }, + "SWIER3": { + "description": "Software Interrupt on line\n 3", + "offset": 3, + "size": 1 + }, + "SWIER4": { + "description": "Software Interrupt on line\n 4", + "offset": 4, + "size": 1 + }, + "SWIER5": { + "description": "Software Interrupt on line\n 5", + "offset": 5, + "size": 1 + }, + "SWIER6": { + "description": "Software Interrupt on line\n 6", + "offset": 6, + "size": 1 + }, + "SWIER7": { + "description": "Software Interrupt on line\n 7", + "offset": 7, + "size": 1 + }, + "SWIER8": { + "description": "Software Interrupt on line\n 8", + "offset": 8, + "size": 1 + }, + "SWIER9": { + "description": "Software Interrupt on line\n 9", + "offset": 9, + "size": 1 + }, + "SWIER10": { + "description": "Software Interrupt on line\n 10", + "offset": 10, + "size": 1 + }, + "SWIER11": { + "description": "Software Interrupt on line\n 11", + "offset": 11, + "size": 1 + }, + "SWIER12": { + "description": "Software Interrupt on line\n 12", + "offset": 12, + "size": 1 + }, + "SWIER13": { + "description": "Software Interrupt on line\n 13", + "offset": 13, + "size": 1 + }, + "SWIER14": { + "description": "Software Interrupt on line\n 14", + "offset": 14, + "size": 1 + }, + "SWIER15": { + "description": "Software Interrupt on line\n 15", + "offset": 15, + "size": 1 + }, + "SWIER16": { + "description": "Software Interrupt on line\n 16", + "offset": 16, + "size": 1 + }, + "SWIER17": { + "description": "Software Interrupt on line\n 17", + "offset": 17, + "size": 1 + }, + "SWIER18": { + "description": "Software Interrupt on line\n 18", + "offset": 18, + "size": 1 + }, + "SWIER19": { + "description": "Software Interrupt on line\n 19", + "offset": 19, + "size": 1 + }, + "SWIER20": { + "description": "Software Interrupt on line\n 20", + "offset": 20, + "size": 1 + }, + "SWIER21": { + "description": "Software Interrupt on line\n 21", + "offset": 21, + "size": 1 + }, + "SWIER22": { + "description": "Software Interrupt on line\n 22", + "offset": 22, + "size": 1 + }, + "SWIER29": { + "description": "Software Interrupt on line\n 29", + "offset": 29, + "size": 1 + }, + "SWIER30": { + "description": "Software Interrupt on line\n 309", + "offset": 30, + "size": 1 + }, + "SWIER31": { + "description": "Software Interrupt on line\n 319", + "offset": 31, + "size": 1 + } + } + } + }, + "PR1": { + "description": "Pending register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR0": { + "description": "Pending bit 0", + "offset": 0, + "size": 1 + }, + "PR1": { + "description": "Pending bit 1", + "offset": 1, + "size": 1 + }, + "PR2": { + "description": "Pending bit 2", + "offset": 2, + "size": 1 + }, + "PR3": { + "description": "Pending bit 3", + "offset": 3, + "size": 1 + }, + "PR4": { + "description": "Pending bit 4", + "offset": 4, + "size": 1 + }, + "PR5": { + "description": "Pending bit 5", + "offset": 5, + "size": 1 + }, + "PR6": { + "description": "Pending bit 6", + "offset": 6, + "size": 1 + }, + "PR7": { + "description": "Pending bit 7", + "offset": 7, + "size": 1 + }, + "PR8": { + "description": "Pending bit 8", + "offset": 8, + "size": 1 + }, + "PR9": { + "description": "Pending bit 9", + "offset": 9, + "size": 1 + }, + "PR10": { + "description": "Pending bit 10", + "offset": 10, + "size": 1 + }, + "PR11": { + "description": "Pending bit 11", + "offset": 11, + "size": 1 + }, + "PR12": { + "description": "Pending bit 12", + "offset": 12, + "size": 1 + }, + "PR13": { + "description": "Pending bit 13", + "offset": 13, + "size": 1 + }, + "PR14": { + "description": "Pending bit 14", + "offset": 14, + "size": 1 + }, + "PR15": { + "description": "Pending bit 15", + "offset": 15, + "size": 1 + }, + "PR16": { + "description": "Pending bit 16", + "offset": 16, + "size": 1 + }, + "PR17": { + "description": "Pending bit 17", + "offset": 17, + "size": 1 + }, + "PR18": { + "description": "Pending bit 18", + "offset": 18, + "size": 1 + }, + "PR19": { + "description": "Pending bit 19", + "offset": 19, + "size": 1 + }, + "PR20": { + "description": "Pending bit 20", + "offset": 20, + "size": 1 + }, + "PR21": { + "description": "Pending bit 21", + "offset": 21, + "size": 1 + }, + "PR22": { + "description": "Pending bit 22", + "offset": 22, + "size": 1 + }, + "PR29": { + "description": "Pending bit 29", + "offset": 29, + "size": 1 + }, + "PR30": { + "description": "Pending bit 30", + "offset": 30, + "size": 1 + }, + "PR31": { + "description": "Pending bit 31", + "offset": 31, + "size": 1 + } + } + } + }, + "IMR2": { + "description": "Interrupt mask register", + "offset": 24, + "size": 32, + "reset_value": 4294967292, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR32": { + "description": "Interrupt Mask on external/internal line\n 32", + "offset": 0, + "size": 1 + }, + "MR33": { + "description": "Interrupt Mask on external/internal line\n 33", + "offset": 1, + "size": 1 + }, + "MR34": { + "description": "Interrupt Mask on external/internal line\n 34", + "offset": 2, + "size": 1 + }, + "MR35": { + "description": "Interrupt Mask on external/internal line\n 35", + "offset": 3, + "size": 1 + } + } + } + }, + "EMR2": { + "description": "Event mask register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR32": { + "description": "Event mask on external/internal line\n 32", + "offset": 0, + "size": 1 + }, + "MR33": { + "description": "Event mask on external/internal line\n 33", + "offset": 1, + "size": 1 + }, + "MR34": { + "description": "Event mask on external/internal line\n 34", + "offset": 2, + "size": 1 + }, + "MR35": { + "description": "Event mask on external/internal line\n 35", + "offset": 3, + "size": 1 + } + } + } + }, + "RTSR2": { + "description": "Rising Trigger selection\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR32": { + "description": "Rising trigger event configuration bit\n of line 32", + "offset": 0, + "size": 1 + }, + "TR33": { + "description": "Rising trigger event configuration bit\n of line 33", + "offset": 1, + "size": 1 + } + } + } + }, + "FTSR2": { + "description": "Falling Trigger selection\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR32": { + "description": "Falling trigger event configuration bit\n of line 32", + "offset": 0, + "size": 1 + }, + "TR33": { + "description": "Falling trigger event configuration bit\n of line 33", + "offset": 1, + "size": 1 + } + } + } + }, + "SWIER2": { + "description": "Software interrupt event\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIER32": { + "description": "Software interrupt on line\n 32", + "offset": 0, + "size": 1 + }, + "SWIER33": { + "description": "Software interrupt on line\n 33", + "offset": 1, + "size": 1 + } + } + } + }, + "PR2": { + "description": "Pending register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR32": { + "description": "Pending bit on line 32", + "offset": 0, + "size": 1 + }, + "PR33": { + "description": "Pending bit on line 33", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "PWR": { + "description": "Power control", + "children": { + "registers": { + "CR": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LPDS": { + "description": "Low-power deep sleep", + "offset": 0, + "size": 1 + }, + "PDDS": { + "description": "Power down deepsleep", + "offset": 1, + "size": 1 + }, + "CWUF": { + "description": "Clear wakeup flag", + "offset": 2, + "size": 1 + }, + "CSBF": { + "description": "Clear standby flag", + "offset": 3, + "size": 1 + }, + "PVDE": { + "description": "Power voltage detector\n enable", + "offset": 4, + "size": 1 + }, + "PLS": { + "description": "PVD level selection", + "offset": 5, + "size": 3 + }, + "DBP": { + "description": "Disable backup domain write\n protection", + "offset": 8, + "size": 1 + } + } + } + }, + "CSR": { + "description": "power control/status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUF": { + "description": "Wakeup flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SBF": { + "description": "Standby flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PVDO": { + "description": "PVD output", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "EWUP1": { + "description": "Enable WKUP1 pin", + "offset": 8, + "size": 1 + }, + "EWUP2": { + "description": "Enable WKUP2 pin", + "offset": 9, + "size": 1 + } + } + } + } + } + } + }, + "CAN": { + "description": "Controller area network", + "children": { + "registers": { + "MCR": { + "description": "master control register", + "offset": 0, + "size": 32, + "reset_value": 65538, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBF": { + "description": "DBF", + "offset": 16, + "size": 1 + }, + "RESET": { + "description": "RESET", + "offset": 15, + "size": 1 + }, + "TTCM": { + "description": "TTCM", + "offset": 7, + "size": 1 + }, + "ABOM": { + "description": "ABOM", + "offset": 6, + "size": 1 + }, + "AWUM": { + "description": "AWUM", + "offset": 5, + "size": 1 + }, + "NART": { + "description": "NART", + "offset": 4, + "size": 1 + }, + "RFLM": { + "description": "RFLM", + "offset": 3, + "size": 1 + }, + "TXFP": { + "description": "TXFP", + "offset": 2, + "size": 1 + }, + "SLEEP": { + "description": "SLEEP", + "offset": 1, + "size": 1 + }, + "INRQ": { + "description": "INRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "MSR": { + "description": "master status register", + "offset": 4, + "size": 32, + "reset_value": 3074, + "reset_mask": 4294967295, + "children": { + "fields": { + "RX": { + "description": "RX", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "SAMP": { + "description": "SAMP", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "RXM": { + "description": "RXM", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "TXM": { + "description": "TXM", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "SLAKI": { + "description": "SLAKI", + "offset": 4, + "size": 1 + }, + "WKUI": { + "description": "WKUI", + "offset": 3, + "size": 1 + }, + "ERRI": { + "description": "ERRI", + "offset": 2, + "size": 1 + }, + "SLAK": { + "description": "SLAK", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "INAK": { + "description": "INAK", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "TSR": { + "description": "transmit status register", + "offset": 8, + "size": 32, + "reset_value": 469762048, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOW2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 31, + "size": 1, + "access": "read-only" + }, + "LOW1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOW0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "TME2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TME1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "TME0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CODE": { + "description": "CODE", + "offset": 24, + "size": 2, + "access": "read-only" + }, + "ABRQ2": { + "description": "ABRQ2", + "offset": 23, + "size": 1 + }, + "TERR2": { + "description": "TERR2", + "offset": 19, + "size": 1 + }, + "ALST2": { + "description": "ALST2", + "offset": 18, + "size": 1 + }, + "TXOK2": { + "description": "TXOK2", + "offset": 17, + "size": 1 + }, + "RQCP2": { + "description": "RQCP2", + "offset": 16, + "size": 1 + }, + "ABRQ1": { + "description": "ABRQ1", + "offset": 15, + "size": 1 + }, + "TERR1": { + "description": "TERR1", + "offset": 11, + "size": 1 + }, + "ALST1": { + "description": "ALST1", + "offset": 10, + "size": 1 + }, + "TXOK1": { + "description": "TXOK1", + "offset": 9, + "size": 1 + }, + "RQCP1": { + "description": "RQCP1", + "offset": 8, + "size": 1 + }, + "ABRQ0": { + "description": "ABRQ0", + "offset": 7, + "size": 1 + }, + "TERR0": { + "description": "TERR0", + "offset": 3, + "size": 1 + }, + "ALST0": { + "description": "ALST0", + "offset": 2, + "size": 1 + }, + "TXOK0": { + "description": "TXOK0", + "offset": 1, + "size": 1 + }, + "RQCP0": { + "description": "RQCP0", + "offset": 0, + "size": 1 + } + } + } + }, + "RF0R": { + "description": "receive FIFO 0 register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM0": { + "description": "RFOM0", + "offset": 5, + "size": 1 + }, + "FOVR0": { + "description": "FOVR0", + "offset": 4, + "size": 1 + }, + "FULL0": { + "description": "FULL0", + "offset": 3, + "size": 1 + }, + "FMP0": { + "description": "FMP0", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "RF1R": { + "description": "receive FIFO 1 register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM1": { + "description": "RFOM1", + "offset": 5, + "size": 1 + }, + "FOVR1": { + "description": "FOVR1", + "offset": 4, + "size": 1 + }, + "FULL1": { + "description": "FULL1", + "offset": 3, + "size": 1 + }, + "FMP1": { + "description": "FMP1", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLKIE": { + "description": "SLKIE", + "offset": 17, + "size": 1 + }, + "WKUIE": { + "description": "WKUIE", + "offset": 16, + "size": 1 + }, + "ERRIE": { + "description": "ERRIE", + "offset": 15, + "size": 1 + }, + "LECIE": { + "description": "LECIE", + "offset": 11, + "size": 1 + }, + "BOFIE": { + "description": "BOFIE", + "offset": 10, + "size": 1 + }, + "EPVIE": { + "description": "EPVIE", + "offset": 9, + "size": 1 + }, + "EWGIE": { + "description": "EWGIE", + "offset": 8, + "size": 1 + }, + "FOVIE1": { + "description": "FOVIE1", + "offset": 6, + "size": 1 + }, + "FFIE1": { + "description": "FFIE1", + "offset": 5, + "size": 1 + }, + "FMPIE1": { + "description": "FMPIE1", + "offset": 4, + "size": 1 + }, + "FOVIE0": { + "description": "FOVIE0", + "offset": 3, + "size": 1 + }, + "FFIE0": { + "description": "FFIE0", + "offset": 2, + "size": 1 + }, + "FMPIE0": { + "description": "FMPIE0", + "offset": 1, + "size": 1 + }, + "TMEIE": { + "description": "TMEIE", + "offset": 0, + "size": 1 + } + } + } + }, + "ESR": { + "description": "error status register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REC": { + "description": "REC", + "offset": 24, + "size": 8, + "access": "read-only" + }, + "TEC": { + "description": "TEC", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "LEC": { + "description": "LEC", + "offset": 4, + "size": 3 + }, + "BOFF": { + "description": "BOFF", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "EPVF": { + "description": "EPVF", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "EWGF": { + "description": "EWGF", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "BTR": { + "description": "bit timing register", + "offset": 28, + "size": 32, + "reset_value": 19070976, + "reset_mask": 4294967295, + "children": { + "fields": { + "SILM": { + "description": "SILM", + "offset": 31, + "size": 1 + }, + "LBKM": { + "description": "LBKM", + "offset": 30, + "size": 1 + }, + "SJW": { + "description": "SJW", + "offset": 24, + "size": 2 + }, + "TS2": { + "description": "TS2", + "offset": 20, + "size": 3 + }, + "TS1": { + "description": "TS1", + "offset": 16, + "size": 4 + }, + "BRP": { + "description": "BRP", + "offset": 0, + "size": 10 + } + } + } + }, + "TI0R": { + "description": "TX mailbox identifier register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT0R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL0R": { + "description": "mailbox data low register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH0R": { + "description": "mailbox data high register", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "TI1R": { + "description": "TX mailbox identifier register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT1R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL1R": { + "description": "mailbox data low register", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH1R": { + "description": "mailbox data high register", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "TI2R": { + "description": "TX mailbox identifier register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT2R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL2R": { + "description": "mailbox data low register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH2R": { + "description": "mailbox data high register", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "RI0R": { + "description": "receive FIFO mailbox identifier\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + } + } + } + }, + "RDT0R": { + "description": "receive FIFO mailbox data length control and\n time stamp register", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "FMI": { + "description": "FMI", + "offset": 8, + "size": 8 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "RDL0R": { + "description": "receive FIFO mailbox data low\n register", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "RDH0R": { + "description": "receive FIFO mailbox data high\n register", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "RI1R": { + "description": "receive FIFO mailbox identifier\n register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + } + } + } + }, + "RDT1R": { + "description": "receive FIFO mailbox data length control and\n time stamp register", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "FMI": { + "description": "FMI", + "offset": 8, + "size": 8 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "RDL1R": { + "description": "receive FIFO mailbox data low\n register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "RDH1R": { + "description": "receive FIFO mailbox data high\n register", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "FMR": { + "description": "filter master register", + "offset": 512, + "size": 32, + "reset_value": 706481665, + "reset_mask": 4294967295, + "children": { + "fields": { + "CAN2SB": { + "description": "CAN2 start bank", + "offset": 8, + "size": 6 + }, + "FINIT": { + "description": "Filter init mode", + "offset": 0, + "size": 1 + } + } + } + }, + "FM1R": { + "description": "filter mode register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FBM0": { + "description": "Filter mode", + "offset": 0, + "size": 1 + }, + "FBM1": { + "description": "Filter mode", + "offset": 1, + "size": 1 + }, + "FBM2": { + "description": "Filter mode", + "offset": 2, + "size": 1 + }, + "FBM3": { + "description": "Filter mode", + "offset": 3, + "size": 1 + }, + "FBM4": { + "description": "Filter mode", + "offset": 4, + "size": 1 + }, + "FBM5": { + "description": "Filter mode", + "offset": 5, + "size": 1 + }, + "FBM6": { + "description": "Filter mode", + "offset": 6, + "size": 1 + }, + "FBM7": { + "description": "Filter mode", + "offset": 7, + "size": 1 + }, + "FBM8": { + "description": "Filter mode", + "offset": 8, + "size": 1 + }, + "FBM9": { + "description": "Filter mode", + "offset": 9, + "size": 1 + }, + "FBM10": { + "description": "Filter mode", + "offset": 10, + "size": 1 + }, + "FBM11": { + "description": "Filter mode", + "offset": 11, + "size": 1 + }, + "FBM12": { + "description": "Filter mode", + "offset": 12, + "size": 1 + }, + "FBM13": { + "description": "Filter mode", + "offset": 13, + "size": 1 + }, + "FBM14": { + "description": "Filter mode", + "offset": 14, + "size": 1 + }, + "FBM15": { + "description": "Filter mode", + "offset": 15, + "size": 1 + }, + "FBM16": { + "description": "Filter mode", + "offset": 16, + "size": 1 + }, + "FBM17": { + "description": "Filter mode", + "offset": 17, + "size": 1 + }, + "FBM18": { + "description": "Filter mode", + "offset": 18, + "size": 1 + }, + "FBM19": { + "description": "Filter mode", + "offset": 19, + "size": 1 + }, + "FBM20": { + "description": "Filter mode", + "offset": 20, + "size": 1 + }, + "FBM21": { + "description": "Filter mode", + "offset": 21, + "size": 1 + }, + "FBM22": { + "description": "Filter mode", + "offset": 22, + "size": 1 + }, + "FBM23": { + "description": "Filter mode", + "offset": 23, + "size": 1 + }, + "FBM24": { + "description": "Filter mode", + "offset": 24, + "size": 1 + }, + "FBM25": { + "description": "Filter mode", + "offset": 25, + "size": 1 + }, + "FBM26": { + "description": "Filter mode", + "offset": 26, + "size": 1 + }, + "FBM27": { + "description": "Filter mode", + "offset": 27, + "size": 1 + } + } + } + }, + "FS1R": { + "description": "filter scale register", + "offset": 524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSC0": { + "description": "Filter scale configuration", + "offset": 0, + "size": 1 + }, + "FSC1": { + "description": "Filter scale configuration", + "offset": 1, + "size": 1 + }, + "FSC2": { + "description": "Filter scale configuration", + "offset": 2, + "size": 1 + }, + "FSC3": { + "description": "Filter scale configuration", + "offset": 3, + "size": 1 + }, + "FSC4": { + "description": "Filter scale configuration", + "offset": 4, + "size": 1 + }, + "FSC5": { + "description": "Filter scale configuration", + "offset": 5, + "size": 1 + }, + "FSC6": { + "description": "Filter scale configuration", + "offset": 6, + "size": 1 + }, + "FSC7": { + "description": "Filter scale configuration", + "offset": 7, + "size": 1 + }, + "FSC8": { + "description": "Filter scale configuration", + "offset": 8, + "size": 1 + }, + "FSC9": { + "description": "Filter scale configuration", + "offset": 9, + "size": 1 + }, + "FSC10": { + "description": "Filter scale configuration", + "offset": 10, + "size": 1 + }, + "FSC11": { + "description": "Filter scale configuration", + "offset": 11, + "size": 1 + }, + "FSC12": { + "description": "Filter scale configuration", + "offset": 12, + "size": 1 + }, + "FSC13": { + "description": "Filter scale configuration", + "offset": 13, + "size": 1 + }, + "FSC14": { + "description": "Filter scale configuration", + "offset": 14, + "size": 1 + }, + "FSC15": { + "description": "Filter scale configuration", + "offset": 15, + "size": 1 + }, + "FSC16": { + "description": "Filter scale configuration", + "offset": 16, + "size": 1 + }, + "FSC17": { + "description": "Filter scale configuration", + "offset": 17, + "size": 1 + }, + "FSC18": { + "description": "Filter scale configuration", + "offset": 18, + "size": 1 + }, + "FSC19": { + "description": "Filter scale configuration", + "offset": 19, + "size": 1 + }, + "FSC20": { + "description": "Filter scale configuration", + "offset": 20, + "size": 1 + }, + "FSC21": { + "description": "Filter scale configuration", + "offset": 21, + "size": 1 + }, + "FSC22": { + "description": "Filter scale configuration", + "offset": 22, + "size": 1 + }, + "FSC23": { + "description": "Filter scale configuration", + "offset": 23, + "size": 1 + }, + "FSC24": { + "description": "Filter scale configuration", + "offset": 24, + "size": 1 + }, + "FSC25": { + "description": "Filter scale configuration", + "offset": 25, + "size": 1 + }, + "FSC26": { + "description": "Filter scale configuration", + "offset": 26, + "size": 1 + }, + "FSC27": { + "description": "Filter scale configuration", + "offset": 27, + "size": 1 + } + } + } + }, + "FFA1R": { + "description": "filter FIFO assignment\n register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FFA0": { + "description": "Filter FIFO assignment for filter\n 0", + "offset": 0, + "size": 1 + }, + "FFA1": { + "description": "Filter FIFO assignment for filter\n 1", + "offset": 1, + "size": 1 + }, + "FFA2": { + "description": "Filter FIFO assignment for filter\n 2", + "offset": 2, + "size": 1 + }, + "FFA3": { + "description": "Filter FIFO assignment for filter\n 3", + "offset": 3, + "size": 1 + }, + "FFA4": { + "description": "Filter FIFO assignment for filter\n 4", + "offset": 4, + "size": 1 + }, + "FFA5": { + "description": "Filter FIFO assignment for filter\n 5", + "offset": 5, + "size": 1 + }, + "FFA6": { + "description": "Filter FIFO assignment for filter\n 6", + "offset": 6, + "size": 1 + }, + "FFA7": { + "description": "Filter FIFO assignment for filter\n 7", + "offset": 7, + "size": 1 + }, + "FFA8": { + "description": "Filter FIFO assignment for filter\n 8", + "offset": 8, + "size": 1 + }, + "FFA9": { + "description": "Filter FIFO assignment for filter\n 9", + "offset": 9, + "size": 1 + }, + "FFA10": { + "description": "Filter FIFO assignment for filter\n 10", + "offset": 10, + "size": 1 + }, + "FFA11": { + "description": "Filter FIFO assignment for filter\n 11", + "offset": 11, + "size": 1 + }, + "FFA12": { + "description": "Filter FIFO assignment for filter\n 12", + "offset": 12, + "size": 1 + }, + "FFA13": { + "description": "Filter FIFO assignment for filter\n 13", + "offset": 13, + "size": 1 + }, + "FFA14": { + "description": "Filter FIFO assignment for filter\n 14", + "offset": 14, + "size": 1 + }, + "FFA15": { + "description": "Filter FIFO assignment for filter\n 15", + "offset": 15, + "size": 1 + }, + "FFA16": { + "description": "Filter FIFO assignment for filter\n 16", + "offset": 16, + "size": 1 + }, + "FFA17": { + "description": "Filter FIFO assignment for filter\n 17", + "offset": 17, + "size": 1 + }, + "FFA18": { + "description": "Filter FIFO assignment for filter\n 18", + "offset": 18, + "size": 1 + }, + "FFA19": { + "description": "Filter FIFO assignment for filter\n 19", + "offset": 19, + "size": 1 + }, + "FFA20": { + "description": "Filter FIFO assignment for filter\n 20", + "offset": 20, + "size": 1 + }, + "FFA21": { + "description": "Filter FIFO assignment for filter\n 21", + "offset": 21, + "size": 1 + }, + "FFA22": { + "description": "Filter FIFO assignment for filter\n 22", + "offset": 22, + "size": 1 + }, + "FFA23": { + "description": "Filter FIFO assignment for filter\n 23", + "offset": 23, + "size": 1 + }, + "FFA24": { + "description": "Filter FIFO assignment for filter\n 24", + "offset": 24, + "size": 1 + }, + "FFA25": { + "description": "Filter FIFO assignment for filter\n 25", + "offset": 25, + "size": 1 + }, + "FFA26": { + "description": "Filter FIFO assignment for filter\n 26", + "offset": 26, + "size": 1 + }, + "FFA27": { + "description": "Filter FIFO assignment for filter\n 27", + "offset": 27, + "size": 1 + } + } + } + }, + "FA1R": { + "description": "CAN filter activation register", + "offset": 540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FACT0": { + "description": "Filter active", + "offset": 0, + "size": 1 + }, + "FACT1": { + "description": "Filter active", + "offset": 1, + "size": 1 + }, + "FACT2": { + "description": "Filter active", + "offset": 2, + "size": 1 + }, + "FACT3": { + "description": "Filter active", + "offset": 3, + "size": 1 + }, + "FACT4": { + "description": "Filter active", + "offset": 4, + "size": 1 + }, + "FACT5": { + "description": "Filter active", + "offset": 5, + "size": 1 + }, + "FACT6": { + "description": "Filter active", + "offset": 6, + "size": 1 + }, + "FACT7": { + "description": "Filter active", + "offset": 7, + "size": 1 + }, + "FACT8": { + "description": "Filter active", + "offset": 8, + "size": 1 + }, + "FACT9": { + "description": "Filter active", + "offset": 9, + "size": 1 + }, + "FACT10": { + "description": "Filter active", + "offset": 10, + "size": 1 + }, + "FACT11": { + "description": "Filter active", + "offset": 11, + "size": 1 + }, + "FACT12": { + "description": "Filter active", + "offset": 12, + "size": 1 + }, + "FACT13": { + "description": "Filter active", + "offset": 13, + "size": 1 + }, + "FACT14": { + "description": "Filter active", + "offset": 14, + "size": 1 + }, + "FACT15": { + "description": "Filter active", + "offset": 15, + "size": 1 + }, + "FACT16": { + "description": "Filter active", + "offset": 16, + "size": 1 + }, + "FACT17": { + "description": "Filter active", + "offset": 17, + "size": 1 + }, + "FACT18": { + "description": "Filter active", + "offset": 18, + "size": 1 + }, + "FACT19": { + "description": "Filter active", + "offset": 19, + "size": 1 + }, + "FACT20": { + "description": "Filter active", + "offset": 20, + "size": 1 + }, + "FACT21": { + "description": "Filter active", + "offset": 21, + "size": 1 + }, + "FACT22": { + "description": "Filter active", + "offset": 22, + "size": 1 + }, + "FACT23": { + "description": "Filter active", + "offset": 23, + "size": 1 + }, + "FACT24": { + "description": "Filter active", + "offset": 24, + "size": 1 + }, + "FACT25": { + "description": "Filter active", + "offset": 25, + "size": 1 + }, + "FACT26": { + "description": "Filter active", + "offset": 26, + "size": 1 + }, + "FACT27": { + "description": "Filter active", + "offset": 27, + "size": 1 + } + } + } + }, + "F0R1": { + "description": "Filter bank 0 register 1", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F0R2": { + "description": "Filter bank 0 register 2", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R1": { + "description": "Filter bank 1 register 1", + "offset": 584, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R2": { + "description": "Filter bank 1 register 2", + "offset": 588, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R1": { + "description": "Filter bank 2 register 1", + "offset": 592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R2": { + "description": "Filter bank 2 register 2", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R1": { + "description": "Filter bank 3 register 1", + "offset": 600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R2": { + "description": "Filter bank 3 register 2", + "offset": 604, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R1": { + "description": "Filter bank 4 register 1", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R2": { + "description": "Filter bank 4 register 2", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R1": { + "description": "Filter bank 5 register 1", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R2": { + "description": "Filter bank 5 register 2", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R1": { + "description": "Filter bank 6 register 1", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R2": { + "description": "Filter bank 6 register 2", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R1": { + "description": "Filter bank 7 register 1", + "offset": 632, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R2": { + "description": "Filter bank 7 register 2", + "offset": 636, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R1": { + "description": "Filter bank 8 register 1", + "offset": 640, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R2": { + "description": "Filter bank 8 register 2", + "offset": 644, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R1": { + "description": "Filter bank 9 register 1", + "offset": 648, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R2": { + "description": "Filter bank 9 register 2", + "offset": 652, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R1": { + "description": "Filter bank 10 register 1", + "offset": 656, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R2": { + "description": "Filter bank 10 register 2", + "offset": 660, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R1": { + "description": "Filter bank 11 register 1", + "offset": 664, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R2": { + "description": "Filter bank 11 register 2", + "offset": 668, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R1": { + "description": "Filter bank 4 register 1", + "offset": 672, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R2": { + "description": "Filter bank 12 register 2", + "offset": 676, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R1": { + "description": "Filter bank 13 register 1", + "offset": 680, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R2": { + "description": "Filter bank 13 register 2", + "offset": 684, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R1": { + "description": "Filter bank 14 register 1", + "offset": 688, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R2": { + "description": "Filter bank 14 register 2", + "offset": 692, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R1": { + "description": "Filter bank 15 register 1", + "offset": 696, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R2": { + "description": "Filter bank 15 register 2", + "offset": 700, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter 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13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R1": { + "description": "Filter bank 16 register 1", + "offset": 704, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R2": { + "description": "Filter bank 16 register 2", + "offset": 708, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter 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bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R1": { + "description": "Filter bank 17 register 1", + "offset": 712, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R2": { + "description": "Filter bank 17 register 2", + "offset": 716, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R1": { + "description": "Filter bank 18 register 1", + "offset": 720, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R2": { + "description": "Filter bank 18 register 2", + "offset": 724, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R1": { + "description": "Filter bank 19 register 1", + "offset": 728, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R2": { + "description": "Filter bank 19 register 2", + "offset": 732, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R1": { + "description": "Filter bank 20 register 1", + "offset": 736, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R2": { + "description": "Filter bank 20 register 2", + "offset": 740, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R1": { + "description": "Filter bank 21 register 1", + "offset": 744, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R2": { + "description": "Filter bank 21 register 2", + "offset": 748, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R1": { + "description": "Filter bank 22 register 1", + "offset": 752, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R2": { + "description": "Filter bank 22 register 2", + "offset": 756, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R1": { + "description": "Filter bank 23 register 1", + "offset": 760, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R2": { + "description": "Filter bank 23 register 2", + "offset": 764, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R1": { + "description": "Filter bank 24 register 1", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R2": { + "description": "Filter bank 24 register 2", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R1": { + "description": "Filter bank 25 register 1", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R2": { + "description": "Filter bank 25 register 2", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R1": { + "description": "Filter bank 26 register 1", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R2": { + "description": "Filter bank 26 register 2", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R1": { + "description": "Filter bank 27 register 1", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R2": { + "description": "Filter bank 27 register 2", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "USB_FS": { + "description": "Universal serial bus full-speed device\n interface", + "children": { + "registers": { + "USB_EP0R": { + "description": "endpoint 0 register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP1R": { + "description": "endpoint 1 register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP2R": { + "description": "endpoint 2 register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP3R": { + "description": "endpoint 3 register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP4R": { + "description": "endpoint 4 register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP5R": { + "description": "endpoint 5 register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP6R": { + "description": "endpoint 6 register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_EP7R": { + "description": "endpoint 7 register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EA": { + "description": "Endpoint address", + "offset": 0, + "size": 4 + }, + "STAT_TX": { + "description": "Status bits, for transmission\n transfers", + "offset": 4, + "size": 2 + }, + "DTOG_TX": { + "description": "Data Toggle, for transmission\n transfers", + "offset": 6, + "size": 1 + }, + "CTR_TX": { + "description": "Correct Transfer for\n transmission", + "offset": 7, + "size": 1 + }, + "EP_KIND": { + "description": "Endpoint kind", + "offset": 8, + "size": 1 + }, + "EP_TYPE": { + "description": "Endpoint type", + "offset": 9, + "size": 2 + }, + "SETUP": { + "description": "Setup transaction\n completed", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "STAT_RX": { + "description": "Status bits, for reception\n transfers", + "offset": 12, + "size": 2 + }, + "DTOG_RX": { + "description": "Data Toggle, for reception\n transfers", + "offset": 14, + "size": 1 + }, + "CTR_RX": { + "description": "Correct transfer for\n reception", + "offset": 15, + "size": 1 + } + } + } + }, + "USB_CNTR": { + "description": "control register", + "offset": 64, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRES": { + "description": "Force USB Reset", + "offset": 0, + "size": 1 + }, + "PDWN": { + "description": "Power down", + "offset": 1, + "size": 1 + }, + "LPMODE": { + "description": "Low-power mode", + "offset": 2, + "size": 1 + }, + "FSUSP": { + "description": "Force suspend", + "offset": 3, + "size": 1 + }, + "RESUME": { + "description": "Resume request", + "offset": 4, + "size": 1 + }, + "ESOFM": { + "description": "Expected start of frame interrupt\n mask", + "offset": 8, + "size": 1 + }, + "SOFM": { + "description": "Start of frame interrupt\n mask", + "offset": 9, + "size": 1 + }, + "RESETM": { + "description": "USB reset interrupt mask", + "offset": 10, + "size": 1 + }, + "SUSPM": { + "description": "Suspend mode interrupt\n mask", + "offset": 11, + "size": 1 + }, + "WKUPM": { + "description": "Wakeup interrupt mask", + "offset": 12, + "size": 1 + }, + "ERRM": { + "description": "Error interrupt mask", + "offset": 13, + "size": 1 + }, + "PMAOVRM": { + "description": "Packet memory area over / underrun\n interrupt mask", + "offset": 14, + "size": 1 + }, + "CTRM": { + "description": "Correct transfer interrupt\n mask", + "offset": 15, + "size": 1 + } + } + } + }, + "ISTR": { + "description": "interrupt status register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EP_ID": { + "description": "Endpoint Identifier", + "offset": 0, + "size": 4, + "access": "read-only" + }, + "DIR": { + "description": "Direction of transaction", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ESOF": { + "description": "Expected start frame", + "offset": 8, + "size": 1 + }, + "SOF": { + "description": "start of frame", + "offset": 9, + "size": 1 + }, + "RESET": { + "description": "reset request", + "offset": 10, + "size": 1 + }, + "SUSP": { + "description": "Suspend mode request", + "offset": 11, + "size": 1 + }, + "WKUP": { + "description": "Wakeup", + "offset": 12, + "size": 1 + }, + "ERR": { + "description": "Error", + "offset": 13, + "size": 1 + }, + "PMAOVR": { + "description": "Packet memory area over /\n underrun", + "offset": 14, + "size": 1 + }, + "CTR": { + "description": "Correct transfer", + "offset": 15, + "size": 1, + "access": "read-only" + } + } + } + }, + "FNR": { + "description": "frame number register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FN": { + "description": "Frame number", + "offset": 0, + "size": 11 + }, + "LSOF": { + "description": "Lost SOF", + "offset": 11, + "size": 2 + }, + "LCK": { + "description": "Locked", + "offset": 13, + "size": 1 + }, + "RXDM": { + "description": "Receive data - line status", + "offset": 14, + "size": 1 + }, + "RXDP": { + "description": "Receive data + line status", + "offset": 15, + "size": 1 + } + } + } + }, + "DADDR": { + "description": "device address", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD": { + "description": "Device address", + "offset": 0, + "size": 1 + }, + "ADD1": { + "description": "Device address", + "offset": 1, + "size": 1 + }, + "ADD2": { + "description": "Device address", + "offset": 2, + "size": 1 + }, + "ADD3": { + "description": "Device address", + "offset": 3, + "size": 1 + }, + "ADD4": { + "description": "Device address", + "offset": 4, + "size": 1 + }, + "ADD5": { + "description": "Device address", + "offset": 5, + "size": 1 + }, + "ADD6": { + "description": "Device address", + "offset": 6, + "size": 1 + }, + "EF": { + "description": "Enable function", + "offset": 7, + "size": 1 + } + } + } + }, + "BTABLE": { + "description": "Buffer table address", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTABLE": { + "description": "Buffer table", + "offset": 3, + "size": 13 + } + } + } + } + } + } + }, + "I2C1": { + "description": "Inter-integrated circuit", + "children": { + "registers": { + "CR1": { + "description": "Control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PE": { + "description": "Peripheral enable", + "offset": 0, + "size": 1 + }, + "TXIE": { + "description": "TX Interrupt enable", + "offset": 1, + "size": 1 + }, + "RXIE": { + "description": "RX Interrupt enable", + "offset": 2, + "size": 1 + }, + "ADDRIE": { + "description": "Address match interrupt enable (slave\n only)", + "offset": 3, + "size": 1 + }, + "NACKIE": { + "description": "Not acknowledge received interrupt\n enable", + "offset": 4, + "size": 1 + }, + "STOPIE": { + "description": "STOP detection Interrupt\n enable", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer Complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupts enable", + "offset": 7, + "size": 1 + }, + "DNF": { + "description": "Digital noise filter", + "offset": 8, + "size": 4 + }, + "ANFOFF": { + "description": "Analog noise filter OFF", + "offset": 12, + "size": 1 + }, + "SWRST": { + "description": "Software reset", + "offset": 13, + "size": 1, + "access": "write-only" + }, + "TXDMAEN": { + "description": "DMA transmission requests\n enable", + "offset": 14, + "size": 1 + }, + "RXDMAEN": { + "description": "DMA reception requests\n enable", + "offset": 15, + "size": 1 + }, + "SBC": { + "description": "Slave byte control", + "offset": 16, + "size": 1 + }, + "NOSTRETCH": { + "description": "Clock stretching disable", + "offset": 17, + "size": 1 + }, + "WUPEN": { + "description": "Wakeup from STOP enable", + "offset": 18, + "size": 1 + }, + "GCEN": { + "description": "General call enable", + "offset": 19, + "size": 1 + }, + "SMBHEN": { + "description": "SMBus Host address enable", + "offset": 20, + "size": 1 + }, + "SMBDEN": { + "description": "SMBus Device Default address\n enable", + "offset": 21, + "size": 1 + }, + "ALERTEN": { + "description": "SMBUS alert enable", + "offset": 22, + "size": 1 + }, + "PECEN": { + "description": "PEC enable", + "offset": 23, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PECBYTE": { + "description": "Packet error checking byte", + "offset": 26, + "size": 1 + }, + "AUTOEND": { + "description": "Automatic end mode (master\n mode)", + "offset": 25, + "size": 1 + }, + "RELOAD": { + "description": "NBYTES reload mode", + "offset": 24, + "size": 1 + }, + "NBYTES": { + "description": "Number of bytes", + "offset": 16, + "size": 8 + }, + "NACK": { + "description": "NACK generation (slave\n mode)", + "offset": 15, + "size": 1 + }, + "STOP": { + "description": "Stop generation (master\n mode)", + "offset": 14, + "size": 1 + }, + "START": { + "description": "Start generation", + "offset": 13, + "size": 1 + }, + "HEAD10R": { + "description": "10-bit address header only read\n direction (master receiver mode)", + "offset": 12, + "size": 1 + }, + "ADD10": { + "description": "10-bit addressing mode (master\n mode)", + "offset": 11, + "size": 1 + }, + "RD_WRN": { + "description": "Transfer direction (master\n mode)", + "offset": 10, + "size": 1 + }, + "SADD8": { + "description": "Slave address bit 9:8 (master\n mode)", + "offset": 8, + "size": 2 + }, + "SADD1": { + "description": "Slave address bit 7:1 (master\n mode)", + "offset": 1, + "size": 7 + }, + "SADD0": { + "description": "Slave address bit 0 (master\n mode)", + "offset": 0, + "size": 1 + } + } + } + }, + "OAR1": { + "description": "Own address register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OA1_0": { + "description": "Interface address", + "offset": 0, + "size": 1 + }, + "OA1_1": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "OA1_8": { + "description": "Interface address", + "offset": 8, + "size": 2 + }, + "OA1MODE": { + "description": "Own Address 1 10-bit mode", + "offset": 10, + "size": 1 + }, + "OA1EN": { + "description": "Own Address 1 enable", + "offset": 15, + "size": 1 + } + } + } + }, + "OAR2": { + "description": "Own address register 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OA2": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "OA2MSK": { + "description": "Own Address 2 masks", + "offset": 8, + "size": 3 + }, + "OA2EN": { + "description": "Own Address 2 enable", + "offset": 15, + "size": 1 + } + } + } + }, + "TIMINGR": { + "description": "Timing register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCLL": { + "description": "SCL low period (master\n mode)", + "offset": 0, + "size": 8 + }, + "SCLH": { + "description": "SCL high period (master\n mode)", + "offset": 8, + "size": 8 + }, + "SDADEL": { + "description": "Data hold time", + "offset": 16, + "size": 4 + }, + "SCLDEL": { + "description": "Data setup time", + "offset": 20, + "size": 4 + }, + "PRESC": { + "description": "Timing prescaler", + "offset": 28, + "size": 4 + } + } + } + }, + "TIMEOUTR": { + "description": "Status register 1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMEOUTA": { + "description": "Bus timeout A", + "offset": 0, + "size": 12 + }, + "TIDLE": { + "description": "Idle clock timeout\n detection", + "offset": 12, + "size": 1 + }, + "TIMOUTEN": { + "description": "Clock timeout enable", + "offset": 15, + "size": 1 + }, + "TIMEOUTB": { + "description": "Bus timeout B", + "offset": 16, + "size": 12 + }, + "TEXTEN": { + "description": "Extended clock timeout\n enable", + "offset": 31, + "size": 1 + } + } + } + }, + "ISR": { + "description": "Interrupt and Status register", + "offset": 24, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDCODE": { + "description": "Address match code (Slave\n mode)", + "offset": 17, + "size": 7, + "access": "read-only" + }, + "DIR": { + "description": "Transfer direction (Slave\n mode)", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "BUSY": { + "description": "Bus busy", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "ALERT": { + "description": "SMBus alert", + "offset": 13, + "size": 1, + "access": "read-only" + }, + "TIMEOUT": { + "description": "Timeout or t_low detection\n flag", + "offset": 12, + "size": 1, + "access": "read-only" + }, + "PECERR": { + "description": "PEC Error in reception", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "OVR": { + "description": "Overrun/Underrun (slave\n mode)", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "ARLO": { + "description": "Arbitration lost", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "BERR": { + "description": "Bus error", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "TCR": { + "description": "Transfer Complete Reload", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transfer Complete (master\n mode)", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "STOPF": { + "description": "Stop detection flag", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "NACKF": { + "description": "Not acknowledge received\n flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ADDR": { + "description": "Address matched (slave\n mode)", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "Receive data register not empty\n (receivers)", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "TXIS": { + "description": "Transmit interrupt status\n (transmitters)", + "offset": 1, + "size": 1 + }, + "TXE": { + "description": "Transmit data register empty\n (transmitters)", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "Interrupt clear register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ALERTCF": { + "description": "Alert flag clear", + "offset": 13, + "size": 1 + }, + "TIMOUTCF": { + "description": "Timeout detection flag\n clear", + "offset": 12, + "size": 1 + }, + "PECCF": { + "description": "PEC Error flag clear", + "offset": 11, + "size": 1 + }, + "OVRCF": { + "description": "Overrun/Underrun flag\n clear", + "offset": 10, + "size": 1 + }, + "ARLOCF": { + "description": "Arbitration lost flag\n clear", + "offset": 9, + "size": 1 + }, + "BERRCF": { + "description": "Bus error flag clear", + "offset": 8, + "size": 1 + }, + "STOPCF": { + "description": "Stop detection flag clear", + "offset": 5, + "size": 1 + }, + "NACKCF": { + "description": "Not Acknowledge flag clear", + "offset": 4, + "size": 1 + }, + "ADDRCF": { + "description": "Address Matched flag clear", + "offset": 3, + "size": 1 + } + } + } + }, + "PECR": { + "description": "PEC register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PEC": { + "description": "Packet error checking\n register", + "offset": 0, + "size": 8 + } + } + } + }, + "RXDR": { + "description": "Receive data register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RXDATA": { + "description": "8-bit receive data", + "offset": 0, + "size": 8 + } + } + } + }, + "TXDR": { + "description": "Transmit data register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXDATA": { + "description": "8-bit transmit data", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TIM1": { + "description": "Advanced timer", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "UIFREMAP": { + "description": "UIF status bit remapping", + "offset": 11, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + }, + "OIS2N": { + "description": "Output Idle state 2", + "offset": 11, + "size": 1 + }, + "OIS3": { + "description": "Output Idle state 3", + "offset": 12, + "size": 1 + }, + "OIS3N": { + "description": "Output Idle state 3", + "offset": 13, + "size": 1 + }, + "OIS4": { + "description": "Output Idle state 4", + "offset": 14, + "size": 1 + }, + "OIS5": { + "description": "Output Idle state 5", + "offset": 16, + "size": 1 + }, + "OIS6": { + "description": "Output Idle state 6", + "offset": 18, + "size": 1 + }, + "MMS2": { + "description": "Master mode selection 2", + "offset": 20, + "size": 4 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + }, + "OCCS": { + "description": "OCREF clear selection", + "offset": 3, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "SMS3": { + "description": "Slave mode selection bit 3", + "offset": 16, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "B2IF": { + "description": "Break 2 interrupt flag", + "offset": 8, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "C5IF": { + "description": "Capture/Compare 5 interrupt\n flag", + "offset": 16, + "size": 1 + }, + "C6IF": { + "description": "Capture/Compare 6 interrupt\n flag", + "offset": 17, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "B2G": { + "description": "Break 2 generation", + "offset": 8, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output Compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output Compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + }, + "OC1M_3": { + "description": "Output Compare 1 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC2M_3": { + "description": "Output Compare 2 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "IC1PCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC4CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + }, + "OC3M_3": { + "description": "Output Compare 3 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC4M_3": { + "description": "Output Compare 4 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2NE": { + "description": "Capture/Compare 2 complementary output\n enable", + "offset": 6, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3NE": { + "description": "Capture/Compare 3 complementary output\n enable", + "offset": 10, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC5E": { + "description": "Capture/Compare 5 output\n enable", + "offset": 16, + "size": 1 + }, + "CC5P": { + "description": "Capture/Compare 5 output\n Polarity", + "offset": 17, + "size": 1 + }, + "CC6E": { + "description": "Capture/Compare 6 output\n enable", + "offset": 20, + "size": 1 + }, + "CC6P": { + "description": "Capture/Compare 6 output\n Polarity", + "offset": 21, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + }, + "UIFCPY": { + "description": "UIF copy", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare 3 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare 3 value", + "offset": 0, + "size": 16 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "BKF": { + "description": "Break filter", + "offset": 16, + "size": 4 + }, + "BK2F": { + "description": "Break 2 filter", + "offset": 20, + "size": 4 + }, + "BK2E": { + "description": "Break 2 enable", + "offset": 24, + "size": 1 + }, + "BK2P": { + "description": "Break 2 polarity", + "offset": 25, + "size": 1 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "CCMR3_Output": { + "description": "capture/compare mode register 3 (output\n mode)", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC5FE": { + "description": "Output compare 5 fast\n enable", + "offset": 2, + "size": 1 + }, + "OC5PE": { + "description": "Output compare 5 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC5M": { + "description": "Output compare 5 mode", + "offset": 4, + "size": 3 + }, + "OC5CE": { + "description": "Output compare 5 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC6FE": { + "description": "Output compare 6 fast\n enable", + "offset": 10, + "size": 1 + }, + "OC6PE": { + "description": "Output compare 6 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC6M": { + "description": "Output compare 6 mode", + "offset": 12, + "size": 3 + }, + "OC6CE": { + "description": "Output compare 6 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC5M_3": { + "description": "Outout Compare 5 mode bit\n 3", + "offset": 16, + "size": 1 + }, + "OC6M_3": { + "description": "Outout Compare 6 mode bit\n 3", + "offset": 24, + "size": 1 + } + } + } + }, + "CCR5": { + "description": "capture/compare register 5", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR5": { + "description": "Capture/Compare 5 value", + "offset": 0, + "size": 16 + }, + "GC5C1": { + "description": "Group Channel 5 and Channel\n 1", + "offset": 29, + "size": 1 + }, + "GC5C2": { + "description": "Group Channel 5 and Channel\n 2", + "offset": 30, + "size": 1 + }, + "GC5C3": { + "description": "Group Channel 5 and Channel\n 3", + "offset": 31, + "size": 1 + } + } + } + }, + "CCR6": { + "description": "capture/compare register 6", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR6": { + "description": "Capture/Compare 6 value", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "option registers", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM1_ETR_ADC1_RMP": { + "description": "TIM1_ETR_ADC1 remapping\n capability", + "offset": 0, + "size": 2 + }, + "TIM1_ETR_ADC4_RMP": { + "description": "TIM1_ETR_ADC4 remapping\n capability", + "offset": 2, + "size": 2 + } + } + } + } + } + } + }, + "DBGMCU": { + "description": "Debug support", + "children": { + "registers": { + "IDCODE": { + "description": "MCU Device ID Code Register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEV_ID": { + "description": "Device Identifier", + "offset": 0, + "size": 12 + }, + "REV_ID": { + "description": "Revision Identifier", + "offset": 16, + "size": 16 + } + } + } + }, + "CR": { + "description": "Debug MCU Configuration\n Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_SLEEP": { + "description": "Debug Sleep mode", + "offset": 0, + "size": 1 + }, + "DBG_STOP": { + "description": "Debug Stop Mode", + "offset": 1, + "size": 1 + }, + "DBG_STANDBY": { + "description": "Debug Standby Mode", + "offset": 2, + "size": 1 + }, + "TRACE_IOEN": { + "description": "Trace pin assignment\n control", + "offset": 5, + "size": 1 + }, + "TRACE_MODE": { + "description": "Trace pin assignment\n control", + "offset": 6, + "size": 2 + } + } + } + }, + "APB1FZ": { + "description": "APB Low Freeze Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM2_STOP": { + "description": "Debug Timer 2 stopped when Core is\n halted", + "offset": 0, + "size": 1 + }, + "DBG_TIM3_STOP": { + "description": "Debug Timer 3 stopped when Core is\n halted", + "offset": 1, + "size": 1 + }, + "DBG_TIM4_STOP": { + "description": "Debug Timer 4 stopped when Core is\n halted", + "offset": 2, + "size": 1 + }, + "DBG_TIM5_STOP": { + "description": "Debug Timer 5 stopped when Core is\n halted", + "offset": 3, + "size": 1 + }, + "DBG_TIM6_STOP": { + "description": "Debug Timer 6 stopped when Core is\n halted", + "offset": 4, + "size": 1 + }, + "DBG_TIM7_STOP": { + "description": "Debug Timer 7 stopped when Core is\n halted", + "offset": 5, + "size": 1 + }, + "DBG_TIM12_STOP": { + "description": "Debug Timer 12 stopped when Core is\n halted", + "offset": 6, + "size": 1 + }, + "DBG_TIM13_STOP": { + "description": "Debug Timer 13 stopped when Core is\n halted", + "offset": 7, + "size": 1 + }, + "DBG_TIMER14_STOP": { + "description": "Debug Timer 14 stopped when Core is\n halted", + "offset": 8, + "size": 1 + }, + "DBG_TIM18_STOP": { + "description": "Debug Timer 18 stopped when Core is\n halted", + "offset": 9, + "size": 1 + }, + "DBG_RTC_STOP": { + "description": "Debug RTC stopped when Core is\n halted", + "offset": 10, + "size": 1 + }, + "DBG_WWDG_STOP": { + "description": "Debug Window Wachdog stopped when Core\n is halted", + "offset": 11, + "size": 1 + }, + "DBG_IWDG_STOP": { + "description": "Debug Independent Wachdog stopped when\n Core is halted", + "offset": 12, + "size": 1 + }, + "I2C1_SMBUS_TIMEOUT": { + "description": "SMBUS timeout mode stopped when Core is\n halted", + "offset": 21, + "size": 1 + }, + "I2C2_SMBUS_TIMEOUT": { + "description": "SMBUS timeout mode stopped when Core is\n halted", + "offset": 22, + "size": 1 + }, + "DBG_CAN_STOP": { + "description": "Debug CAN stopped when core is\n halted", + "offset": 25, + "size": 1 + } + } + } + }, + "APB2FZ": { + "description": "APB High Freeze Register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM15_STOP": { + "description": "Debug Timer 15 stopped when Core is\n halted", + "offset": 2, + "size": 1 + }, + "DBG_TIM16_STOP": { + "description": "Debug Timer 16 stopped when Core is\n halted", + "offset": 3, + "size": 1 + }, + "DBG_TIM17_STO": { + "description": "Debug Timer 17 stopped when Core is\n halted", + "offset": 4, + "size": 1 + }, + "DBG_TIM19_STOP": { + "description": "Debug Timer 19 stopped when Core is\n halted", + "offset": 5, + "size": 1 + } + } + } + } + } + } + } + } + }, + "devices": { + "STM32F303": { + "arch": "cortex_m4", + "description": "STM32F303", + "properties": { + "cpu.nvic_prio_bits": "3", + "cpu.mpu": "false", + "cpu.fpu": "false", + "cpu.revision": "r1p0", + "cpu.vendor_systick_config": "false", + "cpu.endian": "little", + "cpu.name": "CM4" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "EXTI2_TSC": { + "index": 8, + "description": "EXTI Line2 and Touch sensing\n interrupts" + }, + "FLASH": { + "index": 4, + "description": "Flash global interrupt" + }, + "RCC": { + "index": 5, + "description": "RCC global interrupt" + }, + "DMA1_CH1": { + "index": 11, + "description": "DMA1 channel 1 interrupt" + }, + "DMA2_CH1": { + "index": 56, + "description": "DMA2 channel1 global interrupt" + }, + "TIM2": { + "index": 28, + "description": "TIM2 global interrupt" + }, + "TIM3": { + "index": 29, + "description": "TIM3 global interrupt" + }, + "TIM4": { + "index": 30, + "description": "TIM4 global interrupt" + }, + "TIM1_BRK_TIM15": { + "index": 24, + "description": "TIM1 Break/TIM15 global\n interruts" + }, + "TIM1_UP_TIM16": { + "index": 25, + "description": "TIM1 Update/TIM16 global\n interrupts" + }, + "TIM1_TRG_COM_TIM17": { + "index": 26, + "description": "TIM1 trigger and commutation/TIM17\n interrupts" + }, + "USART1_EXTI25": { + "index": 37, + "description": "USART1 global interrupt and EXTI Line 25\n interrupt" + }, + "USART2_EXTI26": { + "index": 38, + "description": "USART2 global interrupt and EXTI Line 26\n interrupt" + }, + "USART3_EXTI28": { + "index": 39, + "description": "USART3 global interrupt and EXTI Line 28\n interrupt" + }, + "UART4_EXTI34": { + "index": 52, + "description": "UART4 global and EXTI Line 34\n interrupts" + }, + "UART5_EXTI35": { + "index": 53, + "description": "UART5 global and EXTI Line 35\n interrupts" + }, + "SPI1": { + "index": 35, + "description": "SPI1 global interrupt" + }, + "SPI2": { + "index": 36, + "description": "SPI2 global interrupt" + }, + "SPI3": { + "index": 51, + "description": "SPI3 global interrupt" + }, + "TAMP_STAMP": { + "index": 2, + "description": "Tamper and TimeStamp interrupts" + }, + "PVD": { + "index": 1, + "description": "PVD through EXTI line detection\n interrupt" + }, + "USB_HP_CAN_TX": { + "index": 19, + "description": "USB High Priority/CAN_TX\n interrupts" + }, + "USB_WKUP": { + "index": 42, + "description": "USB wakeup from Suspend" + }, + "I2C1_EV_EXTI23": { + "index": 31, + "description": "I2C1 event interrupt and EXTI Line23\n interrupt" + }, + "I2C2_EV_EXTI24": { + "index": 33, + "description": "I2C2 event interrupt & EXTI Line24\n interrupt" + }, + "WWDG": { + "index": 0, + "description": "Window Watchdog interrupt" + }, + "RTC_WKUP": { + "index": 3, + "description": "RTC Wakeup interrupt through the EXTI\n line" + }, + "TIM6_DACUNDER": { + "index": 54, + "description": "TIM6 global and DAC12 underrun\n interrupts" + }, + "TIM7": { + "index": 55, + "description": "TIM7 global interrupt" + }, + "TIM1_CC": { + "index": 27, + "description": "TIM1 capture compare interrupt" + }, + "TIM8_BRK": { + "index": 43, + "description": "TIM8 break interrupt" + }, + "ADC1_2": { + "index": 18, + "description": "ADC1 and ADC2 global interrupt" + }, + "ADC3": { + "index": 47, + "description": "ADC3 global interrupt" + }, + "ADC4": { + "index": 61, + "description": "ADC4 global interrupt" + }, + "COMP123": { + "index": 64, + "description": "COMP1 & COMP2 & COMP3 interrupts\n combined with EXTI Lines 21, 22 and 29\n interrupts" + }, + "FMC": { + "index": 48, + "description": "FSMC global interrupt" + }, + "FPU": { + "index": 81, + "description": "Floating point unit interrupt" + } + }, + "peripheral_instances": { + "GPIOA": { + "description": "General-purpose I/Os", + "offset": 1207959552, + "type": "types.peripherals.GPIOA" + }, + "GPIOB": { + "description": "General-purpose I/Os", + "offset": 1207960576, + "type": "types.peripherals.GPIOB" + }, + "GPIOC": { + "offset": 1207961600, + "type": "types.peripherals.GPIOB" + }, + "GPIOD": { + "offset": 1207962624, + "type": "types.peripherals.GPIOB" + }, + "GPIOE": { + "offset": 1207963648, + "type": "types.peripherals.GPIOB" + }, + "GPIOF": { + "offset": 1207964672, + "type": "types.peripherals.GPIOB" + }, + "GPIOG": { + "offset": 1207965696, + "type": "types.peripherals.GPIOB" + }, + "GPIOH": { + "offset": 1207966720, + "type": "types.peripherals.GPIOB" + }, + "TSC": { + "description": "Touch sensing controller", + "offset": 1073889280, + "type": "types.peripherals.TSC" + }, + "CRC": { + "description": "cyclic redundancy check calculation\n unit", + "offset": 1073885184, + "type": "types.peripherals.CRC" + }, + "Flash": { + "description": "Flash", + "offset": 1073881088, + "type": "types.peripherals.Flash" + }, + "RCC": { + "description": "Reset and clock control", + "offset": 1073876992, + "type": "types.peripherals.RCC" + }, + "DMA1": { + "description": "DMA controller 1", + "offset": 1073872896, + "type": "types.peripherals.DMA1" + }, + "DMA2": { + "offset": 1073873920, + "type": "types.peripherals.DMA1" + }, + "TIM2": { + "description": "General purpose timer", + "offset": 1073741824, + "type": "types.peripherals.TIM2" + }, + "TIM3": { + "offset": 1073742848, + "type": "types.peripherals.TIM2" + }, + "TIM4": { + "offset": 1073743872, + "type": "types.peripherals.TIM2" + }, + "TIM15": { + "description": "General purpose timers", + "offset": 1073823744, + "type": "types.peripherals.TIM15" + }, + "TIM16": { + "description": "General-purpose-timers", + "offset": 1073824768, + "type": "types.peripherals.TIM16" + }, + "TIM17": { + "description": "General purpose timer", + "offset": 1073825792, + "type": "types.peripherals.TIM17" + }, + "USART1": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073821696, + "type": "types.peripherals.USART1" + }, + "USART2": { + "offset": 1073759232, + "type": "types.peripherals.USART1" + }, + "USART3": { + "offset": 1073760256, + "type": "types.peripherals.USART1" + }, + "UART4": { + "offset": 1073761280, + "type": "types.peripherals.USART1" + }, + "UART5": { + "offset": 1073762304, + "type": "types.peripherals.USART1" + }, + "SPI1": { + "description": "Serial peripheral interface/Inter-IC\n sound", + "offset": 1073819648, + "type": "types.peripherals.SPI1" + }, + "SPI2": { + "offset": 1073756160, + "type": "types.peripherals.SPI1" + }, + "SPI3": { + "offset": 1073757184, + "type": "types.peripherals.SPI1" + }, + "I2S2ext": { + "offset": 1073755136, + "type": "types.peripherals.SPI1" + }, + "I2S3ext": { + "offset": 1073758208, + "type": "types.peripherals.SPI1" + }, + "SPI4": { + "offset": 1073822720, + "type": "types.peripherals.SPI1" + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "offset": 1073808384, + "type": "types.peripherals.EXTI" + }, + "PWR": { + "description": "Power control", + "offset": 1073770496, + "type": "types.peripherals.PWR" + }, + "CAN": { + "description": "Controller area network", + "offset": 1073767424, + "type": "types.peripherals.CAN" + }, + "USB_FS": { + "description": "Universal serial bus full-speed device\n interface", + "offset": 1073765376, + "type": "types.peripherals.USB_FS" + }, + "I2C1": { + "description": "Inter-integrated circuit", + "offset": 1073763328, + "type": "types.peripherals.I2C1" + }, + "I2C2": { + "offset": 1073764352, + "type": "types.peripherals.I2C1" + }, + "I2C3": { + "offset": 1073772544, + "type": "types.peripherals.I2C1" + }, + "IWDG": { + "description": "Independent watchdog", + "offset": 1073754112, + "type": "types.peripherals.IWDG" + }, + "WWDG": { + "description": "Window watchdog", + "offset": 1073753088, + "type": "types.peripherals.WWDG" + }, + "RTC": { + "description": "Real-time clock", + "offset": 1073752064, + "type": "types.peripherals.RTC" + }, + "TIM6": { + "description": "Basic timers", + "offset": 1073745920, + "type": "types.peripherals.TIM6" + }, + "TIM7": { + "offset": 1073746944, + "type": "types.peripherals.TIM6" + }, + "DAC": { + "description": "Digital-to-analog converter", + "offset": 1073771520, + "type": "types.peripherals.DAC" + }, + "DBGMCU": { + "description": "Debug support", + "offset": 3758366720, + "type": "types.peripherals.DBGMCU" + }, + "TIM1": { + "description": "Advanced timer", + "offset": 1073818624, + "type": "types.peripherals.TIM1" + }, + "TIM20": { + "offset": 1073827840, + "type": "types.peripherals.TIM1" + }, + "TIM8": { + "description": "Advanced-timers", + "offset": 1073820672, + "type": "types.peripherals.TIM8" + }, + "ADC1": { + "description": "Analog-to-Digital Converter", + "offset": 1342177280, + "type": "types.peripherals.ADC1" + }, + "ADC2": { + "offset": 1342177536, + "type": "types.peripherals.ADC1" + }, + "ADC3": { + "offset": 1342178304, + "type": "types.peripherals.ADC1" + }, + "ADC4": { + "offset": 1342178560, + "type": "types.peripherals.ADC1" + }, + "ADC1_2": { + "description": "Analog-to-Digital Converter", + "offset": 1342178048, + "type": "types.peripherals.ADC1_2" + }, + "ADC3_4": { + "offset": 1342179072, + "type": "types.peripherals.ADC1_2" + }, + "SYSCFG_COMP_OPAMP": { + "description": "System configuration controller _Comparator and\n Operational amplifier", + "offset": 1073807360, + "type": "types.peripherals.SYSCFG_COMP_OPAMP" + }, + "FMC": { + "description": "Flexible memory controller", + "offset": 2684355584, + "type": "types.peripherals.FMC" + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "offset": 3758153984, + "type": "types.peripherals.NVIC" + }, + "FPU": { + "description": "Floting point unit", + "offset": 3758157620, + "type": "types.peripherals.FPU" + }, + "MPU": { + "description": "Memory protection unit", + "offset": 3758157200, + "type": "types.peripherals.MPU" + }, + "STK": { + "description": "SysTick timer", + "offset": 3758153744, + "type": "types.peripherals.STK" + }, + "SCB": { + "description": "System control block", + "offset": 3758157056, + "type": "types.peripherals.SCB" + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "offset": 3758157568, + "type": "types.peripherals.NVIC_STIR" + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "offset": 3758157192, + "type": "types.peripherals.FPU_CPACR" + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "offset": 3758153736, + "type": "types.peripherals.SCB_ACTRL" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/STM32F303.zig b/src/chips/STM32F303.zig new file mode 100644 index 0000000..4bb914c --- /dev/null +++ b/src/chips/STM32F303.zig @@ -0,0 +1,13076 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// STM32F303 + pub const STM32F303 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "3"; + pub const @"cpu.mpu" = "false"; + pub const @"cpu.fpu" = "false"; + pub const @"cpu.revision" = "r1p0"; + pub const @"cpu.vendor_systick_config" = "false"; + pub const @"cpu.endian" = "little"; + pub const @"cpu.name" = "CM4"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + /// Window Watchdog interrupt + WWDG: Handler = unhandled, + /// PVD through EXTI line detection interrupt + PVD: Handler = unhandled, + /// Tamper and TimeStamp interrupts + TAMP_STAMP: Handler = unhandled, + /// RTC Wakeup interrupt through the EXTI line + RTC_WKUP: Handler = unhandled, + /// Flash global interrupt + FLASH: Handler = unhandled, + /// RCC global interrupt + RCC: Handler = unhandled, + reserved20: [2]u32 = undefined, + /// EXTI Line2 and Touch sensing interrupts + EXTI2_TSC: Handler = unhandled, + reserved23: [2]u32 = undefined, + /// DMA1 channel 1 interrupt + DMA1_CH1: Handler = unhandled, + reserved26: [6]u32 = undefined, + /// ADC1 and ADC2 global interrupt + ADC1_2: Handler = unhandled, + /// USB High Priority/CAN_TX interrupts + USB_HP_CAN_TX: Handler = unhandled, + reserved34: [4]u32 = undefined, + /// TIM1 Break/TIM15 global interruts + TIM1_BRK_TIM15: Handler = unhandled, + /// TIM1 Update/TIM16 global interrupts + TIM1_UP_TIM16: Handler = unhandled, + /// TIM1 trigger and commutation/TIM17 interrupts + TIM1_TRG_COM_TIM17: Handler = unhandled, + /// TIM1 capture compare interrupt + TIM1_CC: Handler = unhandled, + /// TIM2 global interrupt + TIM2: Handler = unhandled, + /// TIM3 global interrupt + TIM3: Handler = unhandled, + /// TIM4 global interrupt + TIM4: Handler = unhandled, + /// I2C1 event interrupt and EXTI Line23 interrupt + I2C1_EV_EXTI23: Handler = unhandled, + reserved46: [1]u32 = undefined, + /// I2C2 event interrupt & EXTI Line24 interrupt + I2C2_EV_EXTI24: Handler = unhandled, + reserved48: [1]u32 = undefined, + /// SPI1 global interrupt + SPI1: Handler = unhandled, + /// SPI2 global interrupt + SPI2: Handler = unhandled, + /// USART1 global interrupt and EXTI Line 25 interrupt + USART1_EXTI25: Handler = unhandled, + /// USART2 global interrupt and EXTI Line 26 interrupt + USART2_EXTI26: Handler = unhandled, + /// USART3 global interrupt and EXTI Line 28 interrupt + USART3_EXTI28: Handler = unhandled, + reserved54: [2]u32 = undefined, + /// USB wakeup from Suspend + USB_WKUP: Handler = unhandled, + /// TIM8 break interrupt + TIM8_BRK: Handler = unhandled, + reserved58: [3]u32 = undefined, + /// ADC3 global interrupt + ADC3: Handler = unhandled, + /// FSMC global interrupt + FMC: Handler = unhandled, + reserved63: [2]u32 = undefined, + /// SPI3 global interrupt + SPI3: Handler = unhandled, + /// UART4 global and EXTI Line 34 interrupts + UART4_EXTI34: Handler = unhandled, + /// UART5 global and EXTI Line 35 interrupts + UART5_EXTI35: Handler = unhandled, + /// TIM6 global and DAC12 underrun interrupts + TIM6_DACUNDER: Handler = unhandled, + /// TIM7 global interrupt + TIM7: Handler = unhandled, + /// DMA2 channel1 global interrupt + DMA2_CH1: Handler = unhandled, + reserved71: [4]u32 = undefined, + /// ADC4 global interrupt + ADC4: Handler = unhandled, + reserved76: [2]u32 = undefined, + /// COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts + COMP123: Handler = unhandled, + reserved79: [16]u32 = undefined, + /// Floating point unit interrupt + FPU: Handler = unhandled, + }; + + pub const peripherals = struct { + /// General purpose timer + pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000); + /// General purpose timer + pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400); + /// General purpose timer + pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800); + /// Basic timers + pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000); + /// Basic timers + pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400); + /// Real-time clock + pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800); + /// Window watchdog + pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00); + /// Independent watchdog + pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000); + /// Serial peripheral interface/Inter-IC sound + pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400); + /// Serial peripheral interface/Inter-IC sound + pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800); + /// Serial peripheral interface/Inter-IC sound + pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00); + /// Serial peripheral interface/Inter-IC sound + pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800); + /// Universal synchronous asynchronous receiver transmitter + pub const UART4 = @ptrCast(*volatile types.USART1, 0x40004c00); + /// Universal synchronous asynchronous receiver transmitter + pub const UART5 = @ptrCast(*volatile types.USART1, 0x40005000); + /// Inter-integrated circuit + pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400); + /// Inter-integrated circuit + pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800); + /// Universal serial bus full-speed device interface + pub const USB_FS = @ptrCast(*volatile types.USB_FS, 0x40005c00); + /// Controller area network + pub const CAN = @ptrCast(*volatile types.CAN, 0x40006400); + /// Power control + pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000); + /// Digital-to-analog converter + pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400); + /// Inter-integrated circuit + pub const I2C3 = @ptrCast(*volatile types.I2C1, 0x40007800); + /// System configuration controller _Comparator and Operational amplifier + pub const SYSCFG_COMP_OPAMP = @ptrCast(*volatile types.SYSCFG_COMP_OPAMP, 0x40010000); + /// External interrupt/event controller + pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400); + /// Advanced timer + pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00); + /// Serial peripheral interface/Inter-IC sound + pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000); + /// Advanced-timers + pub const TIM8 = @ptrCast(*volatile types.TIM8, 0x40013400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800); + /// Serial peripheral interface/Inter-IC sound + pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013c00); + /// General purpose timers + pub const TIM15 = @ptrCast(*volatile types.TIM15, 0x40014000); + /// General-purpose-timers + pub const TIM16 = @ptrCast(*volatile types.TIM16, 0x40014400); + /// General purpose timer + pub const TIM17 = @ptrCast(*volatile types.TIM17, 0x40014800); + /// Advanced timer + pub const TIM20 = @ptrCast(*volatile types.TIM1, 0x40015000); + /// DMA controller 1 + pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000); + /// DMA controller 1 + pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400); + /// Reset and clock control + pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000); + /// Flash + pub const Flash = @ptrCast(*volatile types.Flash, 0x40022000); + /// cyclic redundancy check calculation unit + pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000); + /// Touch sensing controller + pub const TSC = @ptrCast(*volatile types.TSC, 0x40024000); + /// General-purpose I/Os + pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x48000000); + /// General-purpose I/Os + pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x48000400); + /// General-purpose I/Os + pub const GPIOC = @ptrCast(*volatile types.GPIOB, 0x48000800); + /// General-purpose I/Os + pub const GPIOD = @ptrCast(*volatile types.GPIOB, 0x48000c00); + /// General-purpose I/Os + pub const GPIOE = @ptrCast(*volatile types.GPIOB, 0x48001000); + /// General-purpose I/Os + pub const GPIOF = @ptrCast(*volatile types.GPIOB, 0x48001400); + /// General-purpose I/Os + pub const GPIOG = @ptrCast(*volatile types.GPIOB, 0x48001800); + /// General-purpose I/Os + pub const GPIOH = @ptrCast(*volatile types.GPIOB, 0x48001c00); + /// Analog-to-Digital Converter + pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x50000000); + /// Analog-to-Digital Converter + pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x50000100); + /// Analog-to-Digital Converter + pub const ADC1_2 = @ptrCast(*volatile types.ADC1_2, 0x50000300); + /// Analog-to-Digital Converter + pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x50000400); + /// Analog-to-Digital Converter + pub const ADC4 = @ptrCast(*volatile types.ADC1, 0x50000500); + /// Analog-to-Digital Converter + pub const ADC3_4 = @ptrCast(*volatile types.ADC1_2, 0x50000700); + /// Flexible memory controller + pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000400); + /// System control block ACTLR + pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008); + /// SysTick timer + pub const STK = @ptrCast(*volatile types.STK, 0xe000e010); + /// Nested Vectored Interrupt Controller + pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100); + /// System control block + pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00); + /// Floating point unit CPACR + pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88); + /// Memory protection unit + pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90); + /// Nested vectored interrupt controller + pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00); + /// Floting point unit + pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34); + /// Debug support + pub const DBGMCU = @ptrCast(*volatile types.DBGMCU, 0xe0042000); + }; + }; +}; + +pub const types = struct { + /// General-purpose I/Os + pub const GPIOA = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + /// Port bit reset register + BRR: mmio.Mmio(packed struct(u32) { + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding: u16, + }), + }; + + /// General-purpose I/Os + pub const GPIOB = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bit 0 + OT0: u1, + /// Port x configuration bit 1 + OT1: u1, + /// Port x configuration bit 2 + OT2: u1, + /// Port x configuration bit 3 + OT3: u1, + /// Port x configuration bit 4 + OT4: u1, + /// Port x configuration bit 5 + OT5: u1, + /// Port x configuration bit 6 + OT6: u1, + /// Port x configuration bit 7 + OT7: u1, + /// Port x configuration bit 8 + OT8: u1, + /// Port x configuration bit 9 + OT9: u1, + /// Port x configuration bit 10 + OT10: u1, + /// Port x configuration bit 11 + OT11: u1, + /// Port x configuration bit 12 + OT12: u1, + /// Port x configuration bit 13 + OT13: u1, + /// Port x configuration bit 14 + OT14: u1, + /// Port x configuration bit 15 + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Lok Key + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + /// Port bit reset register + BRR: mmio.Mmio(packed struct(u32) { + /// Port x Reset bit y + BR0: u1, + /// Port x Reset bit y + BR1: u1, + /// Port x Reset bit y + BR2: u1, + /// Port x Reset bit y + BR3: u1, + /// Port x Reset bit y + BR4: u1, + /// Port x Reset bit y + BR5: u1, + /// Port x Reset bit y + BR6: u1, + /// Port x Reset bit y + BR7: u1, + /// Port x Reset bit y + BR8: u1, + /// Port x Reset bit y + BR9: u1, + /// Port x Reset bit y + BR10: u1, + /// Port x Reset bit y + BR11: u1, + /// Port x Reset bit y + BR12: u1, + /// Port x Reset bit y + BR13: u1, + /// Port x Reset bit y + BR14: u1, + /// Port x Reset bit y + BR15: u1, + padding: u16, + }), + }; + + /// System control block ACTLR + pub const SCB_ACTRL = extern struct { + /// Auxiliary control register + ACTRL: mmio.Mmio(packed struct(u32) { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved8: u5, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding: u22, + }), + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = extern struct { + /// Coprocessor access control register + CPACR: mmio.Mmio(packed struct(u32) { + reserved20: u20, + /// CP + CP: u4, + padding: u8, + }), + }; + + /// Nested vectored interrupt controller + pub const NVIC_STIR = extern struct { + /// Software trigger interrupt register + STIR: mmio.Mmio(packed struct(u32) { + /// Software generated interrupt ID + INTID: u9, + padding: u23, + }), + }; + + /// System control block + pub const SCB = extern struct { + /// CPUID base register + CPUID: mmio.Mmio(packed struct(u32) { + /// Revision number + Revision: u4, + /// Part number of the processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), + /// Interrupt control and state register + ICSR: mmio.Mmio(packed struct(u32) { + /// Active vector + VECTACTIVE: u9, + reserved11: u2, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved22: u3, + /// Interrupt pending flag + ISRPENDING: u1, + reserved25: u2, + /// SysTick exception clear-pending bit + PENDSTCLR: u1, + /// SysTick exception set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved31: u2, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), + /// Vector table offset register + VTOR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// Vector table base offset field + TBLOFF: u21, + padding: u2, + }), + /// Application interrupt and reset control register + AIRCR: mmio.Mmio(packed struct(u32) { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved8: u5, + /// PRIGROUP + PRIGROUP: u3, + reserved15: u4, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), + /// System control register + SCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved4: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding: u27, + }), + /// Configuration and control register + CCR: mmio.Mmio(packed struct(u32) { + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved3: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved8: u3, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding: u22, + }), + /// System handler priority registers + SHPR1: mmio.Mmio(packed struct(u32) { + /// Priority of system handler 4 + PRI_4: u8, + /// Priority of system handler 5 + PRI_5: u8, + /// Priority of system handler 6 + PRI_6: u8, + padding: u8, + }), + /// System handler priority registers + SHPR2: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// Priority of system handler 11 + PRI_11: u8, + }), + /// System handler priority registers + SHPR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Priority of system handler 14 + PRI_14: u8, + /// Priority of system handler 15 + PRI_15: u8, + }), + /// System handler control and state register + SHCRS: mmio.Mmio(packed struct(u32) { + /// Memory management fault exception active bit + MEMFAULTACT: u1, + /// Bus fault exception active bit + BUSFAULTACT: u1, + reserved3: u1, + /// Usage fault exception active bit + USGFAULTACT: u1, + reserved7: u3, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved10: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// Usage fault exception pending bit + USGFAULTPENDED: u1, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding: u13, + }), + /// Configurable fault status register + CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Instruction access violation flag + IACCVIOL: u1, + reserved3: u1, + /// Memory manager fault on unstacking for a return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved7: u1, + /// Memory Management Fault Address Register (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception entry + STKERR: u1, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1, + reserved15: u1, + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1, + /// Undefined instruction usage fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage fault + INVPC: u1, + /// No coprocessor usage fault. + NOCP: u1, + reserved24: u4, + /// Unaligned access usage fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding: u6, + }), + /// Hard fault status register + HFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved30: u28, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), + reserved52: [4]u8, + /// Memory management fault address register + MMFAR: mmio.Mmio(packed struct(u32) { + /// Memory management fault address + MMFAR: u32, + }), + /// Bus fault address register + BFAR: mmio.Mmio(packed struct(u32) { + /// Bus fault address + BFAR: u32, + }), + /// Auxiliary fault status register + AFSR: mmio.Mmio(packed struct(u32) { + /// Implementation defined + IMPDEF: u32, + }), + }; + + /// SysTick timer + pub const STK = extern struct { + /// SysTick control and status register + CTRL: mmio.Mmio(packed struct(u32) { + /// Counter enable + ENABLE: u1, + /// SysTick exception request enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved16: u13, + /// COUNTFLAG + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick reload value register + LOAD: mmio.Mmio(packed struct(u32) { + /// RELOAD value + RELOAD: u24, + padding: u8, + }), + /// SysTick current value register + VAL: mmio.Mmio(packed struct(u32) { + /// Current counter value + CURRENT: u24, + padding: u8, + }), + /// SysTick calibration value register + CALIB: mmio.Mmio(packed struct(u32) { + /// Calibration value + TENMS: u24, + reserved30: u6, + /// SKEW flag: Indicates whether the TENMS value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), + }; + + /// Memory protection unit + pub const MPU = extern struct { + /// MPU type register + MPU_TYPER: mmio.Mmio(packed struct(u32) { + /// Separate flag + SEPARATE: u1, + reserved8: u7, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction regions + IREGION: u8, + padding: u8, + }), + /// MPU control register + MPU_CTRL: mmio.Mmio(packed struct(u32) { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1, + padding: u29, + }), + /// MPU region number register + MPU_RNR: mmio.Mmio(packed struct(u32) { + /// MPU region + REGION: u8, + padding: u24, + }), + /// MPU region base address register + MPU_RBAR: mmio.Mmio(packed struct(u32) { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), + /// MPU region attribute and size register + MPU_RASR: mmio.Mmio(packed struct(u32) { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection region + SIZE: u5, + reserved8: u2, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved24: u2, + /// Access permission + AP: u3, + reserved28: u1, + /// Instruction access disable bit + XN: u1, + padding: u3, + }), + }; + + /// Touch sensing controller + pub const TSC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Touch sensing controller enable + TSCE: u1, + /// Start a new acquisition + START: u1, + /// Acquisition mode + AM: u1, + /// Synchronization pin polarity + SYNCPOL: u1, + /// I/O Default mode + IODEF: u1, + /// Max count value + MCV: u3, + reserved12: u4, + /// pulse generator prescaler + PGPSC: u3, + /// Spread spectrum prescaler + SSPSC: u1, + /// Spread spectrum enable + SSE: u1, + /// Spread spectrum deviation + SSD: u7, + /// Charge transfer pulse low + CTPL: u4, + /// Charge transfer pulse high + CTPH: u4, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt enable + EOAIE: u1, + /// Max count error interrupt enable + MCEIE: u1, + padding: u30, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// End of acquisition interrupt clear + EOAIC: u1, + /// Max count error interrupt clear + MCEIC: u1, + padding: u30, + }), + /// interrupt status register + ISR: mmio.Mmio(packed struct(u32) { + /// End of acquisition flag + EOAF: u1, + /// Max count error flag + MCEF: u1, + padding: u30, + }), + /// I/O hysteresis control register + IOHCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 Schmitt trigger hysteresis mode + G1_IO1: u1, + /// G1_IO2 Schmitt trigger hysteresis mode + G1_IO2: u1, + /// G1_IO3 Schmitt trigger hysteresis mode + G1_IO3: u1, + /// G1_IO4 Schmitt trigger hysteresis mode + G1_IO4: u1, + /// G2_IO1 Schmitt trigger hysteresis mode + G2_IO1: u1, + /// G2_IO2 Schmitt trigger hysteresis mode + G2_IO2: u1, + /// G2_IO3 Schmitt trigger hysteresis mode + G2_IO3: u1, + /// G2_IO4 Schmitt trigger hysteresis mode + G2_IO4: u1, + /// G3_IO1 Schmitt trigger hysteresis mode + G3_IO1: u1, + /// G3_IO2 Schmitt trigger hysteresis mode + G3_IO2: u1, + /// G3_IO3 Schmitt trigger hysteresis mode + G3_IO3: u1, + /// G3_IO4 Schmitt trigger hysteresis mode + G3_IO4: u1, + /// G4_IO1 Schmitt trigger hysteresis mode + G4_IO1: u1, + /// G4_IO2 Schmitt trigger hysteresis mode + G4_IO2: u1, + /// G4_IO3 Schmitt trigger hysteresis mode + G4_IO3: u1, + /// G4_IO4 Schmitt trigger hysteresis mode + G4_IO4: u1, + /// G5_IO1 Schmitt trigger hysteresis mode + G5_IO1: u1, + /// G5_IO2 Schmitt trigger hysteresis mode + G5_IO2: u1, + /// G5_IO3 Schmitt trigger hysteresis mode + G5_IO3: u1, + /// G5_IO4 Schmitt trigger hysteresis mode + G5_IO4: u1, + /// G6_IO1 Schmitt trigger hysteresis mode + G6_IO1: u1, + /// G6_IO2 Schmitt trigger hysteresis mode + G6_IO2: u1, + /// G6_IO3 Schmitt trigger hysteresis mode + G6_IO3: u1, + /// G6_IO4 Schmitt trigger hysteresis mode + G6_IO4: u1, + /// G7_IO1 Schmitt trigger hysteresis mode + G7_IO1: u1, + /// G7_IO2 Schmitt trigger hysteresis mode + G7_IO2: u1, + /// G7_IO3 Schmitt trigger hysteresis mode + G7_IO3: u1, + /// G7_IO4 Schmitt trigger hysteresis mode + G7_IO4: u1, + /// G8_IO1 Schmitt trigger hysteresis mode + G8_IO1: u1, + /// G8_IO2 Schmitt trigger hysteresis mode + G8_IO2: u1, + /// G8_IO3 Schmitt trigger hysteresis mode + G8_IO3: u1, + /// G8_IO4 Schmitt trigger hysteresis mode + G8_IO4: u1, + }), + reserved24: [4]u8, + /// I/O analog switch control register + IOASCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 analog switch enable + G1_IO1: u1, + /// G1_IO2 analog switch enable + G1_IO2: u1, + /// G1_IO3 analog switch enable + G1_IO3: u1, + /// G1_IO4 analog switch enable + G1_IO4: u1, + /// G2_IO1 analog switch enable + G2_IO1: u1, + /// G2_IO2 analog switch enable + G2_IO2: u1, + /// G2_IO3 analog switch enable + G2_IO3: u1, + /// G2_IO4 analog switch enable + G2_IO4: u1, + /// G3_IO1 analog switch enable + G3_IO1: u1, + /// G3_IO2 analog switch enable + G3_IO2: u1, + /// G3_IO3 analog switch enable + G3_IO3: u1, + /// G3_IO4 analog switch enable + G3_IO4: u1, + /// G4_IO1 analog switch enable + G4_IO1: u1, + /// G4_IO2 analog switch enable + G4_IO2: u1, + /// G4_IO3 analog switch enable + G4_IO3: u1, + /// G4_IO4 analog switch enable + G4_IO4: u1, + /// G5_IO1 analog switch enable + G5_IO1: u1, + /// G5_IO2 analog switch enable + G5_IO2: u1, + /// G5_IO3 analog switch enable + G5_IO3: u1, + /// G5_IO4 analog switch enable + G5_IO4: u1, + /// G6_IO1 analog switch enable + G6_IO1: u1, + /// G6_IO2 analog switch enable + G6_IO2: u1, + /// G6_IO3 analog switch enable + G6_IO3: u1, + /// G6_IO4 analog switch enable + G6_IO4: u1, + /// G7_IO1 analog switch enable + G7_IO1: u1, + /// G7_IO2 analog switch enable + G7_IO2: u1, + /// G7_IO3 analog switch enable + G7_IO3: u1, + /// G7_IO4 analog switch enable + G7_IO4: u1, + /// G8_IO1 analog switch enable + G8_IO1: u1, + /// G8_IO2 analog switch enable + G8_IO2: u1, + /// G8_IO3 analog switch enable + G8_IO3: u1, + /// G8_IO4 analog switch enable + G8_IO4: u1, + }), + reserved32: [4]u8, + /// I/O sampling control register + IOSCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 sampling mode + G1_IO1: u1, + /// G1_IO2 sampling mode + G1_IO2: u1, + /// G1_IO3 sampling mode + G1_IO3: u1, + /// G1_IO4 sampling mode + G1_IO4: u1, + /// G2_IO1 sampling mode + G2_IO1: u1, + /// G2_IO2 sampling mode + G2_IO2: u1, + /// G2_IO3 sampling mode + G2_IO3: u1, + /// G2_IO4 sampling mode + G2_IO4: u1, + /// G3_IO1 sampling mode + G3_IO1: u1, + /// G3_IO2 sampling mode + G3_IO2: u1, + /// G3_IO3 sampling mode + G3_IO3: u1, + /// G3_IO4 sampling mode + G3_IO4: u1, + /// G4_IO1 sampling mode + G4_IO1: u1, + /// G4_IO2 sampling mode + G4_IO2: u1, + /// G4_IO3 sampling mode + G4_IO3: u1, + /// G4_IO4 sampling mode + G4_IO4: u1, + /// G5_IO1 sampling mode + G5_IO1: u1, + /// G5_IO2 sampling mode + G5_IO2: u1, + /// G5_IO3 sampling mode + G5_IO3: u1, + /// G5_IO4 sampling mode + G5_IO4: u1, + /// G6_IO1 sampling mode + G6_IO1: u1, + /// G6_IO2 sampling mode + G6_IO2: u1, + /// G6_IO3 sampling mode + G6_IO3: u1, + /// G6_IO4 sampling mode + G6_IO4: u1, + /// G7_IO1 sampling mode + G7_IO1: u1, + /// G7_IO2 sampling mode + G7_IO2: u1, + /// G7_IO3 sampling mode + G7_IO3: u1, + /// G7_IO4 sampling mode + G7_IO4: u1, + /// G8_IO1 sampling mode + G8_IO1: u1, + /// G8_IO2 sampling mode + G8_IO2: u1, + /// G8_IO3 sampling mode + G8_IO3: u1, + /// G8_IO4 sampling mode + G8_IO4: u1, + }), + reserved40: [4]u8, + /// I/O channel control register + IOCCR: mmio.Mmio(packed struct(u32) { + /// G1_IO1 channel mode + G1_IO1: u1, + /// G1_IO2 channel mode + G1_IO2: u1, + /// G1_IO3 channel mode + G1_IO3: u1, + /// G1_IO4 channel mode + G1_IO4: u1, + /// G2_IO1 channel mode + G2_IO1: u1, + /// G2_IO2 channel mode + G2_IO2: u1, + /// G2_IO3 channel mode + G2_IO3: u1, + /// G2_IO4 channel mode + G2_IO4: u1, + /// G3_IO1 channel mode + G3_IO1: u1, + /// G3_IO2 channel mode + G3_IO2: u1, + /// G3_IO3 channel mode + G3_IO3: u1, + /// G3_IO4 channel mode + G3_IO4: u1, + /// G4_IO1 channel mode + G4_IO1: u1, + /// G4_IO2 channel mode + G4_IO2: u1, + /// G4_IO3 channel mode + G4_IO3: u1, + /// G4_IO4 channel mode + G4_IO4: u1, + /// G5_IO1 channel mode + G5_IO1: u1, + /// G5_IO2 channel mode + G5_IO2: u1, + /// G5_IO3 channel mode + G5_IO3: u1, + /// G5_IO4 channel mode + G5_IO4: u1, + /// G6_IO1 channel mode + G6_IO1: u1, + /// G6_IO2 channel mode + G6_IO2: u1, + /// G6_IO3 channel mode + G6_IO3: u1, + /// G6_IO4 channel mode + G6_IO4: u1, + /// G7_IO1 channel mode + G7_IO1: u1, + /// G7_IO2 channel mode + G7_IO2: u1, + /// G7_IO3 channel mode + G7_IO3: u1, + /// G7_IO4 channel mode + G7_IO4: u1, + /// G8_IO1 channel mode + G8_IO1: u1, + /// G8_IO2 channel mode + G8_IO2: u1, + /// G8_IO3 channel mode + G8_IO3: u1, + /// G8_IO4 channel mode + G8_IO4: u1, + }), + reserved48: [4]u8, + /// I/O group control status register + IOGCSR: mmio.Mmio(packed struct(u32) { + /// Analog I/O group x enable + G1E: u1, + /// Analog I/O group x enable + G2E: u1, + /// Analog I/O group x enable + G3E: u1, + /// Analog I/O group x enable + G4E: u1, + /// Analog I/O group x enable + G5E: u1, + /// Analog I/O group x enable + G6E: u1, + /// Analog I/O group x enable + G7E: u1, + /// Analog I/O group x enable + G8E: u1, + reserved16: u8, + /// Analog I/O group x status + G1S: u1, + /// Analog I/O group x status + G2S: u1, + /// Analog I/O group x status + G3S: u1, + /// Analog I/O group x status + G4S: u1, + /// Analog I/O group x status + G5S: u1, + /// Analog I/O group x status + G6S: u1, + /// Analog I/O group x status + G7S: u1, + /// Analog I/O group x status + G8S: u1, + padding: u8, + }), + /// I/O group x counter register + IOG1CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG2CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG3CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG4CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG5CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG6CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG7CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + /// I/O group x counter register + IOG8CR: mmio.Mmio(packed struct(u32) { + /// Counter value + CNT: u14, + padding: u18, + }), + }; + + /// cyclic redundancy check calculation unit + pub const CRC = extern struct { + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register bits + DR: u32, + }), + /// Independent data register + IDR: mmio.Mmio(packed struct(u32) { + /// General-purpose 8-bit data register bits + IDR: u8, + padding: u24, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// reset bit + RESET: u1, + reserved3: u2, + /// Polynomial size + POLYSIZE: u2, + /// Reverse input data + REV_IN: u2, + /// Reverse output data + REV_OUT: u1, + padding: u24, + }), + reserved16: [4]u8, + /// Initial CRC value + INIT: mmio.Mmio(packed struct(u32) { + /// Programmable initial CRC value + INIT: u32, + }), + /// CRC polynomial + POL: mmio.Mmio(packed struct(u32) { + /// Programmable polynomial + POL: u32, + }), + }; + + /// Flash + pub const Flash = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// LATENCY + LATENCY: u3, + reserved4: u1, + /// PRFTBE + PRFTBE: u1, + /// PRFTBS + PRFTBS: u1, + padding: u26, + }), + /// Flash key register + KEYR: mmio.Mmio(packed struct(u32) { + /// Flash Key + FKEYR: u32, + }), + /// Flash option key register + OPTKEYR: mmio.Mmio(packed struct(u32) { + /// Option byte key + OPTKEYR: u32, + }), + /// Flash status register + SR: mmio.Mmio(packed struct(u32) { + /// Busy + BSY: u1, + reserved2: u1, + /// Programming error + PGERR: u1, + reserved4: u1, + /// Write protection error + WRPRT: u1, + /// End of operation + EOP: u1, + padding: u26, + }), + /// Flash control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Page erase + PER: u1, + /// Mass erase + MER: u1, + reserved4: u1, + /// Option byte programming + OPTPG: u1, + /// Option byte erase + OPTER: u1, + /// Start + STRT: u1, + /// Lock + LOCK: u1, + reserved9: u1, + /// Option bytes write enable + OPTWRE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable + EOPIE: u1, + /// Force option byte loading + FORCE_OPTLOAD: u1, + padding: u18, + }), + /// Flash address register + AR: mmio.Mmio(packed struct(u32) { + /// Flash address + FAR: u32, + }), + reserved28: [4]u8, + /// Option byte register + OBR: mmio.Mmio(packed struct(u32) { + /// Option byte error + OPTERR: u1, + /// Level 1 protection status + LEVEL1_PROT: u1, + /// Level 2 protection status + LEVEL2_PROT: u1, + reserved8: u5, + /// WDG_SW + WDG_SW: u1, + /// nRST_STOP + nRST_STOP: u1, + /// nRST_STDBY + nRST_STDBY: u1, + reserved12: u1, + /// BOOT1 + BOOT1: u1, + /// VDDA_MONITOR + VDDA_MONITOR: u1, + /// SRAM_PARITY_CHECK + SRAM_PARITY_CHECK: u1, + reserved16: u1, + /// Data0 + Data0: u8, + /// Data1 + Data1: u8, + }), + /// Write protection register + WRPR: mmio.Mmio(packed struct(u32) { + /// Write protect + WRP: u32, + }), + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// Clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal High Speed clock enable + HSION: u1, + /// Internal High Speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal High Speed clock trimming + HSITRIM: u5, + /// Internal High Speed clock Calibration + HSICAL: u8, + /// External High Speed clock enable + HSEON: u1, + /// External High Speed clock ready flag + HSERDY: u1, + /// External High Speed clock Bypass + HSEBYP: u1, + /// Clock Security System enable + CSSON: u1, + reserved24: u4, + /// PLL enable + PLLON: u1, + /// PLL clock ready flag + PLLRDY: u1, + padding: u6, + }), + /// Clock configuration register (RCC_CFGR) + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock Switch + SW: u2, + /// System Clock Switch Status + SWS: u2, + /// AHB prescaler + HPRE: u4, + /// APB Low speed prescaler (APB1) + PPRE1: u3, + /// APB high speed prescaler (APB2) + PPRE2: u3, + reserved15: u1, + /// PLL entry clock source + PLLSRC: u2, + /// HSE divider for PLL entry + PLLXTPRE: u1, + /// PLL Multiplication Factor + PLLMUL: u4, + /// USB prescaler + USBPRES: u1, + /// I2S external clock source selection + I2SSRC: u1, + /// Microcontroller clock output + MCO: u3, + reserved28: u1, + /// Microcontroller Clock Output Flag + MCOF: u1, + padding: u3, + }), + /// Clock interrupt register (RCC_CIR) + CIR: mmio.Mmio(packed struct(u32) { + /// LSI Ready Interrupt flag + LSIRDYF: u1, + /// LSE Ready Interrupt flag + LSERDYF: u1, + /// HSI Ready Interrupt flag + HSIRDYF: u1, + /// HSE Ready Interrupt flag + HSERDYF: u1, + /// PLL Ready Interrupt flag + PLLRDYF: u1, + reserved7: u2, + /// Clock Security System Interrupt flag + CSSF: u1, + /// LSI Ready Interrupt Enable + LSIRDYIE: u1, + /// LSE Ready Interrupt Enable + LSERDYIE: u1, + /// HSI Ready Interrupt Enable + HSIRDYIE: u1, + /// HSE Ready Interrupt Enable + HSERDYIE: u1, + /// PLL Ready Interrupt Enable + PLLRDYIE: u1, + reserved16: u3, + /// LSI Ready Interrupt Clear + LSIRDYC: u1, + /// LSE Ready Interrupt Clear + LSERDYC: u1, + /// HSI Ready Interrupt Clear + HSIRDYC: u1, + /// HSE Ready Interrupt Clear + HSERDYC: u1, + /// PLL Ready Interrupt Clear + PLLRDYC: u1, + reserved23: u2, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// APB2 peripheral reset register (RCC_APB2RSTR) + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// SYSCFG and COMP reset + SYSCFGRST: u1, + reserved11: u10, + /// TIM1 timer reset + TIM1RST: u1, + /// SPI 1 reset + SPI1RST: u1, + /// TIM8 timer reset + TIM8RST: u1, + /// USART1 reset + USART1RST: u1, + reserved16: u1, + /// TIM15 timer reset + TIM15RST: u1, + /// TIM16 timer reset + TIM16RST: u1, + /// TIM17 timer reset + TIM17RST: u1, + padding: u13, + }), + /// APB1 peripheral reset register (RCC_APB1RSTR) + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// Timer 2 reset + TIM2RST: u1, + /// Timer 3 reset + TIM3RST: u1, + /// Timer 14 reset + TIM4RST: u1, + reserved4: u1, + /// Timer 6 reset + TIM6RST: u1, + /// Timer 7 reset + TIM7RST: u1, + reserved11: u5, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI2 reset + SPI2RST: u1, + /// SPI3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + USART2RST: u1, + /// USART3 reset + USART3RST: u1, + /// UART 4 reset + UART4RST: u1, + /// UART 5 reset + UART5RST: u1, + /// I2C1 reset + I2C1RST: u1, + /// I2C2 reset + I2C2RST: u1, + /// USB reset + USBRST: u1, + reserved25: u1, + /// CAN reset + CANRST: u1, + reserved28: u2, + /// Power interface reset + PWRRST: u1, + /// DAC interface reset + DACRST: u1, + /// I2C3 reset + I2C3RST: u1, + padding: u1, + }), + /// AHB Peripheral Clock enable register (RCC_AHBENR) + AHBENR: mmio.Mmio(packed struct(u32) { + /// DMA1 clock enable + DMAEN: u1, + /// DMA2 clock enable + DMA2EN: u1, + /// SRAM interface clock enable + SRAMEN: u1, + reserved4: u1, + /// FLITF clock enable + FLITFEN: u1, + /// FMC clock enable + FMCEN: u1, + /// CRC clock enable + CRCEN: u1, + reserved16: u9, + /// IO port H clock enable + IOPHEN: u1, + /// I/O port A clock enable + IOPAEN: u1, + /// I/O port B clock enable + IOPBEN: u1, + /// I/O port C clock enable + IOPCEN: u1, + /// I/O port D clock enable + IOPDEN: u1, + /// I/O port E clock enable + IOPEEN: u1, + /// I/O port F clock enable + IOPFEN: u1, + /// I/O port G clock enable + IOPGEN: u1, + /// Touch sensing controller clock enable + TSCEN: u1, + reserved28: u3, + /// ADC1 and ADC2 clock enable + ADC12EN: u1, + /// ADC3 and ADC4 clock enable + ADC34EN: u1, + padding: u2, + }), + /// APB2 peripheral clock enable register (RCC_APB2ENR) + APB2ENR: mmio.Mmio(packed struct(u32) { + /// SYSCFG clock enable + SYSCFGEN: u1, + reserved11: u10, + /// TIM1 Timer clock enable + TIM1EN: u1, + /// SPI 1 clock enable + SPI1EN: u1, + /// TIM8 Timer clock enable + TIM8EN: u1, + /// USART1 clock enable + USART1EN: u1, + reserved16: u1, + /// TIM15 timer clock enable + TIM15EN: u1, + /// TIM16 timer clock enable + TIM16EN: u1, + /// TIM17 timer clock enable + TIM17EN: u1, + padding: u13, + }), + /// APB1 peripheral clock enable register (RCC_APB1ENR) + APB1ENR: mmio.Mmio(packed struct(u32) { + /// Timer 2 clock enable + TIM2EN: u1, + /// Timer 3 clock enable + TIM3EN: u1, + /// Timer 4 clock enable + TIM4EN: u1, + reserved4: u1, + /// Timer 6 clock enable + TIM6EN: u1, + /// Timer 7 clock enable + TIM7EN: u1, + reserved11: u5, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI 2 clock enable + SPI2EN: u1, + /// SPI 3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART 3 clock enable + USART3EN: u1, + /// USART 4 clock enable + USART4EN: u1, + /// USART 5 clock enable + USART5EN: u1, + /// I2C 1 clock enable + I2C1EN: u1, + /// I2C 2 clock enable + I2C2EN: u1, + /// USB clock enable + USBEN: u1, + reserved25: u1, + /// CAN clock enable + CANEN: u1, + /// DAC2 interface clock enable + DAC2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + /// I2C3 clock enable + I2C3EN: u1, + padding: u1, + }), + /// Backup domain control register (RCC_BDCR) + BDCR: mmio.Mmio(packed struct(u32) { + /// External Low Speed oscillator enable + LSEON: u1, + /// External Low Speed oscillator ready + LSERDY: u1, + /// External Low Speed oscillator bypass + LSEBYP: u1, + /// LSE oscillator drive capability + LSEDRV: u2, + reserved8: u3, + /// RTC clock source selection + RTCSEL: u2, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// Control/status register (RCC_CSR) + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low speed oscillator enable + LSION: u1, + /// Internal low speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// Option byte loader reset flag + OBLRSTF: u1, + /// PIN reset flag + PINRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + IWDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + /// AHB peripheral reset register + AHBRSTR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// FMC reset + FMCRST: u1, + reserved16: u10, + /// I/O port H reset + IOPHRST: u1, + /// I/O port A reset + IOPARST: u1, + /// I/O port B reset + IOPBRST: u1, + /// I/O port C reset + IOPCRST: u1, + /// I/O port D reset + IOPDRST: u1, + /// I/O port E reset + IOPERST: u1, + /// I/O port F reset + IOPFRST: u1, + /// Touch sensing controller reset + IOPGRST: u1, + /// Touch sensing controller reset + TSCRST: u1, + reserved28: u3, + /// ADC1 and ADC2 reset + ADC12RST: u1, + /// ADC3 and ADC4 reset + ADC34RST: u1, + padding: u2, + }), + /// Clock configuration register 2 + CFGR2: mmio.Mmio(packed struct(u32) { + /// PREDIV division factor + PREDIV: u4, + /// ADC1 and ADC2 prescaler + ADC12PRES: u5, + /// ADC3 and ADC4 prescaler + ADC34PRES: u5, + padding: u18, + }), + /// Clock configuration register 3 + CFGR3: mmio.Mmio(packed struct(u32) { + /// USART1 clock source selection + USART1SW: u2, + reserved4: u2, + /// I2C1 clock source selection + I2C1SW: u1, + /// I2C2 clock source selection + I2C2SW: u1, + /// I2C3 clock source selection + I2C3SW: u1, + reserved8: u1, + /// Timer1 clock source selection + TIM1SW: u1, + /// Timer8 clock source selection + TIM8SW: u1, + reserved16: u6, + /// USART2 clock source selection + USART2SW: u2, + /// USART3 clock source selection + USART3SW: u2, + /// UART4 clock source selection + UART4SW: u2, + /// UART5 clock source selection + UART5SW: u2, + padding: u8, + }), + }; + + /// DMA controller 1 + pub const DMA1 = extern struct { + /// DMA interrupt status register (DMA_ISR) + ISR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt flag + GIF1: u1, + /// Channel 1 Transfer Complete flag + TCIF1: u1, + /// Channel 1 Half Transfer Complete flag + HTIF1: u1, + /// Channel 1 Transfer Error flag + TEIF1: u1, + /// Channel 2 Global interrupt flag + GIF2: u1, + /// Channel 2 Transfer Complete flag + TCIF2: u1, + /// Channel 2 Half Transfer Complete flag + HTIF2: u1, + /// Channel 2 Transfer Error flag + TEIF2: u1, + /// Channel 3 Global interrupt flag + GIF3: u1, + /// Channel 3 Transfer Complete flag + TCIF3: u1, + /// Channel 3 Half Transfer Complete flag + HTIF3: u1, + /// Channel 3 Transfer Error flag + TEIF3: u1, + /// Channel 4 Global interrupt flag + GIF4: u1, + /// Channel 4 Transfer Complete flag + TCIF4: u1, + /// Channel 4 Half Transfer Complete flag + HTIF4: u1, + /// Channel 4 Transfer Error flag + TEIF4: u1, + /// Channel 5 Global interrupt flag + GIF5: u1, + /// Channel 5 Transfer Complete flag + TCIF5: u1, + /// Channel 5 Half Transfer Complete flag + HTIF5: u1, + /// Channel 5 Transfer Error flag + TEIF5: u1, + /// Channel 6 Global interrupt flag + GIF6: u1, + /// Channel 6 Transfer Complete flag + TCIF6: u1, + /// Channel 6 Half Transfer Complete flag + HTIF6: u1, + /// Channel 6 Transfer Error flag + TEIF6: u1, + /// Channel 7 Global interrupt flag + GIF7: u1, + /// Channel 7 Transfer Complete flag + TCIF7: u1, + /// Channel 7 Half Transfer Complete flag + HTIF7: u1, + /// Channel 7 Transfer Error flag + TEIF7: u1, + padding: u4, + }), + /// DMA interrupt flag clear register (DMA_IFCR) + IFCR: mmio.Mmio(packed struct(u32) { + /// Channel 1 Global interrupt clear + CGIF1: u1, + /// Channel 1 Transfer Complete clear + CTCIF1: u1, + /// Channel 1 Half Transfer clear + CHTIF1: u1, + /// Channel 1 Transfer Error clear + CTEIF1: u1, + /// Channel 2 Global interrupt clear + CGIF2: u1, + /// Channel 2 Transfer Complete clear + CTCIF2: u1, + /// Channel 2 Half Transfer clear + CHTIF2: u1, + /// Channel 2 Transfer Error clear + CTEIF2: u1, + /// Channel 3 Global interrupt clear + CGIF3: u1, + /// Channel 3 Transfer Complete clear + CTCIF3: u1, + /// Channel 3 Half Transfer clear + CHTIF3: u1, + /// Channel 3 Transfer Error clear + CTEIF3: u1, + /// Channel 4 Global interrupt clear + CGIF4: u1, + /// Channel 4 Transfer Complete clear + CTCIF4: u1, + /// Channel 4 Half Transfer clear + CHTIF4: u1, + /// Channel 4 Transfer Error clear + CTEIF4: u1, + /// Channel 5 Global interrupt clear + CGIF5: u1, + /// Channel 5 Transfer Complete clear + CTCIF5: u1, + /// Channel 5 Half Transfer clear + CHTIF5: u1, + /// Channel 5 Transfer Error clear + CTEIF5: u1, + /// Channel 6 Global interrupt clear + CGIF6: u1, + /// Channel 6 Transfer Complete clear + CTCIF6: u1, + /// Channel 6 Half Transfer clear + CHTIF6: u1, + /// Channel 6 Transfer Error clear + CTEIF6: u1, + /// Channel 7 Global interrupt clear + CGIF7: u1, + /// Channel 7 Transfer Complete clear + CTCIF7: u1, + /// Channel 7 Half Transfer clear + CHTIF7: u1, + /// Channel 7 Transfer Error clear + CTEIF7: u1, + padding: u4, + }), + /// DMA channel configuration register (DMA_CCR) + CCR1: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 1 number of data register + CNDTR1: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 1 peripheral address register + CPAR1: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 1 memory address register + CMAR1: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved28: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR2: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 2 number of data register + CNDTR2: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 2 peripheral address register + CPAR2: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 2 memory address register + CMAR2: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved48: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR3: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 3 number of data register + CNDTR3: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 3 peripheral address register + CPAR3: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 3 memory address register + CMAR3: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved68: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR4: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 4 number of data register + CNDTR4: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 4 peripheral address register + CPAR4: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 4 memory address register + CMAR4: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved88: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR5: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 5 number of data register + CNDTR5: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 5 peripheral address register + CPAR5: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 5 memory address register + CMAR5: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved108: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR6: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 6 number of data register + CNDTR6: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 6 peripheral address register + CPAR6: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 6 memory address register + CMAR6: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + reserved128: [4]u8, + /// DMA channel configuration register (DMA_CCR) + CCR7: mmio.Mmio(packed struct(u32) { + /// Channel enable + EN: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Half Transfer interrupt enable + HTIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Data transfer direction + DIR: u1, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral size + PSIZE: u2, + /// Memory size + MSIZE: u2, + /// Channel Priority level + PL: u2, + /// Memory to memory mode + MEM2MEM: u1, + padding: u17, + }), + /// DMA channel 7 number of data register + CNDTR7: mmio.Mmio(packed struct(u32) { + /// Number of data to transfer + NDT: u16, + padding: u16, + }), + /// DMA channel 7 peripheral address register + CPAR7: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// DMA channel 7 memory address register + CMAR7: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + }; + + /// Floting point unit + pub const FPU = extern struct { + /// Floating-point context control register + FPCCR: mmio.Mmio(packed struct(u32) { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved3: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved8: u1, + /// MONRDY + MONRDY: u1, + reserved30: u21, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), + /// Floating-point context address register + FPCAR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Location of unpopulated floating-point + ADDRESS: u29, + }), + /// Floating-point status control register + FPSCR: mmio.Mmio(packed struct(u32) { + /// Invalid operation cumulative exception bit + IOC: u1, + /// Division by zero cumulative exception bit. + DZC: u1, + /// Overflow cumulative exception bit + OFC: u1, + /// Underflow cumulative exception bit + UFC: u1, + /// Inexact cumulative exception bit + IXC: u1, + reserved7: u2, + /// Input denormal cumulative exception bit. + IDC: u1, + reserved22: u14, + /// Rounding Mode control field + RMode: u2, + /// Flush-to-zero mode control bit: + FZ: u1, + /// Default NaN mode control bit + DN: u1, + /// Alternative half-precision control bit + AHP: u1, + reserved28: u1, + /// Overflow condition code flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code flag + N: u1, + }), + }; + + /// General purpose timer + pub const TIM2 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit3 + SMS_3: u1, + padding: u15, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output compare 1 fast enable + OC1FE: u1, + /// Output compare 1 preload enable + OC1PE: u1, + /// Output compare 1 mode + OC1M: u3, + /// Output compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output compare 2 fast enable + OC2FE: u1, + /// Output compare 2 preload enable + OC2PE: u1, + /// Output compare 2 mode + OC2M: u3, + /// Output compare 2 clear enable + OC2CE: u1, + /// Output compare 1 mode bit 3 + OC1M_3: u1, + reserved24: u7, + /// Output compare 2 mode bit 3 + OC2M_3: u1, + padding: u7, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + O24CE: u1, + /// Output compare 3 mode bit3 + OC3M_3: u1, + reserved24: u7, + /// Output compare 4 mode bit3 + OC4M_3: u1, + padding: u7, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 3 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNTL: u16, + /// High counter value + CNTH: u15, + /// if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access + CNT_or_UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARRL: u16, + /// High Auto-reload value + ARRH: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1L: u16, + /// High Capture/Compare 1 value (on TIM2) + CCR1H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2L: u16, + /// High Capture/Compare 2 value (on TIM2) + CCR2H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3L: u16, + /// High Capture/Compare value (on TIM2) + CCR3H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4L: u16, + /// High Capture/Compare value (on TIM2) + CCR4H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = extern struct { + /// Interrupt Set-Enable Register + ISER0: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER1: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER2: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + reserved128: [116]u8, + /// Interrupt Clear-Enable Register + ICER0: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER1: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER2: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + reserved256: [116]u8, + /// Interrupt Set-Pending Register + ISPR0: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR1: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR2: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + reserved384: [116]u8, + /// Interrupt Clear-Pending Register + ICPR0: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR1: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR2: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + reserved512: [116]u8, + /// Interrupt Active Bit Register + IABR0: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR1: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR2: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + reserved768: [244]u8, + /// Interrupt Priority Register + IPR0: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR1: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR2: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR3: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR4: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR5: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR6: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR7: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR8: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR9: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR10: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR11: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR12: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR13: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR14: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR15: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR16: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR17: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR18: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR19: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR20: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + }; + + /// Flexible memory controller + pub const FMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved11: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding: u11, + }), + /// SRAM/NOR-Flash chip-select timing register 1 + BTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2 + BCR2: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 2 + BTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 3 + BCR3: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 3 + BTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 4 + BCR4: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 4 + BTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved96: [64]u8, + /// PC Card/NAND Flash control register 2 + PCR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 2 + PMEM2: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 2 + PATT2: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved116: [4]u8, + /// ECC result register 2 + ECCR2: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved128: [8]u8, + /// PC Card/NAND Flash control register 3 + PCR3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 3 + SR3: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 3 + PMEM3: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 3 + PATT3: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved148: [4]u8, + /// ECC result register 3 + ECCR3: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved160: [8]u8, + /// PC Card/NAND Flash control register 4 + PCR4: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 4 + SR4: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 4 + PMEM4: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 4 + PATT4: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1 + BWTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved268: [4]u8, + /// SRAM/NOR-Flash write timing registers 2 + BWTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved276: [4]u8, + /// SRAM/NOR-Flash write timing registers 3 + BWTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved284: [4]u8, + /// SRAM/NOR-Flash write timing registers 4 + BWTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// Bus turnaround phase duration + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + }; + + /// General purpose timers + pub const TIM15 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + padding: u21, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + reserved16: u8, + /// Slave mode selection bit 3 + SMS_3: u1, + padding: u15, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + reserved5: u2, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + reserved13: u2, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + reserved5: u2, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + padding: u21, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + reserved5: u2, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved8: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + reserved16: u1, + /// Output Compare 1 mode bit 3 + OC1M_3: u1, + reserved24: u7, + /// Output Compare 2 mode bit 3 + OC2M_3: u1, + padding: u7, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + padding: u24, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + reserved68: [8]u8, + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding: u12, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// General-purpose-timers + pub const TIM16 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + reserved8: u4, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding: u22, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + reserved5: u3, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + reserved13: u3, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved5: u3, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + reserved5: u3, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved16: u9, + /// Output Compare 1 mode + OC1M_3: u1, + padding: u15, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF Copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + reserved68: [12]u8, + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding: u12, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// option register + OR: u32, + }; + + /// General purpose timer + pub const TIM17 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + reserved8: u4, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + padding: u22, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + reserved5: u3, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + reserved13: u3, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved5: u3, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + reserved5: u3, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved16: u9, + /// Output Compare 1 mode + OC1M_3: u1, + padding: u15, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF Copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + reserved68: [12]u8, + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + padding: u12, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// USART enable + UE: u1, + /// USART enable in Stop mode + UESM: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Receiver wakeup method + WAKE: u1, + /// Word length + M: u1, + /// Mute mode enable + MME: u1, + /// Character match interrupt enable + CMIE: u1, + /// Oversampling mode + OVER8: u1, + /// Driver Enable deassertion time + DEDT: u5, + /// Driver Enable assertion time + DEAT: u5, + /// Receiver timeout interrupt enable + RTOIE: u1, + /// End of Block interrupt enable + EOBIE: u1, + padding: u4, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// 7-bit Address Detection/4-bit Address Detection + ADDM7: u1, + /// LIN break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + /// Swap TX/RX pins + SWAP: u1, + /// RX pin active level inversion + RXINV: u1, + /// TX pin active level inversion + TXINV: u1, + /// Binary data inversion + DATAINV: u1, + /// Most significant bit first + MSBFIRST: u1, + /// Auto baud rate enable + ABREN: u1, + /// Auto baud rate mode + ABRMOD: u2, + /// Receiver timeout enable + RTOEN: u1, + /// Address of the USART node + ADD0: u4, + /// Address of the USART node + ADD4: u4, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + /// Overrun Disable + OVRDIS: u1, + /// DMA Disable on Reception Error + DDRE: u1, + /// Driver enable mode + DEM: u1, + /// Driver enable polarity selection + DEP: u1, + reserved17: u1, + /// Smartcard auto-retry count + SCARCNT: u3, + /// Wakeup from Stop mode interrupt flag selection + WUS: u2, + /// Wakeup from Stop mode interrupt enable + WUFIE: u1, + padding: u9, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + /// Receiver timeout register + RTOR: mmio.Mmio(packed struct(u32) { + /// Receiver timeout value + RTO: u24, + /// Block Length + BLEN: u8, + }), + /// Request register + RQR: mmio.Mmio(packed struct(u32) { + /// Auto baud rate request + ABRRQ: u1, + /// Send break request + SBKRQ: u1, + /// Mute mode request + MMRQ: u1, + /// Receive data flush request + RXFRQ: u1, + /// Transmit data flush request + TXFRQ: u1, + padding: u27, + }), + /// Interrupt & status register + ISR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// Idle line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS interrupt flag + CTSIF: u1, + /// CTS flag + CTS: u1, + /// Receiver timeout + RTOF: u1, + /// End of block flag + EOBF: u1, + reserved14: u1, + /// Auto baud rate error + ABRE: u1, + /// Auto baud rate flag + ABRF: u1, + /// Busy flag + BUSY: u1, + /// character match flag + CMF: u1, + /// Send break flag + SBKF: u1, + /// Receiver wakeup from Mute mode + RWU: u1, + /// Wakeup from Stop mode flag + WUF: u1, + /// Transmit enable acknowledge flag + TEACK: u1, + /// Receive enable acknowledge flag + REACK: u1, + padding: u9, + }), + /// Interrupt flag clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Parity error clear flag + PECF: u1, + /// Framing error clear flag + FECF: u1, + /// Noise detected clear flag + NCF: u1, + /// Overrun error clear flag + ORECF: u1, + /// Idle line detected clear flag + IDLECF: u1, + reserved6: u1, + /// Transmission complete clear flag + TCCF: u1, + reserved8: u1, + /// LIN break detection clear flag + LBDCF: u1, + /// CTS clear flag + CTSCF: u1, + reserved11: u1, + /// Receiver timeout clear flag + RTOCF: u1, + /// End of timeout clear flag + EOBCF: u1, + reserved17: u4, + /// Character match clear flag + CMCF: u1, + reserved20: u2, + /// Wakeup from Stop mode clear flag + WUCF: u1, + padding: u11, + }), + /// Receive data register + RDR: mmio.Mmio(packed struct(u32) { + /// Receive data value + RDR: u9, + padding: u23, + }), + /// Transmit data register + TDR: mmio.Mmio(packed struct(u32) { + /// Transmit data value + TDR: u9, + padding: u23, + }), + }; + + /// System configuration controller _Comparator and Operational amplifier + pub const SYSCFG_COMP_OPAMP = extern struct { + /// configuration register 1 + SYSCFG_CFGR1: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection bits + MEM_MODE: u2, + reserved5: u3, + /// USB interrupt remap + USB_IT_RMP: u1, + /// Timer 1 ITR3 selection + TIM1_ITR_RMP: u1, + /// DAC trigger remap (when TSEL = 001) + DAC_TRIG_RMP: u1, + /// ADC24 DMA remapping bit + ADC24_DMA_RMP: u1, + reserved11: u2, + /// TIM16 DMA request remapping bit + TIM16_DMA_RMP: u1, + /// TIM17 DMA request remapping bit + TIM17_DMA_RMP: u1, + /// TIM6 and DAC1 DMA request remapping bit + TIM6_DAC1_DMA_RMP: u1, + /// TIM7 and DAC2 DMA request remapping bit + TIM7_DAC2_DMA_RMP: u1, + reserved16: u1, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB6_FM: u1, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB7_FM: u1, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB8_FM: u1, + /// Fast Mode Plus (FM+) driving capability activation bits. + I2C_PB9_FM: u1, + /// I2C1 Fast Mode Plus + I2C1_FM: u1, + /// I2C2 Fast Mode Plus + I2C2_FM: u1, + /// Encoder mode + ENCODER_MODE: u2, + reserved26: u2, + /// Interrupt enable bits from FPU + FPU_IT: u6, + }), + /// CCM SRAM protection register + SYSCFG_RCR: mmio.Mmio(packed struct(u32) { + /// CCM SRAM page write protection bit + PAGE0_WP: u1, + /// CCM SRAM page write protection bit + PAGE1_WP: u1, + /// CCM SRAM page write protection bit + PAGE2_WP: u1, + /// CCM SRAM page write protection bit + PAGE3_WP: u1, + /// CCM SRAM page write protection bit + PAGE4_WP: u1, + /// CCM SRAM page write protection bit + PAGE5_WP: u1, + /// CCM SRAM page write protection bit + PAGE6_WP: u1, + /// CCM SRAM page write protection bit + PAGE7_WP: u1, + padding: u24, + }), + /// external interrupt configuration register 1 + SYSCFG_EXTICR1: mmio.Mmio(packed struct(u32) { + /// EXTI 0 configuration bits + EXTI0: u4, + /// EXTI 1 configuration bits + EXTI1: u4, + /// EXTI 2 configuration bits + EXTI2: u4, + /// EXTI 3 configuration bits + EXTI3: u4, + padding: u16, + }), + /// external interrupt configuration register 2 + SYSCFG_EXTICR2: mmio.Mmio(packed struct(u32) { + /// EXTI 4 configuration bits + EXTI4: u4, + /// EXTI 5 configuration bits + EXTI5: u4, + /// EXTI 6 configuration bits + EXTI6: u4, + /// EXTI 7 configuration bits + EXTI7: u4, + padding: u16, + }), + /// external interrupt configuration register 3 + SYSCFG_EXTICR3: mmio.Mmio(packed struct(u32) { + /// EXTI 8 configuration bits + EXTI8: u4, + /// EXTI 9 configuration bits + EXTI9: u4, + /// EXTI 10 configuration bits + EXTI10: u4, + /// EXTI 11 configuration bits + EXTI11: u4, + padding: u16, + }), + /// external interrupt configuration register 4 + SYSCFG_EXTICR4: mmio.Mmio(packed struct(u32) { + /// EXTI 12 configuration bits + EXTI12: u4, + /// EXTI 13 configuration bits + EXTI13: u4, + /// EXTI 14 configuration bits + EXTI14: u4, + /// EXTI 15 configuration bits + EXTI15: u4, + padding: u16, + }), + /// configuration register 2 + SYSCFG_CFGR2: mmio.Mmio(packed struct(u32) { + /// Cortex-M0 LOCKUP bit enable bit + LOCUP_LOCK: u1, + /// SRAM parity lock bit + SRAM_PARITY_LOCK: u1, + /// PVD lock enable bit + PVD_LOCK: u1, + reserved4: u1, + /// Bypass address bit 29 in parity calculation + BYP_ADD_PAR: u1, + reserved8: u3, + /// SRAM parity flag + SRAM_PEF: u1, + padding: u23, + }), + /// control and status register + COMP1_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 1 enable + COMP1EN: u1, + /// COMP1_INP_DAC + COMP1_INP_DAC: u1, + /// Comparator 1 mode + COMP1MODE: u2, + /// Comparator 1 inverting input selection + COMP1INSEL: u3, + reserved10: u3, + /// Comparator 1 output selection + COMP1_OUT_SEL: u4, + reserved15: u1, + /// Comparator 1 output polarity + COMP1POL: u1, + /// Comparator 1 hysteresis + COMP1HYST: u2, + /// Comparator 1 blanking source + COMP1_BLANKING: u3, + reserved30: u9, + /// Comparator 1 output + COMP1OUT: u1, + /// Comparator 1 lock + COMP1LOCK: u1, + }), + /// control and status register + COMP2_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 2 enable + COMP2EN: u1, + reserved2: u1, + /// Comparator 2 mode + COMP2MODE: u2, + /// Comparator 2 inverting input selection + COMP2INSEL: u3, + /// Comparator 2 non inverted input selection + COMP2INPSEL: u1, + reserved9: u1, + /// Comparator 1inverting input selection + COMP2INMSEL: u1, + /// Comparator 2 output selection + COMP2_OUT_SEL: u4, + reserved15: u1, + /// Comparator 2 output polarity + COMP2POL: u1, + /// Comparator 2 hysteresis + COMP2HYST: u2, + /// Comparator 2 blanking source + COMP2_BLANKING: u3, + reserved31: u10, + /// Comparator 2 lock + COMP2LOCK: u1, + }), + /// control and status register + COMP3_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 3 enable + COMP3EN: u1, + reserved2: u1, + /// Comparator 3 mode + COMP3MODE: u2, + /// Comparator 3 inverting input selection + COMP3INSEL: u3, + /// Comparator 3 non inverted input selection + COMP3INPSEL: u1, + reserved10: u2, + /// Comparator 3 output selection + COMP3_OUT_SEL: u4, + reserved15: u1, + /// Comparator 3 output polarity + COMP3POL: u1, + /// Comparator 3 hysteresis + COMP3HYST: u2, + /// Comparator 3 blanking source + COMP3_BLANKING: u3, + reserved30: u9, + /// Comparator 3 output + COMP3OUT: u1, + /// Comparator 3 lock + COMP3LOCK: u1, + }), + /// control and status register + COMP4_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 4 enable + COMP4EN: u1, + reserved2: u1, + /// Comparator 4 mode + COMP4MODE: u2, + /// Comparator 4 inverting input selection + COMP4INSEL: u3, + /// Comparator 4 non inverted input selection + COMP4INPSEL: u1, + reserved9: u1, + /// Comparator 4 window mode + COM4WINMODE: u1, + /// Comparator 4 output selection + COMP4_OUT_SEL: u4, + reserved15: u1, + /// Comparator 4 output polarity + COMP4POL: u1, + /// Comparator 4 hysteresis + COMP4HYST: u2, + /// Comparator 4 blanking source + COMP4_BLANKING: u3, + reserved30: u9, + /// Comparator 4 output + COMP4OUT: u1, + /// Comparator 4 lock + COMP4LOCK: u1, + }), + /// control and status register + COMP5_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 5 enable + COMP5EN: u1, + reserved2: u1, + /// Comparator 5 mode + COMP5MODE: u2, + /// Comparator 5 inverting input selection + COMP5INSEL: u3, + /// Comparator 5 non inverted input selection + COMP5INPSEL: u1, + reserved10: u2, + /// Comparator 5 output selection + COMP5_OUT_SEL: u4, + reserved15: u1, + /// Comparator 5 output polarity + COMP5POL: u1, + /// Comparator 5 hysteresis + COMP5HYST: u2, + /// Comparator 5 blanking source + COMP5_BLANKING: u3, + reserved30: u9, + /// Comparator51 output + COMP5OUT: u1, + /// Comparator 5 lock + COMP5LOCK: u1, + }), + /// control and status register + COMP6_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 6 enable + COMP6EN: u1, + reserved2: u1, + /// Comparator 6 mode + COMP6MODE: u2, + /// Comparator 6 inverting input selection + COMP6INSEL: u3, + /// Comparator 6 non inverted input selection + COMP6INPSEL: u1, + reserved9: u1, + /// Comparator 6 window mode + COM6WINMODE: u1, + /// Comparator 6 output selection + COMP6_OUT_SEL: u4, + reserved15: u1, + /// Comparator 6 output polarity + COMP6POL: u1, + /// Comparator 6 hysteresis + COMP6HYST: u2, + /// Comparator 6 blanking source + COMP6_BLANKING: u3, + reserved30: u9, + /// Comparator 6 output + COMP6OUT: u1, + /// Comparator 6 lock + COMP6LOCK: u1, + }), + /// control and status register + COMP7_CSR: mmio.Mmio(packed struct(u32) { + /// Comparator 7 enable + COMP7EN: u1, + reserved2: u1, + /// Comparator 7 mode + COMP7MODE: u2, + /// Comparator 7 inverting input selection + COMP7INSEL: u3, + /// Comparator 7 non inverted input selection + COMP7INPSEL: u1, + reserved10: u2, + /// Comparator 7 output selection + COMP7_OUT_SEL: u4, + reserved15: u1, + /// Comparator 7 output polarity + COMP7POL: u1, + /// Comparator 7 hysteresis + COMP7HYST: u2, + /// Comparator 7 blanking source + COMP7_BLANKING: u3, + reserved30: u9, + /// Comparator 7 output + COMP7OUT: u1, + /// Comparator 7 lock + COMP7LOCK: u1, + }), + /// control register + OPAMP1_CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP1 enable + OPAMP1_EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP1 Non inverting input selection + VP_SEL: u2, + reserved5: u1, + /// OPAMP1 inverting input selection + VM_SEL: u2, + /// Timer controlled Mux mode enable + TCM_EN: u1, + /// OPAMP1 inverting input secondary selection + VMS_SEL: u1, + /// OPAMP1 Non inverting input secondary selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 1 ouput status flag + OUTCAL: u1, + /// OPAMP 1 lock + LOCK: u1, + }), + /// control register + OPAMP2_CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP2 enable + OPAMP2EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP2 Non inverting input selection + VP_SEL: u2, + reserved5: u1, + /// OPAMP2 inverting input selection + VM_SEL: u2, + /// Timer controlled Mux mode enable + TCM_EN: u1, + /// OPAMP2 inverting input secondary selection + VMS_SEL: u1, + /// OPAMP2 Non inverting input secondary selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CAL_SEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 2 ouput status flag + OUTCAL: u1, + /// OPAMP 2 lock + LOCK: u1, + }), + /// control register + OPAMP3_CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP3 enable + OPAMP3EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP3 Non inverting input selection + VP_SEL: u2, + reserved5: u1, + /// OPAMP3 inverting input selection + VM_SEL: u2, + /// Timer controlled Mux mode enable + TCM_EN: u1, + /// OPAMP3 inverting input secondary selection + VMS_SEL: u1, + /// OPAMP3 Non inverting input secondary selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 3 ouput status flag + OUTCAL: u1, + /// OPAMP 3 lock + LOCK: u1, + }), + /// control register + OPAMP4_CSR: mmio.Mmio(packed struct(u32) { + /// OPAMP4 enable + OPAMP4EN: u1, + /// FORCE_VP + FORCE_VP: u1, + /// OPAMP4 Non inverting input selection + VP_SEL: u2, + reserved5: u1, + /// OPAMP4 inverting input selection + VM_SEL: u2, + /// Timer controlled Mux mode enable + TCM_EN: u1, + /// OPAMP4 inverting input secondary selection + VMS_SEL: u1, + /// OPAMP4 Non inverting input secondary selection + VPS_SEL: u2, + /// Calibration mode enable + CALON: u1, + /// Calibration selection + CALSEL: u2, + /// Gain in PGA mode + PGA_GAIN: u4, + /// User trimming enable + USER_TRIM: u1, + /// Offset trimming value (PMOS) + TRIMOFFSETP: u5, + /// Offset trimming value (NMOS) + TRIMOFFSETN: u5, + /// TSTREF + TSTREF: u1, + /// OPAMP 4 ouput status flag + OUTCAL: u1, + /// OPAMP 4 lock + LOCK: u1, + }), + }; + + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value + KEY: u16, + padding: u16, + }), + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: u3, + padding: u29, + }), + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + /// Watchdog counter window value update + WVU: u1, + padding: u29, + }), + /// Window register + WINR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter window value + WIN: u12, + padding: u20, + }), + }; + + /// Analog-to-Digital Converter + pub const ADC1_2 = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// ADDRDY_MST + ADDRDY_MST: u1, + /// EOSMP_MST + EOSMP_MST: u1, + /// EOC_MST + EOC_MST: u1, + /// EOS_MST + EOS_MST: u1, + /// OVR_MST + OVR_MST: u1, + /// JEOC_MST + JEOC_MST: u1, + /// JEOS_MST + JEOS_MST: u1, + /// AWD1_MST + AWD1_MST: u1, + /// AWD2_MST + AWD2_MST: u1, + /// AWD3_MST + AWD3_MST: u1, + /// JQOVF_MST + JQOVF_MST: u1, + reserved16: u5, + /// ADRDY_SLV + ADRDY_SLV: u1, + /// EOSMP_SLV + EOSMP_SLV: u1, + /// End of regular conversion of the slave ADC + EOC_SLV: u1, + /// End of regular sequence flag of the slave ADC + EOS_SLV: u1, + /// Overrun flag of the slave ADC + OVR_SLV: u1, + /// End of injected conversion flag of the slave ADC + JEOC_SLV: u1, + /// End of injected sequence flag of the slave ADC + JEOS_SLV: u1, + /// Analog watchdog 1 flag of the slave ADC + AWD1_SLV: u1, + /// Analog watchdog 2 flag of the slave ADC + AWD2_SLV: u1, + /// Analog watchdog 3 flag of the slave ADC + AWD3_SLV: u1, + /// Injected Context Queue Overflow flag of the slave ADC + JQOVF_SLV: u1, + padding: u5, + }), + reserved8: [4]u8, + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Multi ADC mode selection + MULT: u5, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// DMA configuration (for multi-ADC mode) + DMACFG: u1, + /// Direct memory access mode for multi ADC mode + MDMA: u2, + /// ADC clock mode + CKMODE: u2, + reserved22: u4, + /// VREFINT enable + VREFEN: u1, + /// Temperature sensor enable + TSEN: u1, + /// VBAT enable + VBATEN: u1, + padding: u7, + }), + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// Regular data of the master ADC + RDATA_MST: u16, + /// Regular data of the slave ADC + RDATA_SLV: u16, + }), + }; + + /// Window watchdog + pub const WWDG = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// 7-bit counter + T: u7, + /// Activation bit + WDGA: u1, + padding: u24, + }), + /// Configuration register + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB: u2, + /// Early wakeup interrupt + EWI: u1, + padding: u22, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, + }), + }; + + /// Serial peripheral interface/Inter-IC sound + pub const SPI1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// CRC length + CRCL: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Output enable in bidirectional mode + BIDIOE: u1, + /// Bidirectional data mode enable + BIDIMODE: u1, + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + /// NSS pulse management + NSSP: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + /// Data size + DS: u4, + /// FIFO reception threshold + FRXTH: u1, + /// Last DMA transfer for reception + LDMA_RX: u1, + /// Last DMA transfer for transmission + LDMA_TX: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + /// FIFO reception level + FRLVL: u2, + /// FIFO transmission level + FTLVL: u2, + padding: u19, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, + padding: u16, + }), + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, + }), + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, + }), + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, + }), + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: u1, + /// Data length to be transferred + DATLEN: u2, + /// Steady state clock polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding: u22, + }), + }; + + /// Real-time clock + pub const RTC = extern struct { + /// time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, + }), + /// date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active edge + TSEDGE: u1, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + /// Bypass the shadow registers + BYPSHAD: u1, + /// Hour format + FMT: u1, + reserved8: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Time-stamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + /// Calibration output selection + COSEL: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// RTC_TAMP2 detection flag + TAMP2F: u1, + /// RTC_TAMP3 detection flag + TAMP3F: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding: u15, + }), + /// prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + reserved28: [4]u8, + /// alarm A register + ALRMAR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), + /// alarm B register + ALRMBR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), + /// write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// time stamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, + }), + /// time stamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, + }), + /// timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: u1, + /// Use an 8-second calibration cycle period + CALW8: u1, + /// Increase frequency of RTC by 488.5 ppm + CALP: u1, + padding: u16, + }), + /// tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + /// Tamper 3 detection enable + TAMP3E: u1, + /// Active level for tamper 3 + TAMP3TRG: u1, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + reserved18: u2, + /// PC13 value + PC13VALUE: u1, + /// PC13 mode + PC13MODE: u1, + /// PC14 value + PC14VALUE: u1, + /// PC 14 mode + PC14MODE: u1, + /// PC15 value + PC15VALUE: u1, + /// PC15 mode + PC15MODE: u1, + padding: u8, + }), + /// alarm A sub second register + ALRMASSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + /// alarm B sub second register + ALRMBSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [4]u8, + /// backup register + BKP0R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP1R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP2R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP3R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP4R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP5R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP6R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP7R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP8R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP9R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP10R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP11R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP12R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP13R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP14R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP15R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP16R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP17R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP18R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP19R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP20R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP21R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP22R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP23R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP24R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP25R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP26R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP27R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP28R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP29R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP30R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP31R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + }; + + /// Basic timers + pub const TIM6 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + reserved11: u3, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT: u16, + reserved31: u15, + /// UIF Copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// Analog-to-Digital Converter + pub const ADC1 = extern struct { + /// interrupt and status register + ISR: mmio.Mmio(packed struct(u32) { + /// ADRDY + ADRDY: u1, + /// EOSMP + EOSMP: u1, + /// EOC + EOC: u1, + /// EOS + EOS: u1, + /// OVR + OVR: u1, + /// JEOC + JEOC: u1, + /// JEOS + JEOS: u1, + /// AWD1 + AWD1: u1, + /// AWD2 + AWD2: u1, + /// AWD3 + AWD3: u1, + /// JQOVF + JQOVF: u1, + padding: u21, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// ADRDYIE + ADRDYIE: u1, + /// EOSMPIE + EOSMPIE: u1, + /// EOCIE + EOCIE: u1, + /// EOSIE + EOSIE: u1, + /// OVRIE + OVRIE: u1, + /// JEOCIE + JEOCIE: u1, + /// JEOSIE + JEOSIE: u1, + /// AWD1IE + AWD1IE: u1, + /// AWD2IE + AWD2IE: u1, + /// AWD3IE + AWD3IE: u1, + /// JQOVFIE + JQOVFIE: u1, + padding: u21, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// ADEN + ADEN: u1, + /// ADDIS + ADDIS: u1, + /// ADSTART + ADSTART: u1, + /// JADSTART + JADSTART: u1, + /// ADSTP + ADSTP: u1, + /// JADSTP + JADSTP: u1, + reserved28: u22, + /// ADVREGEN + ADVREGEN: u1, + /// DEEPPWD + DEEPPWD: u1, + /// ADCALDIF + ADCALDIF: u1, + /// ADCAL + ADCAL: u1, + }), + /// configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// DMAEN + DMAEN: u1, + /// DMACFG + DMACFG: u1, + reserved3: u1, + /// RES + RES: u2, + /// ALIGN + ALIGN: u1, + /// EXTSEL + EXTSEL: u4, + /// EXTEN + EXTEN: u2, + /// OVRMOD + OVRMOD: u1, + /// CONT + CONT: u1, + /// AUTDLY + AUTDLY: u1, + /// AUTOFF + AUTOFF: u1, + /// DISCEN + DISCEN: u1, + /// DISCNUM + DISCNUM: u3, + /// JDISCEN + JDISCEN: u1, + /// JQM + JQM: u1, + /// AWD1SGL + AWD1SGL: u1, + /// AWD1EN + AWD1EN: u1, + /// JAWD1EN + JAWD1EN: u1, + /// JAUTO + JAUTO: u1, + /// AWDCH1CH + AWDCH1CH: u5, + padding: u1, + }), + reserved20: [4]u8, + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// SMP1 + SMP1: u3, + /// SMP2 + SMP2: u3, + /// SMP3 + SMP3: u3, + /// SMP4 + SMP4: u3, + /// SMP5 + SMP5: u3, + /// SMP6 + SMP6: u3, + /// SMP7 + SMP7: u3, + /// SMP8 + SMP8: u3, + /// SMP9 + SMP9: u3, + padding: u2, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// SMP10 + SMP10: u3, + /// SMP11 + SMP11: u3, + /// SMP12 + SMP12: u3, + /// SMP13 + SMP13: u3, + /// SMP14 + SMP14: u3, + /// SMP15 + SMP15: u3, + /// SMP16 + SMP16: u3, + /// SMP17 + SMP17: u3, + /// SMP18 + SMP18: u3, + padding: u5, + }), + reserved32: [4]u8, + /// watchdog threshold register 1 + TR1: mmio.Mmio(packed struct(u32) { + /// LT1 + LT1: u12, + reserved16: u4, + /// HT1 + HT1: u12, + padding: u4, + }), + /// watchdog threshold register + TR2: mmio.Mmio(packed struct(u32) { + /// LT2 + LT2: u8, + reserved16: u8, + /// HT2 + HT2: u8, + padding: u8, + }), + /// watchdog threshold register 3 + TR3: mmio.Mmio(packed struct(u32) { + /// LT3 + LT3: u8, + reserved16: u8, + /// HT3 + HT3: u8, + padding: u8, + }), + reserved48: [4]u8, + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// L3 + L3: u4, + reserved6: u2, + /// SQ1 + SQ1: u5, + reserved12: u1, + /// SQ2 + SQ2: u5, + reserved18: u1, + /// SQ3 + SQ3: u5, + reserved24: u1, + /// SQ4 + SQ4: u5, + padding: u3, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// SQ5 + SQ5: u5, + reserved6: u1, + /// SQ6 + SQ6: u5, + reserved12: u1, + /// SQ7 + SQ7: u5, + reserved18: u1, + /// SQ8 + SQ8: u5, + reserved24: u1, + /// SQ9 + SQ9: u5, + padding: u3, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// SQ10 + SQ10: u5, + reserved6: u1, + /// SQ11 + SQ11: u5, + reserved12: u1, + /// SQ12 + SQ12: u5, + reserved18: u1, + /// SQ13 + SQ13: u5, + reserved24: u1, + /// SQ14 + SQ14: u5, + padding: u3, + }), + /// regular sequence register 4 + SQR4: mmio.Mmio(packed struct(u32) { + /// SQ15 + SQ15: u5, + reserved6: u1, + /// SQ16 + SQ16: u5, + padding: u21, + }), + /// regular Data Register + DR: mmio.Mmio(packed struct(u32) { + /// regularDATA + regularDATA: u16, + padding: u16, + }), + reserved76: [8]u8, + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// JL + JL: u2, + /// JEXTSEL + JEXTSEL: u4, + /// JEXTEN + JEXTEN: u2, + /// JSQ1 + JSQ1: u5, + reserved14: u1, + /// JSQ2 + JSQ2: u5, + reserved20: u1, + /// JSQ3 + JSQ3: u5, + reserved26: u1, + /// JSQ4 + JSQ4: u5, + padding: u1, + }), + reserved96: [16]u8, + /// offset register 1 + OFR1: mmio.Mmio(packed struct(u32) { + /// OFFSET1 + OFFSET1: u12, + reserved26: u14, + /// OFFSET1_CH + OFFSET1_CH: u5, + /// OFFSET1_EN + OFFSET1_EN: u1, + }), + /// offset register 2 + OFR2: mmio.Mmio(packed struct(u32) { + /// OFFSET2 + OFFSET2: u12, + reserved26: u14, + /// OFFSET2_CH + OFFSET2_CH: u5, + /// OFFSET2_EN + OFFSET2_EN: u1, + }), + /// offset register 3 + OFR3: mmio.Mmio(packed struct(u32) { + /// OFFSET3 + OFFSET3: u12, + reserved26: u14, + /// OFFSET3_CH + OFFSET3_CH: u5, + /// OFFSET3_EN + OFFSET3_EN: u1, + }), + /// offset register 4 + OFR4: mmio.Mmio(packed struct(u32) { + /// OFFSET4 + OFFSET4: u12, + reserved26: u14, + /// OFFSET4_CH + OFFSET4_CH: u5, + /// OFFSET4_EN + OFFSET4_EN: u1, + }), + reserved128: [16]u8, + /// injected data register 1 + JDR1: mmio.Mmio(packed struct(u32) { + /// JDATA1 + JDATA1: u16, + padding: u16, + }), + /// injected data register 2 + JDR2: mmio.Mmio(packed struct(u32) { + /// JDATA2 + JDATA2: u16, + padding: u16, + }), + /// injected data register 3 + JDR3: mmio.Mmio(packed struct(u32) { + /// JDATA3 + JDATA3: u16, + padding: u16, + }), + /// injected data register 4 + JDR4: mmio.Mmio(packed struct(u32) { + /// JDATA4 + JDATA4: u16, + padding: u16, + }), + reserved160: [16]u8, + /// Analog Watchdog 2 Configuration Register + AWD2CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// AWD2CH + AWD2CH: u18, + padding: u13, + }), + /// Analog Watchdog 3 Configuration Register + AWD3CR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// AWD3CH + AWD3CH: u18, + padding: u13, + }), + reserved176: [8]u8, + /// Differential Mode Selection Register 2 + DIFSEL: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Differential mode for channels 15 to 1 + DIFSEL_1_15: u15, + /// Differential mode for channels 18 to 16 + DIFSEL_16_18: u3, + padding: u13, + }), + /// Calibration Factors + CALFACT: mmio.Mmio(packed struct(u32) { + /// CALFACT_S + CALFACT_S: u7, + reserved16: u9, + /// CALFACT_D + CALFACT_D: u7, + padding: u9, + }), + }; + + /// Advanced-timers + pub const TIM8 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved16: u1, + /// Output Idle state 5 + OIS5: u1, + reserved18: u1, + /// Output Idle state 6 + OIS6: u1, + reserved20: u1, + /// Master mode selection 2 + MMS2: u4, + padding: u8, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding: u15, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + reserved16: u3, + /// Capture/Compare 5 interrupt flag + C5IF: u1, + /// Capture/Compare 6 interrupt flag + C6IF: u1, + padding: u14, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding: u23, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear enable + OC2CE: u1, + /// Output Compare 1 mode bit 3 + OC1M_3: u1, + reserved24: u7, + /// Output Compare 2 mode bit 3 + OC2M_3: u1, + padding: u7, + }), + /// capture/compare mode register (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + OC4CE: u1, + /// Output Compare 3 mode bit 3 + OC3M_3: u1, + reserved24: u7, + /// Output Compare 4 mode bit 3 + OC4M_3: u1, + padding: u7, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output enable + CC2NE: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output enable + CC3NE: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + /// Capture/Compare 5 output enable + CC5E: u1, + /// Capture/Compare 5 output Polarity + CC5P: u1, + reserved20: u2, + /// Capture/Compare 6 output enable + CC6E: u1, + /// Capture/Compare 6 output Polarity + CC6P: u1, + padding: u10, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u16, + padding: u16, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 value + CCR4: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding: u6, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + reserved84: [4]u8, + /// capture/compare mode register 3 (output mode) + CCMR3_Output: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Output compare 5 fast enable + OC5FE: u1, + /// Output compare 5 preload enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear enable + OC5CE: u1, + reserved10: u2, + /// Output compare 6 fast enable + OC6FE: u1, + /// Output compare 6 preload enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear enable + OC6CE: u1, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1, + reserved24: u7, + /// Outout Compare 6 mode bit 3 + OC6M_3: u1, + padding: u7, + }), + /// capture/compare register 5 + CCR5: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 5 value + CCR5: u16, + reserved29: u13, + /// Group Channel 5 and Channel 1 + GC5C1: u1, + /// Group Channel 5 and Channel 2 + GC5C2: u1, + /// Group Channel 5 and Channel 3 + GC5C3: u1, + }), + /// capture/compare register 6 + CCR6: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 6 value + CCR6: u16, + padding: u16, + }), + /// option registers + OR: mmio.Mmio(packed struct(u32) { + /// TIM8_ETR_ADC2 remapping capability + TIM8_ETR_ADC2_RMP: u2, + /// TIM8_ETR_ADC3 remapping capability + TIM8_ETR_ADC3_RMP: u2, + padding: u28, + }), + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer disable + BOFF1: u1, + /// DAC channel1 trigger enable + TEN1: u1, + /// DAC channel1 trigger selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt enable + DMAUDRIE1: u1, + reserved16: u2, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer disable + BOFF2: u1, + /// DAC channel2 trigger enable + TEN2: u1, + /// DAC channel2 trigger selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt enable + DMAUDRIE2: u1, + padding: u2, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 software trigger + SWTRIG1: u1, + /// DAC channel2 software trigger + SWTRIG2: u1, + padding: u30, + }), + /// channel1 12-bit right-aligned data holding register + DHR12R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + padding: u20, + }), + /// channel1 12-bit left aligned data holding register + DHR12L1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + padding: u16, + }), + /// channel1 8-bit right aligned data holding register + DHR8R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + padding: u24, + }), + /// channel2 12-bit right aligned data holding register + DHR12R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u20, + }), + /// channel2 12-bit left aligned data holding register + DHR12L2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + padding: u16, + }), + /// channel2 8-bit right-aligned data holding register + DHR8R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u24, + }), + /// Dual DAC 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + reserved16: u4, + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u4, + }), + /// DUAL DAC 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + reserved20: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + }), + /// DUAL DAC 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u16, + }), + /// channel1 data output register + DOR1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 data output + DACC1DOR: u12, + padding: u20, + }), + /// channel2 data output register + DOR2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 data output + DACC2DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// DAC channel1 DMA underrun flag + DMAUDR1: u1, + reserved29: u15, + /// DAC channel2 DMA underrun flag + DMAUDR2: u1, + padding: u2, + }), + }; + + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Interrupt mask register + IMR1: mmio.Mmio(packed struct(u32) { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + /// Interrupt Mask on line 23 + MR23: u1, + /// Interrupt Mask on line 24 + MR24: u1, + /// Interrupt Mask on line 25 + MR25: u1, + /// Interrupt Mask on line 26 + MR26: u1, + /// Interrupt Mask on line 27 + MR27: u1, + /// Interrupt Mask on line 28 + MR28: u1, + /// Interrupt Mask on line 29 + MR29: u1, + /// Interrupt Mask on line 30 + MR30: u1, + /// Interrupt Mask on line 31 + MR31: u1, + }), + /// Event mask register + EMR1: mmio.Mmio(packed struct(u32) { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + /// Event Mask on line 23 + MR23: u1, + /// Event Mask on line 24 + MR24: u1, + /// Event Mask on line 25 + MR25: u1, + /// Event Mask on line 26 + MR26: u1, + /// Event Mask on line 27 + MR27: u1, + /// Event Mask on line 28 + MR28: u1, + /// Event Mask on line 29 + MR29: u1, + /// Event Mask on line 30 + MR30: u1, + /// Event Mask on line 31 + MR31: u1, + }), + /// Rising Trigger selection register + RTSR1: mmio.Mmio(packed struct(u32) { + /// Rising trigger event configuration of line 0 + TR0: u1, + /// Rising trigger event configuration of line 1 + TR1: u1, + /// Rising trigger event configuration of line 2 + TR2: u1, + /// Rising trigger event configuration of line 3 + TR3: u1, + /// Rising trigger event configuration of line 4 + TR4: u1, + /// Rising trigger event configuration of line 5 + TR5: u1, + /// Rising trigger event configuration of line 6 + TR6: u1, + /// Rising trigger event configuration of line 7 + TR7: u1, + /// Rising trigger event configuration of line 8 + TR8: u1, + /// Rising trigger event configuration of line 9 + TR9: u1, + /// Rising trigger event configuration of line 10 + TR10: u1, + /// Rising trigger event configuration of line 11 + TR11: u1, + /// Rising trigger event configuration of line 12 + TR12: u1, + /// Rising trigger event configuration of line 13 + TR13: u1, + /// Rising trigger event configuration of line 14 + TR14: u1, + /// Rising trigger event configuration of line 15 + TR15: u1, + /// Rising trigger event configuration of line 16 + TR16: u1, + /// Rising trigger event configuration of line 17 + TR17: u1, + /// Rising trigger event configuration of line 18 + TR18: u1, + /// Rising trigger event configuration of line 19 + TR19: u1, + /// Rising trigger event configuration of line 20 + TR20: u1, + /// Rising trigger event configuration of line 21 + TR21: u1, + /// Rising trigger event configuration of line 22 + TR22: u1, + reserved29: u6, + /// Rising trigger event configuration of line 29 + TR29: u1, + /// Rising trigger event configuration of line 30 + TR30: u1, + /// Rising trigger event configuration of line 31 + TR31: u1, + }), + /// Falling Trigger selection register + FTSR1: mmio.Mmio(packed struct(u32) { + /// Falling trigger event configuration of line 0 + TR0: u1, + /// Falling trigger event configuration of line 1 + TR1: u1, + /// Falling trigger event configuration of line 2 + TR2: u1, + /// Falling trigger event configuration of line 3 + TR3: u1, + /// Falling trigger event configuration of line 4 + TR4: u1, + /// Falling trigger event configuration of line 5 + TR5: u1, + /// Falling trigger event configuration of line 6 + TR6: u1, + /// Falling trigger event configuration of line 7 + TR7: u1, + /// Falling trigger event configuration of line 8 + TR8: u1, + /// Falling trigger event configuration of line 9 + TR9: u1, + /// Falling trigger event configuration of line 10 + TR10: u1, + /// Falling trigger event configuration of line 11 + TR11: u1, + /// Falling trigger event configuration of line 12 + TR12: u1, + /// Falling trigger event configuration of line 13 + TR13: u1, + /// Falling trigger event configuration of line 14 + TR14: u1, + /// Falling trigger event configuration of line 15 + TR15: u1, + /// Falling trigger event configuration of line 16 + TR16: u1, + /// Falling trigger event configuration of line 17 + TR17: u1, + /// Falling trigger event configuration of line 18 + TR18: u1, + /// Falling trigger event configuration of line 19 + TR19: u1, + /// Falling trigger event configuration of line 20 + TR20: u1, + /// Falling trigger event configuration of line 21 + TR21: u1, + /// Falling trigger event configuration of line 22 + TR22: u1, + reserved29: u6, + /// Falling trigger event configuration of line 29 + TR29: u1, + /// Falling trigger event configuration of line 30. + TR30: u1, + /// Falling trigger event configuration of line 31 + TR31: u1, + }), + /// Software interrupt event register + SWIER1: mmio.Mmio(packed struct(u32) { + /// Software Interrupt on line 0 + SWIER0: u1, + /// Software Interrupt on line 1 + SWIER1: u1, + /// Software Interrupt on line 2 + SWIER2: u1, + /// Software Interrupt on line 3 + SWIER3: u1, + /// Software Interrupt on line 4 + SWIER4: u1, + /// Software Interrupt on line 5 + SWIER5: u1, + /// Software Interrupt on line 6 + SWIER6: u1, + /// Software Interrupt on line 7 + SWIER7: u1, + /// Software Interrupt on line 8 + SWIER8: u1, + /// Software Interrupt on line 9 + SWIER9: u1, + /// Software Interrupt on line 10 + SWIER10: u1, + /// Software Interrupt on line 11 + SWIER11: u1, + /// Software Interrupt on line 12 + SWIER12: u1, + /// Software Interrupt on line 13 + SWIER13: u1, + /// Software Interrupt on line 14 + SWIER14: u1, + /// Software Interrupt on line 15 + SWIER15: u1, + /// Software Interrupt on line 16 + SWIER16: u1, + /// Software Interrupt on line 17 + SWIER17: u1, + /// Software Interrupt on line 18 + SWIER18: u1, + /// Software Interrupt on line 19 + SWIER19: u1, + /// Software Interrupt on line 20 + SWIER20: u1, + /// Software Interrupt on line 21 + SWIER21: u1, + /// Software Interrupt on line 22 + SWIER22: u1, + reserved29: u6, + /// Software Interrupt on line 29 + SWIER29: u1, + /// Software Interrupt on line 309 + SWIER30: u1, + /// Software Interrupt on line 319 + SWIER31: u1, + }), + /// Pending register + PR1: mmio.Mmio(packed struct(u32) { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + reserved29: u6, + /// Pending bit 29 + PR29: u1, + /// Pending bit 30 + PR30: u1, + /// Pending bit 31 + PR31: u1, + }), + /// Interrupt mask register + IMR2: mmio.Mmio(packed struct(u32) { + /// Interrupt Mask on external/internal line 32 + MR32: u1, + /// Interrupt Mask on external/internal line 33 + MR33: u1, + /// Interrupt Mask on external/internal line 34 + MR34: u1, + /// Interrupt Mask on external/internal line 35 + MR35: u1, + padding: u28, + }), + /// Event mask register + EMR2: mmio.Mmio(packed struct(u32) { + /// Event mask on external/internal line 32 + MR32: u1, + /// Event mask on external/internal line 33 + MR33: u1, + /// Event mask on external/internal line 34 + MR34: u1, + /// Event mask on external/internal line 35 + MR35: u1, + padding: u28, + }), + /// Rising Trigger selection register + RTSR2: mmio.Mmio(packed struct(u32) { + /// Rising trigger event configuration bit of line 32 + TR32: u1, + /// Rising trigger event configuration bit of line 33 + TR33: u1, + padding: u30, + }), + /// Falling Trigger selection register + FTSR2: mmio.Mmio(packed struct(u32) { + /// Falling trigger event configuration bit of line 32 + TR32: u1, + /// Falling trigger event configuration bit of line 33 + TR33: u1, + padding: u30, + }), + /// Software interrupt event register + SWIER2: mmio.Mmio(packed struct(u32) { + /// Software interrupt on line 32 + SWIER32: u1, + /// Software interrupt on line 33 + SWIER33: u1, + padding: u30, + }), + /// Pending register + PR2: mmio.Mmio(packed struct(u32) { + /// Pending bit on line 32 + PR32: u1, + /// Pending bit on line 33 + PR33: u1, + padding: u30, + }), + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + padding: u23, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + reserved8: u5, + /// Enable WKUP1 pin + EWUP1: u1, + /// Enable WKUP2 pin + EWUP2: u1, + padding: u22, + }), + }; + + /// Controller area network + pub const CAN = extern struct { + /// master control register + MCR: mmio.Mmio(packed struct(u32) { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved15: u7, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding: u15, + }), + /// master status register + MSR: mmio.Mmio(packed struct(u32) { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved8: u3, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding: u20, + }), + /// transmit status register + TSR: mmio.Mmio(packed struct(u32) { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved7: u3, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved15: u3, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved23: u3, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox 0 + TME0: u1, + /// Lowest priority flag for mailbox 1 + TME1: u1, + /// Lowest priority flag for mailbox 2 + TME2: u1, + /// Lowest priority flag for mailbox 0 + LOW0: u1, + /// Lowest priority flag for mailbox 1 + LOW1: u1, + /// Lowest priority flag for mailbox 2 + LOW2: u1, + }), + /// receive FIFO 0 register + RF0R: mmio.Mmio(packed struct(u32) { + /// FMP0 + FMP0: u2, + reserved3: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding: u26, + }), + /// receive FIFO 1 register + RF1R: mmio.Mmio(packed struct(u32) { + /// FMP1 + FMP1: u2, + reserved3: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding: u26, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved8: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved15: u3, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding: u14, + }), + /// error status register + ESR: mmio.Mmio(packed struct(u32) { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved4: u1, + /// LEC + LEC: u3, + reserved16: u9, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), + /// bit timing register + BTR: mmio.Mmio(packed struct(u32) { + /// BRP + BRP: u10, + reserved16: u6, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved24: u1, + /// SJW + SJW: u2, + reserved30: u4, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), + reserved384: [352]u8, + /// TX mailbox identifier register + TI0R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// TX mailbox identifier register + TI1R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// TX mailbox identifier register + TI2R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT2R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL2R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH2R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// receive FIFO mailbox identifier register + RI0R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// receive FIFO mailbox data length control and time stamp register + RDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// receive FIFO mailbox data low register + RDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// receive FIFO mailbox data high register + RDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// receive FIFO mailbox identifier register + RI1R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// receive FIFO mailbox data length control and time stamp register + RDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// receive FIFO mailbox data low register + RDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// receive FIFO mailbox data high register + RDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + reserved512: [48]u8, + /// filter master register + FMR: mmio.Mmio(packed struct(u32) { + /// Filter init mode + FINIT: u1, + reserved8: u7, + /// CAN2 start bank + CAN2SB: u6, + padding: u18, + }), + /// filter mode register + FM1R: mmio.Mmio(packed struct(u32) { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding: u4, + }), + reserved524: [4]u8, + /// filter scale register + FS1R: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding: u4, + }), + reserved532: [4]u8, + /// filter FIFO assignment register + FFA1R: mmio.Mmio(packed struct(u32) { + /// Filter FIFO assignment for filter 0 + FFA0: u1, + /// Filter FIFO assignment for filter 1 + FFA1: u1, + /// Filter FIFO assignment for filter 2 + FFA2: u1, + /// Filter FIFO assignment for filter 3 + FFA3: u1, + /// Filter FIFO assignment for filter 4 + FFA4: u1, + /// Filter FIFO assignment for filter 5 + FFA5: u1, + /// Filter FIFO assignment for filter 6 + FFA6: u1, + /// Filter FIFO assignment for filter 7 + FFA7: u1, + /// Filter FIFO assignment for filter 8 + FFA8: u1, + /// Filter FIFO assignment for filter 9 + FFA9: u1, + /// Filter FIFO assignment for filter 10 + FFA10: u1, + /// Filter FIFO assignment for filter 11 + FFA11: u1, + /// Filter FIFO assignment for filter 12 + FFA12: u1, + /// Filter FIFO assignment for filter 13 + FFA13: u1, + /// Filter FIFO assignment for filter 14 + FFA14: u1, + /// Filter FIFO assignment for filter 15 + FFA15: u1, + /// Filter FIFO assignment for filter 16 + FFA16: u1, + /// Filter FIFO assignment for filter 17 + FFA17: u1, + /// Filter FIFO assignment for filter 18 + FFA18: u1, + /// Filter FIFO assignment for filter 19 + FFA19: u1, + /// Filter FIFO assignment for filter 20 + FFA20: u1, + /// Filter FIFO assignment for filter 21 + FFA21: u1, + /// Filter FIFO assignment for filter 22 + FFA22: u1, + /// Filter FIFO assignment for filter 23 + FFA23: u1, + /// Filter FIFO assignment for filter 24 + FFA24: u1, + /// Filter FIFO assignment for filter 25 + FFA25: u1, + /// Filter FIFO assignment for filter 26 + FFA26: u1, + /// Filter FIFO assignment for filter 27 + FFA27: u1, + padding: u4, + }), + reserved540: [4]u8, + /// CAN filter activation register + FA1R: mmio.Mmio(packed struct(u32) { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding: u4, + }), + reserved576: [32]u8, + /// Filter bank 0 register 1 + F0R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 0 register 2 + F0R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 1 + F1R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 2 + F1R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 1 + F2R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 2 + F2R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 1 + F3R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 2 + F3R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F4R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 2 + F4R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 1 + F5R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 2 + F5R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 1 + F6R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 2 + F6R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 1 + F7R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 2 + F7R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 1 + F8R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 2 + F8R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 1 + F9R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 2 + F9R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 1 + F10R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 2 + F10R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 1 + F11R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 2 + F11R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F12R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 12 register 2 + F12R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 1 + F13R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 2 + F13R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 1 + F14R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 2 + F14R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 1 + F15R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 2 + F15R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 1 + F16R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 2 + F16R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 1 + F17R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 2 + F17R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 1 + F18R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 2 + F18R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 1 + F19R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 2 + F19R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 1 + F20R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 2 + F20R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 1 + F21R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 2 + F21R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 1 + F22R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 2 + F22R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 1 + F23R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 2 + F23R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 1 + F24R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 2 + F24R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 1 + F25R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 2 + F25R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 1 + F26R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 2 + F26R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 1 + F27R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 2 + F27R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + }; + + /// Universal serial bus full-speed device interface + pub const USB_FS = extern struct { + /// endpoint 0 register + USB_EP0R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 1 register + USB_EP1R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 2 register + USB_EP2R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 3 register + USB_EP3R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 4 register + USB_EP4R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 5 register + USB_EP5R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 6 register + USB_EP6R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + /// endpoint 7 register + USB_EP7R: mmio.Mmio(packed struct(u32) { + /// Endpoint address + EA: u4, + /// Status bits, for transmission transfers + STAT_TX: u2, + /// Data Toggle, for transmission transfers + DTOG_TX: u1, + /// Correct Transfer for transmission + CTR_TX: u1, + /// Endpoint kind + EP_KIND: u1, + /// Endpoint type + EP_TYPE: u2, + /// Setup transaction completed + SETUP: u1, + /// Status bits, for reception transfers + STAT_RX: u2, + /// Data Toggle, for reception transfers + DTOG_RX: u1, + /// Correct transfer for reception + CTR_RX: u1, + padding: u16, + }), + reserved64: [32]u8, + /// control register + USB_CNTR: mmio.Mmio(packed struct(u32) { + /// Force USB Reset + FRES: u1, + /// Power down + PDWN: u1, + /// Low-power mode + LPMODE: u1, + /// Force suspend + FSUSP: u1, + /// Resume request + RESUME: u1, + reserved8: u3, + /// Expected start of frame interrupt mask + ESOFM: u1, + /// Start of frame interrupt mask + SOFM: u1, + /// USB reset interrupt mask + RESETM: u1, + /// Suspend mode interrupt mask + SUSPM: u1, + /// Wakeup interrupt mask + WKUPM: u1, + /// Error interrupt mask + ERRM: u1, + /// Packet memory area over / underrun interrupt mask + PMAOVRM: u1, + /// Correct transfer interrupt mask + CTRM: u1, + padding: u16, + }), + /// interrupt status register + ISTR: mmio.Mmio(packed struct(u32) { + /// Endpoint Identifier + EP_ID: u4, + /// Direction of transaction + DIR: u1, + reserved8: u3, + /// Expected start frame + ESOF: u1, + /// start of frame + SOF: u1, + /// reset request + RESET: u1, + /// Suspend mode request + SUSP: u1, + /// Wakeup + WKUP: u1, + /// Error + ERR: u1, + /// Packet memory area over / underrun + PMAOVR: u1, + /// Correct transfer + CTR: u1, + padding: u16, + }), + /// frame number register + FNR: mmio.Mmio(packed struct(u32) { + /// Frame number + FN: u11, + /// Lost SOF + LSOF: u2, + /// Locked + LCK: u1, + /// Receive data - line status + RXDM: u1, + /// Receive data + line status + RXDP: u1, + padding: u16, + }), + /// device address + DADDR: mmio.Mmio(packed struct(u32) { + /// Device address + ADD: u1, + /// Device address + ADD1: u1, + /// Device address + ADD2: u1, + /// Device address + ADD3: u1, + /// Device address + ADD4: u1, + /// Device address + ADD5: u1, + /// Device address + ADD6: u1, + /// Enable function + EF: u1, + padding: u24, + }), + /// Buffer table address + BTABLE: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Buffer table + BTABLE: u13, + padding: u16, + }), + }; + + /// Inter-integrated circuit + pub const I2C1 = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// TX Interrupt enable + TXIE: u1, + /// RX Interrupt enable + RXIE: u1, + /// Address match interrupt enable (slave only) + ADDRIE: u1, + /// Not acknowledge received interrupt enable + NACKIE: u1, + /// STOP detection Interrupt enable + STOPIE: u1, + /// Transfer Complete interrupt enable + TCIE: u1, + /// Error interrupts enable + ERRIE: u1, + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANFOFF: u1, + /// Software reset + SWRST: u1, + /// DMA transmission requests enable + TXDMAEN: u1, + /// DMA reception requests enable + RXDMAEN: u1, + /// Slave byte control + SBC: u1, + /// Clock stretching disable + NOSTRETCH: u1, + /// Wakeup from STOP enable + WUPEN: u1, + /// General call enable + GCEN: u1, + /// SMBus Host address enable + SMBHEN: u1, + /// SMBus Device Default address enable + SMBDEN: u1, + /// SMBUS alert enable + ALERTEN: u1, + /// PEC enable + PECEN: u1, + padding: u8, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Slave address bit 0 (master mode) + SADD0: u1, + /// Slave address bit 7:1 (master mode) + SADD1: u7, + /// Slave address bit 9:8 (master mode) + SADD8: u2, + /// Transfer direction (master mode) + RD_WRN: u1, + /// 10-bit addressing mode (master mode) + ADD10: u1, + /// 10-bit address header only read direction (master receiver mode) + HEAD10R: u1, + /// Start generation + START: u1, + /// Stop generation (master mode) + STOP: u1, + /// NACK generation (slave mode) + NACK: u1, + /// Number of bytes + NBYTES: u8, + /// NBYTES reload mode + RELOAD: u1, + /// Automatic end mode (master mode) + AUTOEND: u1, + /// Packet error checking byte + PECBYTE: u1, + padding: u5, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + OA1_0: u1, + /// Interface address + OA1_1: u7, + /// Interface address + OA1_8: u2, + /// Own Address 1 10-bit mode + OA1MODE: u1, + reserved15: u4, + /// Own Address 1 enable + OA1EN: u1, + padding: u16, + }), + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Interface address + OA2: u7, + /// Own Address 2 masks + OA2MSK: u3, + reserved15: u4, + /// Own Address 2 enable + OA2EN: u1, + padding: u16, + }), + /// Timing register + TIMINGR: mmio.Mmio(packed struct(u32) { + /// SCL low period (master mode) + SCLL: u8, + /// SCL high period (master mode) + SCLH: u8, + /// Data hold time + SDADEL: u4, + /// Data setup time + SCLDEL: u4, + reserved28: u4, + /// Timing prescaler + PRESC: u4, + }), + /// Status register 1 + TIMEOUTR: mmio.Mmio(packed struct(u32) { + /// Bus timeout A + TIMEOUTA: u12, + /// Idle clock timeout detection + TIDLE: u1, + reserved15: u2, + /// Clock timeout enable + TIMOUTEN: u1, + /// Bus timeout B + TIMEOUTB: u12, + reserved31: u3, + /// Extended clock timeout enable + TEXTEN: u1, + }), + /// Interrupt and Status register + ISR: mmio.Mmio(packed struct(u32) { + /// Transmit data register empty (transmitters) + TXE: u1, + /// Transmit interrupt status (transmitters) + TXIS: u1, + /// Receive data register not empty (receivers) + RXNE: u1, + /// Address matched (slave mode) + ADDR: u1, + /// Not acknowledge received flag + NACKF: u1, + /// Stop detection flag + STOPF: u1, + /// Transfer Complete (master mode) + TC: u1, + /// Transfer Complete Reload + TCR: u1, + /// Bus error + BERR: u1, + /// Arbitration lost + ARLO: u1, + /// Overrun/Underrun (slave mode) + OVR: u1, + /// PEC Error in reception + PECERR: u1, + /// Timeout or t_low detection flag + TIMEOUT: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Bus busy + BUSY: u1, + /// Transfer direction (Slave mode) + DIR: u1, + /// Address match code (Slave mode) + ADDCODE: u7, + padding: u8, + }), + /// Interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Address Matched flag clear + ADDRCF: u1, + /// Not Acknowledge flag clear + NACKCF: u1, + /// Stop detection flag clear + STOPCF: u1, + reserved8: u2, + /// Bus error flag clear + BERRCF: u1, + /// Arbitration lost flag clear + ARLOCF: u1, + /// Overrun/Underrun flag clear + OVRCF: u1, + /// PEC Error flag clear + PECCF: u1, + /// Timeout detection flag clear + TIMOUTCF: u1, + /// Alert flag clear + ALERTCF: u1, + padding: u18, + }), + /// PEC register + PECR: mmio.Mmio(packed struct(u32) { + /// Packet error checking register + PEC: u8, + padding: u24, + }), + /// Receive data register + RXDR: mmio.Mmio(packed struct(u32) { + /// 8-bit receive data + RXDATA: u8, + padding: u24, + }), + /// Transmit data register + TXDR: mmio.Mmio(packed struct(u32) { + /// 8-bit transmit data + TXDATA: u8, + padding: u24, + }), + }; + + /// Advanced timer + pub const TIM1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + reserved11: u1, + /// UIF status bit remapping + UIFREMAP: u1, + padding: u20, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + reserved16: u1, + /// Output Idle state 5 + OIS5: u1, + reserved18: u1, + /// Output Idle state 6 + OIS6: u1, + reserved20: u1, + /// Master mode selection 2 + MMS2: u4, + padding: u8, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + /// OCREF clear selection + OCCS: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + /// Slave mode selection bit 3 + SMS3: u1, + padding: u15, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + /// Break 2 interrupt flag + B2IF: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + reserved16: u3, + /// Capture/Compare 5 interrupt flag + C5IF: u1, + /// Capture/Compare 6 interrupt flag + C6IF: u1, + padding: u14, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + /// Break 2 generation + B2G: u1, + padding: u23, + }), + /// capture/compare mode register (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear enable + OC2CE: u1, + /// Output Compare 1 mode bit 3 + OC1M_3: u1, + reserved24: u7, + /// Output Compare 2 mode bit 3 + OC2M_3: u1, + padding: u7, + }), + /// capture/compare mode register (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + OC4CE: u1, + /// Output Compare 3 mode bit 3 + OC3M_3: u1, + reserved24: u7, + /// Output Compare 4 mode bit 3 + OC4M_3: u1, + padding: u7, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output enable + CC2NE: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output enable + CC3NE: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + /// Capture/Compare 5 output enable + CC5E: u1, + /// Capture/Compare 5 output Polarity + CC5P: u1, + reserved20: u2, + /// Capture/Compare 6 output enable + CC6E: u1, + /// Capture/Compare 6 output Polarity + CC6P: u1, + padding: u10, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + reserved31: u15, + /// UIF copy + UIFCPY: u1, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u16, + padding: u16, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 value + CCR4: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + /// Break filter + BKF: u4, + /// Break 2 filter + BK2F: u4, + /// Break 2 enable + BK2E: u1, + /// Break 2 polarity + BK2P: u1, + padding: u6, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + reserved84: [4]u8, + /// capture/compare mode register 3 (output mode) + CCMR3_Output: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Output compare 5 fast enable + OC5FE: u1, + /// Output compare 5 preload enable + OC5PE: u1, + /// Output compare 5 mode + OC5M: u3, + /// Output compare 5 clear enable + OC5CE: u1, + reserved10: u2, + /// Output compare 6 fast enable + OC6FE: u1, + /// Output compare 6 preload enable + OC6PE: u1, + /// Output compare 6 mode + OC6M: u3, + /// Output compare 6 clear enable + OC6CE: u1, + /// Outout Compare 5 mode bit 3 + OC5M_3: u1, + reserved24: u7, + /// Outout Compare 6 mode bit 3 + OC6M_3: u1, + padding: u7, + }), + /// capture/compare register 5 + CCR5: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 5 value + CCR5: u16, + reserved29: u13, + /// Group Channel 5 and Channel 1 + GC5C1: u1, + /// Group Channel 5 and Channel 2 + GC5C2: u1, + /// Group Channel 5 and Channel 3 + GC5C3: u1, + }), + /// capture/compare register 6 + CCR6: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 6 value + CCR6: u16, + padding: u16, + }), + /// option registers + OR: mmio.Mmio(packed struct(u32) { + /// TIM1_ETR_ADC1 remapping capability + TIM1_ETR_ADC1_RMP: u2, + /// TIM1_ETR_ADC4 remapping capability + TIM1_ETR_ADC4_RMP: u2, + padding: u28, + }), + }; + + /// Debug support + pub const DBGMCU = extern struct { + /// MCU Device ID Code Register + IDCODE: mmio.Mmio(packed struct(u32) { + /// Device Identifier + DEV_ID: u12, + reserved16: u4, + /// Revision Identifier + REV_ID: u16, + }), + /// Debug MCU Configuration Register + CR: mmio.Mmio(packed struct(u32) { + /// Debug Sleep mode + DBG_SLEEP: u1, + /// Debug Stop Mode + DBG_STOP: u1, + /// Debug Standby Mode + DBG_STANDBY: u1, + reserved5: u2, + /// Trace pin assignment control + TRACE_IOEN: u1, + /// Trace pin assignment control + TRACE_MODE: u2, + padding: u24, + }), + /// APB Low Freeze Register + APB1FZ: mmio.Mmio(packed struct(u32) { + /// Debug Timer 2 stopped when Core is halted + DBG_TIM2_STOP: u1, + /// Debug Timer 3 stopped when Core is halted + DBG_TIM3_STOP: u1, + /// Debug Timer 4 stopped when Core is halted + DBG_TIM4_STOP: u1, + /// Debug Timer 5 stopped when Core is halted + DBG_TIM5_STOP: u1, + /// Debug Timer 6 stopped when Core is halted + DBG_TIM6_STOP: u1, + /// Debug Timer 7 stopped when Core is halted + DBG_TIM7_STOP: u1, + /// Debug Timer 12 stopped when Core is halted + DBG_TIM12_STOP: u1, + /// Debug Timer 13 stopped when Core is halted + DBG_TIM13_STOP: u1, + /// Debug Timer 14 stopped when Core is halted + DBG_TIMER14_STOP: u1, + /// Debug Timer 18 stopped when Core is halted + DBG_TIM18_STOP: u1, + /// Debug RTC stopped when Core is halted + DBG_RTC_STOP: u1, + /// Debug Window Wachdog stopped when Core is halted + DBG_WWDG_STOP: u1, + /// Debug Independent Wachdog stopped when Core is halted + DBG_IWDG_STOP: u1, + reserved21: u8, + /// SMBUS timeout mode stopped when Core is halted + I2C1_SMBUS_TIMEOUT: u1, + /// SMBUS timeout mode stopped when Core is halted + I2C2_SMBUS_TIMEOUT: u1, + reserved25: u2, + /// Debug CAN stopped when core is halted + DBG_CAN_STOP: u1, + padding: u6, + }), + /// APB High Freeze Register + APB2FZ: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Debug Timer 15 stopped when Core is halted + DBG_TIM15_STOP: u1, + /// Debug Timer 16 stopped when Core is halted + DBG_TIM16_STOP: u1, + /// Debug Timer 17 stopped when Core is halted + DBG_TIM17_STO: u1, + /// Debug Timer 19 stopped when Core is halted + DBG_TIM19_STOP: u1, + padding: u26, + }), + }; +}; diff --git a/src/chips/STM32F407.json b/src/chips/STM32F407.json new file mode 100644 index 0000000..7f592e5 --- /dev/null +++ b/src/chips/STM32F407.json @@ -0,0 +1,50953 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "RNG": { + "description": "Random number generator", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "Interrupt enable", + "offset": 3, + "size": 1 + }, + "RNGEN": { + "description": "Random number generator\n enable", + "offset": 2, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEIS": { + "description": "Seed error interrupt\n status", + "offset": 6, + "size": 1 + }, + "CEIS": { + "description": "Clock error interrupt\n status", + "offset": 5, + "size": 1 + }, + "SECS": { + "description": "Seed error current status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "CECS": { + "description": "Clock error current status", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "DRDY": { + "description": "Data ready", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RNDATA": { + "description": "Random data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "DCMI": { + "description": "Digital camera interface", + "children": { + "registers": { + "CR": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "DCMI enable", + "offset": 14, + "size": 1 + }, + "EDM": { + "description": "Extended data mode", + "offset": 10, + "size": 2 + }, + "FCRC": { + "description": "Frame capture rate control", + "offset": 8, + "size": 2 + }, + "VSPOL": { + "description": "Vertical synchronization\n polarity", + "offset": 7, + "size": 1 + }, + "HSPOL": { + "description": "Horizontal synchronization\n polarity", + "offset": 6, + "size": 1 + }, + "PCKPOL": { + "description": "Pixel clock polarity", + "offset": 5, + "size": 1 + }, + "ESS": { + "description": "Embedded synchronization\n select", + "offset": 4, + "size": 1 + }, + "JPEG": { + "description": "JPEG format", + "offset": 3, + "size": 1 + }, + "CROP": { + "description": "Crop feature", + "offset": 2, + "size": 1 + }, + "CM": { + "description": "Capture mode", + "offset": 1, + "size": 1 + }, + "CAPTURE": { + "description": "Capture enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FNE": { + "description": "FIFO not empty", + "offset": 2, + "size": 1 + }, + "VSYNC": { + "description": "VSYNC", + "offset": 1, + "size": 1 + }, + "HSYNC": { + "description": "HSYNC", + "offset": 0, + "size": 1 + } + } + } + }, + "RIS": { + "description": "raw interrupt status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "LINE_RIS": { + "description": "Line raw interrupt status", + "offset": 4, + "size": 1 + }, + "VSYNC_RIS": { + "description": "VSYNC raw interrupt status", + "offset": 3, + "size": 1 + }, + "ERR_RIS": { + "description": "Synchronization error raw interrupt\n status", + "offset": 2, + "size": 1 + }, + "OVR_RIS": { + "description": "Overrun raw interrupt\n status", + "offset": 1, + "size": 1 + }, + "FRAME_RIS": { + "description": "Capture complete raw interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINE_IE": { + "description": "Line interrupt enable", + "offset": 4, + "size": 1 + }, + "VSYNC_IE": { + "description": "VSYNC interrupt enable", + "offset": 3, + "size": 1 + }, + "ERR_IE": { + "description": "Synchronization error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "OVR_IE": { + "description": "Overrun interrupt enable", + "offset": 1, + "size": 1 + }, + "FRAME_IE": { + "description": "Capture complete interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "MIS": { + "description": "masked interrupt status\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "LINE_MIS": { + "description": "Line masked interrupt\n status", + "offset": 4, + "size": 1 + }, + "VSYNC_MIS": { + "description": "VSYNC masked interrupt\n status", + "offset": 3, + "size": 1 + }, + "ERR_MIS": { + "description": "Synchronization error masked interrupt\n status", + "offset": 2, + "size": 1 + }, + "OVR_MIS": { + "description": "Overrun masked interrupt\n status", + "offset": 1, + "size": 1 + }, + "FRAME_MIS": { + "description": "Capture complete masked interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "interrupt clear register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "LINE_ISC": { + "description": "line interrupt status\n clear", + "offset": 4, + "size": 1 + }, + "VSYNC_ISC": { + "description": "Vertical synch interrupt status\n clear", + "offset": 3, + "size": 1 + }, + "ERR_ISC": { + "description": "Synchronization error interrupt status\n clear", + "offset": 2, + "size": 1 + }, + "OVR_ISC": { + "description": "Overrun interrupt status\n clear", + "offset": 1, + "size": 1 + }, + "FRAME_ISC": { + "description": "Capture complete interrupt status\n clear", + "offset": 0, + "size": 1 + } + } + } + }, + "ESCR": { + "description": "embedded synchronization code\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEC": { + "description": "Frame end delimiter code", + "offset": 24, + "size": 8 + }, + "LEC": { + "description": "Line end delimiter code", + "offset": 16, + "size": 8 + }, + "LSC": { + "description": "Line start delimiter code", + "offset": 8, + "size": 8 + }, + "FSC": { + "description": "Frame start delimiter code", + "offset": 0, + "size": 8 + } + } + } + }, + "ESUR": { + "description": "embedded synchronization unmask\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEU": { + "description": "Frame end delimiter unmask", + "offset": 24, + "size": 8 + }, + "LEU": { + "description": "Line end delimiter unmask", + "offset": 16, + "size": 8 + }, + "LSU": { + "description": "Line start delimiter\n unmask", + "offset": 8, + "size": 8 + }, + "FSU": { + "description": "Frame start delimiter\n unmask", + "offset": 0, + "size": 8 + } + } + } + }, + "CWSTRT": { + "description": "crop window start", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VST": { + "description": "Vertical start line count", + "offset": 16, + "size": 13 + }, + "HOFFCNT": { + "description": "Horizontal offset count", + "offset": 0, + "size": 14 + } + } + } + }, + "CWSIZE": { + "description": "crop window size", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VLINE": { + "description": "Vertical line count", + "offset": 16, + "size": 14 + }, + "CAPCNT": { + "description": "Capture count", + "offset": 0, + "size": 14 + } + } + } + }, + "DR": { + "description": "data register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Byte3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "Byte2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "Byte1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "Byte0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "FSMC": { + "description": "Flexible static memory controller", + "children": { + "registers": { + "BCR1": { + "description": "SRAM/NOR-Flash chip-select control register\n 1", + "offset": 0, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR1": { + "description": "SRAM/NOR-Flash chip-select timing register\n 1", + "offset": 4, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR2": { + "description": "SRAM/NOR-Flash chip-select control register\n 2", + "offset": 8, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR2": { + "description": "SRAM/NOR-Flash chip-select timing register\n 2", + "offset": 12, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR3": { + "description": "SRAM/NOR-Flash chip-select control register\n 3", + "offset": 16, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR3": { + "description": "SRAM/NOR-Flash chip-select timing register\n 3", + "offset": 20, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR4": { + "description": "SRAM/NOR-Flash chip-select control register\n 4", + "offset": 24, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR4": { + "description": "SRAM/NOR-Flash chip-select timing register\n 4", + "offset": 28, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "PCR2": { + "description": "PC Card/NAND Flash control register\n 2", + "offset": 96, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR2": { + "description": "FIFO status and interrupt register\n 2", + "offset": 100, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM2": { + "description": "Common memory space timing register\n 2", + "offset": 104, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT2": { + "description": "Attribute memory space timing register\n 2", + "offset": 108, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR2": { + "description": "ECC result register 2", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECCx", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR3": { + "description": "PC Card/NAND Flash control register\n 3", + "offset": 128, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR3": { + "description": "FIFO status and interrupt register\n 3", + "offset": 132, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM3": { + "description": "Common memory space timing register\n 3", + "offset": 136, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT3": { + "description": "Attribute memory space timing register\n 3", + "offset": 140, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR3": { + "description": "ECC result register 3", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECCx", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR4": { + "description": "PC Card/NAND Flash control register\n 4", + "offset": 160, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR4": { + "description": "FIFO status and interrupt register\n 4", + "offset": 164, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM4": { + "description": "Common memory space timing register\n 4", + "offset": 168, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT4": { + "description": "Attribute memory space timing register\n 4", + "offset": 172, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PIO4": { + "description": "I/O space timing register 4", + "offset": 176, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOHIZx": { + "description": "IOHIZx", + "offset": 24, + "size": 8 + }, + "IOHOLDx": { + "description": "IOHOLDx", + "offset": 16, + "size": 8 + }, + "IOWAITx": { + "description": "IOWAITx", + "offset": 8, + "size": 8 + }, + "IOSETx": { + "description": "IOSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "BWTR1": { + "description": "SRAM/NOR-Flash write timing registers\n 1", + "offset": 260, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR2": { + "description": "SRAM/NOR-Flash write timing registers\n 2", + "offset": 268, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR3": { + "description": "SRAM/NOR-Flash write timing registers\n 3", + "offset": 276, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR4": { + "description": "SRAM/NOR-Flash write timing registers\n 4", + "offset": 284, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "DBG": { + "description": "Debug support", + "children": { + "registers": { + "DBGMCU_IDCODE": { + "description": "IDCODE", + "offset": 0, + "size": 32, + "reset_value": 268461073, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEV_ID": { + "description": "DEV_ID", + "offset": 0, + "size": 12 + }, + "REV_ID": { + "description": "REV_ID", + "offset": 16, + "size": 16 + } + } + } + }, + "DBGMCU_CR": { + "description": "Control Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_SLEEP": { + "description": "DBG_SLEEP", + "offset": 0, + "size": 1 + }, + "DBG_STOP": { + "description": "DBG_STOP", + "offset": 1, + "size": 1 + }, + "DBG_STANDBY": { + "description": "DBG_STANDBY", + "offset": 2, + "size": 1 + }, + "TRACE_IOEN": { + "description": "TRACE_IOEN", + "offset": 5, + "size": 1 + }, + "TRACE_MODE": { + "description": "TRACE_MODE", + "offset": 6, + "size": 2 + }, + "DBG_I2C2_SMBUS_TIMEOUT": { + "description": "DBG_I2C2_SMBUS_TIMEOUT", + "offset": 16, + "size": 1 + }, + "DBG_TIM8_STOP": { + "description": "DBG_TIM8_STOP", + "offset": 17, + "size": 1 + }, + "DBG_TIM5_STOP": { + "description": "DBG_TIM5_STOP", + "offset": 18, + "size": 1 + }, + "DBG_TIM6_STOP": { + "description": "DBG_TIM6_STOP", + "offset": 19, + "size": 1 + }, + "DBG_TIM7_STOP": { + "description": "DBG_TIM7_STOP", + "offset": 20, + "size": 1 + } + } + } + }, + "DBGMCU_APB1_FZ": { + "description": "Debug MCU APB1 Freeze registe", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM2_STOP": { + "description": "DBG_TIM2_STOP", + "offset": 0, + "size": 1 + }, + "DBG_TIM3_STOP": { + "description": "DBG_TIM3 _STOP", + "offset": 1, + "size": 1 + }, + "DBG_TIM4_STOP": { + "description": "DBG_TIM4_STOP", + "offset": 2, + "size": 1 + }, + "DBG_TIM5_STOP": { + "description": "DBG_TIM5_STOP", + "offset": 3, + "size": 1 + }, + "DBG_TIM6_STOP": { + "description": "DBG_TIM6_STOP", + "offset": 4, + "size": 1 + }, + "DBG_TIM7_STOP": { + "description": "DBG_TIM7_STOP", + "offset": 5, + "size": 1 + }, + "DBG_TIM12_STOP": { + "description": "DBG_TIM12_STOP", + "offset": 6, + "size": 1 + }, + "DBG_TIM13_STOP": { + "description": "DBG_TIM13_STOP", + "offset": 7, + "size": 1 + }, + "DBG_TIM14_STOP": { + "description": "DBG_TIM14_STOP", + "offset": 8, + "size": 1 + }, + "DBG_WWDG_STOP": { + "description": "DBG_WWDG_STOP", + "offset": 11, + "size": 1 + }, + "DBG_IWDEG_STOP": { + "description": "DBG_IWDEG_STOP", + "offset": 12, + "size": 1 + }, + "DBG_J2C1_SMBUS_TIMEOUT": { + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "offset": 21, + "size": 1 + }, + "DBG_J2C2_SMBUS_TIMEOUT": { + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "offset": 22, + "size": 1 + }, + "DBG_J2C3SMBUS_TIMEOUT": { + "description": "DBG_J2C3SMBUS_TIMEOUT", + "offset": 23, + "size": 1 + }, + "DBG_CAN1_STOP": { + "description": "DBG_CAN1_STOP", + "offset": 25, + "size": 1 + }, + "DBG_CAN2_STOP": { + "description": "DBG_CAN2_STOP", + "offset": 26, + "size": 1 + } + } + } + }, + "DBGMCU_APB2_FZ": { + "description": "Debug MCU APB2 Freeze registe", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM1_STOP": { + "description": "TIM1 counter stopped when core is\n halted", + "offset": 0, + "size": 1 + }, + "DBG_TIM8_STOP": { + "description": "TIM8 counter stopped when core is\n halted", + "offset": 1, + "size": 1 + }, + "DBG_TIM9_STOP": { + "description": "TIM9 counter stopped when core is\n halted", + "offset": 16, + "size": 1 + }, + "DBG_TIM10_STOP": { + "description": "TIM10 counter stopped when core is\n halted", + "offset": 17, + "size": 1 + }, + "DBG_TIM11_STOP": { + "description": "TIM11 counter stopped when core is\n halted", + "offset": 18, + "size": 1 + } + } + } + } + } + } + }, + "DMA2": { + "description": "DMA controller", + "children": { + "registers": { + "LISR": { + "description": "low interrupt status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TCIF3": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 27, + "size": 1 + }, + "HTIF3": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 26, + "size": 1 + }, + "TEIF3": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 25, + "size": 1 + }, + "DMEIF3": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 24, + "size": 1 + }, + "FEIF3": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 22, + "size": 1 + }, + "TCIF2": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 21, + "size": 1 + }, + "HTIF2": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 20, + "size": 1 + }, + "TEIF2": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 19, + "size": 1 + }, + "DMEIF2": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 18, + "size": 1 + }, + "FEIF2": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 16, + "size": 1 + }, + "TCIF1": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 11, + "size": 1 + }, + "HTIF1": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 10, + "size": 1 + }, + "TEIF1": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 9, + "size": 1 + }, + "DMEIF1": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 8, + "size": 1 + }, + "FEIF1": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 6, + "size": 1 + }, + "TCIF0": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 5, + "size": 1 + }, + "HTIF0": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 4, + "size": 1 + }, + "TEIF0": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 3, + "size": 1 + }, + "DMEIF0": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 2, + "size": 1 + }, + "FEIF0": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 0, + "size": 1 + } + } + } + }, + "HISR": { + "description": "high interrupt status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TCIF7": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 27, + "size": 1 + }, + "HTIF7": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 26, + "size": 1 + }, + "TEIF7": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 25, + "size": 1 + }, + "DMEIF7": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 24, + "size": 1 + }, + "FEIF7": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 22, + "size": 1 + }, + "TCIF6": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 21, + "size": 1 + }, + "HTIF6": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 20, + "size": 1 + }, + "TEIF6": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 19, + "size": 1 + }, + "DMEIF6": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 18, + "size": 1 + }, + "FEIF6": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 16, + "size": 1 + }, + "TCIF5": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 11, + "size": 1 + }, + "HTIF5": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 10, + "size": 1 + }, + "TEIF5": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 9, + "size": 1 + }, + "DMEIF5": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 8, + "size": 1 + }, + "FEIF5": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 6, + "size": 1 + }, + "TCIF4": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 5, + "size": 1 + }, + "HTIF4": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 4, + "size": 1 + }, + "TEIF4": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 3, + "size": 1 + }, + "DMEIF4": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 2, + "size": 1 + }, + "FEIF4": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 0, + "size": 1 + } + } + } + }, + "LIFCR": { + "description": "low interrupt flag clear\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTCIF3": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 27, + "size": 1 + }, + "CHTIF3": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 26, + "size": 1 + }, + "CTEIF3": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 25, + "size": 1 + }, + "CDMEIF3": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 24, + "size": 1 + }, + "CFEIF3": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 22, + "size": 1 + }, + "CTCIF2": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 21, + "size": 1 + }, + "CHTIF2": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 20, + "size": 1 + }, + "CTEIF2": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 19, + "size": 1 + }, + "CDMEIF2": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 18, + "size": 1 + }, + "CFEIF2": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 16, + "size": 1 + }, + "CTCIF1": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 11, + "size": 1 + }, + "CHTIF1": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 10, + "size": 1 + }, + "CTEIF1": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 9, + "size": 1 + }, + "CDMEIF1": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 8, + "size": 1 + }, + "CFEIF1": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 6, + "size": 1 + }, + "CTCIF0": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 5, + "size": 1 + }, + "CHTIF0": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 4, + "size": 1 + }, + "CTEIF0": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 3, + "size": 1 + }, + "CDMEIF0": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 2, + "size": 1 + }, + "CFEIF0": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 0, + "size": 1 + } + } + } + }, + "HIFCR": { + "description": "high interrupt flag clear\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTCIF7": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 27, + "size": 1 + }, + "CHTIF7": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 26, + "size": 1 + }, + "CTEIF7": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 25, + "size": 1 + }, + "CDMEIF7": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 24, + "size": 1 + }, + "CFEIF7": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 22, + "size": 1 + }, + "CTCIF6": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 21, + "size": 1 + }, + "CHTIF6": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 20, + "size": 1 + }, + "CTEIF6": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 19, + "size": 1 + }, + "CDMEIF6": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 18, + "size": 1 + }, + "CFEIF6": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 16, + "size": 1 + }, + "CTCIF5": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 11, + "size": 1 + }, + "CHTIF5": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 10, + "size": 1 + }, + "CTEIF5": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 9, + "size": 1 + }, + "CDMEIF5": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 8, + "size": 1 + }, + "CFEIF5": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 6, + "size": 1 + }, + "CTCIF4": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 5, + "size": 1 + }, + "CHTIF4": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 4, + "size": 1 + }, + "CTEIF4": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 3, + "size": 1 + }, + "CDMEIF4": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 2, + "size": 1 + }, + "CFEIF4": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 0, + "size": 1 + } + } + } + }, + "S0CR": { + "description": "stream x configuration\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S0NDTR": { + "description": "stream x number of data\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S0PAR": { + "description": "stream x peripheral address\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S0M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S0M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S0FCR": { + "description": "stream x FIFO control register", + "offset": 36, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S1CR": { + "description": "stream x configuration\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S1NDTR": { + "description": "stream x number of data\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S1PAR": { + "description": "stream x peripheral address\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S1M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S1M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S1FCR": { + "description": "stream x FIFO control register", + "offset": 60, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S2CR": { + "description": "stream x configuration\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S2NDTR": { + "description": "stream x number of data\n register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S2PAR": { + "description": "stream x peripheral address\n register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S2M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S2M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S2FCR": { + "description": "stream x FIFO control register", + "offset": 84, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S3CR": { + "description": "stream x configuration\n register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S3NDTR": { + "description": "stream x number of data\n register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S3PAR": { + "description": "stream x peripheral address\n register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S3M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S3M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S3FCR": { + "description": "stream x FIFO control register", + "offset": 108, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S4CR": { + "description": "stream x configuration\n register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S4NDTR": { + "description": "stream x number of data\n register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S4PAR": { + "description": "stream x peripheral address\n register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S4M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S4M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S4FCR": { + "description": "stream x FIFO control register", + "offset": 132, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S5CR": { + "description": "stream x configuration\n register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S5NDTR": { + "description": "stream x number of data\n register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S5PAR": { + "description": "stream x peripheral address\n register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S5M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S5M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S5FCR": { + "description": "stream x FIFO control register", + "offset": 156, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S6CR": { + "description": "stream x configuration\n register", + "offset": 160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S6NDTR": { + "description": "stream x number of data\n register", + "offset": 164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S6PAR": { + "description": "stream x peripheral address\n register", + "offset": 168, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S6M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S6M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S6FCR": { + "description": "stream x FIFO control register", + "offset": 180, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S7CR": { + "description": "stream x configuration\n register", + "offset": 184, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S7NDTR": { + "description": "stream x number of data\n register", + "offset": 188, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S7PAR": { + "description": "stream x peripheral address\n register", + "offset": 192, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S7M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S7M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 200, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S7FCR": { + "description": "stream x FIFO control register", + "offset": 204, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + } + } + } + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "children": { + "registers": { + "ACTRL": { + "description": "Auxiliary control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DISMCYCINT": { + "description": "DISMCYCINT", + "offset": 0, + "size": 1 + }, + "DISDEFWBUF": { + "description": "DISDEFWBUF", + "offset": 1, + "size": 1 + }, + "DISFOLD": { + "description": "DISFOLD", + "offset": 2, + "size": 1 + }, + "DISFPCA": { + "description": "DISFPCA", + "offset": 8, + "size": 1 + }, + "DISOOFP": { + "description": "DISOOFP", + "offset": 9, + "size": 1 + } + } + } + } + } + } + }, + "RCC": { + "description": "Reset and clock control", + "children": { + "registers": { + "CR": { + "description": "clock control register", + "offset": 0, + "size": 32, + "reset_value": 131, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLI2SRDY": { + "description": "PLLI2S clock ready flag", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PLLI2SON": { + "description": "PLLI2S enable", + "offset": 26, + "size": 1 + }, + "PLLRDY": { + "description": "Main PLL (PLL) clock ready\n flag", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PLLON": { + "description": "Main PLL (PLL) enable", + "offset": 24, + "size": 1 + }, + "CSSON": { + "description": "Clock security system\n enable", + "offset": 19, + "size": 1 + }, + "HSEBYP": { + "description": "HSE clock bypass", + "offset": 18, + "size": 1 + }, + "HSERDY": { + "description": "HSE clock ready flag", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "HSEON": { + "description": "HSE clock enable", + "offset": 16, + "size": 1 + }, + "HSICAL": { + "description": "Internal high-speed clock\n calibration", + "offset": 8, + "size": 8, + "access": "read-only" + }, + "HSITRIM": { + "description": "Internal high-speed clock\n trimming", + "offset": 3, + "size": 5 + }, + "HSIRDY": { + "description": "Internal high-speed clock ready\n flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSION": { + "description": "Internal high-speed clock\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "PLLCFGR": { + "description": "PLL configuration register", + "offset": 4, + "size": 32, + "reset_value": 603992080, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLQ3": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 27, + "size": 1 + }, + "PLLQ2": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 26, + "size": 1 + }, + "PLLQ1": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 25, + "size": 1 + }, + "PLLQ0": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 24, + "size": 1 + }, + "PLLSRC": { + "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n entry clock source", + "offset": 22, + "size": 1 + }, + "PLLP1": { + "description": "Main PLL (PLL) division factor for main\n system clock", + "offset": 17, + "size": 1 + }, + "PLLP0": { + "description": "Main PLL (PLL) division factor for main\n system clock", + "offset": 16, + "size": 1 + }, + "PLLN8": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 14, + "size": 1 + }, + "PLLN7": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 13, + "size": 1 + }, + "PLLN6": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 12, + "size": 1 + }, + "PLLN5": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 11, + "size": 1 + }, + "PLLN4": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 10, + "size": 1 + }, + "PLLN3": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 9, + "size": 1 + }, + "PLLN2": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 8, + "size": 1 + }, + "PLLN1": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 7, + "size": 1 + }, + "PLLN0": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 6, + "size": 1 + }, + "PLLM5": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 5, + "size": 1 + }, + "PLLM4": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 4, + "size": 1 + }, + "PLLM3": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 3, + "size": 1 + }, + "PLLM2": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 2, + "size": 1 + }, + "PLLM1": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 1, + "size": 1 + }, + "PLLM0": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 0, + "size": 1 + } + } + } + }, + "CFGR": { + "description": "clock configuration register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCO2": { + "description": "Microcontroller clock output\n 2", + "offset": 30, + "size": 2 + }, + "MCO2PRE": { + "description": "MCO2 prescaler", + "offset": 27, + "size": 3 + }, + "MCO1PRE": { + "description": "MCO1 prescaler", + "offset": 24, + "size": 3 + }, + "I2SSRC": { + "description": "I2S clock selection", + "offset": 23, + "size": 1 + }, + "MCO1": { + "description": "Microcontroller clock output\n 1", + "offset": 21, + "size": 2 + }, + "RTCPRE": { + "description": "HSE division factor for RTC\n clock", + "offset": 16, + "size": 5 + }, + "PPRE2": { + "description": "APB high-speed prescaler\n (APB2)", + "offset": 13, + "size": 3 + }, + "PPRE1": { + "description": "APB Low speed prescaler\n (APB1)", + "offset": 10, + "size": 3 + }, + "HPRE": { + "description": "AHB prescaler", + "offset": 4, + "size": 4 + }, + "SWS1": { + "description": "System clock switch status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "SWS0": { + "description": "System clock switch status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SW1": { + "description": "System clock switch", + "offset": 1, + "size": 1 + }, + "SW0": { + "description": "System clock switch", + "offset": 0, + "size": 1 + } + } + } + }, + "CIR": { + "description": "clock interrupt register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSSC": { + "description": "Clock security system interrupt\n clear", + "offset": 23, + "size": 1, + "access": "write-only" + }, + "PLLI2SRDYC": { + "description": "PLLI2S ready interrupt\n clear", + "offset": 21, + "size": 1, + "access": "write-only" + }, + "PLLRDYC": { + "description": "Main PLL(PLL) ready interrupt\n clear", + "offset": 20, + "size": 1, + "access": "write-only" + }, + "HSERDYC": { + "description": "HSE ready interrupt clear", + "offset": 19, + "size": 1, + "access": "write-only" + }, + "HSIRDYC": { + "description": "HSI ready interrupt clear", + "offset": 18, + "size": 1, + "access": "write-only" + }, + "LSERDYC": { + "description": "LSE ready interrupt clear", + "offset": 17, + "size": 1, + "access": "write-only" + }, + "LSIRDYC": { + "description": "LSI ready interrupt clear", + "offset": 16, + "size": 1, + "access": "write-only" + }, + "PLLI2SRDYIE": { + "description": "PLLI2S ready interrupt\n enable", + "offset": 13, + "size": 1 + }, + "PLLRDYIE": { + "description": "Main PLL (PLL) ready interrupt\n enable", + "offset": 12, + "size": 1 + }, + "HSERDYIE": { + "description": "HSE ready interrupt enable", + "offset": 11, + "size": 1 + }, + "HSIRDYIE": { + "description": "HSI ready interrupt enable", + "offset": 10, + "size": 1 + }, + "LSERDYIE": { + "description": "LSE ready interrupt enable", + "offset": 9, + "size": 1 + }, + "LSIRDYIE": { + "description": "LSI ready interrupt enable", + "offset": 8, + "size": 1 + }, + "CSSF": { + "description": "Clock security system interrupt\n flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "PLLI2SRDYF": { + "description": "PLLI2S ready interrupt\n flag", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "PLLRDYF": { + "description": "Main PLL (PLL) ready interrupt\n flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "HSERDYF": { + "description": "HSE ready interrupt flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "HSIRDYF": { + "description": "HSI ready interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "LSERDYF": { + "description": "LSE ready interrupt flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSIRDYF": { + "description": "LSI ready interrupt flag", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "AHB1RSTR": { + "description": "AHB1 peripheral reset register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGHSRST": { + "description": "USB OTG HS module reset", + "offset": 29, + "size": 1 + }, + "ETHMACRST": { + "description": "Ethernet MAC reset", + "offset": 25, + "size": 1 + }, + "DMA2RST": { + "description": "DMA2 reset", + "offset": 22, + "size": 1 + }, + "DMA1RST": { + "description": "DMA2 reset", + "offset": 21, + "size": 1 + }, + "CRCRST": { + "description": "CRC reset", + "offset": 12, + "size": 1 + }, + "GPIOIRST": { + "description": "IO port I reset", + "offset": 8, + "size": 1 + }, + "GPIOHRST": { + "description": "IO port H reset", + "offset": 7, + "size": 1 + }, + "GPIOGRST": { + "description": "IO port G reset", + "offset": 6, + "size": 1 + }, + "GPIOFRST": { + "description": "IO port F reset", + "offset": 5, + "size": 1 + }, + "GPIOERST": { + "description": "IO port E reset", + "offset": 4, + "size": 1 + }, + "GPIODRST": { + "description": "IO port D reset", + "offset": 3, + "size": 1 + }, + "GPIOCRST": { + "description": "IO port C reset", + "offset": 2, + "size": 1 + }, + "GPIOBRST": { + "description": "IO port B reset", + "offset": 1, + "size": 1 + }, + "GPIOARST": { + "description": "IO port A reset", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB2RSTR": { + "description": "AHB2 peripheral reset register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSRST": { + "description": "USB OTG FS module reset", + "offset": 7, + "size": 1 + }, + "RNGRST": { + "description": "Random number generator module\n reset", + "offset": 6, + "size": 1 + }, + "DCMIRST": { + "description": "Camera interface reset", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3RSTR": { + "description": "AHB3 peripheral reset register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSMCRST": { + "description": "Flexible static memory controller module\n reset", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1RSTR": { + "description": "APB1 peripheral reset register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACRST": { + "description": "DAC reset", + "offset": 29, + "size": 1 + }, + "PWRRST": { + "description": "Power interface reset", + "offset": 28, + "size": 1 + }, + "CAN2RST": { + "description": "CAN2 reset", + "offset": 26, + "size": 1 + }, + "CAN1RST": { + "description": "CAN1 reset", + "offset": 25, + "size": 1 + }, + "I2C3RST": { + "description": "I2C3 reset", + "offset": 23, + "size": 1 + }, + "I2C2RST": { + "description": "I2C 2 reset", + "offset": 22, + "size": 1 + }, + "I2C1RST": { + "description": "I2C 1 reset", + "offset": 21, + "size": 1 + }, + "UART5RST": { + "description": "USART 5 reset", + "offset": 20, + "size": 1 + }, + "UART4RST": { + "description": "USART 4 reset", + "offset": 19, + "size": 1 + }, + "UART3RST": { + "description": "USART 3 reset", + "offset": 18, + "size": 1 + }, + "UART2RST": { + "description": "USART 2 reset", + "offset": 17, + "size": 1 + }, + "SPI3RST": { + "description": "SPI 3 reset", + "offset": 15, + "size": 1 + }, + "SPI2RST": { + "description": "SPI 2 reset", + "offset": 14, + "size": 1 + }, + "WWDGRST": { + "description": "Window watchdog reset", + "offset": 11, + "size": 1 + }, + "TIM14RST": { + "description": "TIM14 reset", + "offset": 8, + "size": 1 + }, + "TIM13RST": { + "description": "TIM13 reset", + "offset": 7, + "size": 1 + }, + "TIM12RST": { + "description": "TIM12 reset", + "offset": 6, + "size": 1 + }, + "TIM7RST": { + "description": "TIM7 reset", + "offset": 5, + "size": 1 + }, + "TIM6RST": { + "description": "TIM6 reset", + "offset": 4, + "size": 1 + }, + "TIM5RST": { + "description": "TIM5 reset", + "offset": 3, + "size": 1 + }, + "TIM4RST": { + "description": "TIM4 reset", + "offset": 2, + "size": 1 + }, + "TIM3RST": { + "description": "TIM3 reset", + "offset": 1, + "size": 1 + }, + "TIM2RST": { + "description": "TIM2 reset", + "offset": 0, + "size": 1 + } + } + } + }, + "APB2RSTR": { + "description": "APB2 peripheral reset register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM11RST": { + "description": "TIM11 reset", + "offset": 18, + "size": 1 + }, + "TIM10RST": { + "description": "TIM10 reset", + "offset": 17, + "size": 1 + }, + "TIM9RST": { + "description": "TIM9 reset", + "offset": 16, + "size": 1 + }, + "SYSCFGRST": { + "description": "System configuration controller\n reset", + "offset": 14, + "size": 1 + }, + "SPI1RST": { + "description": "SPI 1 reset", + "offset": 12, + "size": 1 + }, + "SDIORST": { + "description": "SDIO reset", + "offset": 11, + "size": 1 + }, + "ADCRST": { + "description": "ADC interface reset (common to all\n ADCs)", + "offset": 8, + "size": 1 + }, + "USART6RST": { + "description": "USART6 reset", + "offset": 5, + "size": 1 + }, + "USART1RST": { + "description": "USART1 reset", + "offset": 4, + "size": 1 + }, + "TIM8RST": { + "description": "TIM8 reset", + "offset": 1, + "size": 1 + }, + "TIM1RST": { + "description": "TIM1 reset", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB1ENR": { + "description": "AHB1 peripheral clock register", + "offset": 48, + "size": 32, + "reset_value": 1048576, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGHSULPIEN": { + "description": "USB OTG HSULPI clock\n enable", + "offset": 30, + "size": 1 + }, + "OTGHSEN": { + "description": "USB OTG HS clock enable", + "offset": 29, + "size": 1 + }, + "ETHMACPTPEN": { + "description": "Ethernet PTP clock enable", + "offset": 28, + "size": 1 + }, + "ETHMACRXEN": { + "description": "Ethernet Reception clock\n enable", + "offset": 27, + "size": 1 + }, + "ETHMACTXEN": { + "description": "Ethernet Transmission clock\n enable", + "offset": 26, + "size": 1 + }, + "ETHMACEN": { + "description": "Ethernet MAC clock enable", + "offset": 25, + "size": 1 + }, + "DMA2EN": { + "description": "DMA2 clock enable", + "offset": 22, + "size": 1 + }, + "DMA1EN": { + "description": "DMA1 clock enable", + "offset": 21, + "size": 1 + }, + "BKPSRAMEN": { + "description": "Backup SRAM interface clock\n enable", + "offset": 18, + "size": 1 + }, + "CRCEN": { + "description": "CRC clock enable", + "offset": 12, + "size": 1 + }, + "GPIOIEN": { + "description": "IO port I clock enable", + "offset": 8, + "size": 1 + }, + "GPIOHEN": { + "description": "IO port H clock enable", + "offset": 7, + "size": 1 + }, + "GPIOGEN": { + "description": "IO port G clock enable", + "offset": 6, + "size": 1 + }, + "GPIOFEN": { + "description": "IO port F clock enable", + "offset": 5, + "size": 1 + }, + "GPIOEEN": { + "description": "IO port E clock enable", + "offset": 4, + "size": 1 + }, + "GPIODEN": { + "description": "IO port D clock enable", + "offset": 3, + "size": 1 + }, + "GPIOCEN": { + "description": "IO port C clock enable", + "offset": 2, + "size": 1 + }, + "GPIOBEN": { + "description": "IO port B clock enable", + "offset": 1, + "size": 1 + }, + "GPIOAEN": { + "description": "IO port A clock enable", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB2ENR": { + "description": "AHB2 peripheral clock enable\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSEN": { + "description": "USB OTG FS clock enable", + "offset": 7, + "size": 1 + }, + "RNGEN": { + "description": "Random number generator clock\n enable", + "offset": 6, + "size": 1 + }, + "DCMIEN": { + "description": "Camera interface enable", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3ENR": { + "description": "AHB3 peripheral clock enable\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSMCEN": { + "description": "Flexible static memory controller module\n clock enable", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1ENR": { + "description": "APB1 peripheral clock enable\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACEN": { + "description": "DAC interface clock enable", + "offset": 29, + "size": 1 + }, + "PWREN": { + "description": "Power interface clock\n enable", + "offset": 28, + "size": 1 + }, + "CAN2EN": { + "description": "CAN 2 clock enable", + "offset": 26, + "size": 1 + }, + "CAN1EN": { + "description": "CAN 1 clock enable", + "offset": 25, + "size": 1 + }, + "I2C3EN": { + "description": "I2C3 clock enable", + "offset": 23, + "size": 1 + }, + "I2C2EN": { + "description": "I2C2 clock enable", + "offset": 22, + "size": 1 + }, + "I2C1EN": { + "description": "I2C1 clock enable", + "offset": 21, + "size": 1 + }, + "UART5EN": { + "description": "UART5 clock enable", + "offset": 20, + "size": 1 + }, + "UART4EN": { + "description": "UART4 clock enable", + "offset": 19, + "size": 1 + }, + "USART3EN": { + "description": "USART3 clock enable", + "offset": 18, + "size": 1 + }, + "USART2EN": { + "description": "USART 2 clock enable", + "offset": 17, + "size": 1 + }, + "SPI3EN": { + "description": "SPI3 clock enable", + "offset": 15, + "size": 1 + }, + "SPI2EN": { + "description": "SPI2 clock enable", + "offset": 14, + "size": 1 + }, + "WWDGEN": { + "description": "Window watchdog clock\n enable", + "offset": 11, + "size": 1 + }, + "TIM14EN": { + "description": "TIM14 clock enable", + "offset": 8, + "size": 1 + }, + "TIM13EN": { + "description": "TIM13 clock enable", + "offset": 7, + "size": 1 + }, + "TIM12EN": { + "description": "TIM12 clock enable", + "offset": 6, + "size": 1 + }, + "TIM7EN": { + "description": "TIM7 clock enable", + "offset": 5, + "size": 1 + }, + "TIM6EN": { + "description": "TIM6 clock enable", + "offset": 4, + "size": 1 + }, + "TIM5EN": { + "description": "TIM5 clock enable", + "offset": 3, + "size": 1 + }, + "TIM4EN": { + "description": "TIM4 clock enable", + "offset": 2, + "size": 1 + }, + "TIM3EN": { + "description": "TIM3 clock enable", + "offset": 1, + "size": 1 + }, + "TIM2EN": { + "description": "TIM2 clock enable", + "offset": 0, + "size": 1 + } + } + } + }, + "APB2ENR": { + "description": "APB2 peripheral clock enable\n register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM11EN": { + "description": "TIM11 clock enable", + "offset": 18, + "size": 1 + }, + "TIM10EN": { + "description": "TIM10 clock enable", + "offset": 17, + "size": 1 + }, + "TIM9EN": { + "description": "TIM9 clock enable", + "offset": 16, + "size": 1 + }, + "SYSCFGEN": { + "description": "System configuration controller clock\n enable", + "offset": 14, + "size": 1 + }, + "SPI1EN": { + "description": "SPI1 clock enable", + "offset": 12, + "size": 1 + }, + "SDIOEN": { + "description": "SDIO clock enable", + "offset": 11, + "size": 1 + }, + "ADC3EN": { + "description": "ADC3 clock enable", + "offset": 10, + "size": 1 + }, + "ADC2EN": { + "description": "ADC2 clock enable", + "offset": 9, + "size": 1 + }, + "ADC1EN": { + "description": "ADC1 clock enable", + "offset": 8, + "size": 1 + }, + "USART6EN": { + "description": "USART6 clock enable", + "offset": 5, + "size": 1 + }, + "USART1EN": { + "description": "USART1 clock enable", + "offset": 4, + "size": 1 + }, + "TIM8EN": { + "description": "TIM8 clock enable", + "offset": 1, + "size": 1 + }, + "TIM1EN": { + "description": "TIM1 clock enable", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB1LPENR": { + "description": "AHB1 peripheral clock enable in low power\n mode register", + "offset": 80, + "size": 32, + "reset_value": 2120716799, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGHSULPILPEN": { + "description": "USB OTG HS ULPI clock enable during\n Sleep mode", + "offset": 30, + "size": 1 + }, + "OTGHSLPEN": { + "description": "USB OTG HS clock enable during Sleep\n mode", + "offset": 29, + "size": 1 + }, + "ETHMACPTPLPEN": { + "description": "Ethernet PTP clock enable during Sleep\n mode", + "offset": 28, + "size": 1 + }, + "ETHMACRXLPEN": { + "description": "Ethernet reception clock enable during\n Sleep mode", + "offset": 27, + "size": 1 + }, + "ETHMACTXLPEN": { + "description": "Ethernet transmission clock enable\n during Sleep mode", + "offset": 26, + "size": 1 + }, + "ETHMACLPEN": { + "description": "Ethernet MAC clock enable during Sleep\n mode", + "offset": 25, + "size": 1 + }, + "DMA2LPEN": { + "description": "DMA2 clock enable during Sleep\n mode", + "offset": 22, + "size": 1 + }, + "DMA1LPEN": { + "description": "DMA1 clock enable during Sleep\n mode", + "offset": 21, + "size": 1 + }, + "BKPSRAMLPEN": { + "description": "Backup SRAM interface clock enable\n during Sleep mode", + "offset": 18, + "size": 1 + }, + "SRAM2LPEN": { + "description": "SRAM 2 interface clock enable during\n Sleep mode", + "offset": 17, + "size": 1 + }, + "SRAM1LPEN": { + "description": "SRAM 1interface clock enable during\n Sleep mode", + "offset": 16, + "size": 1 + }, + "FLITFLPEN": { + "description": "Flash interface clock enable during\n Sleep mode", + "offset": 15, + "size": 1 + }, + "CRCLPEN": { + "description": "CRC clock enable during Sleep\n mode", + "offset": 12, + "size": 1 + }, + "GPIOILPEN": { + "description": "IO port I clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "GPIOHLPEN": { + "description": "IO port H clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "GPIOGLPEN": { + "description": "IO port G clock enable during Sleep\n mode", + "offset": 6, + "size": 1 + }, + "GPIOFLPEN": { + "description": "IO port F clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "GPIOELPEN": { + "description": "IO port E clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "GPIODLPEN": { + "description": "IO port D clock enable during Sleep\n mode", + "offset": 3, + "size": 1 + }, + "GPIOCLPEN": { + "description": "IO port C clock enable during Sleep\n mode", + "offset": 2, + "size": 1 + }, + "GPIOBLPEN": { + "description": "IO port B clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "GPIOALPEN": { + "description": "IO port A clock enable during sleep\n mode", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB2LPENR": { + "description": "AHB2 peripheral clock enable in low power\n mode register", + "offset": 84, + "size": 32, + "reset_value": 241, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSLPEN": { + "description": "USB OTG FS clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "RNGLPEN": { + "description": "Random number generator clock enable\n during Sleep mode", + "offset": 6, + "size": 1 + }, + "DCMILPEN": { + "description": "Camera interface enable during Sleep\n mode", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3LPENR": { + "description": "AHB3 peripheral clock enable in low power\n mode register", + "offset": 88, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSMCLPEN": { + "description": "Flexible static memory controller module\n clock enable during Sleep mode", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1LPENR": { + "description": "APB1 peripheral clock enable in low power\n mode register", + "offset": 96, + "size": 32, + "reset_value": 922667519, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACLPEN": { + "description": "DAC interface clock enable during Sleep\n mode", + "offset": 29, + "size": 1 + }, + "PWRLPEN": { + "description": "Power interface clock enable during\n Sleep mode", + "offset": 28, + "size": 1 + }, + "CAN2LPEN": { + "description": "CAN 2 clock enable during Sleep\n mode", + "offset": 26, + "size": 1 + }, + "CAN1LPEN": { + "description": "CAN 1 clock enable during Sleep\n mode", + "offset": 25, + "size": 1 + }, + "I2C3LPEN": { + "description": "I2C3 clock enable during Sleep\n mode", + "offset": 23, + "size": 1 + }, + "I2C2LPEN": { + "description": "I2C2 clock enable during Sleep\n mode", + "offset": 22, + "size": 1 + }, + "I2C1LPEN": { + "description": "I2C1 clock enable during Sleep\n mode", + "offset": 21, + "size": 1 + }, + "UART5LPEN": { + "description": "UART5 clock enable during Sleep\n mode", + "offset": 20, + "size": 1 + }, + "UART4LPEN": { + "description": "UART4 clock enable during Sleep\n mode", + "offset": 19, + "size": 1 + }, + "USART3LPEN": { + "description": "USART3 clock enable during Sleep\n mode", + "offset": 18, + "size": 1 + }, + "USART2LPEN": { + "description": "USART2 clock enable during Sleep\n mode", + "offset": 17, + "size": 1 + }, + "SPI3LPEN": { + "description": "SPI3 clock enable during Sleep\n mode", + "offset": 15, + "size": 1 + }, + "SPI2LPEN": { + "description": "SPI2 clock enable during Sleep\n mode", + "offset": 14, + "size": 1 + }, + "WWDGLPEN": { + "description": "Window watchdog clock enable during\n Sleep mode", + "offset": 11, + "size": 1 + }, + "TIM14LPEN": { + "description": "TIM14 clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "TIM13LPEN": { + "description": "TIM13 clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "TIM12LPEN": { + "description": "TIM12 clock enable during Sleep\n mode", + "offset": 6, + "size": 1 + }, + "TIM7LPEN": { + "description": "TIM7 clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "TIM6LPEN": { + "description": "TIM6 clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "TIM5LPEN": { + "description": "TIM5 clock enable during Sleep\n mode", + "offset": 3, + "size": 1 + }, + "TIM4LPEN": { + "description": "TIM4 clock enable during Sleep\n mode", + "offset": 2, + "size": 1 + }, + "TIM3LPEN": { + "description": "TIM3 clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "TIM2LPEN": { + "description": "TIM2 clock enable during Sleep\n mode", + "offset": 0, + "size": 1 + } + } + } + }, + "APB2LPENR": { + "description": "APB2 peripheral clock enabled in low power\n mode register", + "offset": 100, + "size": 32, + "reset_value": 483123, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM11LPEN": { + "description": "TIM11 clock enable during Sleep\n mode", + "offset": 18, + "size": 1 + }, + "TIM10LPEN": { + "description": "TIM10 clock enable during Sleep\n mode", + "offset": 17, + "size": 1 + }, + "TIM9LPEN": { + "description": "TIM9 clock enable during sleep\n mode", + "offset": 16, + "size": 1 + }, + "SYSCFGLPEN": { + "description": "System configuration controller clock\n enable during Sleep mode", + "offset": 14, + "size": 1 + }, + "SPI1LPEN": { + "description": "SPI 1 clock enable during Sleep\n mode", + "offset": 12, + "size": 1 + }, + "SDIOLPEN": { + "description": "SDIO clock enable during Sleep\n mode", + "offset": 11, + "size": 1 + }, + "ADC3LPEN": { + "description": "ADC 3 clock enable during Sleep\n mode", + "offset": 10, + "size": 1 + }, + "ADC2LPEN": { + "description": "ADC2 clock enable during Sleep\n mode", + "offset": 9, + "size": 1 + }, + "ADC1LPEN": { + "description": "ADC1 clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "USART6LPEN": { + "description": "USART6 clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "USART1LPEN": { + "description": "USART1 clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "TIM8LPEN": { + "description": "TIM8 clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "TIM1LPEN": { + "description": "TIM1 clock enable during Sleep\n mode", + "offset": 0, + "size": 1 + } + } + } + }, + "BDCR": { + "description": "Backup domain control register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BDRST": { + "description": "Backup domain software\n reset", + "offset": 16, + "size": 1 + }, + "RTCEN": { + "description": "RTC clock enable", + "offset": 15, + "size": 1 + }, + "RTCSEL1": { + "description": "RTC clock source selection", + "offset": 9, + "size": 1 + }, + "RTCSEL0": { + "description": "RTC clock source selection", + "offset": 8, + "size": 1 + }, + "LSEBYP": { + "description": "External low-speed oscillator\n bypass", + "offset": 2, + "size": 1 + }, + "LSERDY": { + "description": "External low-speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSEON": { + "description": "External low-speed oscillator\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CSR": { + "description": "clock control & status\n register", + "offset": 116, + "size": 32, + "reset_value": 234881024, + "reset_mask": 4294967295, + "children": { + "fields": { + "LPWRRSTF": { + "description": "Low-power reset flag", + "offset": 31, + "size": 1 + }, + "WWDGRSTF": { + "description": "Window watchdog reset flag", + "offset": 30, + "size": 1 + }, + "WDGRSTF": { + "description": "Independent watchdog reset\n flag", + "offset": 29, + "size": 1 + }, + "SFTRSTF": { + "description": "Software reset flag", + "offset": 28, + "size": 1 + }, + "PORRSTF": { + "description": "POR/PDR reset flag", + "offset": 27, + "size": 1 + }, + "PADRSTF": { + "description": "PIN reset flag", + "offset": 26, + "size": 1 + }, + "BORRSTF": { + "description": "BOR reset flag", + "offset": 25, + "size": 1 + }, + "RMVF": { + "description": "Remove reset flag", + "offset": 24, + "size": 1 + }, + "LSIRDY": { + "description": "Internal low-speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSION": { + "description": "Internal low-speed oscillator\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SSCGR": { + "description": "spread spectrum clock generation\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SSCGEN": { + "description": "Spread spectrum modulation\n enable", + "offset": 31, + "size": 1 + }, + "SPREADSEL": { + "description": "Spread Select", + "offset": 30, + "size": 1 + }, + "INCSTEP": { + "description": "Incrementation step", + "offset": 13, + "size": 15 + }, + "MODPER": { + "description": "Modulation period", + "offset": 0, + "size": 13 + } + } + } + }, + "PLLI2SCFGR": { + "description": "PLLI2S configuration register", + "offset": 132, + "size": 32, + "reset_value": 536883200, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLI2SRx": { + "description": "PLLI2S division factor for I2S\n clocks", + "offset": 28, + "size": 3 + }, + "PLLI2SNx": { + "description": "PLLI2S multiplication factor for\n VCO", + "offset": 6, + "size": 9 + } + } + } + } + } + } + }, + "GPIOI": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "children": { + "registers": { + "CPACR": { + "description": "Coprocessor access control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CP": { + "description": "CP", + "offset": 20, + "size": 4 + } + } + } + } + } + } + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "children": { + "registers": { + "STIR": { + "description": "Software trigger interrupt\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTID": { + "description": "Software generated interrupt\n ID", + "offset": 0, + "size": 9 + } + } + } + } + } + } + }, + "SCB": { + "description": "System control block", + "children": { + "registers": { + "CPUID": { + "description": "CPUID base register", + "offset": 0, + "size": 32, + "reset_value": 1091551809, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Revision": { + "description": "Revision number", + "offset": 0, + "size": 4 + }, + "PartNo": { + "description": "Part number of the\n processor", + "offset": 4, + "size": 12 + }, + "Constant": { + "description": "Reads as 0xF", + "offset": 16, + "size": 4 + }, + "Variant": { + "description": "Variant number", + "offset": 20, + "size": 4 + }, + "Implementer": { + "description": "Implementer code", + "offset": 24, + "size": 8 + } + } + } + }, + "ICSR": { + "description": "Interrupt control and state\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTACTIVE": { + "description": "Active vector", + "offset": 0, + "size": 9 + }, + "RETTOBASE": { + "description": "Return to base level", + "offset": 11, + "size": 1 + }, + "VECTPENDING": { + "description": "Pending vector", + "offset": 12, + "size": 7 + }, + "ISRPENDING": { + "description": "Interrupt pending flag", + "offset": 22, + "size": 1 + }, + "PENDSTCLR": { + "description": "SysTick exception clear-pending\n bit", + "offset": 25, + "size": 1 + }, + "PENDSTSET": { + "description": "SysTick exception set-pending\n bit", + "offset": 26, + "size": 1 + }, + "PENDSVCLR": { + "description": "PendSV clear-pending bit", + "offset": 27, + "size": 1 + }, + "PENDSVSET": { + "description": "PendSV set-pending bit", + "offset": 28, + "size": 1 + }, + "NMIPENDSET": { + "description": "NMI set-pending bit.", + "offset": 31, + "size": 1 + } + } + } + }, + "VTOR": { + "description": "Vector table offset register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TBLOFF": { + "description": "Vector table base offset\n field", + "offset": 9, + "size": 21 + } + } + } + }, + "AIRCR": { + "description": "Application interrupt and reset control\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTRESET": { + "description": "VECTRESET", + "offset": 0, + "size": 1 + }, + "VECTCLRACTIVE": { + "description": "VECTCLRACTIVE", + "offset": 1, + "size": 1 + }, + "SYSRESETREQ": { + "description": "SYSRESETREQ", + "offset": 2, + "size": 1 + }, + "PRIGROUP": { + "description": "PRIGROUP", + "offset": 8, + "size": 3 + }, + "ENDIANESS": { + "description": "ENDIANESS", + "offset": 15, + "size": 1 + }, + "VECTKEYSTAT": { + "description": "Register key", + "offset": 16, + "size": 16 + } + } + } + }, + "SCR": { + "description": "System control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEPONEXIT": { + "description": "SLEEPONEXIT", + "offset": 1, + "size": 1 + }, + "SLEEPDEEP": { + "description": "SLEEPDEEP", + "offset": 2, + "size": 1 + }, + "SEVEONPEND": { + "description": "Send Event on Pending bit", + "offset": 4, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Configuration and control\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONBASETHRDENA": { + "description": "Configures how the processor enters\n Thread mode", + "offset": 0, + "size": 1 + }, + "USERSETMPEND": { + "description": "USERSETMPEND", + "offset": 1, + "size": 1 + }, + "UNALIGN__TRP": { + "description": "UNALIGN_ TRP", + "offset": 3, + "size": 1 + }, + "DIV_0_TRP": { + "description": "DIV_0_TRP", + "offset": 4, + "size": 1 + }, + "BFHFNMIGN": { + "description": "BFHFNMIGN", + "offset": 8, + "size": 1 + }, + "STKALIGN": { + "description": "STKALIGN", + "offset": 9, + "size": 1 + } + } + } + }, + "SHPR1": { + "description": "System handler priority\n registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_4": { + "description": "Priority of system handler\n 4", + "offset": 0, + "size": 8 + }, + "PRI_5": { + "description": "Priority of system handler\n 5", + "offset": 8, + "size": 8 + }, + "PRI_6": { + "description": "Priority of system handler\n 6", + "offset": 16, + "size": 8 + } + } + } + }, + "SHPR2": { + "description": "System handler priority\n registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_11": { + "description": "Priority of system handler\n 11", + "offset": 24, + "size": 8 + } + } + } + }, + "SHPR3": { + "description": "System handler priority\n registers", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_14": { + "description": "Priority of system handler\n 14", + "offset": 16, + "size": 8 + }, + "PRI_15": { + "description": "Priority of system handler\n 15", + "offset": 24, + "size": 8 + } + } + } + }, + "SHCRS": { + "description": "System handler control and state\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMFAULTACT": { + "description": "Memory management fault exception active\n bit", + "offset": 0, + "size": 1 + }, + "BUSFAULTACT": { + "description": "Bus fault exception active\n bit", + "offset": 1, + "size": 1 + }, + "USGFAULTACT": { + "description": "Usage fault exception active\n bit", + "offset": 3, + "size": 1 + }, + "SVCALLACT": { + "description": "SVC call active bit", + "offset": 7, + "size": 1 + }, + "MONITORACT": { + "description": "Debug monitor active bit", + "offset": 8, + "size": 1 + }, + "PENDSVACT": { + "description": "PendSV exception active\n bit", + "offset": 10, + "size": 1 + }, + "SYSTICKACT": { + "description": "SysTick exception active\n bit", + "offset": 11, + "size": 1 + }, + "USGFAULTPENDED": { + "description": "Usage fault exception pending\n bit", + "offset": 12, + "size": 1 + }, + "MEMFAULTPENDED": { + "description": "Memory management fault exception\n pending bit", + "offset": 13, + "size": 1 + }, + "BUSFAULTPENDED": { + "description": "Bus fault exception pending\n bit", + "offset": 14, + "size": 1 + }, + "SVCALLPENDED": { + "description": "SVC call pending bit", + "offset": 15, + "size": 1 + }, + "MEMFAULTENA": { + "description": "Memory management fault enable\n bit", + "offset": 16, + "size": 1 + }, + "BUSFAULTENA": { + "description": "Bus fault enable bit", + "offset": 17, + "size": 1 + }, + "USGFAULTENA": { + "description": "Usage fault enable bit", + "offset": 18, + "size": 1 + } + } + } + }, + "CFSR_UFSR_BFSR_MMFSR": { + "description": "Configurable fault status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IACCVIOL": { + "description": "Instruction access violation\n flag", + "offset": 1, + "size": 1 + }, + "MUNSTKERR": { + "description": "Memory manager fault on unstacking for a\n return from exception", + "offset": 3, + "size": 1 + }, + "MSTKERR": { + "description": "Memory manager fault on stacking for\n exception entry.", + "offset": 4, + "size": 1 + }, + "MLSPERR": { + "description": "MLSPERR", + "offset": 5, + "size": 1 + }, + "MMARVALID": { + "description": "Memory Management Fault Address Register\n (MMAR) valid flag", + "offset": 7, + "size": 1 + }, + "IBUSERR": { + "description": "Instruction bus error", + "offset": 8, + "size": 1 + }, + "PRECISERR": { + "description": "Precise data bus error", + "offset": 9, + "size": 1 + }, + "IMPRECISERR": { + "description": "Imprecise data bus error", + "offset": 10, + "size": 1 + }, + "UNSTKERR": { + "description": "Bus fault on unstacking for a return\n from exception", + "offset": 11, + "size": 1 + }, + "STKERR": { + "description": "Bus fault on stacking for exception\n entry", + "offset": 12, + "size": 1 + }, + "LSPERR": { + "description": "Bus fault on floating-point lazy state\n preservation", + "offset": 13, + "size": 1 + }, + "BFARVALID": { + "description": "Bus Fault Address Register (BFAR) valid\n flag", + "offset": 15, + "size": 1 + }, + "UNDEFINSTR": { + "description": "Undefined instruction usage\n fault", + "offset": 16, + "size": 1 + }, + "INVSTATE": { + "description": "Invalid state usage fault", + "offset": 17, + "size": 1 + }, + "INVPC": { + "description": "Invalid PC load usage\n fault", + "offset": 18, + "size": 1 + }, + "NOCP": { + "description": "No coprocessor usage\n fault.", + "offset": 19, + "size": 1 + }, + "UNALIGNED": { + "description": "Unaligned access usage\n fault", + "offset": 24, + "size": 1 + }, + "DIVBYZERO": { + "description": "Divide by zero usage fault", + "offset": 25, + "size": 1 + } + } + } + }, + "HFSR": { + "description": "Hard fault status register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTTBL": { + "description": "Vector table hard fault", + "offset": 1, + "size": 1 + }, + "FORCED": { + "description": "Forced hard fault", + "offset": 30, + "size": 1 + }, + "DEBUG_VT": { + "description": "Reserved for Debug use", + "offset": 31, + "size": 1 + } + } + } + }, + "MMFAR": { + "description": "Memory management fault address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMFAR": { + "description": "Memory management fault\n address", + "offset": 0, + "size": 32 + } + } + } + }, + "BFAR": { + "description": "Bus fault address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BFAR": { + "description": "Bus fault address", + "offset": 0, + "size": 32 + } + } + } + }, + "AFSR": { + "description": "Auxiliary fault status\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IMPDEF": { + "description": "Implementation defined", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "STK": { + "description": "SysTick timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "TICKINT": { + "description": "SysTick exception request\n enable", + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "description": "Clock source selection", + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "description": "COUNTFLAG", + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick reload value register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RELOAD": { + "description": "RELOAD value", + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick current value register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CURRENT": { + "description": "Current counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick calibration value\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TENMS": { + "description": "Calibration value", + "offset": 0, + "size": 24 + }, + "SKEW": { + "description": "SKEW flag: Indicates whether the TENMS\n value is exact", + "offset": 30, + "size": 1 + }, + "NOREF": { + "description": "NOREF flag. Reads as zero", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "MPU": { + "description": "Memory protection unit", + "children": { + "registers": { + "MPU_TYPER": { + "description": "MPU type register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEPARATE": { + "description": "Separate flag", + "offset": 0, + "size": 1 + }, + "DREGION": { + "description": "Number of MPU data regions", + "offset": 8, + "size": 8 + }, + "IREGION": { + "description": "Number of MPU instruction\n regions", + "offset": 16, + "size": 8 + } + } + } + }, + "MPU_CTRL": { + "description": "MPU control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ENABLE": { + "description": "Enables the MPU", + "offset": 0, + "size": 1 + }, + "HFNMIENA": { + "description": "Enables the operation of MPU during hard\n fault", + "offset": 1, + "size": 1 + }, + "PRIVDEFENA": { + "description": "Enable priviliged software access to\n default memory map", + "offset": 2, + "size": 1 + } + } + } + }, + "MPU_RNR": { + "description": "MPU region number register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region", + "offset": 0, + "size": 8 + } + } + } + }, + "MPU_RBAR": { + "description": "MPU region base address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region field", + "offset": 0, + "size": 4 + }, + "VALID": { + "description": "MPU region number valid", + "offset": 4, + "size": 1 + }, + "ADDR": { + "description": "Region base address field", + "offset": 5, + "size": 27 + } + } + } + }, + "MPU_RASR": { + "description": "MPU region attribute and size\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Region enable bit.", + "offset": 0, + "size": 1 + }, + "SIZE": { + "description": "Size of the MPU protection\n region", + "offset": 1, + "size": 5 + }, + "SRD": { + "description": "Subregion disable bits", + "offset": 8, + "size": 8 + }, + "B": { + "description": "memory attribute", + "offset": 16, + "size": 1 + }, + "C": { + "description": "memory attribute", + "offset": 17, + "size": 1 + }, + "S": { + "description": "Shareable memory attribute", + "offset": 18, + "size": 1 + }, + "TEX": { + "description": "memory attribute", + "offset": 19, + "size": 3 + }, + "AP": { + "description": "Access permission", + "offset": 24, + "size": 3 + }, + "XN": { + "description": "Instruction access disable\n bit", + "offset": 28, + "size": 1 + } + } + } + } + } + } + }, + "FPU": { + "description": "Floting point unit", + "children": { + "registers": { + "FPCCR": { + "description": "Floating-point context control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSPACT": { + "description": "LSPACT", + "offset": 0, + "size": 1 + }, + "USER": { + "description": "USER", + "offset": 1, + "size": 1 + }, + "THREAD": { + "description": "THREAD", + "offset": 3, + "size": 1 + }, + "HFRDY": { + "description": "HFRDY", + "offset": 4, + "size": 1 + }, + "MMRDY": { + "description": "MMRDY", + "offset": 5, + "size": 1 + }, + "BFRDY": { + "description": "BFRDY", + "offset": 6, + "size": 1 + }, + "MONRDY": { + "description": "MONRDY", + "offset": 8, + "size": 1 + }, + "LSPEN": { + "description": "LSPEN", + "offset": 30, + "size": 1 + }, + "ASPEN": { + "description": "ASPEN", + "offset": 31, + "size": 1 + } + } + } + }, + "FPCAR": { + "description": "Floating-point context address\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Location of unpopulated\n floating-point", + "offset": 3, + "size": 29 + } + } + } + }, + "FPSCR": { + "description": "Floating-point status control\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOC": { + "description": "Invalid operation cumulative exception\n bit", + "offset": 0, + "size": 1 + }, + "DZC": { + "description": "Division by zero cumulative exception\n bit.", + "offset": 1, + "size": 1 + }, + "OFC": { + "description": "Overflow cumulative exception\n bit", + "offset": 2, + "size": 1 + }, + "UFC": { + "description": "Underflow cumulative exception\n bit", + "offset": 3, + "size": 1 + }, + "IXC": { + "description": "Inexact cumulative exception\n bit", + "offset": 4, + "size": 1 + }, + "IDC": { + "description": "Input denormal cumulative exception\n bit.", + "offset": 7, + "size": 1 + }, + "RMode": { + "description": "Rounding Mode control\n field", + "offset": 22, + "size": 2 + }, + "FZ": { + "description": "Flush-to-zero mode control\n bit:", + "offset": 24, + "size": 1 + }, + "DN": { + "description": "Default NaN mode control\n bit", + "offset": 25, + "size": 1 + }, + "AHP": { + "description": "Alternative half-precision control\n bit", + "offset": 26, + "size": 1 + }, + "V": { + "description": "Overflow condition code\n flag", + "offset": 28, + "size": 1 + }, + "C": { + "description": "Carry condition code flag", + "offset": 29, + "size": 1 + }, + "Z": { + "description": "Zero condition code flag", + "offset": 30, + "size": 1 + }, + "N": { + "description": "Negative condition code\n flag", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "CRYP": { + "description": "Cryptographic processor", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALGODIR": { + "description": "Algorithm direction", + "offset": 2, + "size": 1 + }, + "ALGOMODE0": { + "description": "Algorithm mode", + "offset": 3, + "size": 3 + }, + "DATATYPE": { + "description": "Data type selection", + "offset": 6, + "size": 2 + }, + "KEYSIZE": { + "description": "Key size selection (AES mode\n only)", + "offset": 8, + "size": 2 + }, + "FFLUSH": { + "description": "FIFO flush", + "offset": 14, + "size": 1, + "access": "write-only" + }, + "CRYPEN": { + "description": "Cryptographic processor\n enable", + "offset": 15, + "size": 1 + }, + "GCM_CCMPH": { + "description": "GCM_CCMPH", + "offset": 16, + "size": 2 + }, + "ALGOMODE3": { + "description": "ALGOMODE", + "offset": 19, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "BUSY": { + "description": "Busy bit", + "offset": 4, + "size": 1 + }, + "OFFU": { + "description": "Output FIFO full", + "offset": 3, + "size": 1 + }, + "OFNE": { + "description": "Output FIFO not empty", + "offset": 2, + "size": 1 + }, + "IFNF": { + "description": "Input FIFO not full", + "offset": 1, + "size": 1 + }, + "IFEM": { + "description": "Input FIFO empty", + "offset": 0, + "size": 1 + } + } + } + }, + "DIN": { + "description": "data input register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAIN": { + "description": "Data input", + "offset": 0, + "size": 32 + } + } + } + }, + "DOUT": { + "description": "data output register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATAOUT": { + "description": "Data output", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACR": { + "description": "DMA control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DOEN": { + "description": "DMA output enable", + "offset": 1, + "size": 1 + }, + "DIEN": { + "description": "DMA input enable", + "offset": 0, + "size": 1 + } + } + } + }, + "IMSCR": { + "description": "interrupt mask set/clear\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OUTIM": { + "description": "Output FIFO service interrupt\n mask", + "offset": 1, + "size": 1 + }, + "INIM": { + "description": "Input FIFO service interrupt\n mask", + "offset": 0, + "size": 1 + } + } + } + }, + "RISR": { + "description": "raw interrupt status register", + "offset": 24, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OUTRIS": { + "description": "Output FIFO service raw interrupt\n status", + "offset": 1, + "size": 1 + }, + "INRIS": { + "description": "Input FIFO service raw interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "MISR": { + "description": "masked interrupt status\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OUTMIS": { + "description": "Output FIFO service masked interrupt\n status", + "offset": 1, + "size": 1 + }, + "INMIS": { + "description": "Input FIFO service masked interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "K0LR": { + "description": "key registers", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "b224": { + "description": "b224", + "offset": 0, + "size": 1 + }, + "b225": { + "description": "b225", + "offset": 1, + "size": 1 + }, + "b226": { + "description": "b226", + "offset": 2, + "size": 1 + }, + "b227": { + "description": "b227", + "offset": 3, + "size": 1 + }, + "b228": { + "description": "b228", + "offset": 4, + "size": 1 + }, + "b229": { + "description": "b229", + "offset": 5, + "size": 1 + }, + "b230": { + "description": "b230", + "offset": 6, + "size": 1 + }, + "b231": { + "description": "b231", + "offset": 7, + "size": 1 + }, + "b232": { + "description": "b232", + "offset": 8, + "size": 1 + }, + "b233": { + "description": "b233", + "offset": 9, + "size": 1 + }, + "b234": { + "description": "b234", + "offset": 10, + "size": 1 + }, + "b235": { + "description": "b235", + "offset": 11, + "size": 1 + }, + "b236": { + "description": "b236", + "offset": 12, + "size": 1 + }, + "b237": { + "description": "b237", + "offset": 13, + "size": 1 + }, + "b238": { + "description": "b238", + "offset": 14, + "size": 1 + }, + "b239": { + "description": "b239", + "offset": 15, + "size": 1 + }, + "b240": { + "description": "b240", + "offset": 16, + "size": 1 + }, + "b241": { + "description": "b241", + "offset": 17, + "size": 1 + }, + "b242": { + "description": "b242", + "offset": 18, + "size": 1 + }, + "b243": { + "description": "b243", + "offset": 19, + "size": 1 + }, + "b244": { + "description": "b244", + "offset": 20, + "size": 1 + }, + "b245": { + "description": "b245", + "offset": 21, + "size": 1 + }, + "b246": { + "description": "b246", + "offset": 22, + "size": 1 + }, + "b247": { + "description": "b247", + "offset": 23, + "size": 1 + }, + "b248": { + "description": "b248", + "offset": 24, + "size": 1 + }, + "b249": { + "description": "b249", + "offset": 25, + "size": 1 + }, + "b250": { + "description": "b250", + "offset": 26, + "size": 1 + }, + "b251": { + "description": "b251", + "offset": 27, + "size": 1 + }, + "b252": { + "description": "b252", + "offset": 28, + "size": 1 + }, + "b253": { + "description": "b253", + "offset": 29, + "size": 1 + }, + "b254": { + "description": "b254", + "offset": 30, + "size": 1 + }, + "b255": { + "description": "b255", + "offset": 31, + "size": 1 + } + } + } + }, + "K0RR": { + "description": "key registers", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "b192": { + "description": "b192", + "offset": 0, + "size": 1 + }, + "b193": { + "description": "b193", + "offset": 1, + "size": 1 + }, + "b194": { + "description": "b194", + "offset": 2, + "size": 1 + }, + "b195": { + "description": "b195", + "offset": 3, + "size": 1 + }, + "b196": { + "description": "b196", + "offset": 4, + "size": 1 + }, + "b197": { + "description": "b197", + "offset": 5, + "size": 1 + }, + "b198": { + "description": "b198", + "offset": 6, + "size": 1 + }, + "b199": { + "description": "b199", + "offset": 7, + "size": 1 + }, + "b200": { + "description": "b200", + "offset": 8, + "size": 1 + }, + "b201": { + "description": "b201", + "offset": 9, + "size": 1 + }, + "b202": { + "description": "b202", + "offset": 10, + "size": 1 + }, + "b203": { + "description": "b203", + "offset": 11, + "size": 1 + }, + "b204": { + "description": "b204", + "offset": 12, + "size": 1 + }, + "b205": { + "description": "b205", + "offset": 13, + "size": 1 + }, + "b206": { + "description": "b206", + "offset": 14, + "size": 1 + }, + "b207": { + "description": "b207", + "offset": 15, + "size": 1 + }, + "b208": { + "description": "b208", + "offset": 16, + "size": 1 + }, + "b209": { + "description": "b209", + "offset": 17, + "size": 1 + }, + "b210": { + "description": "b210", + "offset": 18, + "size": 1 + }, + "b211": { + "description": "b211", + "offset": 19, + "size": 1 + }, + "b212": { + "description": "b212", + "offset": 20, + "size": 1 + }, + "b213": { + "description": "b213", + "offset": 21, + "size": 1 + }, + "b214": { + "description": "b214", + "offset": 22, + "size": 1 + }, + "b215": { + "description": "b215", + "offset": 23, + "size": 1 + }, + "b216": { + "description": "b216", + "offset": 24, + "size": 1 + }, + "b217": { + "description": "b217", + "offset": 25, + "size": 1 + }, + "b218": { + "description": "b218", + "offset": 26, + "size": 1 + }, + "b219": { + "description": "b219", + "offset": 27, + "size": 1 + }, + "b220": { + "description": "b220", + "offset": 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1 + }, + "IV89": { + "description": "IV89", + "offset": 6, + "size": 1 + }, + "IV88": { + "description": "IV88", + "offset": 7, + "size": 1 + }, + "IV87": { + "description": "IV87", + "offset": 8, + "size": 1 + }, + "IV86": { + "description": "IV86", + "offset": 9, + "size": 1 + }, + "IV85": { + "description": "IV85", + "offset": 10, + "size": 1 + }, + "IV84": { + "description": "IV84", + "offset": 11, + "size": 1 + }, + "IV83": { + "description": "IV83", + "offset": 12, + "size": 1 + }, + "IV82": { + "description": "IV82", + "offset": 13, + "size": 1 + }, + "IV81": { + "description": "IV81", + "offset": 14, + "size": 1 + }, + "IV80": { + "description": "IV80", + "offset": 15, + "size": 1 + }, + "IV79": { + "description": "IV79", + "offset": 16, + "size": 1 + }, + "IV78": { + "description": "IV78", + "offset": 17, + "size": 1 + }, + "IV77": { + "description": "IV77", + "offset": 18, + "size": 1 + }, + "IV76": { + "description": "IV76", + "offset": 19, + "size": 1 + }, + "IV75": { + "description": "IV75", + "offset": 20, + "size": 1 + }, + "IV74": { + "description": "IV74", + "offset": 21, + "size": 1 + }, + "IV73": { + "description": "IV73", + "offset": 22, + "size": 1 + }, + "IV72": { + "description": "IV72", + "offset": 23, + "size": 1 + }, + "IV71": { + "description": "IV71", + "offset": 24, + "size": 1 + }, + "IV70": { + "description": "IV70", + "offset": 25, + "size": 1 + }, + "IV69": { + "description": "IV69", + "offset": 26, + "size": 1 + }, + "IV68": { + "description": "IV68", + "offset": 27, + "size": 1 + }, + "IV67": { + "description": "IV67", + "offset": 28, + "size": 1 + }, + "IV66": { + "description": "IV66", + "offset": 29, + "size": 1 + }, + "IV65": { + "description": "IV65", + "offset": 30, + "size": 1 + }, + "IV64": { + "description": "IV64", + "offset": 31, + "size": 1 + } + } + } + }, + "IV1RR": { + "description": "initialization vector\n registers", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IV127": { + "description": "IV127", + "offset": 0, + "size": 1 + }, + "IV126": { + "description": "IV126", + "offset": 1, + "size": 1 + }, + "IV125": { + "description": "IV125", + "offset": 2, + "size": 1 + }, + "IV124": { + "description": "IV124", + "offset": 3, + "size": 1 + }, + "IV123": { + "description": "IV123", + "offset": 4, + "size": 1 + }, + "IV122": { + "description": "IV122", + "offset": 5, + "size": 1 + }, + "IV121": { + "description": "IV121", + "offset": 6, + "size": 1 + }, + "IV120": { + "description": "IV120", + "offset": 7, + "size": 1 + }, + "IV119": { + "description": "IV119", + "offset": 8, + "size": 1 + }, + "IV118": { + "description": "IV118", + "offset": 9, + "size": 1 + }, + "IV117": { + "description": "IV117", + "offset": 10, + "size": 1 + }, + "IV116": { + "description": "IV116", + "offset": 11, + "size": 1 + }, + "IV115": { + "description": "IV115", + "offset": 12, + "size": 1 + }, + "IV114": { + "description": "IV114", + "offset": 13, + "size": 1 + }, + "IV113": { + "description": "IV113", + "offset": 14, + "size": 1 + }, + "IV112": { + "description": "IV112", + "offset": 15, + "size": 1 + }, + "IV111": { + "description": "IV111", + "offset": 16, + "size": 1 + }, + "IV110": { + "description": "IV110", + "offset": 17, + "size": 1 + }, + "IV109": { + "description": "IV109", + "offset": 18, + "size": 1 + }, + "IV108": { + "description": "IV108", + "offset": 19, + "size": 1 + }, + "IV107": { + "description": "IV107", + "offset": 20, + "size": 1 + }, + "IV106": { + "description": "IV106", + "offset": 21, + "size": 1 + }, + "IV105": { + "description": "IV105", + "offset": 22, + "size": 1 + }, + "IV104": { + "description": "IV104", + "offset": 23, + "size": 1 + }, + "IV103": { + "description": "IV103", + "offset": 24, + "size": 1 + }, + "IV102": { + "description": "IV102", + "offset": 25, + "size": 1 + }, + "IV101": { + "description": "IV101", + "offset": 26, + "size": 1 + }, + "IV100": { + "description": "IV100", + "offset": 27, + "size": 1 + }, + "IV99": { + "description": "IV99", + "offset": 28, + "size": 1 + }, + "IV98": { + "description": "IV98", + "offset": 29, + "size": 1 + }, + "IV97": { + "description": "IV97", + "offset": 30, + "size": 1 + }, + "IV96": { + "description": "IV96", + "offset": 31, + "size": 1 + } + } + } + }, + "CSGCMCCM0R": { + "description": "context swap register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM0R": { + "description": "CSGCMCCM0R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM1R": { + "description": "context swap register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM1R": { + "description": "CSGCMCCM1R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM2R": { + "description": "context swap register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM2R": { + "description": "CSGCMCCM2R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM3R": { + "description": "context swap register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM3R": { + "description": "CSGCMCCM3R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM4R": { + "description": "context swap register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM4R": { + "description": "CSGCMCCM4R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM5R": { + "description": "context swap register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM5R": { + "description": "CSGCMCCM5R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM6R": { + "description": "context swap register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM6R": { + "description": "CSGCMCCM6R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM7R": { + "description": "context swap register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM7R": { + "description": "CSGCMCCM7R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM0R": { + "description": "context swap register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM0R": { + "description": "CSGCM0R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM1R": { + "description": "context swap register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM1R": { + "description": "CSGCM1R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM2R": { + "description": "context swap register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM2R": { + "description": "CSGCM2R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM3R": { + "description": "context swap register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM3R": { + "description": "CSGCM3R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM4R": { + "description": "context swap register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM4R": { + "description": "CSGCM4R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM5R": { + "description": "context swap register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM5R": { + "description": "CSGCM5R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM6R": { + "description": "context swap register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM6R": { + "description": "CSGCM6R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM7R": { + "description": "context swap register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM7R": { + "description": "CSGCM7R", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "HASH": { + "description": "Hash processor", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INIT": { + "description": "Initialize message digest\n calculation", + "offset": 2, + "size": 1, + "access": "write-only" + }, + "DMAE": { + "description": "DMA enable", + "offset": 3, + "size": 1 + }, + "DATATYPE": { + "description": "Data type selection", + "offset": 4, + "size": 2 + }, + "MODE": { + "description": "Mode selection", + "offset": 6, + "size": 1 + }, + "ALGO0": { + "description": "Algorithm selection", + "offset": 7, + "size": 1 + }, + "NBW": { + "description": "Number of words already\n pushed", + "offset": 8, + "size": 4, + "access": "read-only" + }, + "DINNE": { + "description": "DIN not empty", + "offset": 12, + "size": 1, + "access": "read-only" + }, + "MDMAT": { + "description": "Multiple DMA Transfers", + "offset": 13, + "size": 1 + }, + "LKEY": { + "description": "Long key selection", + "offset": 16, + "size": 1 + }, + "ALGO1": { + "description": "ALGO", + "offset": 18, + "size": 1 + } + } + } + }, + "DIN": { + "description": "data input register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAIN": { + "description": "Data input", + "offset": 0, + "size": 32 + } + } + } + }, + "STR": { + "description": "start register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCAL": { + "description": "Digest calculation", + "offset": 8, + "size": 1, + "access": "write-only" + }, + "NBLW": { + "description": "Number of valid bits in the last word of\n the message", + "offset": 0, + "size": 5 + } + } + } + }, + "HR0": { + "description": "digest registers", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H0": { + "description": "H0", + "offset": 0, + "size": 32 + } + } + } + }, + "HR1": { + "description": "digest registers", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H1": { + "description": "H1", + "offset": 0, + "size": 32 + } + } + } + }, + "HR2": { + "description": "digest registers", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H2": { + "description": "H2", + "offset": 0, + "size": 32 + } + } + } + }, + "HR3": { + "description": "digest registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H3": { + "description": "H3", + "offset": 0, + "size": 32 + } + } + } + }, + "HR4": { + "description": "digest registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H4": { + "description": "H4", + "offset": 0, + "size": 32 + } + } + } + }, + "IMR": { + "description": "interrupt enable register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCIE": { + "description": "Digest calculation completion interrupt\n enable", + "offset": 1, + "size": 1 + }, + "DINIE": { + "description": "Data input interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 36, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "BUSY": { + "description": "Busy bit", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "DMAS": { + "description": "DMA Status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "DCIS": { + "description": "Digest calculation completion interrupt\n status", + "offset": 1, + "size": 1 + }, + "DINIS": { + "description": "Data input interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "CSR0": { + "description": "context swap registers", + "offset": 248, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR0": { + "description": "CSR0", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR1": { + "description": "context swap registers", + "offset": 252, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR1": { + "description": "CSR1", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR2": { + "description": "context swap registers", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR2": { + "description": "CSR2", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR3": { + "description": "context swap registers", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR3": { + "description": "CSR3", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR4": { + "description": "context swap registers", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR4": { + "description": "CSR4", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR5": { + "description": "context swap registers", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR5": { + "description": "CSR5", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR6": { + "description": "context swap registers", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR6": { + "description": "CSR6", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR7": { + "description": "context swap registers", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR7": { + "description": "CSR7", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR8": { + "description": "context swap registers", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR8": { + "description": "CSR8", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR9": { + "description": "context swap registers", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR9": { + "description": "CSR9", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR10": { + "description": "context swap registers", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR10": { + "description": "CSR10", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR11": { + "description": "context swap registers", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR11": { + "description": "CSR11", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR12": { + "description": "context swap registers", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR12": { + "description": "CSR12", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR13": { + "description": "context swap registers", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR13": { + "description": "CSR13", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR14": { + "description": "context swap registers", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR14": { + "description": "CSR14", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR15": { + "description": "context swap registers", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR15": { + "description": "CSR15", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR16": { + "description": "context swap registers", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR16": { + "description": "CSR16", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR17": { + "description": "context swap registers", + "offset": 316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR17": { + "description": "CSR17", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR18": { + "description": "context swap registers", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR18": { + "description": "CSR18", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR19": { + "description": "context swap registers", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR19": { + "description": "CSR19", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR20": { + "description": "context swap registers", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR20": { + "description": "CSR20", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR21": { + "description": "context swap registers", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR21": { + "description": "CSR21", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR22": { + "description": "context swap registers", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR22": { + "description": "CSR22", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR23": { + "description": "context swap registers", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR23": { + "description": "CSR23", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR24": { + "description": "context swap registers", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR24": { + "description": "CSR24", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR25": { + "description": "context swap registers", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR25": { + "description": "CSR25", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR26": { + "description": "context swap registers", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR26": { + "description": "CSR26", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR27": { + "description": "context swap registers", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR27": { + "description": "CSR27", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR28": { + "description": "context swap registers", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR28": { + "description": "CSR28", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR29": { + "description": "context swap registers", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR29": { + "description": "CSR29", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR30": { + "description": "context swap registers", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR30": { + "description": "CSR30", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR31": { + "description": "context swap registers", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR31": { + "description": "CSR31", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR32": { + "description": "context swap registers", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR32": { + "description": "CSR32", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR33": { + "description": "context swap registers", + "offset": 380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR33": { + "description": "CSR33", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR34": { + "description": "context swap registers", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR34": { + "description": "CSR34", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR35": { + "description": "context swap registers", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR35": { + "description": "CSR35", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR36": { + "description": "context swap registers", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR36": { + "description": "CSR36", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR37": { + "description": "context swap registers", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR37": { + "description": "CSR37", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR38": { + "description": "context swap registers", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR38": { + "description": "CSR38", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR39": { + "description": "context swap registers", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR39": { + "description": "CSR39", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR40": { + "description": "context swap registers", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR40": { + "description": "CSR40", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR41": { + "description": "context swap registers", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR41": { + "description": "CSR41", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR42": { + "description": "context swap registers", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR42": { + "description": "CSR42", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR43": { + "description": "context swap registers", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR43": { + "description": "CSR43", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR44": { + "description": "context swap registers", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR44": { + "description": "CSR44", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR45": { + "description": "context swap registers", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR45": { + "description": "CSR45", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR46": { + "description": "context swap registers", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR46": { + "description": "CSR46", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR47": { + "description": "context swap registers", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR47": { + "description": "CSR47", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR48": { + "description": "context swap registers", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR48": { + "description": "CSR48", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR49": { + "description": "context swap registers", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR49": { + "description": "CSR49", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR50": { + "description": "context swap registers", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR50": { + "description": "CSR50", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR51": { + "description": "context swap registers", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR51": { + "description": "CSR51", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR52": { + "description": "context swap registers", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR52": { + "description": "CSR52", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR53": { + "description": "context swap registers", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR53": { + "description": "CSR53", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR0": { + "description": "HASH digest register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H0": { + "description": "H0", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR1": { + "description": "read-only", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H1": { + "description": "H1", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR2": { + "description": "read-only", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H2": { + "description": "H2", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR3": { + "description": "read-only", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H3": { + "description": "H3", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR4": { + "description": "read-only", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H4": { + "description": "H4", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR5": { + "description": "read-only", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H5": { + "description": "H5", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR6": { + "description": "read-only", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H6": { + "description": "H6", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR7": { + "description": "read-only", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H7": { + "description": "H7", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "GPIOB": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 640, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 256, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "GPIOA": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 2818572288, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 1677721600, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "SYSCFG": { + "description": "System configuration controller", + "children": { + "registers": { + "MEMRM": { + "description": "memory remap register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEM_MODE": { + "description": "MEM_MODE", + "offset": 0, + "size": 2 + } + } + } + }, + "PMC": { + "description": "peripheral mode configuration\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MII_RMII_SEL": { + "description": "Ethernet PHY interface\n selection", + "offset": 23, + "size": 1 + } + } + } + }, + "EXTICR1": { + "description": "external interrupt configuration register\n 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI3": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 12, + "size": 4 + }, + "EXTI2": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 8, + "size": 4 + }, + "EXTI1": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 4, + "size": 4 + }, + "EXTI0": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR2": { + "description": "external interrupt configuration register\n 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI7": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 12, + "size": 4 + }, + "EXTI6": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 8, + "size": 4 + }, + "EXTI5": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 4, + "size": 4 + }, + "EXTI4": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR3": { + "description": "external interrupt configuration register\n 3", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI11": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 12, + "size": 4 + }, + "EXTI10": { + "description": "EXTI10", + "offset": 8, + "size": 4 + }, + "EXTI9": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 4, + "size": 4 + }, + "EXTI8": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR4": { + "description": "external interrupt configuration register\n 4", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI15": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 12, + "size": 4 + }, + "EXTI14": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 8, + "size": 4 + }, + "EXTI13": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 4, + "size": 4 + }, + "EXTI12": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 0, + "size": 4 + } + } + } + }, + "CMPCR": { + "description": "Compensation cell control\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "READY": { + "description": "READY", + "offset": 8, + "size": 1 + }, + "CMP_PD": { + "description": "Compensation cell\n power-down", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "SPI1": { + "description": "Serial peripheral interface", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BIDIMODE": { + "description": "Bidirectional data mode\n enable", + "offset": 15, + "size": 1 + }, + "BIDIOE": { + "description": "Output enable in bidirectional\n mode", + "offset": 14, + "size": 1 + }, + "CRCEN": { + "description": "Hardware CRC calculation\n enable", + "offset": 13, + "size": 1 + }, + "CRCNEXT": { + "description": "CRC transfer next", + "offset": 12, + "size": 1 + }, + "DFF": { + "description": "Data frame format", + "offset": 11, + "size": 1 + }, + "RXONLY": { + "description": "Receive only", + "offset": 10, + "size": 1 + }, + "SSM": { + "description": "Software slave management", + "offset": 9, + "size": 1 + }, + "SSI": { + "description": "Internal slave select", + "offset": 8, + "size": 1 + }, + "LSBFIRST": { + "description": "Frame format", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI enable", + "offset": 6, + "size": 1 + }, + "BR": { + "description": "Baud rate control", + "offset": 3, + "size": 3 + }, + "MSTR": { + "description": "Master selection", + "offset": 2, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 1, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXEIE": { + "description": "Tx buffer empty interrupt\n enable", + "offset": 7, + "size": 1 + }, + "RXNEIE": { + "description": "RX buffer not empty interrupt\n enable", + "offset": 6, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 5, + "size": 1 + }, + "FRF": { + "description": "Frame format", + "offset": 4, + "size": 1 + }, + "SSOE": { + "description": "SS output enable", + "offset": 2, + "size": 1 + }, + "TXDMAEN": { + "description": "Tx buffer DMA enable", + "offset": 1, + "size": 1 + }, + "RXDMAEN": { + "description": "Rx buffer DMA enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 8, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIFRFE": { + "description": "TI frame format error", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "BSY": { + "description": "Busy flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "OVR": { + "description": "Overrun flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "MODF": { + "description": "Mode fault", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "CRCERR": { + "description": "CRC error flag", + "offset": 4, + "size": 1 + }, + "UDR": { + "description": "Underrun flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "CHSIDE": { + "description": "Channel side", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "TXE": { + "description": "Transmit buffer empty", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "Receive buffer not empty", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 16 + } + } + } + }, + "CRCPR": { + "description": "CRC polynomial register", + "offset": 16, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial register", + "offset": 0, + "size": 16 + } + } + } + }, + "RXCRCR": { + "description": "RX CRC register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RxCRC": { + "description": "Rx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "TXCRCR": { + "description": "TX CRC register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TxCRC": { + "description": "Tx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "I2SCFGR": { + "description": "I2S configuration register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "I2SMOD": { + "description": "I2S mode selection", + "offset": 11, + "size": 1 + }, + "I2SE": { + "description": "I2S Enable", + "offset": 10, + "size": 1 + }, + "I2SCFG": { + "description": "I2S configuration mode", + "offset": 8, + "size": 2 + }, + "PCMSYNC": { + "description": "PCM frame synchronization", + "offset": 7, + "size": 1 + }, + "I2SSTD": { + "description": "I2S standard selection", + "offset": 4, + "size": 2 + }, + "CKPOL": { + "description": "Steady state clock\n polarity", + "offset": 3, + "size": 1 + }, + "DATLEN": { + "description": "Data length to be\n transferred", + "offset": 1, + "size": 2 + }, + "CHLEN": { + "description": "Channel length (number of bits per audio\n channel)", + "offset": 0, + "size": 1 + } + } + } + }, + "I2SPR": { + "description": "I2S prescaler register", + "offset": 32, + "size": 32, + "reset_value": 10, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKOE": { + "description": "Master clock output enable", + "offset": 9, + "size": 1 + }, + "ODD": { + "description": "Odd factor for the\n prescaler", + "offset": 8, + "size": 1 + }, + "I2SDIV": { + "description": "I2S Linear prescaler", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "LTDC": { + "description": "LCD-TFT Controller", + "children": { + "registers": { + "SSCR": { + "description": "Synchronization Size Configuration\n Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSW": { + "description": "Horizontal Synchronization Width (in\n units of pixel clock period)", + "offset": 16, + "size": 10 + }, + "VSH": { + "description": "Vertical Synchronization Height (in\n units of horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "BPCR": { + "description": "Back Porch Configuration\n Register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AHBP": { + "description": "Accumulated Horizontal back porch (in\n units of pixel clock period)", + "offset": 16, + "size": 10 + }, + "AVBP": { + "description": "Accumulated Vertical back porch (in\n units of horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "AWCR": { + "description": "Active Width Configuration\n Register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AAV": { + "description": "AAV", + "offset": 16, + "size": 10 + }, + "AAH": { + "description": "Accumulated Active Height (in units of\n horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "TWCR": { + "description": "Total Width Configuration\n Register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOTALW": { + "description": "Total Width (in units of pixel clock\n period)", + "offset": 16, + "size": 10 + }, + "TOTALH": { + "description": "Total Height (in units of horizontal\n scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "GCR": { + "description": "Global Control Register", + "offset": 24, + "size": 32, + "reset_value": 8736, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSPOL": { + "description": "Horizontal Synchronization\n Polarity", + "offset": 31, + "size": 1 + }, + "VSPOL": { + "description": "Vertical Synchronization\n Polarity", + "offset": 30, + "size": 1 + }, + "DEPOL": { + "description": "Data Enable Polarity", + "offset": 29, + "size": 1 + }, + "PCPOL": { + "description": "Pixel Clock Polarity", + "offset": 28, + "size": 1 + }, + "DEN": { + "description": "Dither Enable", + "offset": 16, + "size": 1 + }, + "DRW": { + "description": "Dither Red Width", + "offset": 12, + "size": 3, + "access": "read-only" + }, + "DGW": { + "description": "Dither Green Width", + "offset": 8, + "size": 3, + "access": "read-only" + }, + "DBW": { + "description": "Dither Blue Width", + "offset": 4, + "size": 3, + "access": "read-only" + }, + "LTDCEN": { + "description": "LCD-TFT controller enable\n bit", + "offset": 0, + "size": 1 + } + } + } + }, + "SRCR": { + "description": "Shadow Reload Configuration\n Register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBR": { + "description": "Vertical Blanking Reload", + "offset": 1, + "size": 1 + }, + "IMR": { + "description": "Immediate Reload", + "offset": 0, + "size": 1 + } + } + } + }, + "BCCR": { + "description": "Background Color Configuration\n Register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BC": { + "description": "Background Color Red value", + "offset": 0, + "size": 24 + } + } + } + }, + "IER": { + "description": "Interrupt Enable Register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RRIE": { + "description": "Register Reload interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TERRIE": { + "description": "Transfer Error Interrupt\n Enable", + "offset": 2, + "size": 1 + }, + "FUIE": { + "description": "FIFO Underrun Interrupt\n Enable", + "offset": 1, + "size": 1 + }, + "LIE": { + "description": "Line Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ISR": { + "description": "Interrupt Status Register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RRIF": { + "description": "Register Reload Interrupt\n Flag", + "offset": 3, + "size": 1 + }, + "TERRIF": { + "description": "Transfer Error interrupt\n flag", + "offset": 2, + "size": 1 + }, + "FUIF": { + "description": "FIFO Underrun Interrupt\n flag", + "offset": 1, + "size": 1 + }, + "LIF": { + "description": "Line Interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "Interrupt Clear Register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CRRIF": { + "description": "Clears Register Reload Interrupt\n Flag", + "offset": 3, + "size": 1 + }, + "CTERRIF": { + "description": "Clears the Transfer Error Interrupt\n Flag", + "offset": 2, + "size": 1 + }, + "CFUIF": { + "description": "Clears the FIFO Underrun Interrupt\n flag", + "offset": 1, + "size": 1 + }, + "CLIF": { + "description": "Clears the Line Interrupt\n Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "LIPCR": { + "description": "Line Interrupt Position Configuration\n Register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LIPOS": { + "description": "Line Interrupt Position", + "offset": 0, + "size": 11 + } + } + } + }, + "CPSR": { + "description": "Current Position Status\n Register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CXPOS": { + "description": "Current X Position", + "offset": 16, + "size": 16 + }, + "CYPOS": { + "description": "Current Y Position", + "offset": 0, + "size": 16 + } + } + } + }, + "CDSR": { + "description": "Current Display Status\n Register", + "offset": 72, + "size": 32, + "reset_value": 15, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HSYNCS": { + "description": "Horizontal Synchronization display\n Status", + "offset": 3, + "size": 1 + }, + "VSYNCS": { + "description": "Vertical Synchronization display\n Status", + "offset": 2, + "size": 1 + }, + "HDES": { + "description": "Horizontal Data Enable display\n Status", + "offset": 1, + "size": 1 + }, + "VDES": { + "description": "Vertical Data Enable display\n Status", + "offset": 0, + "size": 1 + } + } + } + }, + "L1CR": { + "description": "Layerx Control Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLUTEN": { + "description": "Color Look-Up Table Enable", + "offset": 4, + "size": 1 + }, + "COLKEN": { + "description": "Color Keying Enable", + "offset": 1, + "size": 1 + }, + "LEN": { + "description": "Layer Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "L1WHPCR": { + "description": "Layerx Window Horizontal Position\n Configuration Register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WHSPPOS": { + "description": "Window Horizontal Stop\n Position", + "offset": 16, + "size": 12 + }, + "WHSTPOS": { + "description": "Window Horizontal Start\n Position", + "offset": 0, + "size": 12 + } + } + } + }, + "L1WVPCR": { + "description": "Layerx Window Vertical Position\n Configuration Register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WVSPPOS": { + "description": "Window Vertical Stop\n Position", + "offset": 16, + "size": 11 + }, + "WVSTPOS": { + "description": "Window Vertical Start\n Position", + "offset": 0, + "size": 11 + } + } + } + }, + "L1CKCR": { + "description": "Layerx Color Keying Configuration\n Register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKRED": { + "description": "Color Key Red value", + "offset": 16, + "size": 8 + }, + "CKGREEN": { + "description": "Color Key Green value", + "offset": 8, + "size": 8 + }, + "CKBLUE": { + "description": "Color Key Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L1PFCR": { + "description": "Layerx Pixel Format Configuration\n Register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PF": { + "description": "Pixel Format", + "offset": 0, + "size": 3 + } + } + } + }, + "L1CACR": { + "description": "Layerx Constant Alpha Configuration\n Register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CONSTA": { + "description": "Constant Alpha", + "offset": 0, + "size": 8 + } + } + } + }, + "L1DCCR": { + "description": "Layerx Default Color Configuration\n Register", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCALPHA": { + "description": "Default Color Alpha", + "offset": 24, + "size": 8 + }, + "DCRED": { + "description": "Default Color Red", + "offset": 16, + "size": 8 + }, + "DCGREEN": { + "description": "Default Color Green", + "offset": 8, + "size": 8 + }, + "DCBLUE": { + "description": "Default Color Blue", + "offset": 0, + "size": 8 + } + } + } + }, + "L1BFCR": { + "description": "Layerx Blending Factors Configuration\n Register", + "offset": 160, + "size": 32, + "reset_value": 1543, + "reset_mask": 4294967295, + "children": { + "fields": { + "BF1": { + "description": "Blending Factor 1", + "offset": 8, + "size": 3 + }, + "BF2": { + "description": "Blending Factor 2", + "offset": 0, + "size": 3 + } + } + } + }, + "L1CFBAR": { + "description": "Layerx Color Frame Buffer Address\n Register", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBADD": { + "description": "Color Frame Buffer Start\n Address", + "offset": 0, + "size": 32 + } + } + } + }, + "L1CFBLR": { + "description": "Layerx Color Frame Buffer Length\n Register", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBP": { + "description": "Color Frame Buffer Pitch in\n bytes", + "offset": 16, + "size": 13 + }, + "CFBLL": { + "description": "Color Frame Buffer Line\n Length", + "offset": 0, + "size": 13 + } + } + } + }, + "L1CFBLNR": { + "description": "Layerx ColorFrame Buffer Line Number\n Register", + "offset": 180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBLNBR": { + "description": "Frame Buffer Line Number", + "offset": 0, + "size": 11 + } + } + } + }, + "L1CLUTWR": { + "description": "Layerx CLUT Write Register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CLUTADD": { + "description": "CLUT Address", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "Red value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L2CR": { + "description": "Layerx Control Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLUTEN": { + "description": "Color Look-Up Table Enable", + "offset": 4, + "size": 1 + }, + "COLKEN": { + "description": "Color Keying Enable", + "offset": 1, + "size": 1 + }, + "LEN": { + "description": "Layer Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "L2WHPCR": { + "description": "Layerx Window Horizontal Position\n Configuration Register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WHSPPOS": { + "description": "Window Horizontal Stop\n Position", + "offset": 16, + "size": 12 + }, + "WHSTPOS": { + "description": "Window Horizontal Start\n Position", + "offset": 0, + "size": 12 + } + } + } + }, + "L2WVPCR": { + "description": "Layerx Window Vertical Position\n Configuration Register", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WVSPPOS": { + "description": "Window Vertical Stop\n Position", + "offset": 16, + "size": 11 + }, + "WVSTPOS": { + "description": "Window Vertical Start\n Position", + "offset": 0, + "size": 11 + } + } + } + }, + "L2CKCR": { + "description": "Layerx Color Keying Configuration\n Register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKRED": { + "description": "Color Key Red value", + "offset": 15, + "size": 9 + }, + "CKGREEN": { + "description": "Color Key Green value", + "offset": 8, + "size": 7 + }, + "CKBLUE": { + "description": "Color Key Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L2PFCR": { + "description": "Layerx Pixel Format Configuration\n Register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PF": { + "description": "Pixel Format", + "offset": 0, + "size": 3 + } + } + } + }, + "L2CACR": { + "description": "Layerx Constant Alpha Configuration\n Register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CONSTA": { + "description": "Constant Alpha", + "offset": 0, + "size": 8 + } + } + } + }, + "L2DCCR": { + "description": "Layerx Default Color Configuration\n Register", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCALPHA": { + "description": "Default Color Alpha", + "offset": 24, + "size": 8 + }, + "DCRED": { + "description": "Default Color Red", + "offset": 16, + "size": 8 + }, + "DCGREEN": { + "description": "Default Color Green", + "offset": 8, + "size": 8 + }, + "DCBLUE": { + "description": "Default Color Blue", + "offset": 0, + "size": 8 + } + } + } + }, + "L2BFCR": { + "description": "Layerx Blending Factors Configuration\n Register", + "offset": 288, + "size": 32, + "reset_value": 1543, + "reset_mask": 4294967295, + "children": { + "fields": { + "BF1": { + "description": "Blending Factor 1", + "offset": 8, + "size": 3 + }, + "BF2": { + "description": "Blending Factor 2", + "offset": 0, + "size": 3 + } + } + } + }, + "L2CFBAR": { + "description": "Layerx Color Frame Buffer Address\n Register", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBADD": { + "description": "Color Frame Buffer Start\n Address", + "offset": 0, + "size": 32 + } + } + } + }, + "L2CFBLR": { + "description": "Layerx Color Frame Buffer Length\n Register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBP": { + "description": "Color Frame Buffer Pitch in\n bytes", + "offset": 16, + "size": 13 + }, + "CFBLL": { + "description": "Color Frame Buffer Line\n Length", + "offset": 0, + "size": 13 + } + } + } + }, + "L2CFBLNR": { + "description": "Layerx ColorFrame Buffer Line Number\n Register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBLNBR": { + "description": "Frame Buffer Line Number", + "offset": 0, + "size": 11 + } + } + } + }, + "L2CLUTWR": { + "description": "Layerx CLUT Write Register", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CLUTADD": { + "description": "CLUT Address", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "Red value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SAI1": { + "description": "Serial audio interface", + "children": { + "registers": { + "SAI_ACR1": { + "description": "SAI AConfiguration register 1", + "offset": 4, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKDIV": { + "description": "Master clock divider", + "offset": 20, + "size": 4 + }, + "MODE": { + "description": "Audio block mode", + "offset": 0, + "size": 2 + }, + "PRTCFG": { + "description": "Protocol configuration", + "offset": 2, + "size": 2 + }, + "DS": { + "description": "Data size", + "offset": 5, + "size": 3 + }, + "LSBFIRST": { + "description": "Least significant bit\n first", + "offset": 8, + "size": 1 + }, + "CKSTR": { + "description": "Clock strobing edge", + "offset": 9, + "size": 1 + }, + "SYNCEN": { + "description": "Synchronization enable", + "offset": 10, + "size": 2 + }, + "MONO": { + "description": "Mono mode", + "offset": 12, + "size": 1 + }, + "OUTDRIV": { + "description": "Output drive", + "offset": 13, + "size": 1 + }, + "SAIAEN": { + "description": "Audio block enable", + "offset": 16, + "size": 1 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 17, + "size": 1 + }, + "NODIV": { + "description": "No divider", + "offset": 19, + "size": 1 + } + } + } + }, + "SAI_BCR1": { + "description": "SAI BConfiguration register 1", + "offset": 36, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Audio block mode", + "offset": 0, + "size": 2 + }, + "PRTCFG": { + "description": "Protocol configuration", + "offset": 2, + "size": 2 + }, + "DS": { + "description": "Data size", + "offset": 5, + "size": 3 + }, + "LSBFIRST": { + "description": "Least significant bit\n first", + "offset": 8, + "size": 1 + }, + "CKSTR": { + "description": "Clock strobing edge", + "offset": 9, + "size": 1 + }, + "SYNCEN": { + "description": "Synchronization enable", + "offset": 10, + "size": 2 + }, + "MONO": { + "description": "Mono mode", + "offset": 12, + "size": 1 + }, + "OUTDRIV": { + "description": "Output drive", + "offset": 13, + "size": 1 + }, + "SAIBEN": { + "description": "Audio block enable", + "offset": 16, + "size": 1 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 17, + "size": 1 + }, + "NODIV": { + "description": "No divider", + "offset": 19, + "size": 1 + }, + "MCKDIV": { + "description": "Master clock divider", + "offset": 20, + "size": 4 + } + } + } + }, + "SAI_ACR2": { + "description": "SAI AConfiguration register 2", + "offset": 8, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FTH": { + "description": "FIFO threshold", + "offset": 0, + "size": 3 + }, + "FFLUSH": { + "description": "FIFO flush", + "offset": 3, + "size": 1 + }, + "TRIS": { + "description": "Tristate management on data\n line", + "offset": 4, + "size": 1 + }, + "MUTE": { + "description": "Mute", + "offset": 5, + "size": 1 + }, + "MUTEVAL": { + "description": "Mute value", + "offset": 6, + "size": 1 + }, + "MUTECNT": { + "description": "Mute counter", + "offset": 7, + "size": 6 + }, + "CPL": { + "description": "Complement bit", + "offset": 13, + "size": 1 + }, + "COMP": { + "description": "Companding mode", + "offset": 14, + "size": 2 + } + } + } + }, + "SAI_BCR2": { + "description": "SAI BConfiguration register 2", + "offset": 40, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FTH": { + "description": "FIFO threshold", + "offset": 0, + "size": 3 + }, + "FFLUSH": { + "description": "FIFO flush", + "offset": 3, + "size": 1 + }, + "TRIS": { + "description": "Tristate management on data\n line", + "offset": 4, + "size": 1 + }, + "MUTE": { + "description": "Mute", + "offset": 5, + "size": 1 + }, + "MUTEVAL": { + "description": "Mute value", + "offset": 6, + "size": 1 + }, + "MUTECNT": { + "description": "Mute counter", + "offset": 7, + "size": 6 + }, + "CPL": { + "description": "Complement bit", + "offset": 13, + "size": 1 + }, + "COMP": { + "description": "Companding mode", + "offset": 14, + "size": 2 + } + } + } + }, + "SAI_AFRCR": { + "description": "SAI AFrame configuration\n register", + "offset": 12, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRL": { + "description": "Frame length", + "offset": 0, + "size": 8 + }, + "FSALL": { + "description": "Frame synchronization active level\n length", + "offset": 8, + "size": 7 + }, + "FSDEF": { + "description": "Frame synchronization\n definition", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "FSPOL": { + "description": "Frame synchronization\n polarity", + "offset": 17, + "size": 1 + }, + "FSOFF": { + "description": "Frame synchronization\n offset", + "offset": 18, + "size": 1 + } + } + } + }, + "SAI_BFRCR": { + "description": "SAI BFrame configuration\n register", + "offset": 44, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRL": { + "description": "Frame length", + "offset": 0, + "size": 8 + }, + "FSALL": { + "description": "Frame synchronization active level\n length", + "offset": 8, + "size": 7 + }, + "FSDEF": { + "description": "Frame synchronization\n definition", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "FSPOL": { + "description": "Frame synchronization\n polarity", + "offset": 17, + "size": 1 + }, + "FSOFF": { + "description": "Frame synchronization\n offset", + "offset": 18, + "size": 1 + } + } + } + }, + "SAI_ASLOTR": { + "description": "SAI ASlot register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FBOFF": { + "description": "First bit offset", + "offset": 0, + "size": 5 + }, + "SLOTSZ": { + "description": "Slot size", + "offset": 6, + "size": 2 + }, + "NBSLOT": { + "description": "Number of slots in an audio\n frame", + "offset": 8, + "size": 4 + }, + "SLOTEN": { + "description": "Slot enable", + "offset": 16, + "size": 16 + } + } + } + }, + "SAI_BSLOTR": { + "description": "SAI BSlot register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FBOFF": { + "description": "First bit offset", + "offset": 0, + "size": 5 + }, + "SLOTSZ": { + "description": "Slot size", + "offset": 6, + "size": 2 + }, + "NBSLOT": { + "description": "Number of slots in an audio\n frame", + "offset": 8, + "size": 4 + }, + "SLOTEN": { + "description": "Slot enable", + "offset": 16, + "size": 16 + } + } + } + }, + "SAI_AIM": { + "description": "SAI AInterrupt mask register2", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVRUDRIE": { + "description": "Overrun/underrun interrupt\n enable", + "offset": 0, + "size": 1 + }, + "MUTEDETIE": { + "description": "Mute detection interrupt\n enable", + "offset": 1, + "size": 1 + }, + "WCKCFGIE": { + "description": "Wrong clock configuration interrupt\n enable", + "offset": 2, + "size": 1 + }, + "FREQIE": { + "description": "FIFO request interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CNRDYIE": { + "description": "Codec not ready interrupt\n enable", + "offset": 4, + "size": 1 + }, + "AFSDETIE": { + "description": "Anticipated frame synchronization\n detection interrupt enable", + "offset": 5, + "size": 1 + }, + "LFSDETIE": { + "description": "Late frame synchronization detection\n interrupt enable", + "offset": 6, + "size": 1 + } + } + } + }, + "SAI_BIM": { + "description": "SAI BInterrupt mask register2", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVRUDRIE": { + "description": "Overrun/underrun interrupt\n enable", + "offset": 0, + "size": 1 + }, + "MUTEDETIE": { + "description": "Mute detection interrupt\n enable", + "offset": 1, + "size": 1 + }, + "WCKCFGIE": { + "description": "Wrong clock configuration interrupt\n enable", + "offset": 2, + "size": 1 + }, + "FREQIE": { + "description": "FIFO request interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CNRDYIE": { + "description": "Codec not ready interrupt\n enable", + "offset": 4, + "size": 1 + }, + "AFSDETIE": { + "description": "Anticipated frame synchronization\n detection interrupt enable", + "offset": 5, + "size": 1 + }, + "LFSDETIE": { + "description": "Late frame synchronization detection\n interrupt enable", + "offset": 6, + "size": 1 + } + } + } + }, + "SAI_ASR": { + "description": "SAI AStatus register", + "offset": 24, + "size": 32, + "reset_value": 8, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OVRUDR": { + "description": "Overrun / underrun", + "offset": 0, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection", + "offset": 1, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "FREQ": { + "description": "FIFO request", + "offset": 3, + "size": 1 + }, + "CNRDY": { + "description": "Codec not ready", + "offset": 4, + "size": 1 + }, + "AFSDET": { + "description": "Anticipated frame synchronization\n detection", + "offset": 5, + "size": 1 + }, + "LFSDET": { + "description": "Late frame synchronization\n detection", + "offset": 6, + "size": 1 + }, + "FLTH": { + "description": "FIFO level threshold", + "offset": 16, + "size": 3 + } + } + } + }, + "SAI_BSR": { + "description": "SAI BStatus register", + "offset": 56, + "size": 32, + "reset_value": 8, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OVRUDR": { + "description": "Overrun / underrun", + "offset": 0, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection", + "offset": 1, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "FREQ": { + "description": "FIFO request", + "offset": 3, + "size": 1 + }, + "CNRDY": { + "description": "Codec not ready", + "offset": 4, + "size": 1 + }, + "AFSDET": { + "description": "Anticipated frame synchronization\n detection", + "offset": 5, + "size": 1 + }, + "LFSDET": { + "description": "Late frame synchronization\n detection", + "offset": 6, + "size": 1 + }, + "FLTH": { + "description": "FIFO level threshold", + "offset": 16, + "size": 3 + } + } + } + }, + "SAI_ACLRFR": { + "description": "SAI AClear flag register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COVRUDR": { + "description": "Clear overrun / underrun", + "offset": 0, + "size": 1 + }, + "CMUTEDET": { + "description": "Mute detection flag", + "offset": 1, + "size": 1 + }, + "CWCKCFG": { + "description": "Clear wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "CCNRDY": { + "description": "Clear codec not ready flag", + "offset": 4, + "size": 1 + }, + "CAFSDET": { + "description": "Clear anticipated frame synchronization\n detection flag", + "offset": 5, + "size": 1 + }, + "CLFSDET": { + "description": "Clear late frame synchronization\n detection flag", + "offset": 6, + "size": 1 + } + } + } + }, + "SAI_BCLRFR": { + "description": "SAI BClear flag register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COVRUDR": { + "description": "Clear overrun / underrun", + "offset": 0, + "size": 1 + }, + "CMUTEDET": { + "description": "Mute detection flag", + "offset": 1, + "size": 1 + }, + "CWCKCFG": { + "description": "Clear wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "CCNRDY": { + "description": "Clear codec not ready flag", + "offset": 4, + "size": 1 + }, + "CAFSDET": { + "description": "Clear anticipated frame synchronization\n detection flag", + "offset": 5, + "size": 1 + }, + "CLFSDET": { + "description": "Clear late frame synchronization\n detection flag", + "offset": 6, + "size": 1 + } + } + } + }, + "SAI_ADR": { + "description": "SAI AData register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Data", + "offset": 0, + "size": 32 + } + } + } + }, + "SAI_BDR": { + "description": "SAI BData register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "children": { + "registers": { + "ISER0": { + "description": "Interrupt Set-Enable Register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER1": { + "description": "Interrupt Set-Enable Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER2": { + "description": "Interrupt Set-Enable Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER0": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER1": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER2": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR0": { + "description": "Interrupt Set-Pending Register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR1": { + "description": "Interrupt Set-Pending Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR2": { + "description": "Interrupt Set-Pending Register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR0": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR1": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR2": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR0": { + "description": "Interrupt Active Bit Register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR1": { + "description": "Interrupt Active Bit Register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR2": { + "description": "Interrupt Active Bit Register", + "offset": 520, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IPR0": { + "description": "Interrupt Priority Register", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR1": { + "description": "Interrupt Priority Register", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR2": { + "description": "Interrupt Priority Register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR3": { + "description": "Interrupt Priority Register", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR4": { + "description": "Interrupt Priority Register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR5": { + "description": "Interrupt Priority Register", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR6": { + "description": "Interrupt Priority Register", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR7": { + "description": "Interrupt Priority Register", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR8": { + "description": "Interrupt Priority Register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR9": { + "description": "Interrupt Priority Register", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR10": { + "description": "Interrupt Priority Register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR11": { + "description": "Interrupt Priority Register", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR12": { + "description": "Interrupt Priority Register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR13": { + "description": "Interrupt Priority Register", + "offset": 820, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR14": { + "description": "Interrupt Priority Register", + "offset": 824, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR15": { + "description": "Interrupt Priority Register", + "offset": 828, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR16": { + "description": "Interrupt Priority Register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR17": { + "description": "Interrupt Priority Register", + "offset": 836, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR18": { + "description": "Interrupt Priority Register", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR19": { + "description": "Interrupt Priority Register", + "offset": 844, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + } + } + } + }, + "OTG_HS_PWRCLK": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_PCGCR": { + "description": "Power and clock gating control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPPCLK": { + "description": "Stop PHY clock", + "offset": 0, + "size": 1 + }, + "GATEHCLK": { + "description": "Gate HCLK", + "offset": 1, + "size": 1 + }, + "PHYSUSP": { + "description": "PHY suspended", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "OTG_HS_DEVICE": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_DCFG": { + "description": "OTG_HS device configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 35651584, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSPD": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOHSK": { + "description": "Nonzero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAD": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "PFIVL": { + "description": "Periodic (micro)frame\n interval", + "offset": 11, + "size": 2 + }, + "PERSCHIVL": { + "description": "Periodic scheduling\n interval", + "offset": 24, + "size": 2 + } + } + } + }, + "OTG_HS_DCTL": { + "description": "OTG_HS device control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWUSIG": { + "description": "Remote wakeup signaling", + "offset": 0, + "size": 1 + }, + "SDIS": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINSTS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONSTS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "TCTL": { + "description": "Test control", + "offset": 4, + "size": 3 + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1, + "access": "write-only" + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1, + "access": "write-only" + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1, + "access": "write-only" + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1, + "access": "write-only" + }, + "POPRGDNE": { + "description": "Power-on programming done", + "offset": 11, + "size": 1 + } + } + } + }, + "OTG_HS_DSTS": { + "description": "OTG_HS device status register", + "offset": 8, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SUSPSTS": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ENUMSPD": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "EERR": { + "description": "Erratic error", + "offset": 3, + "size": 1 + }, + "FNSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "OTG_HS_DIEPMSK": { + "description": "OTG_HS device IN endpoint common interrupt\n mask register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (nonisochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "FIFO underrun mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPMSK": { + "description": "OTG_HS device OUT endpoint common interrupt\n mask register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "STUPM": { + "description": "SETUP phase done mask", + "offset": 3, + "size": 1 + }, + "OTEPDM": { + "description": "OUT token received when endpoint\n disabled mask", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets received\n mask", + "offset": 6, + "size": 1 + }, + "OPEM": { + "description": "OUT packet error mask", + "offset": 8, + "size": 1 + }, + "BOIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + } + } + } + }, + "OTG_HS_DAINT": { + "description": "OTG_HS device all endpoints interrupt\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPINT": { + "description": "IN endpoint interrupt bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DAINTMSK": { + "description": "OTG_HS all endpoints interrupt mask\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPM": { + "description": "IN EP interrupt mask bits", + "offset": 0, + "size": 16 + }, + "OEPM": { + "description": "OUT EP interrupt mask bits", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DVBUSDIS": { + "description": "OTG_HS device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DVBUSPULSE": { + "description": "OTG_HS device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSP": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "OTG_HS_DTHRCTL": { + "description": "OTG_HS Device threshold control\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONISOTHREN": { + "description": "Nonisochronous IN endpoints threshold\n enable", + "offset": 0, + "size": 1 + }, + "ISOTHREN": { + "description": "ISO IN endpoint threshold\n enable", + "offset": 1, + "size": 1 + }, + "TXTHRLEN": { + "description": "Transmit threshold length", + "offset": 2, + "size": 9 + }, + "RXTHREN": { + "description": "Receive threshold enable", + "offset": 16, + "size": 1 + }, + "RXTHRLEN": { + "description": "Receive threshold length", + "offset": 17, + "size": 9 + }, + "ARPEN": { + "description": "Arbiter parking enable", + "offset": 27, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPEMPMSK": { + "description": "OTG_HS device IN endpoint FIFO empty\n interrupt mask register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXFEM": { + "description": "IN EP Tx FIFO empty interrupt mask\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DEACHINT": { + "description": "OTG_HS device each endpoint interrupt\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEP1INT": { + "description": "IN endpoint 1interrupt bit", + "offset": 1, + "size": 1 + }, + "OEP1INT": { + "description": "OUT endpoint 1 interrupt\n bit", + "offset": 17, + "size": 1 + } + } + } + }, + "OTG_HS_DEACHINTMSK": { + "description": "OTG_HS device each endpoint interrupt\n register mask", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEP1INTM": { + "description": "IN Endpoint 1 interrupt mask\n bit", + "offset": 1, + "size": 1 + }, + "OEP1INTM": { + "description": "OUT Endpoint 1 interrupt mask\n bit", + "offset": 17, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPEACHMSK1": { + "description": "OTG_HS device each in endpoint-1 interrupt\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (nonisochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "FIFO underrun mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + }, + "NAKM": { + "description": "NAK interrupt mask", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPEACHMSK1": { + "description": "OTG_HS device each OUT endpoint-1 interrupt\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "OUT packet error mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + }, + "BERRM": { + "description": "Bubble error interrupt\n mask", + "offset": 12, + "size": 1 + }, + "NAKM": { + "description": "NAK interrupt mask", + "offset": 13, + "size": 1 + }, + "NYETM": { + "description": "NYET interrupt mask", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL0": { + "description": "OTG device endpoint-0 control\n register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL4": { + "description": "OTG device endpoint-4 control\n register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL5": { + "description": "OTG device endpoint-5 control\n register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL6": { + "description": "OTG device endpoint-6 control\n register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL7": { + "description": "OTG device endpoint-7 control\n register", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT0": { + "description": "OTG device endpoint-0 interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT1": { + "description": "OTG device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT2": { + "description": "OTG device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT3": { + "description": "OTG device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT4": { + "description": "OTG device endpoint-4 interrupt\n register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT5": { + "description": "OTG device endpoint-5 interrupt\n register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT6": { + "description": "OTG device endpoint-6 interrupt\n register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT7": { + "description": "OTG device endpoint-7 interrupt\n register", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPTSIZ0": { + "description": "OTG_HS device IN endpoint 0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPDMA1": { + "description": "OTG_HS device endpoint-1 DMA address\n register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA2": { + "description": "OTG_HS device endpoint-2 DMA address\n register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA3": { + "description": "OTG_HS device endpoint-3 DMA address\n register", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA4": { + "description": "OTG_HS device endpoint-4 DMA address\n register", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA5": { + "description": "OTG_HS device endpoint-5 DMA address\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DTXFSTS0": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS1": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS2": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS3": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS4": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS5": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTSIZ1": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ2": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ3": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ4": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ5": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPCTL0": { + "description": "OTG_HS device control OUT endpoint 0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 2, + "access": "read-only" + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1, + "access": "write-only" + } + } + } + }, + "OTG_HS_DOEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT0": { + "description": "OTG_HS device endpoint-0 interrupt\n register", + "offset": 776, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT1": { + "description": "OTG_HS device endpoint-1 interrupt\n register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT2": { + "description": "OTG_HS device endpoint-2 interrupt\n register", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT3": { + "description": "OTG_HS device endpoint-3 interrupt\n register", + "offset": 872, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT4": { + "description": "OTG_HS device endpoint-4 interrupt\n register", + "offset": 904, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT5": { + "description": "OTG_HS device endpoint-5 interrupt\n register", + "offset": 936, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT6": { + "description": "OTG_HS device endpoint-6 interrupt\n register", + "offset": 968, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT7": { + "description": "OTG_HS device endpoint-7 interrupt\n register", + "offset": 1000, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPTSIZ0": { + "description": "OTG_HS device endpoint-1 transfer size\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "STUPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ1": { + "description": "OTG_HS device endpoint-2 transfer size\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ2": { + "description": "OTG_HS device endpoint-3 transfer size\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ3": { + "description": "OTG_HS device endpoint-4 transfer size\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ4": { + "description": "OTG_HS device endpoint-5 transfer size\n register", + "offset": 912, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "OTG_HS_HOST": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_HCFG": { + "description": "OTG_HS host configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSLSPCS": { + "description": "FS/LS PHY clock select", + "offset": 0, + "size": 2 + }, + "FSLSS": { + "description": "FS- and LS-only support", + "offset": 2, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_HFIR": { + "description": "OTG_HS Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 60000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRIVL": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HFNUM": { + "description": "OTG_HS host frame number/frame time\n remaining register", + "offset": 8, + "size": 32, + "reset_value": 16383, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FTREM": { + "description": "Frame time remaining", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_HPTXSTS": { + "description": "OTG_HS_Host periodic transmit FIFO/queue\n status register", + "offset": 16, + "size": 32, + "reset_value": 524544, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFSAVL": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16 + }, + "PTXQSAV": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXQTOP": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "OTG_HS_HAINT": { + "description": "OTG_HS Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HAINT": { + "description": "Channel interrupts", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HAINTMSK": { + "description": "OTG_HS host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HAINTM": { + "description": "Channel interrupt mask", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HPRT": { + "description": "OTG_HS host port control and status\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCSTS": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCDET": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PENA": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PENCHNG": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "POCA": { + "description": "Port overcurrent active", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "POCCHNG": { + "description": "Port overcurrent change", + "offset": 5, + "size": 1 + }, + "PRES": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSUSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLSTS": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PPWR": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PTCTL": { + "description": "Port test control", + "offset": 13, + "size": 4 + }, + "PSPD": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "OTG_HS_HCCHAR0": { + "description": "OTG_HS host channel-0 characteristics\n register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR1": { + "description": "OTG_HS host channel-1 characteristics\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR2": { + "description": "OTG_HS host channel-2 characteristics\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR3": { + "description": "OTG_HS host channel-3 characteristics\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR4": { + "description": "OTG_HS host channel-4 characteristics\n register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR5": { + "description": "OTG_HS host channel-5 characteristics\n register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR6": { + "description": "OTG_HS host channel-6 characteristics\n register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR7": { + "description": "OTG_HS host channel-7 characteristics\n register", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR8": { + "description": "OTG_HS host channel-8 characteristics\n register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR9": { + "description": "OTG_HS host channel-9 characteristics\n register", + "offset": 544, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR10": { + "description": "OTG_HS host channel-10 characteristics\n register", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR11": { + "description": "OTG_HS host channel-11 characteristics\n register", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT0": { + "description": "OTG_HS host channel-0 split control\n register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT1": { + "description": "OTG_HS host channel-1 split control\n register", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT2": { + "description": "OTG_HS host channel-2 split control\n register", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT3": { + "description": "OTG_HS host channel-3 split control\n register", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT4": { + "description": "OTG_HS host channel-4 split control\n register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT5": { + "description": "OTG_HS host channel-5 split control\n register", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT6": { + "description": "OTG_HS host channel-6 split control\n register", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT7": { + "description": "OTG_HS host channel-7 split control\n register", + "offset": 484, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT8": { + "description": "OTG_HS host channel-8 split control\n register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT9": { + "description": "OTG_HS host channel-9 split control\n register", + "offset": 548, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT10": { + "description": "OTG_HS host channel-10 split control\n register", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT11": { + "description": "OTG_HS host channel-11 split control\n register", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT0": { + "description": "OTG_HS host channel-11 interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT1": { + "description": "OTG_HS host channel-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT2": { + "description": "OTG_HS host channel-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT3": { + "description": "OTG_HS host channel-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT4": { + "description": "OTG_HS host channel-4 interrupt\n register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT5": { + "description": "OTG_HS host channel-5 interrupt\n register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT6": { + "description": "OTG_HS host channel-6 interrupt\n register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT7": { + "description": "OTG_HS host channel-7 interrupt\n register", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT8": { + "description": "OTG_HS host channel-8 interrupt\n register", + "offset": 520, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT9": { + "description": "OTG_HS host channel-9 interrupt\n register", + "offset": 552, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT10": { + "description": "OTG_HS host channel-10 interrupt\n register", + "offset": 584, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT11": { + "description": "OTG_HS host channel-11 interrupt\n register", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK0": { + "description": "OTG_HS host channel-11 interrupt mask\n register", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK1": { + "description": "OTG_HS host channel-1 interrupt mask\n register", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK2": { + "description": "OTG_HS host channel-2 interrupt mask\n register", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK3": { + "description": "OTG_HS host channel-3 interrupt mask\n register", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK4": { + "description": "OTG_HS host channel-4 interrupt mask\n register", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK5": { + "description": "OTG_HS host channel-5 interrupt mask\n register", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK6": { + "description": "OTG_HS host channel-6 interrupt mask\n register", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK7": { + "description": "OTG_HS host channel-7 interrupt mask\n register", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK8": { + "description": "OTG_HS host channel-8 interrupt mask\n register", + "offset": 524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK9": { + "description": "OTG_HS host channel-9 interrupt mask\n register", + "offset": 556, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK10": { + "description": "OTG_HS host channel-10 interrupt mask\n register", + "offset": 588, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK11": { + "description": "OTG_HS host channel-11 interrupt mask\n register", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCTSIZ0": { + "description": "OTG_HS host channel-11 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ1": { + "description": "OTG_HS host channel-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ2": { + "description": "OTG_HS host channel-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ3": { + "description": "OTG_HS host channel-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ4": { + "description": "OTG_HS host channel-4 transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ5": { + "description": "OTG_HS host channel-5 transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ6": { + "description": "OTG_HS host channel-6 transfer size\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ7": { + "description": "OTG_HS host channel-7 transfer size\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ8": { + "description": "OTG_HS host channel-8 transfer size\n register", + "offset": 528, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ9": { + "description": "OTG_HS host channel-9 transfer size\n register", + "offset": 560, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ10": { + "description": "OTG_HS host channel-10 transfer size\n register", + "offset": 592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ11": { + "description": "OTG_HS host channel-11 transfer size\n register", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCDMA0": { + "description": "OTG_HS host channel-0 DMA address\n register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA1": { + "description": "OTG_HS host channel-1 DMA address\n register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA2": { + "description": "OTG_HS host channel-2 DMA address\n register", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA3": { + "description": "OTG_HS host channel-3 DMA address\n register", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA4": { + "description": "OTG_HS host channel-4 DMA address\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA5": { + "description": "OTG_HS host channel-5 DMA address\n register", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA6": { + "description": "OTG_HS host channel-6 DMA address\n register", + "offset": 468, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA7": { + "description": "OTG_HS host channel-7 DMA address\n register", + "offset": 500, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA8": { + "description": "OTG_HS host channel-8 DMA address\n register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA9": { + "description": "OTG_HS host channel-9 DMA address\n register", + "offset": 564, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA10": { + "description": "OTG_HS host channel-10 DMA address\n register", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA11": { + "description": "OTG_HS host channel-11 DMA address\n register", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "OTG_HS_GLOBAL": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_GOTGCTL": { + "description": "OTG_HS control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRQSCS": { + "description": "Session request success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRQ": { + "description": "Session request", + "offset": 1, + "size": 1 + }, + "HNGSCS": { + "description": "Host negotiation success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPRQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HSHNPEN": { + "description": "Host set HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "CIDSTS": { + "description": "Connector ID status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DBCT": { + "description": "Long/short debounce time", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASVLD": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSVLD": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_GOTGINT": { + "description": "OTG_HS interrupt register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEDET": { + "description": "Session end detected", + "offset": 2, + "size": 1 + }, + "SRSSCHG": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNSSCHG": { + "description": "Host negotiation success status\n change", + "offset": 9, + "size": 1 + }, + "HNGDET": { + "description": "Host negotiation detected", + "offset": 17, + "size": 1 + }, + "ADTOCHG": { + "description": "A-device timeout change", + "offset": 18, + "size": 1 + }, + "DBCDNE": { + "description": "Debounce done", + "offset": 19, + "size": 1 + } + } + } + }, + "OTG_HS_GAHBCFG": { + "description": "OTG_HS AHB configuration\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINT": { + "description": "Global interrupt mask", + "offset": 0, + "size": 1 + }, + "HBSTLEN": { + "description": "Burst length/type", + "offset": 1, + "size": 4 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 5, + "size": 1 + }, + "TXFELVL": { + "description": "TxFIFO empty level", + "offset": 7, + "size": 1 + }, + "PTXFELVL": { + "description": "Periodic TxFIFO empty\n level", + "offset": 8, + "size": 1 + } + } + } + }, + "OTG_HS_GUSBCFG": { + "description": "OTG_HS USB configuration\n register", + "offset": 12, + "size": 32, + "reset_value": 2560, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOCAL": { + "description": "FS timeout calibration", + "offset": 0, + "size": 3 + }, + "PHYSEL": { + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n full-speed serial transceiver select", + "offset": 6, + "size": 1, + "access": "write-only" + }, + "SRPCAP": { + "description": "SRP-capable", + "offset": 8, + "size": 1 + }, + "HNPCAP": { + "description": "HNP-capable", + "offset": 9, + "size": 1 + }, + "TRDT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "PHYLPCS": { + "description": "PHY Low-power clock select", + "offset": 15, + "size": 1 + }, + "ULPIFSLS": { + "description": "ULPI FS/LS select", + "offset": 17, + "size": 1 + }, + "ULPIAR": { + "description": "ULPI Auto-resume", + "offset": 18, + "size": 1 + }, + "ULPICSM": { + "description": "ULPI Clock SuspendM", + "offset": 19, + "size": 1 + }, + "ULPIEVBUSD": { + "description": "ULPI External VBUS Drive", + "offset": 20, + "size": 1 + }, + "ULPIEVBUSI": { + "description": "ULPI external VBUS\n indicator", + "offset": 21, + "size": 1 + }, + "TSDPS": { + "description": "TermSel DLine pulsing\n selection", + "offset": 22, + "size": 1 + }, + "PCCI": { + "description": "Indicator complement", + "offset": 23, + "size": 1 + }, + "PTCI": { + "description": "Indicator pass through", + "offset": 24, + "size": 1 + }, + "ULPIIPD": { + "description": "ULPI interface protect\n disable", + "offset": 25, + "size": 1 + }, + "FHMOD": { + "description": "Forced host mode", + "offset": 29, + "size": 1 + }, + "FDMOD": { + "description": "Forced peripheral mode", + "offset": 30, + "size": 1 + }, + "CTXPKT": { + "description": "Corrupt Tx packet", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GRSTCTL": { + "description": "OTG_HS reset register", + "offset": 16, + "size": 32, + "reset_value": 536870912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "FCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFFLSH": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFFLSH": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + }, + "DMAREQ": { + "description": "DMA request signal", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "AHBIDL": { + "description": "AHB master idle", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_GINTSTS": { + "description": "OTG_HS core interrupt register", + "offset": 20, + "size": 32, + "reset_value": 67108896, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMOD": { + "description": "Current mode of operation", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MMIS": { + "description": "Mode mismatch interrupt", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFLVL": { + "description": "RxFIFO nonempty", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFE": { + "description": "Nonperiodic TxFIFO empty", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GINAKEFF": { + "description": "Global IN nonperiodic NAK\n effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "BOUTNAKEFF": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESUSP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "USBSUSP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMDNE": { + "description": "Enumeration done", + "offset": 13, + "size": 1 + }, + "ISOODRP": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPF": { + "description": "End of periodic frame\n interrupt", + "offset": 15, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoint interrupt", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPINT": { + "description": "OUT endpoint interrupt", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "IISOIXFR": { + "description": "Incomplete isochronous IN\n transfer", + "offset": 20, + "size": 1 + }, + "PXFR_INCOMPISOOUT": { + "description": "Incomplete periodic\n transfer", + "offset": 21, + "size": 1 + }, + "DATAFSUSP": { + "description": "Data fetch suspended", + "offset": 22, + "size": 1 + }, + "HPRTINT": { + "description": "Host port interrupt", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCINT": { + "description": "Host channels interrupt", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFE": { + "description": "Periodic TxFIFO empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CIDSCHG": { + "description": "Connector ID status change", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected\n interrupt", + "offset": 29, + "size": 1 + }, + "SRQINT": { + "description": "Session request/new session detected\n interrupt", + "offset": 30, + "size": 1 + }, + "WKUINT": { + "description": "Resume/remote wakeup detected\n interrupt", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GINTMSK": { + "description": "OTG_HS interrupt mask register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMISM": { + "description": "Mode mismatch interrupt\n mask", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt mask", + "offset": 2, + "size": 1 + }, + "SOFM": { + "description": "Start of frame mask", + "offset": 3, + "size": 1 + }, + "RXFLVLM": { + "description": "Receive FIFO nonempty mask", + "offset": 4, + "size": 1 + }, + "NPTXFEM": { + "description": "Nonperiodic TxFIFO empty\n mask", + "offset": 5, + "size": 1 + }, + "GINAKEFFM": { + "description": "Global nonperiodic IN NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "GONAKEFFM": { + "description": "Global OUT NAK effective\n mask", + "offset": 7, + "size": 1 + }, + "ESUSPM": { + "description": "Early suspend mask", + "offset": 10, + "size": 1 + }, + "USBSUSPM": { + "description": "USB suspend mask", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset mask", + "offset": 12, + "size": 1 + }, + "ENUMDNEM": { + "description": "Enumeration done mask", + "offset": 13, + "size": 1 + }, + "ISOODRPM": { + "description": "Isochronous OUT packet dropped interrupt\n mask", + "offset": 14, + "size": 1 + }, + "EOPFM": { + "description": "End of periodic frame interrupt\n mask", + "offset": 15, + "size": 1 + }, + "EPMISM": { + "description": "Endpoint mismatch interrupt\n mask", + "offset": 17, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoints interrupt\n mask", + "offset": 18, + "size": 1 + }, + "OEPINT": { + "description": "OUT endpoints interrupt\n mask", + "offset": 19, + "size": 1 + }, + "IISOIXFRM": { + "description": "Incomplete isochronous IN transfer\n mask", + "offset": 20, + "size": 1 + }, + "PXFRM_IISOOXFRM": { + "description": "Incomplete periodic transfer\n mask", + "offset": 21, + "size": 1 + }, + "FSUSPM": { + "description": "Data fetch suspended mask", + "offset": 22, + "size": 1 + }, + "PRTIM": { + "description": "Host port interrupt mask", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIM": { + "description": "Host channels interrupt\n mask", + "offset": 25, + "size": 1 + }, + "PTXFEM": { + "description": "Periodic TxFIFO empty mask", + "offset": 26, + "size": 1 + }, + "CIDSCHGM": { + "description": "Connector ID status change\n mask", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected interrupt\n mask", + "offset": 29, + "size": 1 + }, + "SRQIM": { + "description": "Session request/new session detected\n interrupt mask", + "offset": 30, + "size": 1 + }, + "WUIM": { + "description": "Resume/remote wakeup detected interrupt\n mask", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GRXSTSR_Host": { + "description": "OTG_HS Receive status debug read register\n (host mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CHNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "OTG_HS_GRXSTSP_Host": { + "description": "OTG_HS status read and pop register (host\n mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CHNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "OTG_HS_GRXFSIZ": { + "description": "OTG_HS Receive FIFO size\n register", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "RxFIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_GNPTXFSIZ_Host": { + "description": "OTG_HS nonperiodic transmit FIFO size\n register (host mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "NPTXFSA": { + "description": "Nonperiodic transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "NPTXFD": { + "description": "Nonperiodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_TX0FSIZ_Peripheral": { + "description": "Endpoint 0 transmit FIFO size (peripheral\n mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX0FSA": { + "description": "Endpoint 0 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "TX0FD": { + "description": "Endpoint 0 TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_GNPTXSTS": { + "description": "OTG_HS nonperiodic transmit FIFO/queue\n status register", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFSAV": { + "description": "Nonperiodic TxFIFO space\n available", + "offset": 0, + "size": 16 + }, + "NPTQXSAV": { + "description": "Nonperiodic transmit request queue space\n available", + "offset": 16, + "size": 8 + }, + "NPTXQTOP": { + "description": "Top of the nonperiodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "OTG_HS_GCCFG": { + "description": "OTG_HS general core configuration\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRDWN": { + "description": "Power down", + "offset": 16, + "size": 1 + }, + "I2CPADEN": { + "description": "Enable I2C bus connection for the\n external I2C PHY interface", + "offset": 17, + "size": 1 + }, + "VBUSASEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 18, + "size": 1 + }, + "VBUSBSEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 19, + "size": 1 + }, + "SOFOUTEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + }, + "NOVBUSSENS": { + "description": "VBUS sensing disable\n option", + "offset": 21, + "size": 1 + } + } + } + }, + "OTG_HS_CID": { + "description": "OTG_HS core ID register", + "offset": 60, + "size": 32, + "reset_value": 4608, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRODUCT_ID": { + "description": "Product ID field", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HPTXFSIZ": { + "description": "OTG_HS Host periodic transmit FIFO size\n register", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXSA": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "PTXFD": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF1": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF2": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF3": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 284, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF4": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 288, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF5": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 292, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF6": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 296, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF7": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 300, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_GRXSTSR_Peripheral": { + "description": "OTG_HS Receive status debug read register\n (peripheral mode mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "OTG_HS_GRXSTSP_Peripheral": { + "description": "OTG_HS status read and pop register\n (peripheral mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + } + } + } + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "children": { + "registers": { + "POWER": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRCTRL": { + "description": "PWRCTRL", + "offset": 0, + "size": 2 + } + } + } + }, + "CLKCR": { + "description": "SDI clock control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC_EN": { + "description": "HW Flow Control enable", + "offset": 14, + "size": 1 + }, + "NEGEDGE": { + "description": "SDIO_CK dephasing selection\n bit", + "offset": 13, + "size": 1 + }, + "WIDBUS": { + "description": "Wide bus mode enable bit", + "offset": 11, + "size": 2 + }, + "BYPASS": { + "description": "Clock divider bypass enable\n bit", + "offset": 10, + "size": 1 + }, + "PWRSAV": { + "description": "Power saving configuration\n bit", + "offset": 9, + "size": 1 + }, + "CLKEN": { + "description": "Clock enable bit", + "offset": 8, + "size": 1 + }, + "CLKDIV": { + "description": "Clock divide factor", + "offset": 0, + "size": 8 + } + } + } + }, + "ARG": { + "description": "argument register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMDARG": { + "description": "Command argument", + "offset": 0, + "size": 32 + } + } + } + }, + "CMD": { + "description": "command register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CE_ATACMD": { + "description": "CE-ATA command", + "offset": 14, + "size": 1 + }, + "nIEN": { + "description": "not Interrupt Enable", + "offset": 13, + "size": 1 + }, + "ENCMDcompl": { + "description": "Enable CMD completion", + "offset": 12, + "size": 1 + }, + "SDIOSuspend": { + "description": "SD I/O suspend command", + "offset": 11, + "size": 1 + }, + "CPSMEN": { + "description": "Command path state machine (CPSM) Enable\n bit", + "offset": 10, + "size": 1 + }, + "WAITPEND": { + "description": "CPSM Waits for ends of data transfer\n (CmdPend internal signal).", + "offset": 9, + "size": 1 + }, + "WAITINT": { + "description": "CPSM waits for interrupt\n request", + "offset": 8, + "size": 1 + }, + "WAITRESP": { + "description": "Wait for response bits", + "offset": 6, + "size": 2 + }, + "CMDINDEX": { + "description": "Command index", + "offset": 0, + "size": 6 + } + } + } + }, + "RESPCMD": { + "description": "command response register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESPCMD": { + "description": "Response command index", + "offset": 0, + "size": 6 + } + } + } + }, + "RESP1": { + "description": "response 1..4 register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS1": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP2": { + "description": "response 1..4 register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS2": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP3": { + "description": "response 1..4 register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS3": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP4": { + "description": "response 1..4 register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS4": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "DTIMER": { + "description": "data timer register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATATIME": { + "description": "Data timeout period", + "offset": 0, + "size": 32 + } + } + } + }, + "DLEN": { + "description": "data length register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATALENGTH": { + "description": "Data length value", + "offset": 0, + "size": 25 + } + } + } + }, + "DCTRL": { + "description": "data control register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SDIOEN": { + "description": "SD I/O enable functions", + "offset": 11, + "size": 1 + }, + "RWMOD": { + "description": "Read wait mode", + "offset": 10, + "size": 1 + }, + "RWSTOP": { + "description": "Read wait stop", + "offset": 9, + "size": 1 + }, + "RWSTART": { + "description": "Read wait start", + "offset": 8, + "size": 1 + }, + "DBLOCKSIZE": { + "description": "Data block size", + "offset": 4, + "size": 4 + }, + "DMAEN": { + "description": "DMA enable bit", + "offset": 3, + "size": 1 + }, + "DTMODE": { + "description": "Data transfer mode selection 1: Stream\n or SDIO multibyte data transfer.", + "offset": 2, + "size": 1 + }, + "DTDIR": { + "description": "Data transfer direction\n selection", + "offset": 1, + "size": 1 + }, + "DTEN": { + "description": "DTEN", + "offset": 0, + "size": 1 + } + } + } + }, + "DCOUNT": { + "description": "data counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATACOUNT": { + "description": "Data count value", + "offset": 0, + "size": 25 + } + } + } + }, + "STA": { + "description": "status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CEATAEND": { + "description": "CE-ATA command completion signal\n received for CMD61", + "offset": 23, + "size": 1 + }, + "SDIOIT": { + "description": "SDIO interrupt received", + "offset": 22, + "size": 1 + }, + "RXDAVL": { + "description": "Data available in receive\n FIFO", + "offset": 21, + "size": 1 + }, + "TXDAVL": { + "description": "Data available in transmit\n FIFO", + "offset": 20, + "size": 1 + }, + "RXFIFOE": { + "description": "Receive FIFO empty", + "offset": 19, + "size": 1 + }, + "TXFIFOE": { + "description": "Transmit FIFO empty", + "offset": 18, + "size": 1 + }, + "RXFIFOF": { + "description": "Receive FIFO full", + "offset": 17, + "size": 1 + }, + "TXFIFOF": { + "description": "Transmit FIFO full", + "offset": 16, + "size": 1 + }, + "RXFIFOHF": { + "description": "Receive FIFO half full: there are at\n least 8 words in the FIFO", + "offset": 15, + "size": 1 + }, + "TXFIFOHE": { + "description": "Transmit FIFO half empty: at least 8\n words can be written into the FIFO", + "offset": 14, + "size": 1 + }, + "RXACT": { + "description": "Data receive in progress", + "offset": 13, + "size": 1 + }, + "TXACT": { + "description": "Data transmit in progress", + "offset": 12, + "size": 1 + }, + "CMDACT": { + "description": "Command transfer in\n progress", + "offset": 11, + "size": 1 + }, + "DBCKEND": { + "description": "Data block sent/received (CRC check\n passed)", + "offset": 10, + "size": 1 + }, + "STBITERR": { + "description": "Start bit not detected on all data\n signals in wide bus mode", + "offset": 9, + "size": 1 + }, + "DATAEND": { + "description": "Data end (data counter, SDIDCOUNT, is\n zero)", + "offset": 8, + "size": 1 + }, + "CMDSENT": { + "description": "Command sent (no response\n required)", + "offset": 7, + "size": 1 + }, + "CMDREND": { + "description": "Command response received (CRC check\n passed)", + "offset": 6, + "size": 1 + }, + "RXOVERR": { + "description": "Received FIFO overrun\n error", + "offset": 5, + "size": 1 + }, + "TXUNDERR": { + "description": "Transmit FIFO underrun\n error", + "offset": 4, + "size": 1 + }, + "DTIMEOUT": { + "description": "Data timeout", + "offset": 3, + "size": 1 + }, + "CTIMEOUT": { + "description": "Command response timeout", + "offset": 2, + "size": 1 + }, + "DCRCFAIL": { + "description": "Data block sent/received (CRC check\n failed)", + "offset": 1, + "size": 1 + }, + "CCRCFAIL": { + "description": "Command response received (CRC check\n failed)", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "interrupt clear register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEATAENDC": { + "description": "CEATAEND flag clear bit", + "offset": 23, + "size": 1 + }, + "SDIOITC": { + "description": "SDIOIT flag clear bit", + "offset": 22, + "size": 1 + }, + "DBCKENDC": { + "description": "DBCKEND flag clear bit", + "offset": 10, + "size": 1 + }, + "STBITERRC": { + "description": "STBITERR flag clear bit", + "offset": 9, + "size": 1 + }, + "DATAENDC": { + "description": "DATAEND flag clear bit", + "offset": 8, + "size": 1 + }, + "CMDSENTC": { + "description": "CMDSENT flag clear bit", + "offset": 7, + "size": 1 + }, + "CMDRENDC": { + "description": "CMDREND flag clear bit", + "offset": 6, + "size": 1 + }, + "RXOVERRC": { + "description": "RXOVERR flag clear bit", + "offset": 5, + "size": 1 + }, + "TXUNDERRC": { + "description": "TXUNDERR flag clear bit", + "offset": 4, + "size": 1 + }, + "DTIMEOUTC": { + "description": "DTIMEOUT flag clear bit", + "offset": 3, + "size": 1 + }, + "CTIMEOUTC": { + "description": "CTIMEOUT flag clear bit", + "offset": 2, + "size": 1 + }, + "DCRCFAILC": { + "description": "DCRCFAIL flag clear bit", + "offset": 1, + "size": 1 + }, + "CCRCFAILC": { + "description": "CCRCFAIL flag clear bit", + "offset": 0, + "size": 1 + } + } + } + }, + "MASK": { + "description": "mask register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEATAENDIE": { + "description": "CE-ATA command completion signal\n received interrupt enable", + "offset": 23, + "size": 1 + }, + "SDIOITIE": { + "description": "SDIO mode interrupt received interrupt\n enable", + "offset": 22, + "size": 1 + }, + "RXDAVLIE": { + "description": "Data available in Rx FIFO interrupt\n enable", + "offset": 21, + "size": 1 + }, + "TXDAVLIE": { + "description": "Data available in Tx FIFO interrupt\n enable", + "offset": 20, + "size": 1 + }, + "RXFIFOEIE": { + "description": "Rx FIFO empty interrupt\n enable", + "offset": 19, + "size": 1 + }, + "TXFIFOEIE": { + "description": "Tx FIFO empty interrupt\n enable", + "offset": 18, + "size": 1 + }, + "RXFIFOFIE": { + "description": "Rx FIFO full interrupt\n enable", + "offset": 17, + "size": 1 + }, + "TXFIFOFIE": { + "description": "Tx FIFO full interrupt\n enable", + "offset": 16, + "size": 1 + }, + "RXFIFOHFIE": { + "description": "Rx FIFO half full interrupt\n enable", + "offset": 15, + "size": 1 + }, + "TXFIFOHEIE": { + "description": "Tx FIFO half empty interrupt\n enable", + "offset": 14, + "size": 1 + }, + "RXACTIE": { + "description": "Data receive acting interrupt\n enable", + "offset": 13, + "size": 1 + }, + "TXACTIE": { + "description": "Data transmit acting interrupt\n enable", + "offset": 12, + "size": 1 + }, + "CMDACTIE": { + "description": "Command acting interrupt\n enable", + "offset": 11, + "size": 1 + }, + "DBCKENDIE": { + "description": "Data block end interrupt\n enable", + "offset": 10, + "size": 1 + }, + "STBITERRIE": { + "description": "Start bit error interrupt\n enable", + "offset": 9, + "size": 1 + }, + "DATAENDIE": { + "description": "Data end interrupt enable", + "offset": 8, + "size": 1 + }, + "CMDSENTIE": { + "description": "Command sent interrupt\n enable", + "offset": 7, + "size": 1 + }, + "CMDRENDIE": { + "description": "Command response received interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXOVERRIE": { + "description": "Rx FIFO overrun error interrupt\n enable", + "offset": 5, + "size": 1 + }, + "TXUNDERRIE": { + "description": "Tx FIFO underrun error interrupt\n enable", + "offset": 4, + "size": 1 + }, + "DTIMEOUTIE": { + "description": "Data timeout interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CTIMEOUTIE": { + "description": "Command timeout interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DCRCFAILIE": { + "description": "Data CRC fail interrupt\n enable", + "offset": 1, + "size": 1 + }, + "CCRCFAILIE": { + "description": "Command CRC fail interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "FIFOCNT": { + "description": "FIFO counter register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FIFOCOUNT": { + "description": "Remaining number of words to be written\n to or read from the FIFO.", + "offset": 0, + "size": 24 + } + } + } + }, + "FIFO": { + "description": "data FIFO register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FIFOData": { + "description": "Receive and transmit FIFO\n data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "ADC1": { + "description": "Analog-to-digital converter", + "children": { + "registers": { + "SR": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVR": { + "description": "Overrun", + "offset": 5, + "size": 1 + }, + "STRT": { + "description": "Regular channel start flag", + "offset": 4, + "size": 1 + }, + "JSTRT": { + "description": "Injected channel start\n flag", + "offset": 3, + "size": 1 + }, + "JEOC": { + "description": "Injected channel end of\n conversion", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "Regular channel end of\n conversion", + "offset": 1, + "size": 1 + }, + "AWD": { + "description": "Analog watchdog flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CR1": { + "description": "control register 1", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVRIE": { + "description": "Overrun interrupt enable", + "offset": 26, + "size": 1 + }, + "RES": { + "description": "Resolution", + "offset": 24, + "size": 2 + }, + "AWDEN": { + "description": "Analog watchdog enable on regular\n channels", + "offset": 23, + "size": 1 + }, + "JAWDEN": { + "description": "Analog watchdog enable on injected\n channels", + "offset": 22, + "size": 1 + }, + "DISCNUM": { + "description": "Discontinuous mode channel\n count", + "offset": 13, + "size": 3 + }, + "JDISCEN": { + "description": "Discontinuous mode on injected\n channels", + "offset": 12, + "size": 1 + }, + "DISCEN": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "JAUTO": { + "description": "Automatic injected group\n conversion", + "offset": 10, + "size": 1 + }, + "AWDSGL": { + "description": "Enable the watchdog on a single channel\n in scan mode", + "offset": 9, + "size": 1 + }, + "SCAN": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "JEOCIE": { + "description": "Interrupt enable for injected\n channels", + "offset": 7, + "size": 1 + }, + "AWDIE": { + "description": "Analog watchdog interrupt\n enable", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "AWDCH": { + "description": "Analog watchdog channel select\n bits", + "offset": 0, + "size": 5 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWSTART": { + "description": "Start conversion of regular\n channels", + "offset": 30, + "size": 1 + }, + "EXTEN": { + "description": "External trigger enable for regular\n channels", + "offset": 28, + "size": 2 + }, + "EXTSEL": { + "description": "External event select for regular\n group", + "offset": 24, + "size": 4 + }, + "JSWSTART": { + "description": "Start conversion of injected\n channels", + "offset": 22, + "size": 1 + }, + "JEXTEN": { + "description": "External trigger enable for injected\n channels", + "offset": 20, + "size": 2 + }, + "JEXTSEL": { + "description": "External event select for injected\n group", + "offset": 16, + "size": 4 + }, + "ALIGN": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "EOCS": { + "description": "End of conversion\n selection", + "offset": 10, + "size": 1 + }, + "DDS": { + "description": "DMA disable selection (for single ADC\n mode)", + "offset": 9, + "size": 1 + }, + "DMA": { + "description": "Direct memory access mode (for single\n ADC mode)", + "offset": 8, + "size": 1 + }, + "CONT": { + "description": "Continuous conversion", + "offset": 1, + "size": 1 + }, + "ADON": { + "description": "A/D Converter ON / OFF", + "offset": 0, + "size": 1 + } + } + } + }, + "SMPR1": { + "description": "sample time register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMPx_x": { + "description": "Sample time bits", + "offset": 0, + "size": 32 + } + } + } + }, + "SMPR2": { + "description": "sample time register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMPx_x": { + "description": "Sample time bits", + "offset": 0, + "size": 32 + } + } + } + }, + "JOFR1": { + "description": "injected channel data offset register\n x", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET1": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR2": { + "description": "injected channel data offset register\n x", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET2": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR3": { + "description": "injected channel data offset register\n x", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET3": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR4": { + "description": "injected channel data offset register\n x", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET4": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "HTR": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "LTR": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "SQR1": { + "description": "regular sequence register 1", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "L": { + "description": "Regular channel sequence\n length", + "offset": 20, + "size": 4 + }, + "SQ16": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ15": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ14": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ13": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR2": { + "description": "regular sequence register 2", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ12": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ11": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ10": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ9": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ8": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ7": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR3": { + "description": "regular sequence register 3", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ6": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ5": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ4": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ3": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ2": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ1": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JSQR": { + "description": "injected sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JL": { + "description": "Injected sequence length", + "offset": 20, + "size": 2 + }, + "JSQ4": { + "description": "4th conversion in injected\n sequence", + "offset": 15, + "size": 5 + }, + "JSQ3": { + "description": "3rd conversion in injected\n sequence", + "offset": 10, + "size": 5 + }, + "JSQ2": { + "description": "2nd conversion in injected\n sequence", + "offset": 5, + "size": 5 + }, + "JSQ1": { + "description": "1st conversion in injected\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JDR1": { + "description": "injected data register x", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR2": { + "description": "injected data register x", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR3": { + "description": "injected data register x", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR4": { + "description": "injected data register x", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA": { + "description": "Regular data", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "children": { + "registers": { + "IMR": { + "description": "Interrupt mask register\n (EXTI_IMR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Interrupt Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Interrupt Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Interrupt Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Interrupt Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Interrupt Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Interrupt Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Interrupt Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Interrupt Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Interrupt Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Interrupt Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Interrupt Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Interrupt Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Interrupt Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Interrupt Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Interrupt Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Interrupt Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Interrupt Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Interrupt Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Interrupt Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Interrupt Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Interrupt Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Interrupt Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Interrupt Mask on line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "EMR": { + "description": "Event mask register (EXTI_EMR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Event Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Event Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Event Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Event Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Event Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Event Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Event Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Event Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Event Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Event Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Event Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Event Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Event Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Event Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Event Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Event Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Event Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Event Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Event Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Event Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Event Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Event Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Event Mask on line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "RTSR": { + "description": "Rising Trigger selection register\n (EXTI_RTSR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Rising trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Rising trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Rising trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Rising trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Rising trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Rising trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Rising trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Rising trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Rising trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Rising trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Rising trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Rising trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Rising trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Rising trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Rising trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Rising trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Rising trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Rising trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Rising trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Rising trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Rising trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Rising trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Rising trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "FTSR": { + "description": "Falling Trigger selection register\n (EXTI_FTSR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Falling trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Falling trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Falling trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Falling trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Falling trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Falling trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Falling trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Falling trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Falling trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Falling trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Falling trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Falling trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Falling trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Falling trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Falling trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Falling trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Falling trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Falling trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Falling trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Falling trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Falling trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Falling trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Falling trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "SWIER": { + "description": "Software interrupt event register\n (EXTI_SWIER)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIER0": { + "description": "Software Interrupt on line\n 0", + "offset": 0, + "size": 1 + }, + "SWIER1": { + "description": "Software Interrupt on line\n 1", + "offset": 1, + "size": 1 + }, + "SWIER2": { + "description": "Software Interrupt on line\n 2", + "offset": 2, + "size": 1 + }, + "SWIER3": { + "description": "Software Interrupt on line\n 3", + "offset": 3, + "size": 1 + }, + "SWIER4": { + "description": "Software Interrupt on line\n 4", + "offset": 4, + "size": 1 + }, + "SWIER5": { + "description": "Software Interrupt on line\n 5", + "offset": 5, + "size": 1 + }, + "SWIER6": { + "description": "Software Interrupt on line\n 6", + "offset": 6, + "size": 1 + }, + "SWIER7": { + "description": "Software Interrupt on line\n 7", + "offset": 7, + "size": 1 + }, + "SWIER8": { + "description": "Software Interrupt on line\n 8", + "offset": 8, + "size": 1 + }, + "SWIER9": { + "description": "Software Interrupt on line\n 9", + "offset": 9, + "size": 1 + }, + "SWIER10": { + "description": "Software Interrupt on line\n 10", + "offset": 10, + "size": 1 + }, + "SWIER11": { + "description": "Software Interrupt on line\n 11", + "offset": 11, + "size": 1 + }, + "SWIER12": { + "description": "Software Interrupt on line\n 12", + "offset": 12, + "size": 1 + }, + "SWIER13": { + "description": "Software Interrupt on line\n 13", + "offset": 13, + "size": 1 + }, + "SWIER14": { + "description": "Software Interrupt on line\n 14", + "offset": 14, + "size": 1 + }, + "SWIER15": { + "description": "Software Interrupt on line\n 15", + "offset": 15, + "size": 1 + }, + "SWIER16": { + "description": "Software Interrupt on line\n 16", + "offset": 16, + "size": 1 + }, + "SWIER17": { + "description": "Software Interrupt on line\n 17", + "offset": 17, + "size": 1 + }, + "SWIER18": { + "description": "Software Interrupt on line\n 18", + "offset": 18, + "size": 1 + }, + "SWIER19": { + "description": "Software Interrupt on line\n 19", + "offset": 19, + "size": 1 + }, + "SWIER20": { + "description": "Software Interrupt on line\n 20", + "offset": 20, + "size": 1 + }, + "SWIER21": { + "description": "Software Interrupt on line\n 21", + "offset": 21, + "size": 1 + }, + "SWIER22": { + "description": "Software Interrupt on line\n 22", + "offset": 22, + "size": 1 + } + } + } + }, + "PR": { + "description": "Pending register (EXTI_PR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR0": { + "description": "Pending bit 0", + "offset": 0, + "size": 1 + }, + "PR1": { + "description": "Pending bit 1", + "offset": 1, + "size": 1 + }, + "PR2": { + "description": "Pending bit 2", + "offset": 2, + "size": 1 + }, + "PR3": { + "description": "Pending bit 3", + "offset": 3, + "size": 1 + }, + "PR4": { + "description": "Pending bit 4", + "offset": 4, + "size": 1 + }, + "PR5": { + "description": "Pending bit 5", + "offset": 5, + "size": 1 + }, + "PR6": { + "description": "Pending bit 6", + "offset": 6, + "size": 1 + }, + "PR7": { + "description": "Pending bit 7", + "offset": 7, + "size": 1 + }, + "PR8": { + "description": "Pending bit 8", + "offset": 8, + "size": 1 + }, + "PR9": { + "description": "Pending bit 9", + "offset": 9, + "size": 1 + }, + "PR10": { + "description": "Pending bit 10", + "offset": 10, + "size": 1 + }, + "PR11": { + "description": "Pending bit 11", + "offset": 11, + "size": 1 + }, + "PR12": { + "description": "Pending bit 12", + "offset": 12, + "size": 1 + }, + "PR13": { + "description": "Pending bit 13", + "offset": 13, + "size": 1 + }, + "PR14": { + "description": "Pending bit 14", + "offset": 14, + "size": 1 + }, + "PR15": { + "description": "Pending bit 15", + "offset": 15, + "size": 1 + }, + "PR16": { + "description": "Pending bit 16", + "offset": 16, + "size": 1 + }, + "PR17": { + "description": "Pending bit 17", + "offset": 17, + "size": 1 + }, + "PR18": { + "description": "Pending bit 18", + "offset": 18, + "size": 1 + }, + "PR19": { + "description": "Pending bit 19", + "offset": 19, + "size": 1 + }, + "PR20": { + "description": "Pending bit 20", + "offset": 20, + "size": 1 + }, + "PR21": { + "description": "Pending bit 21", + "offset": 21, + "size": 1 + }, + "PR22": { + "description": "Pending bit 22", + "offset": 22, + "size": 1 + } + } + } + } + } + } + }, + "FLASH": { + "description": "FLASH", + "children": { + "registers": { + "ACR": { + "description": "Flash access control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LATENCY": { + "description": "Latency", + "offset": 0, + "size": 3 + }, + "PRFTEN": { + "description": "Prefetch enable", + "offset": 8, + "size": 1 + }, + "ICEN": { + "description": "Instruction cache enable", + "offset": 9, + "size": 1 + }, + "DCEN": { + "description": "Data cache enable", + "offset": 10, + "size": 1 + }, + "ICRST": { + "description": "Instruction cache reset", + "offset": 11, + "size": 1, + "access": "write-only" + }, + "DCRST": { + "description": "Data cache reset", + "offset": 12, + "size": 1 + } + } + } + }, + "KEYR": { + "description": "Flash key register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "FPEC key", + "offset": 0, + "size": 32 + } + } + } + }, + "OPTKEYR": { + "description": "Flash option key register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "OPTKEY": { + "description": "Option byte key", + "offset": 0, + "size": 32 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOP": { + "description": "End of operation", + "offset": 0, + "size": 1 + }, + "OPERR": { + "description": "Operation error", + "offset": 1, + "size": 1 + }, + "WRPERR": { + "description": "Write protection error", + "offset": 4, + "size": 1 + }, + "PGAERR": { + "description": "Programming alignment\n error", + "offset": 5, + "size": 1 + }, + "PGPERR": { + "description": "Programming parallelism\n error", + "offset": 6, + "size": 1 + }, + "PGSERR": { + "description": "Programming sequence error", + "offset": 7, + "size": 1 + }, + "BSY": { + "description": "Busy", + "offset": 16, + "size": 1, + "access": "read-only" + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 16, + "size": 32, + "reset_value": 2147483648, + "reset_mask": 4294967295, + "children": { + "fields": { + "PG": { + "description": "Programming", + "offset": 0, + "size": 1 + }, + "SER": { + "description": "Sector Erase", + "offset": 1, + "size": 1 + }, + "MER": { + "description": "Mass Erase", + "offset": 2, + "size": 1 + }, + "SNB": { + "description": "Sector number", + "offset": 3, + "size": 4 + }, + "PSIZE": { + "description": "Program size", + "offset": 8, + "size": 2 + }, + "STRT": { + "description": "Start", + "offset": 16, + "size": 1 + }, + "EOPIE": { + "description": "End of operation interrupt\n enable", + "offset": 24, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 25, + "size": 1 + }, + "LOCK": { + "description": "Lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPTCR": { + "description": "Flash option control register", + "offset": 20, + "size": 32, + "reset_value": 20, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPTLOCK": { + "description": "Option lock", + "offset": 0, + "size": 1 + }, + "OPTSTRT": { + "description": "Option start", + "offset": 1, + "size": 1 + }, + "BOR_LEV": { + "description": "BOR reset Level", + "offset": 2, + "size": 2 + }, + "WDG_SW": { + "description": "WDG_SW User option bytes", + "offset": 5, + "size": 1 + }, + "nRST_STOP": { + "description": "nRST_STOP User option\n bytes", + "offset": 6, + "size": 1 + }, + "nRST_STDBY": { + "description": "nRST_STDBY User option\n bytes", + "offset": 7, + "size": 1 + }, + "RDP": { + "description": "Read protect", + "offset": 8, + "size": 8 + }, + "nWRP": { + "description": "Not write protect", + "offset": 16, + "size": 12 + } + } + } + } + } + } + }, + "USART6": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "Status register", + "offset": 0, + "size": 32, + "reset_value": 12582912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "CTS flag", + "offset": 9, + "size": 1 + }, + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NF": { + "description": "Noise detected flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "CR1": { + "description": "Control register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVER8": { + "description": "Oversampling mode", + "offset": 15, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "CLKEN": { + "description": "Clock enable", + "offset": 11, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 10, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 9, + "size": 1 + }, + "LBCL": { + "description": "Last bit clock pulse", + "offset": 8, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONEBIT": { + "description": "One sample bit method\n enable", + "offset": 11, + "size": 1 + }, + "CTSIE": { + "description": "CTS interrupt enable", + "offset": 10, + "size": 1 + }, + "CTSE": { + "description": "CTS enable", + "offset": 9, + "size": 1 + }, + "RTSE": { + "description": "RTS enable", + "offset": 8, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "SCEN": { + "description": "Smartcard mode enable", + "offset": 5, + "size": 1 + }, + "NACK": { + "description": "Smartcard NACK enable", + "offset": 4, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GTPR": { + "description": "Guard time and prescaler\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GT": { + "description": "Guard time value", + "offset": 8, + "size": 8 + }, + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TIM6": { + "description": "Basic timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "CAN1": { + "description": "Controller area network", + "children": { + "registers": { + "MCR": { + "description": "master control register", + "offset": 0, + "size": 32, + "reset_value": 65538, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBF": { + "description": "DBF", + "offset": 16, + "size": 1 + }, + "RESET": { + "description": "RESET", + "offset": 15, + "size": 1 + }, + "TTCM": { + "description": "TTCM", + "offset": 7, + "size": 1 + }, + "ABOM": { + "description": "ABOM", + "offset": 6, + "size": 1 + }, + "AWUM": { + "description": "AWUM", + "offset": 5, + "size": 1 + }, + "NART": { + "description": "NART", + "offset": 4, + "size": 1 + }, + "RFLM": { + "description": "RFLM", + "offset": 3, + "size": 1 + }, + "TXFP": { + "description": "TXFP", + "offset": 2, + "size": 1 + }, + "SLEEP": { + "description": "SLEEP", + "offset": 1, + "size": 1 + }, + "INRQ": { + "description": "INRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "MSR": { + "description": "master status register", + "offset": 4, + "size": 32, + "reset_value": 3074, + "reset_mask": 4294967295, + "children": { + "fields": { + "RX": { + "description": "RX", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "SAMP": { + "description": "SAMP", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "RXM": { + "description": "RXM", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "TXM": { + "description": "TXM", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "SLAKI": { + "description": "SLAKI", + "offset": 4, + "size": 1 + }, + "WKUI": { + "description": "WKUI", + "offset": 3, + "size": 1 + }, + "ERRI": { + "description": "ERRI", + "offset": 2, + "size": 1 + }, + "SLAK": { + "description": "SLAK", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "INAK": { + "description": "INAK", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "TSR": { + "description": "transmit status register", + "offset": 8, + "size": 32, + "reset_value": 469762048, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOW2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 31, + "size": 1, + "access": "read-only" + }, + "LOW1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOW0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "TME2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TME1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "TME0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CODE": { + "description": "CODE", + "offset": 24, + "size": 2, + "access": "read-only" + }, + "ABRQ2": { + "description": "ABRQ2", + "offset": 23, + "size": 1 + }, + "TERR2": { + "description": "TERR2", + "offset": 19, + "size": 1 + }, + "ALST2": { + "description": "ALST2", + "offset": 18, + "size": 1 + }, + "TXOK2": { + "description": "TXOK2", + "offset": 17, + "size": 1 + }, + "RQCP2": { + "description": "RQCP2", + "offset": 16, + "size": 1 + }, + "ABRQ1": { + "description": "ABRQ1", + "offset": 15, + "size": 1 + }, + "TERR1": { + "description": "TERR1", + "offset": 11, + "size": 1 + }, + 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+ "size": 1 + }, + "FSC19": { + "description": "Filter scale configuration", + "offset": 19, + "size": 1 + }, + "FSC20": { + "description": "Filter scale configuration", + "offset": 20, + "size": 1 + }, + "FSC21": { + "description": "Filter scale configuration", + "offset": 21, + "size": 1 + }, + "FSC22": { + "description": "Filter scale configuration", + "offset": 22, + "size": 1 + }, + "FSC23": { + "description": "Filter scale configuration", + "offset": 23, + "size": 1 + }, + "FSC24": { + "description": "Filter scale configuration", + "offset": 24, + "size": 1 + }, + "FSC25": { + "description": "Filter scale configuration", + "offset": 25, + "size": 1 + }, + "FSC26": { + "description": "Filter scale configuration", + "offset": 26, + "size": 1 + }, + "FSC27": { + "description": "Filter scale configuration", + "offset": 27, + "size": 1 + } + } + } + }, + "FFA1R": { + "description": "filter FIFO assignment\n register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FFA0": { + "description": "Filter FIFO assignment for filter\n 0", + "offset": 0, + "size": 1 + }, + "FFA1": { + "description": "Filter FIFO assignment for filter\n 1", + "offset": 1, + "size": 1 + }, + "FFA2": { + "description": "Filter FIFO assignment for filter\n 2", + "offset": 2, + "size": 1 + }, + "FFA3": { + "description": "Filter FIFO assignment for filter\n 3", + "offset": 3, + "size": 1 + }, + "FFA4": { + "description": "Filter FIFO assignment for filter\n 4", + "offset": 4, + "size": 1 + }, + "FFA5": { + "description": "Filter FIFO assignment for filter\n 5", + "offset": 5, + "size": 1 + }, + "FFA6": { + "description": "Filter FIFO assignment for filter\n 6", + "offset": 6, + "size": 1 + }, + "FFA7": { + "description": "Filter FIFO assignment for filter\n 7", + "offset": 7, + "size": 1 + }, + "FFA8": { + "description": "Filter FIFO assignment for filter\n 8", + "offset": 8, + "size": 1 + }, + "FFA9": { + "description": "Filter FIFO assignment for filter\n 9", + "offset": 9, + "size": 1 + }, + "FFA10": { + "description": "Filter FIFO assignment for filter\n 10", + "offset": 10, + "size": 1 + }, + "FFA11": { + "description": "Filter FIFO assignment for filter\n 11", + "offset": 11, + "size": 1 + }, + "FFA12": { + "description": "Filter FIFO assignment for filter\n 12", + "offset": 12, + "size": 1 + }, + "FFA13": { + "description": "Filter FIFO assignment for filter\n 13", + "offset": 13, + "size": 1 + }, + "FFA14": { + "description": "Filter FIFO assignment for filter\n 14", + "offset": 14, + "size": 1 + }, + "FFA15": { + "description": "Filter FIFO assignment for filter\n 15", + "offset": 15, + "size": 1 + }, + "FFA16": { + "description": "Filter FIFO assignment for filter\n 16", + "offset": 16, + "size": 1 + }, + "FFA17": { + "description": "Filter FIFO assignment for filter\n 17", + "offset": 17, + "size": 1 + }, + "FFA18": { + "description": "Filter FIFO assignment for filter\n 18", + "offset": 18, + "size": 1 + }, + "FFA19": { + "description": "Filter FIFO assignment for filter\n 19", + "offset": 19, + "size": 1 + }, + "FFA20": { + "description": "Filter FIFO assignment for filter\n 20", + "offset": 20, + "size": 1 + }, + "FFA21": { + "description": "Filter FIFO assignment for filter\n 21", + "offset": 21, + "size": 1 + }, + "FFA22": { + "description": "Filter FIFO assignment for filter\n 22", + "offset": 22, + "size": 1 + }, + "FFA23": { + "description": "Filter FIFO assignment for filter\n 23", + "offset": 23, + "size": 1 + }, + "FFA24": { + "description": "Filter FIFO assignment for filter\n 24", + "offset": 24, + "size": 1 + }, + "FFA25": { + "description": "Filter FIFO assignment for filter\n 25", + "offset": 25, + "size": 1 + }, + "FFA26": { + "description": "Filter FIFO assignment for filter\n 26", + "offset": 26, + "size": 1 + }, + "FFA27": { + "description": "Filter FIFO assignment for filter\n 27", + "offset": 27, + "size": 1 + } + } + } + }, + "FA1R": { + "description": "filter activation register", + "offset": 540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FACT0": { + "description": "Filter active", + "offset": 0, + "size": 1 + }, + "FACT1": { + "description": "Filter active", + "offset": 1, + "size": 1 + }, + "FACT2": { + "description": "Filter active", + "offset": 2, + "size": 1 + }, + "FACT3": { + "description": "Filter active", + "offset": 3, + "size": 1 + }, + "FACT4": { + "description": "Filter active", + "offset": 4, + "size": 1 + }, + "FACT5": { + "description": "Filter active", + "offset": 5, + "size": 1 + }, + "FACT6": { + "description": "Filter active", + "offset": 6, + "size": 1 + }, + "FACT7": { + "description": "Filter active", + "offset": 7, + "size": 1 + }, + "FACT8": { + "description": "Filter active", + "offset": 8, + "size": 1 + }, + "FACT9": { + "description": "Filter active", + "offset": 9, + "size": 1 + }, + "FACT10": { + "description": "Filter active", + "offset": 10, + "size": 1 + }, + "FACT11": { + "description": "Filter active", + "offset": 11, + "size": 1 + }, + "FACT12": { + "description": "Filter active", + "offset": 12, + "size": 1 + }, + "FACT13": { + "description": "Filter active", + "offset": 13, + "size": 1 + }, + "FACT14": { + "description": "Filter active", + "offset": 14, + "size": 1 + }, + "FACT15": { + "description": "Filter active", + "offset": 15, + "size": 1 + }, + "FACT16": { + "description": "Filter active", + "offset": 16, + "size": 1 + }, + "FACT17": { + "description": "Filter active", + "offset": 17, + "size": 1 + }, + "FACT18": { + "description": "Filter active", + "offset": 18, + "size": 1 + }, + "FACT19": { + "description": "Filter active", + "offset": 19, + "size": 1 + }, + "FACT20": { + "description": "Filter active", + "offset": 20, + "size": 1 + }, + "FACT21": { + "description": "Filter active", + "offset": 21, + "size": 1 + }, + "FACT22": { + "description": "Filter active", + "offset": 22, + "size": 1 + }, + "FACT23": { + "description": "Filter active", + "offset": 23, + "size": 1 + }, + "FACT24": { + "description": "Filter active", + "offset": 24, + "size": 1 + }, + "FACT25": { + "description": "Filter active", + "offset": 25, + "size": 1 + }, + "FACT26": { + "description": "Filter active", + "offset": 26, + "size": 1 + }, + "FACT27": { + "description": "Filter active", + "offset": 27, + "size": 1 + } + } + } + }, + "F0R1": { + "description": "Filter bank 0 register 1", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F0R2": { + "description": "Filter bank 0 register 2", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R1": { + "description": "Filter bank 1 register 1", + "offset": 584, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R2": { + "description": "Filter bank 1 register 2", + "offset": 588, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R1": { + "description": "Filter bank 2 register 1", + "offset": 592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R2": { + "description": "Filter bank 2 register 2", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R1": { + "description": "Filter bank 3 register 1", + "offset": 600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R2": { + "description": "Filter bank 3 register 2", + "offset": 604, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R1": { + "description": "Filter bank 4 register 1", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R2": { + "description": "Filter bank 4 register 2", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R1": { + "description": "Filter bank 5 register 1", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R2": { + "description": "Filter bank 5 register 2", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R1": { + "description": "Filter bank 6 register 1", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R2": { + "description": "Filter bank 6 register 2", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R1": { + "description": "Filter bank 7 register 1", + "offset": 632, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R2": { + "description": "Filter bank 7 register 2", + "offset": 636, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter 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"offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R2": { + "description": "Filter bank 8 register 2", + "offset": 644, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter 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"description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": 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"description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R1": { + "description": "Filter bank 10 register 1", + "offset": 656, + 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"FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R2": { + "description": "Filter bank 10 register 2", + "offset": 660, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R1": { + "description": "Filter bank 11 register 1", + "offset": 664, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R2": { + "description": "Filter bank 11 register 2", + "offset": 668, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R1": { + "description": "Filter bank 4 register 1", + "offset": 672, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R2": { + "description": "Filter bank 12 register 2", + "offset": 676, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R1": { + "description": "Filter bank 13 register 1", + "offset": 680, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R2": { + "description": "Filter bank 13 register 2", + "offset": 684, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R1": { + "description": "Filter bank 14 register 1", + "offset": 688, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R2": { + "description": "Filter bank 14 register 2", + "offset": 692, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R1": { + "description": "Filter bank 15 register 1", + "offset": 696, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R2": { + "description": "Filter bank 15 register 2", + "offset": 700, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R1": { + "description": "Filter bank 16 register 1", + "offset": 704, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R2": { + "description": "Filter bank 16 register 2", + "offset": 708, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R1": { + "description": "Filter bank 17 register 1", + "offset": 712, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R2": { + "description": "Filter bank 17 register 2", + "offset": 716, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R1": { + "description": "Filter bank 18 register 1", + "offset": 720, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R2": { + "description": "Filter bank 18 register 2", + "offset": 724, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R1": { + "description": "Filter bank 19 register 1", + "offset": 728, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R2": { + "description": "Filter bank 19 register 2", + "offset": 732, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R1": { + "description": "Filter bank 20 register 1", + "offset": 736, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R2": { + "description": "Filter bank 20 register 2", + "offset": 740, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R1": { + "description": "Filter bank 21 register 1", + "offset": 744, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R2": { + "description": "Filter bank 21 register 2", + "offset": 748, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R1": { + "description": "Filter bank 22 register 1", + "offset": 752, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R2": { + "description": "Filter bank 22 register 2", + "offset": 756, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R1": { + "description": "Filter bank 23 register 1", + "offset": 760, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R2": { + "description": "Filter bank 23 register 2", + "offset": 764, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R1": { + "description": "Filter bank 24 register 1", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R2": { + "description": "Filter bank 24 register 2", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R1": { + "description": "Filter bank 25 register 1", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R2": { + "description": "Filter bank 25 register 2", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R1": { + "description": "Filter bank 26 register 1", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R2": { + "description": "Filter bank 26 register 2", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R1": { + "description": "Filter bank 27 register 1", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R2": { + "description": "Filter bank 27 register 2", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_PCGCCTL": { + "description": "OTG_FS power and clock gating control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPPCLK": { + "description": "Stop PHY clock", + "offset": 0, + "size": 1 + }, + "GATEHCLK": { + "description": "Gate HCLK", + "offset": 1, + "size": 1 + }, + "PHYSUSP": { + "description": "PHY Suspended", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "DAC": { + "description": "Digital-to-analog converter", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDRIE2": { + "description": "DAC channel2 DMA underrun interrupt\n enable", + "offset": 29, + "size": 1 + }, + "DMAEN2": { + "description": "DAC channel2 DMA enable", + "offset": 28, + "size": 1 + }, + "MAMP2": { + "description": "DAC channel2 mask/amplitude\n selector", + "offset": 24, + "size": 4 + }, + "WAVE2": { + "description": "DAC channel2 noise/triangle wave\n generation enable", + "offset": 22, + "size": 2 + }, + "TSEL2": { + "description": "DAC channel2 trigger\n selection", + "offset": 19, + "size": 3 + }, + "TEN2": { + "description": "DAC channel2 trigger\n enable", + "offset": 18, + "size": 1 + }, + "BOFF2": { + "description": "DAC channel2 output buffer\n disable", + "offset": 17, + "size": 1 + }, + "EN2": { + "description": "DAC channel2 enable", + "offset": 16, + "size": 1 + }, + "DMAUDRIE1": { + "description": "DAC channel1 DMA Underrun Interrupt\n enable", + "offset": 13, + "size": 1 + }, + "DMAEN1": { + "description": "DAC channel1 DMA enable", + "offset": 12, + "size": 1 + }, + "MAMP1": { + "description": "DAC channel1 mask/amplitude\n selector", + "offset": 8, + "size": 4 + }, + "WAVE1": { + "description": "DAC channel1 noise/triangle wave\n generation enable", + "offset": 6, + "size": 2 + }, + "TSEL1": { + "description": "DAC channel1 trigger\n selection", + "offset": 3, + "size": 3 + }, + "TEN1": { + "description": "DAC channel1 trigger\n enable", + "offset": 2, + "size": 1 + }, + "BOFF1": { + "description": "DAC channel1 output buffer\n disable", + "offset": 1, + "size": 1 + }, + "EN1": { + "description": "DAC channel1 enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SWTRIGR": { + "description": "software trigger register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SWTRIG2": { + "description": "DAC channel2 software\n trigger", + "offset": 1, + "size": 1 + }, + "SWTRIG1": { + "description": "DAC channel1 software\n trigger", + "offset": 0, + "size": 1 + } + } + } + }, + "DHR12R1": { + "description": "channel1 12-bit right-aligned data holding\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L1": { + "description": "channel1 12-bit left aligned data holding\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R1": { + "description": "channel1 8-bit right aligned data holding\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12R2": { + "description": "channel2 12-bit right aligned data holding\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L2": { + "description": "channel2 12-bit left aligned data holding\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R2": { + "description": "channel2 8-bit right-aligned data holding\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12RD": { + "description": "Dual DAC 12-bit right-aligned data holding\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 16, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12LD": { + "description": "DUAL DAC 12-bit left aligned data holding\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 20, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8RD": { + "description": "DUAL DAC 8-bit right aligned data holding\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 8, + "size": 8 + }, + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DOR1": { + "description": "channel1 data output register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC1DOR": { + "description": "DAC channel1 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "DOR2": { + "description": "channel2 data output register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC2DOR": { + "description": "DAC channel2 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDR2": { + "description": "DAC channel2 DMA underrun\n flag", + "offset": 29, + "size": 1 + }, + "DMAUDR1": { + "description": "DAC channel1 DMA underrun\n flag", + "offset": 13, + "size": 1 + } + } + } + } + } + } + }, + "PWR": { + "description": "Power control", + "children": { + "registers": { + "CR": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FPDS": { + "description": "Flash power down in Stop\n mode", + "offset": 9, + "size": 1 + }, + "DBP": { + "description": "Disable backup domain write\n protection", + "offset": 8, + "size": 1 + }, + "PLS": { + "description": "PVD level selection", + "offset": 5, + "size": 3 + }, + "PVDE": { + "description": "Power voltage detector\n enable", + "offset": 4, + "size": 1 + }, + "CSBF": { + "description": "Clear standby flag", + "offset": 3, + "size": 1 + }, + "CWUF": { + "description": "Clear wakeup flag", + "offset": 2, + "size": 1 + }, + "PDDS": { + "description": "Power down deepsleep", + "offset": 1, + "size": 1 + }, + "LPDS": { + "description": "Low-power deep sleep", + "offset": 0, + "size": 1 + } + } + } + }, + "CSR": { + "description": "power control/status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUF": { + "description": "Wakeup flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SBF": { + "description": "Standby flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PVDO": { + "description": "PVD output", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "BRR": { + "description": "Backup regulator ready", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "EWUP": { + "description": "Enable WKUP pin", + "offset": 8, + "size": 1 + }, + "BRE": { + "description": "Backup regulator enable", + "offset": 9, + "size": 1 + }, + "VOSRDY": { + "description": "Regulator voltage scaling output\n selection ready bit", + "offset": 14, + "size": 1 + } + } + } + } + } + } + }, + "I2C3": { + "description": "Inter-integrated circuit", + "children": { + "registers": { + "CR1": { + "description": "Control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWRST": { + "description": "Software reset", + "offset": 15, + "size": 1 + }, + "ALERT": { + "description": "SMBus alert", + "offset": 13, + "size": 1 + }, + "PEC": { + "description": "Packet error checking", + "offset": 12, + "size": 1 + }, + "POS": { + "description": "Acknowledge/PEC Position (for data\n reception)", + "offset": 11, + "size": 1 + }, + "ACK": { + "description": "Acknowledge enable", + "offset": 10, + "size": 1 + }, + "STOP": { + "description": "Stop generation", + "offset": 9, + "size": 1 + }, + "START": { + "description": "Start generation", + "offset": 8, + "size": 1 + }, + "NOSTRETCH": { + "description": "Clock stretching disable (Slave\n mode)", + "offset": 7, + "size": 1 + }, + "ENGC": { + "description": "General call enable", + "offset": 6, + "size": 1 + }, + "ENPEC": { + "description": "PEC enable", + "offset": 5, + "size": 1 + }, + "ENARP": { + "description": "ARP enable", + "offset": 4, + "size": 1 + }, + "SMBTYPE": { + "description": "SMBus type", + "offset": 3, + "size": 1 + }, + "SMBUS": { + "description": "SMBus mode", + "offset": 1, + "size": 1 + }, + "PE": { + "description": "Peripheral enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LAST": { + "description": "DMA last transfer", + "offset": 12, + "size": 1 + }, + "DMAEN": { + "description": "DMA requests enable", + "offset": 11, + "size": 1 + }, + "ITBUFEN": { + "description": "Buffer interrupt enable", + "offset": 10, + "size": 1 + }, + "ITEVTEN": { + "description": "Event interrupt enable", + "offset": 9, + "size": 1 + }, + "ITERREN": { + "description": "Error interrupt enable", + "offset": 8, + "size": 1 + }, + "FREQ": { + "description": "Peripheral clock frequency", + "offset": 0, + "size": 6 + } + } + } + }, + "OAR1": { + "description": "Own address register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDMODE": { + "description": "Addressing mode (slave\n mode)", + "offset": 15, + "size": 1 + }, + "ADD10": { + "description": "Interface address", + "offset": 8, + "size": 2 + }, + "ADD7": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ADD0": { + "description": "Interface address", + "offset": 0, + "size": 1 + } + } + } + }, + "OAR2": { + "description": "Own address register 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD2": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ENDUAL": { + "description": "Dual addressing mode\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "8-bit data register", + "offset": 0, + "size": 8 + } + } + } + }, + "SR1": { + "description": "Status register 1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMBALERT": { + "description": "SMBus alert", + "offset": 15, + "size": 1 + }, + "TIMEOUT": { + "description": "Timeout or Tlow error", + "offset": 14, + "size": 1 + }, + "PECERR": { + "description": "PEC Error in reception", + "offset": 12, + "size": 1 + }, + "OVR": { + "description": "Overrun/Underrun", + "offset": 11, + "size": 1 + }, + "AF": { + "description": "Acknowledge failure", + "offset": 10, + "size": 1 + }, + "ARLO": { + "description": "Arbitration lost (master\n mode)", + "offset": 9, + "size": 1 + }, + "BERR": { + "description": "Bus error", + "offset": 8, + "size": 1 + }, + "TxE": { + "description": "Data register empty\n (transmitters)", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "RxNE": { + "description": "Data register not empty\n (receivers)", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "STOPF": { + "description": "Stop detection (slave\n mode)", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ADD10": { + "description": "10-bit header sent (Master\n mode)", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "BTF": { + "description": "Byte transfer finished", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ADDR": { + "description": "Address sent (master mode)/matched\n (slave mode)", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "SB": { + "description": "Start bit (Master mode)", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "SR2": { + "description": "Status register 2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PEC": { + "description": "acket error checking\n register", + "offset": 8, + "size": 8 + }, + "DUALF": { + "description": "Dual flag (Slave mode)", + "offset": 7, + "size": 1 + }, + "SMBHOST": { + "description": "SMBus host header (Slave\n mode)", + "offset": 6, + "size": 1 + }, + "SMBDEFAULT": { + "description": "SMBus device default address (Slave\n mode)", + "offset": 5, + "size": 1 + }, + "GENCALL": { + "description": "General call address (Slave\n mode)", + "offset": 4, + "size": 1 + }, + "TRA": { + "description": "Transmitter/receiver", + "offset": 2, + "size": 1 + }, + "BUSY": { + "description": "Bus busy", + "offset": 1, + "size": 1 + }, + "MSL": { + "description": "Master/slave", + "offset": 0, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Clock control register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "F_S": { + "description": "I2C master mode selection", + "offset": 15, + "size": 1 + }, + "DUTY": { + "description": "Fast mode duty cycle", + "offset": 14, + "size": 1 + }, + "CCR": { + "description": "Clock control register in Fast/Standard\n mode (Master mode)", + "offset": 0, + "size": 12 + } + } + } + }, + "TRISE": { + "description": "TRISE register", + "offset": 32, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRISE": { + "description": "Maximum rise time in Fast/Standard mode\n (Master mode)", + "offset": 0, + "size": 6 + } + } + } + } + } + } + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_DCFG": { + "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)", + "offset": 0, + "size": 32, + "reset_value": 35651584, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSPD": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOHSK": { + "description": "Non-zero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAD": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "PFIVL": { + "description": "Periodic frame interval", + "offset": 11, + "size": 2 + } + } + } + }, + "FS_DCTL": { + "description": "OTG_FS device control register\n (OTG_FS_DCTL)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWUSIG": { + "description": "Remote wakeup signaling", + "offset": 0, + "size": 1 + }, + "SDIS": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINSTS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONSTS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "TCTL": { + "description": "Test control", + "offset": 4, + "size": 3 + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1 + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1 + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1 + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1 + }, + "POPRGDNE": { + "description": "Power-on programming done", + "offset": 11, + "size": 1 + } + } + } + }, + "FS_DSTS": { + "description": "OTG_FS device status register\n (OTG_FS_DSTS)", + "offset": 8, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SUSPSTS": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ENUMSPD": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "EERR": { + "description": "Erratic error", + "offset": 3, + "size": 1 + }, + "FNSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "FS_DIEPMSK": { + "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (Non-isochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + } + } + } + }, + "FS_DOEPMSK": { + "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "STUPM": { + "description": "SETUP phase done mask", + "offset": 3, + "size": 1 + }, + "OTEPDM": { + "description": "OUT token received when endpoint\n disabled mask", + "offset": 4, + "size": 1 + } + } + } + }, + "FS_DAINT": { + "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPINT": { + "description": "IN endpoint interrupt bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DAINTMSK": { + "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPM": { + "description": "IN EP interrupt mask bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "DVBUSDIS": { + "description": "OTG_FS device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "DVBUSPULSE": { + "description": "OTG_FS device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSP": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "DIEPEMPMSK": { + "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXFEM": { + "description": "IN EP Tx FIFO empty interrupt mask\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_DIEPCTL0": { + "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 2 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "DIEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM_SD1PID": { + "description": "SODDFRM/SD1PID", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL0": { + "description": "device endpoint-0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "DOEPCTL1": { + "description": "device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL2": { + "description": "device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL3": { + "description": "device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPINT0": { + "description": "device endpoint-x interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT0": { + "description": "device endpoint-0 interrupt\n register", + "offset": 776, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 808, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 840, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 872, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPTSIZ0": { + "description": "device endpoint-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DOEPTSIZ0": { + "description": "device OUT endpoint-0 transfer size\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STUPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DIEPTSIZ1": { + "description": "device endpoint-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ2": { + "description": "device endpoint-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ3": { + "description": "device endpoint-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DTXFSTS0": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS1": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS2": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS3": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DOEPTSIZ1": { + "description": "device OUT endpoint-1 transfer size\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ2": { + "description": "device OUT endpoint-2 transfer size\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ3": { + "description": "device OUT endpoint-3 transfer size\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + } + } + } + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_HCFG": { + "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSLSPCS": { + "description": "FS/LS PHY clock select", + "offset": 0, + "size": 2 + }, + "FSLSS": { + "description": "FS- and LS-only support", + "offset": 2, + "size": 1, + "access": "read-only" + } + } + } + }, + "HFIR": { + "description": "OTG_FS Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 60000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRIVL": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HFNUM": { + "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)", + "offset": 8, + "size": 32, + "reset_value": 16383, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FTREM": { + "description": "Frame time remaining", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_HPTXSTS": { + "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)", + "offset": 16, + "size": 32, + "reset_value": 524544, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFSAVL": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16 + }, + "PTXQSAV": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXQTOP": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "HAINT": { + "description": "OTG_FS Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HAINT": { + "description": "Channel interrupts", + "offset": 0, + "size": 16 + } + } + } + }, + "HAINTMSK": { + "description": "OTG_FS host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HAINTM": { + "description": "Channel interrupt mask", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HPRT": { + "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCSTS": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCDET": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PENA": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PENCHNG": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "POCA": { + "description": "Port overcurrent active", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "POCCHNG": { + "description": "Port overcurrent change", + "offset": 5, + "size": 1 + }, + "PRES": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSUSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLSTS": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PPWR": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PTCTL": { + "description": "Port test control", + "offset": 13, + "size": 4 + }, + "PSPD": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "FS_HCCHAR0": { + "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR1": { + "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR2": { + "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR3": { + "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR4": { + "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR5": { + "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR6": { + "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR7": { + "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCINT0": { + "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT1": { + "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT2": { + "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT3": { + "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT4": { + "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT5": { + "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT6": { + "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT7": { + "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK0": { + "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK1": { + "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK2": { + "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK3": { + "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK4": { + "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK5": { + "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK6": { + "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK7": { + "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCTSIZ0": { + "description": "OTG_FS host channel-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ1": { + "description": "OTG_FS host channel-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ2": { + "description": "OTG_FS host channel-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ3": { + "description": "OTG_FS host channel-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ4": { + "description": "OTG_FS host channel-x transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ5": { + "description": "OTG_FS host channel-5 transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ6": { + "description": "OTG_FS host channel-6 transfer size\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ7": { + "description": "OTG_FS host channel-7 transfer size\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "IWDG": { + "description": "Independent watchdog", + "children": { + "registers": { + "KR": { + "description": "Key register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Key value (write only, read\n 0000h)", + "offset": 0, + "size": 16 + } + } + } + }, + "PR": { + "description": "Prescaler register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR": { + "description": "Prescaler divider", + "offset": 0, + "size": 3 + } + } + } + }, + "RLR": { + "description": "Reload register", + "offset": 8, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Watchdog counter reload\n value", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RVU": { + "description": "Watchdog counter reload value\n update", + "offset": 1, + "size": 1 + }, + "PVU": { + "description": "Watchdog prescaler value\n update", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "WWDG": { + "description": "Window watchdog", + "children": { + "registers": { + "CR": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDGA": { + "description": "Activation bit", + "offset": 7, + "size": 1 + }, + "T": { + "description": "7-bit counter (MSB to LSB)", + "offset": 0, + "size": 7 + } + } + } + }, + "CFR": { + "description": "Configuration register", + "offset": 4, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWI": { + "description": "Early wakeup interrupt", + "offset": 9, + "size": 1 + }, + "WDGTB1": { + "description": "Timer base", + "offset": 8, + "size": 1 + }, + "WDGTB0": { + "description": "Timer base", + "offset": 7, + "size": 1 + }, + "W": { + "description": "7-bit window value", + "offset": 0, + "size": 7 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWIF": { + "description": "Early wakeup interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "RTC": { + "description": "Real-time clock", + "children": { + "registers": { + "TR": { + "description": "time register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "DR": { + "description": "date register", + "offset": 4, + "size": 32, + "reset_value": 8449, + "reset_mask": 4294967295, + "children": { + "fields": { + "YT": { + "description": "Year tens in BCD format", + "offset": 20, + "size": 4 + }, + "YU": { + "description": "Year units in BCD format", + "offset": 16, + "size": 4 + }, + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "CR": { + "description": "control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COE": { + "description": "Calibration output enable", + "offset": 23, + "size": 1 + }, + "OSEL": { + "description": "Output selection", + "offset": 21, + "size": 2 + }, + "POL": { + "description": "Output polarity", + "offset": 20, + "size": 1 + }, + "BKP": { + "description": "Backup", + "offset": 18, + "size": 1 + }, + "SUB1H": { + "description": "Subtract 1 hour (winter time\n change)", + "offset": 17, + "size": 1 + }, + "ADD1H": { + "description": "Add 1 hour (summer time\n change)", + "offset": 16, + "size": 1 + }, + "TSIE": { + "description": "Time-stamp interrupt\n enable", + "offset": 15, + "size": 1 + }, + "WUTIE": { + "description": "Wakeup timer interrupt\n enable", + "offset": 14, + "size": 1 + }, + "ALRBIE": { + "description": "Alarm B interrupt enable", + "offset": 13, + "size": 1 + }, + "ALRAIE": { + "description": "Alarm A interrupt enable", + "offset": 12, + "size": 1 + }, + "TSE": { + "description": "Time stamp enable", + "offset": 11, + "size": 1 + }, + "WUTE": { + "description": "Wakeup timer enable", + "offset": 10, + "size": 1 + }, + "ALRBE": { + "description": "Alarm B enable", + "offset": 9, + "size": 1 + }, + "ALRAE": { + "description": "Alarm A enable", + "offset": 8, + "size": 1 + }, + "DCE": { + "description": "Coarse digital calibration\n enable", + "offset": 7, + "size": 1 + }, + "FMT": { + "description": "Hour format", + "offset": 6, + "size": 1 + }, + "REFCKON": { + "description": "Reference clock detection enable (50 or\n 60 Hz)", + "offset": 4, + "size": 1 + }, + "TSEDGE": { + "description": "Time-stamp event active\n edge", + "offset": 3, + "size": 1 + }, + "WCKSEL": { + "description": "Wakeup clock selection", + "offset": 0, + "size": 3 + } + } + } + }, + "ISR": { + "description": "initialization and status\n register", + "offset": 12, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALRAWF": { + "description": "Alarm A write flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "ALRBWF": { + "description": "Alarm B write flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "WUTWF": { + "description": "Wakeup timer write flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SHPF": { + "description": "Shift operation pending", + "offset": 3, + "size": 1 + }, + "INITS": { + "description": "Initialization status flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "RSF": { + "description": "Registers synchronization\n flag", + "offset": 5, + "size": 1 + }, + "INITF": { + "description": "Initialization flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "INIT": { + "description": "Initialization mode", + "offset": 7, + "size": 1 + }, + "ALRAF": { + "description": "Alarm A flag", + "offset": 8, + "size": 1 + }, + "ALRBF": { + "description": "Alarm B flag", + "offset": 9, + "size": 1 + }, + "WUTF": { + "description": "Wakeup timer flag", + "offset": 10, + "size": 1 + }, + "TSF": { + "description": "Time-stamp flag", + "offset": 11, + "size": 1 + }, + "TSOVF": { + "description": "Time-stamp overflow flag", + "offset": 12, + "size": 1 + }, + "TAMP1F": { + "description": "Tamper detection flag", + "offset": 13, + "size": 1 + }, + "TAMP2F": { + "description": "TAMPER2 detection flag", + "offset": 14, + "size": 1 + }, + "RECALPF": { + "description": "Recalibration pending Flag", + "offset": 16, + "size": 1, + "access": "read-only" + } + } + } + }, + "PRER": { + "description": "prescaler register", + "offset": 16, + "size": 32, + "reset_value": 8323327, + "reset_mask": 4294967295, + "children": { + "fields": { + "PREDIV_A": { + "description": "Asynchronous prescaler\n factor", + "offset": 16, + "size": 7 + }, + "PREDIV_S": { + "description": "Synchronous prescaler\n factor", + "offset": 0, + "size": 15 + } + } + } + }, + "WUTR": { + "description": "wakeup timer register", + "offset": 20, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUT": { + "description": "Wakeup auto-reload value\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "CALIBR": { + "description": "calibration register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCS": { + "description": "Digital calibration sign", + "offset": 7, + "size": 1 + }, + "DC": { + "description": "Digital calibration", + "offset": 0, + "size": 5 + } + } + } + }, + "ALRMAR": { + "description": "alarm A register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm A date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm A hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm A minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm A seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "ALRMBR": { + "description": "alarm B register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm B date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm B hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm B minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm B seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "WPR": { + "description": "write protection register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Write protection key", + "offset": 0, + "size": 8 + } + } + } + }, + "SSR": { + "description": "sub second register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "SHIFTR": { + "description": "shift control register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ADD1S": { + "description": "Add one second", + "offset": 31, + "size": 1 + }, + "SUBFS": { + "description": "Subtract a fraction of a\n second", + "offset": 0, + "size": 15 + } + } + } + }, + "TSTR": { + "description": "time stamp time register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ALARMOUTTYPE": { + "description": "AFO_ALARM output type", + "offset": 18, + "size": 1 + }, + "TSINSEL": { + "description": "TIMESTAMP mapping", + "offset": 17, + "size": 1 + }, + "TAMP1INSEL": { + "description": "TAMPER1 mapping", + "offset": 16, + "size": 1 + }, + "TAMPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TAMP1TRG": { + "description": "Active level for tamper 1", + "offset": 1, + "size": 1 + }, + "TAMP1E": { + "description": "Tamper 1 detection enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TSDR": { + "description": "time stamp date register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "TSSSR": { + "description": "timestamp sub second register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "CALR": { + "description": "calibration register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CALP": { + "description": "Increase frequency of RTC by 488.5\n ppm", + "offset": 15, + "size": 1 + }, + "CALW8": { + "description": "Use an 8-second calibration cycle\n period", + "offset": 14, + "size": 1 + }, + "CALW16": { + "description": "Use a 16-second calibration cycle\n period", + "offset": 13, + "size": 1 + }, + "CALM": { + "description": "Calibration minus", + "offset": 0, + "size": 9 + } + } + } + }, + "TAFCR": { + "description": "tamper and alternate function configuration\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALARMOUTTYPE": { + "description": "AFO_ALARM output type", + "offset": 18, + "size": 1 + }, + "TSINSEL": { + "description": "TIMESTAMP mapping", + "offset": 17, + "size": 1 + }, + "TAMP1INSEL": { + "description": "TAMPER1 mapping", + "offset": 16, + "size": 1 + }, + "TAMPPUDIS": { + "description": "TAMPER pull-up disable", + "offset": 15, + "size": 1 + }, + "TAMPPRCH": { + "description": "Tamper precharge duration", + "offset": 13, + "size": 2 + }, + "TAMPFLT": { + "description": "Tamper filter count", + "offset": 11, + "size": 2 + }, + "TAMPFREQ": { + "description": "Tamper sampling frequency", + "offset": 8, + "size": 3 + }, + "TAMPTS": { + "description": "Activate timestamp on tamper detection\n event", + "offset": 7, + "size": 1 + }, + "TAMP2TRG": { + "description": "Active level for tamper 2", + "offset": 4, + "size": 1 + }, + "TAMP2E": { + "description": "Tamper 2 detection enable", + "offset": 3, + "size": 1 + }, + "TAMPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TAMP1TRG": { + "description": "Active level for tamper 1", + "offset": 1, + "size": 1 + }, + "TAMP1E": { + "description": "Tamper 1 detection enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ALRMASSR": { + "description": "alarm A sub second register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "ALRMBSSR": { + "description": "alarm B sub second register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "BKP0R": { + "description": "backup register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP1R": { + "description": "backup register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP2R": { + "description": "backup register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP3R": { + "description": "backup register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP4R": { + "description": "backup register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP5R": { + "description": "backup register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP6R": { + "description": "backup register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP7R": { + "description": "backup register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP8R": { + "description": "backup register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP9R": { + "description": "backup register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP10R": { + "description": "backup register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP11R": { + "description": "backup register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP12R": { + "description": "backup register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP13R": { + "description": "backup register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP14R": { + "description": "backup register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP15R": { + "description": "backup register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP16R": { + "description": "backup register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP17R": { + "description": "backup register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP18R": { + "description": "backup register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP19R": { + "description": "backup register", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "UART4": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "Status register", + "offset": 0, + "size": 32, + "reset_value": 12582912, + "reset_mask": 4294967295, + "children": { + "fields": { + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NF": { + "description": "Noise detected flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "CR1": { + "description": "Control register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVER8": { + "description": "Oversampling mode", + "offset": 15, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONEBIT": { + "description": "One sample bit method\n enable", + "offset": 11, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_GOTGCTL": { + "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRQSCS": { + "description": "Session request success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRQ": { + "description": "Session request", + "offset": 1, + "size": 1 + }, + "HNGSCS": { + "description": "Host negotiation success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPRQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HSHNPEN": { + "description": "Host set HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "CIDSTS": { + "description": "Connector ID status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DBCT": { + "description": "Long/short debounce time", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASVLD": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSVLD": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GOTGINT": { + "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEDET": { + "description": "Session end detected", + "offset": 2, + "size": 1 + }, + "SRSSCHG": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNSSCHG": { + "description": "Host negotiation success status\n change", + "offset": 9, + "size": 1 + }, + "HNGDET": { + "description": "Host negotiation detected", + "offset": 17, + "size": 1 + }, + "ADTOCHG": { + "description": "A-device timeout change", + "offset": 18, + "size": 1 + }, + "DBCDNE": { + "description": "Debounce done", + "offset": 19, + "size": 1 + } + } + } + }, + "FS_GAHBCFG": { + "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINT": { + "description": "Global interrupt mask", + "offset": 0, + "size": 1 + }, + "TXFELVL": { + "description": "TxFIFO empty level", + "offset": 7, + "size": 1 + }, + "PTXFELVL": { + "description": "Periodic TxFIFO empty\n level", + "offset": 8, + "size": 1 + } + } + } + }, + "FS_GUSBCFG": { + "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)", + "offset": 12, + "size": 32, + "reset_value": 2560, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOCAL": { + "description": "FS timeout calibration", + "offset": 0, + "size": 3 + }, + "PHYSEL": { + "description": "Full Speed serial transceiver\n select", + "offset": 6, + "size": 1, + "access": "write-only" + }, + "SRPCAP": { + "description": "SRP-capable", + "offset": 8, + "size": 1 + }, + "HNPCAP": { + "description": "HNP-capable", + "offset": 9, + "size": 1 + }, + "TRDT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "FHMOD": { + "description": "Force host mode", + "offset": 29, + "size": 1 + }, + "FDMOD": { + "description": "Force device mode", + "offset": 30, + "size": 1 + }, + "CTXPKT": { + "description": "Corrupt Tx packet", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRSTCTL": { + "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)", + "offset": 16, + "size": 32, + "reset_value": 536870912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "FCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFFLSH": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFFLSH": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + }, + "AHBIDL": { + "description": "AHB master idle", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GINTSTS": { + "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)", + "offset": 20, + "size": 32, + "reset_value": 67108896, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMOD": { + "description": "Current mode of operation", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MMIS": { + "description": "Mode mismatch interrupt", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFLVL": { + "description": "RxFIFO non-empty", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFE": { + "description": "Non-periodic TxFIFO empty", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GINAKEFF": { + "description": "Global IN non-periodic NAK\n effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "GOUTNAKEFF": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESUSP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "USBSUSP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMDNE": { + "description": "Enumeration done", + "offset": 13, + "size": 1 + }, + "ISOODRP": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPF": { + "description": "End of periodic frame\n interrupt", + "offset": 15, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoint interrupt", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPINT": { + "description": "OUT endpoint interrupt", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "IISOIXFR": { + "description": "Incomplete isochronous IN\n transfer", + "offset": 20, + "size": 1 + }, + "IPXFR_INCOMPISOOUT": { + "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)", + "offset": 21, + "size": 1 + }, + "HPRTINT": { + "description": "Host port interrupt", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCINT": { + "description": "Host channels interrupt", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFE": { + "description": "Periodic TxFIFO empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CIDSCHG": { + "description": "Connector ID status change", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected\n interrupt", + "offset": 29, + "size": 1 + }, + "SRQINT": { + "description": "Session request/new session detected\n interrupt", + "offset": 30, + "size": 1 + }, + "WKUPINT": { + "description": "Resume/remote wakeup detected\n interrupt", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GINTMSK": { + "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMISM": { + "description": "Mode mismatch interrupt\n mask", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt mask", + "offset": 2, + "size": 1 + }, + "SOFM": { + "description": "Start of frame mask", + "offset": 3, + "size": 1 + }, + "RXFLVLM": { + "description": "Receive FIFO non-empty\n mask", + "offset": 4, + "size": 1 + }, + "NPTXFEM": { + "description": "Non-periodic TxFIFO empty\n mask", + "offset": 5, + "size": 1 + }, + "GINAKEFFM": { + "description": "Global non-periodic IN NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "GONAKEFFM": { + "description": "Global OUT NAK effective\n mask", + "offset": 7, + "size": 1 + }, + "ESUSPM": { + "description": "Early suspend mask", + "offset": 10, + "size": 1 + }, + "USBSUSPM": { + "description": "USB suspend mask", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset mask", + "offset": 12, + "size": 1 + }, + "ENUMDNEM": { + "description": "Enumeration done mask", + "offset": 13, + "size": 1 + }, + "ISOODRPM": { + "description": "Isochronous OUT packet dropped interrupt\n mask", + "offset": 14, + "size": 1 + }, + "EOPFM": { + "description": "End of periodic frame interrupt\n mask", + "offset": 15, + "size": 1 + }, + "EPMISM": { + "description": "Endpoint mismatch interrupt\n mask", + "offset": 17, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoints interrupt\n mask", + "offset": 18, + "size": 1 + }, + "OEPINT": { + "description": "OUT endpoints interrupt\n mask", + "offset": 19, + "size": 1 + }, + "IISOIXFRM": { + "description": "Incomplete isochronous IN transfer\n mask", + "offset": 20, + "size": 1 + }, + "IPXFRM_IISOOXFRM": { + "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)", + "offset": 21, + "size": 1 + }, + "PRTIM": { + "description": "Host port interrupt mask", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIM": { + "description": "Host channels interrupt\n mask", + "offset": 25, + "size": 1 + }, + "PTXFEM": { + "description": "Periodic TxFIFO empty mask", + "offset": 26, + "size": 1 + }, + "CIDSCHGM": { + "description": "Connector ID status change\n mask", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected interrupt\n mask", + "offset": 29, + "size": 1 + }, + "SRQIM": { + "description": "Session request/new session detected\n interrupt mask", + "offset": 30, + "size": 1 + }, + "WUIM": { + "description": "Resume/remote wakeup detected interrupt\n mask", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRXSTSR_Device": { + "description": "OTG_FS Receive status debug read(Device\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXSTSR_Host": { + "description": "OTG_FS Receive status debug read(Host\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXFSIZ": { + "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "RxFIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Device": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX0FSA": { + "description": "Endpoint 0 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "TX0FD": { + "description": "Endpoint 0 TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Host": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "NPTXFSA": { + "description": "Non-periodic transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "NPTXFD": { + "description": "Non-periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXSTS": { + "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFSAV": { + "description": "Non-periodic TxFIFO space\n available", + "offset": 0, + "size": 16 + }, + "NPTQXSAV": { + "description": "Non-periodic transmit request queue\n space available", + "offset": 16, + "size": 8 + }, + "NPTXQTOP": { + "description": "Top of the non-periodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "FS_GCCFG": { + "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRDWN": { + "description": "Power down", + "offset": 16, + "size": 1 + }, + "VBUSASEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 18, + "size": 1 + }, + "VBUSBSEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 19, + "size": 1 + }, + "SOFOUTEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + } + } + } + }, + "FS_CID": { + "description": "core ID register", + "offset": 60, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRODUCT_ID": { + "description": "Product ID field", + "offset": 0, + "size": 32 + } + } + } + }, + "FS_HPTXFSIZ": { + "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXSA": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "PTXFSIZ": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF1": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO2 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF2": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO3 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF3": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)", + "offset": 268, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO4 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + } + } + } + }, + "CRC": { + "description": "Cryptographic processor", + "children": { + "registers": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data Register", + "offset": 0, + "size": 32 + } + } + } + }, + "IDR": { + "description": "Independent Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IDR": { + "description": "Independent Data register", + "offset": 0, + "size": 8 + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CR": { + "description": "Control regidter", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "Ethernet_DMA": { + "description": "Ethernet: DMA controller operation", + "children": { + "registers": { + "DMABMR": { + "description": "Ethernet DMA bus mode register", + "offset": 0, + "size": 32, + "reset_value": 8449, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "SR", + "offset": 0, + "size": 1 + }, + "DA": { + "description": "DA", + "offset": 1, + "size": 1 + }, + "DSL": { + "description": "DSL", + "offset": 2, + "size": 5 + }, + "EDFE": { + "description": "EDFE", + "offset": 7, + "size": 1 + }, + "PBL": { + "description": "PBL", + "offset": 8, + "size": 6 + }, + "RTPR": { + "description": "RTPR", + "offset": 14, + "size": 2 + }, + "FB": { + "description": "FB", + "offset": 16, + "size": 1 + }, + "RDP": { + "description": "RDP", + "offset": 17, + "size": 6 + }, + "USP": { + "description": "USP", + "offset": 23, + "size": 1 + }, + "FPM": { + "description": "FPM", + "offset": 24, + "size": 1 + }, + "AAB": { + "description": "AAB", + "offset": 25, + "size": 1 + }, + "MB": { + "description": "MB", + "offset": 26, + "size": 1 + } + } + } + }, + "DMATPDR": { + "description": "Ethernet DMA transmit poll demand\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TPD": { + "description": "TPD", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARPDR": { + "description": "EHERNET DMA receive poll demand\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RPD": { + "description": "RPD", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARDLAR": { + "description": "Ethernet DMA receive descriptor list address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRL": { + "description": "SRL", + "offset": 0, + "size": 32 + } + } + } + }, + "DMATDLAR": { + "description": "Ethernet DMA transmit descriptor list\n address register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STL": { + "description": "STL", + "offset": 0, + "size": 32 + } + } + } + }, + "DMASR": { + "description": "Ethernet DMA status register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "TS", + "offset": 0, + "size": 1 + }, + "TPSS": { + "description": "TPSS", + "offset": 1, + "size": 1 + }, + "TBUS": { + "description": "TBUS", + "offset": 2, + "size": 1 + }, + "TJTS": { + "description": "TJTS", + "offset": 3, + "size": 1 + }, + "ROS": { + "description": "ROS", + "offset": 4, + "size": 1 + }, + "TUS": { + "description": "TUS", + "offset": 5, + "size": 1 + }, + "RS": { + "description": "RS", + "offset": 6, + "size": 1 + }, + "RBUS": { + "description": "RBUS", + "offset": 7, + "size": 1 + }, + "RPSS": { + "description": "RPSS", + "offset": 8, + "size": 1 + }, + "PWTS": { + "description": "PWTS", + "offset": 9, + "size": 1 + }, + "ETS": { + "description": "ETS", + "offset": 10, + "size": 1 + }, + "FBES": { + "description": "FBES", + "offset": 13, + "size": 1 + }, + "ERS": { + "description": "ERS", + "offset": 14, + "size": 1 + }, + "AIS": { + "description": "AIS", + "offset": 15, + "size": 1 + }, + "NIS": { + "description": "NIS", + "offset": 16, + "size": 1 + }, + "RPS": { + "description": "RPS", + "offset": 17, + "size": 3, + "access": "read-only" + }, + "TPS": { + "description": "TPS", + "offset": 20, + "size": 3, + "access": "read-only" + }, + "EBS": { + "description": "EBS", + "offset": 23, + "size": 3, + "access": "read-only" + }, + "MMCS": { + "description": "MMCS", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PMTS": { + "description": "PMTS", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TSTS": { + "description": "TSTS", + "offset": 29, + "size": 1, + "access": "read-only" + } + } + } + }, + "DMAOMR": { + "description": "Ethernet DMA operation mode\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "SR", + "offset": 1, + "size": 1 + }, + "OSF": { + "description": "OSF", + "offset": 2, + "size": 1 + }, + "RTC": { + "description": "RTC", + "offset": 3, + "size": 2 + }, + "FUGF": { + "description": "FUGF", + "offset": 6, + "size": 1 + }, + "FEF": { + "description": "FEF", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "ST", + "offset": 13, + "size": 1 + }, + "TTC": { + "description": "TTC", + "offset": 14, + "size": 3 + }, + "FTF": { + "description": "FTF", + "offset": 20, + "size": 1 + }, + "TSF": { + "description": "TSF", + "offset": 21, + "size": 1 + }, + "DFRF": { + "description": "DFRF", + "offset": 24, + "size": 1 + }, + "RSF": { + "description": "RSF", + "offset": 25, + "size": 1 + }, + "DTCEFD": { + "description": "DTCEFD", + "offset": 26, + "size": 1 + } + } + } + }, + "DMAIER": { + "description": "Ethernet DMA interrupt enable\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "TIE", + "offset": 0, + "size": 1 + }, + "TPSIE": { + "description": "TPSIE", + "offset": 1, + "size": 1 + }, + "TBUIE": { + "description": "TBUIE", + "offset": 2, + "size": 1 + }, + "TJTIE": { + "description": "TJTIE", + "offset": 3, + "size": 1 + }, + "ROIE": { + "description": "ROIE", + "offset": 4, + "size": 1 + }, + "TUIE": { + "description": "TUIE", + "offset": 5, + "size": 1 + }, + "RIE": { + "description": "RIE", + "offset": 6, + "size": 1 + }, + "RBUIE": { + "description": "RBUIE", + "offset": 7, + "size": 1 + }, + "RPSIE": { + "description": "RPSIE", + "offset": 8, + "size": 1 + }, + "RWTIE": { + "description": "RWTIE", + "offset": 9, + "size": 1 + }, + "ETIE": { + "description": "ETIE", + "offset": 10, + "size": 1 + }, + "FBEIE": { + "description": "FBEIE", + "offset": 13, + "size": 1 + }, + "ERIE": { + "description": "ERIE", + "offset": 14, + "size": 1 + }, + "AISE": { + "description": "AISE", + "offset": 15, + "size": 1 + }, + "NISE": { + "description": "NISE", + "offset": 16, + "size": 1 + } + } + } + }, + "DMAMFBOCR": { + "description": "Ethernet DMA missed frame and buffer\n overflow counter register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MFC": { + "description": "MFC", + "offset": 0, + "size": 16 + }, + "OMFC": { + "description": "OMFC", + "offset": 16, + "size": 1 + }, + "MFA": { + "description": "MFA", + "offset": 17, + "size": 11 + }, + "OFOC": { + "description": "OFOC", + "offset": 28, + "size": 1 + } + } + } + }, + "DMARSWTR": { + "description": "Ethernet DMA receive status watchdog timer\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSWTC": { + "description": "RSWTC", + "offset": 0, + "size": 8 + } + } + } + }, + "DMACHTDR": { + "description": "Ethernet DMA current host transmit\n descriptor register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTDAP": { + "description": "HTDAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRDR": { + "description": "Ethernet DMA current host receive descriptor\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRDAP": { + "description": "HRDAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHTBAR": { + "description": "Ethernet DMA current host transmit buffer\n address register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTBAP": { + "description": "HTBAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRBAR": { + "description": "Ethernet DMA current host receive buffer\n address register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRBAP": { + "description": "HRBAP", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "C_ADC": { + "description": "Common ADC registers", + "children": { + "registers": { + "CSR": { + "description": "ADC Common status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OVR3": { + "description": "Overrun flag of ADC3", + "offset": 21, + "size": 1 + }, + "STRT3": { + "description": "Regular channel Start flag of ADC\n 3", + "offset": 20, + "size": 1 + }, + "JSTRT3": { + "description": "Injected channel Start flag of ADC\n 3", + "offset": 19, + "size": 1 + }, + "JEOC3": { + "description": "Injected channel end of conversion of\n ADC 3", + "offset": 18, + "size": 1 + }, + "EOC3": { + "description": "End of conversion of ADC 3", + "offset": 17, + "size": 1 + }, + "AWD3": { + "description": "Analog watchdog flag of ADC\n 3", + "offset": 16, + "size": 1 + }, + "OVR2": { + "description": "Overrun flag of ADC 2", + "offset": 13, + "size": 1 + }, + "STRT2": { + "description": "Regular channel Start flag of ADC\n 2", + "offset": 12, + "size": 1 + }, + "JSTRT2": { + "description": "Injected channel Start flag of ADC\n 2", + "offset": 11, + "size": 1 + }, + "JEOC2": { + "description": "Injected channel end of conversion of\n ADC 2", + "offset": 10, + "size": 1 + }, + "EOC2": { + "description": "End of conversion of ADC 2", + "offset": 9, + "size": 1 + }, + "AWD2": { + "description": "Analog watchdog flag of ADC\n 2", + "offset": 8, + "size": 1 + }, + "OVR1": { + "description": "Overrun flag of ADC 1", + "offset": 5, + "size": 1 + }, + "STRT1": { + "description": "Regular channel Start flag of ADC\n 1", + "offset": 4, + "size": 1 + }, + "JSTRT1": { + "description": "Injected channel Start flag of ADC\n 1", + "offset": 3, + "size": 1 + }, + "JEOC1": { + "description": "Injected channel end of conversion of\n ADC 1", + "offset": 2, + "size": 1 + }, + "EOC1": { + "description": "End of conversion of ADC 1", + "offset": 1, + "size": 1 + }, + "AWD1": { + "description": "Analog watchdog flag of ADC\n 1", + "offset": 0, + "size": 1 + } + } + } + }, + "CCR": { + "description": "ADC common control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSVREFE": { + "description": "Temperature sensor and VREFINT\n enable", + "offset": 23, + "size": 1 + }, + "VBATE": { + "description": "VBAT enable", + "offset": 22, + "size": 1 + }, + "ADCPRE": { + "description": "ADC prescaler", + "offset": 16, + "size": 2 + }, + "DMA": { + "description": "Direct memory access mode for multi ADC\n mode", + "offset": 14, + "size": 2 + }, + "DDS": { + "description": "DMA disable selection for multi-ADC\n mode", + "offset": 13, + "size": 1 + }, + "DELAY": { + "description": "Delay between 2 sampling\n phases", + "offset": 8, + "size": 4 + }, + "MULT": { + "description": "Multi ADC mode selection", + "offset": 0, + "size": 5 + } + } + } + }, + "CDR": { + "description": "ADC common regular data register for dual\n and triple modes", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA2": { + "description": "2nd data item of a pair of regular\n conversions", + "offset": 16, + "size": 16 + }, + "DATA1": { + "description": "1st data item of a pair of regular\n conversions", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "TIM1": { + "description": "Advanced-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OIS4": { + "description": "Output Idle state 4", + "offset": 14, + "size": 1 + }, + "OIS3N": { + "description": "Output Idle state 3", + "offset": 13, + "size": 1 + }, + "OIS3": { + "description": "Output Idle state 3", + "offset": 12, + "size": 1 + }, + "OIS2N": { + "description": "Output Idle state 2", + "offset": 11, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output Compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output Compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC4CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3NE": { + "description": "Capture/Compare 3 complementary output\n enable", + "offset": 10, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2NE": { + "description": "Capture/Compare 2 complementary output\n enable", + "offset": 6, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "Ethernet_PTP": { + "description": "Ethernet: Precision time protocol", + "children": { + "registers": { + "PTPTSCR": { + "description": "Ethernet PTP time stamp control\n register", + "offset": 0, + "size": 32, + "reset_value": 8192, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSE": { + "description": "TSE", + "offset": 0, + "size": 1 + }, + "TSFCU": { + "description": "TSFCU", + "offset": 1, + "size": 1 + }, + "TSPTPPSV2E": { + "description": "TSPTPPSV2E", + "offset": 10, + "size": 1 + }, + "TSSPTPOEFE": { + "description": "TSSPTPOEFE", + "offset": 11, + "size": 1 + }, + "TSSIPV6FE": { + "description": "TSSIPV6FE", + "offset": 12, + "size": 1 + }, + "TSSIPV4FE": { + "description": "TSSIPV4FE", + "offset": 13, + "size": 1 + }, + "TSSEME": { + "description": "TSSEME", + "offset": 14, + "size": 1 + }, + "TSSMRME": { + "description": "TSSMRME", + "offset": 15, + "size": 1 + }, + "TSCNT": { + "description": "TSCNT", + "offset": 16, + "size": 2 + }, + "TSPFFMAE": { + "description": "TSPFFMAE", + "offset": 18, + "size": 1 + }, + "TSSTI": { + "description": "TSSTI", + "offset": 2, + "size": 1 + }, + "TSSTU": { + "description": "TSSTU", + "offset": 3, + "size": 1 + }, + "TSITE": { + "description": "TSITE", + "offset": 4, + "size": 1 + }, + "TTSARU": { + "description": "TTSARU", + "offset": 5, + "size": 1 + }, + "TSSARFE": { + "description": "TSSARFE", + "offset": 8, + "size": 1 + }, + "TSSSR": { + "description": "TSSSR", + "offset": 9, + "size": 1 + } + } + } + }, + "PTPSSIR": { + "description": "Ethernet PTP subsecond increment\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STSSI": { + "description": "STSSI", + "offset": 0, + "size": 8 + } + } + } + }, + "PTPTSHR": { + "description": "Ethernet PTP time stamp high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STS": { + "description": "STS", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLR": { + "description": "Ethernet PTP time stamp low\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STSS": { + "description": "STSS", + "offset": 0, + "size": 31 + }, + "STPNS": { + "description": "STPNS", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSHUR": { + "description": "Ethernet PTP time stamp high update\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUS": { + "description": "TSUS", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLUR": { + "description": "Ethernet PTP time stamp low update\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUSS": { + "description": "TSUSS", + "offset": 0, + "size": 31 + }, + "TSUPNS": { + "description": "TSUPNS", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSAR": { + "description": "Ethernet PTP time stamp addend\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSA": { + "description": "TSA", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTHR": { + "description": "Ethernet PTP target time high\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSH": { + "description": "0", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTLR": { + "description": "Ethernet PTP target time low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSL": { + "description": "TTSL", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSSR": { + "description": "Ethernet PTP time stamp status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TSSO": { + "description": "TSSO", + "offset": 0, + "size": 1 + }, + "TSTTR": { + "description": "TSTTR", + "offset": 1, + "size": 1 + } + } + } + }, + "PTPPPSCR": { + "description": "Ethernet PTP PPS control\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TSSO": { + "description": "TSSO", + "offset": 0, + "size": 1 + }, + "TSTTR": { + "description": "TSTTR", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "TIM2": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "TIM5 option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ITR1_RMP": { + "description": "Timer Input 4 remap", + "offset": 10, + "size": 2 + } + } + } + } + } + } + }, + "TIM3": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "Ethernet_MMC": { + "description": "Ethernet: MAC management counters", + "children": { + "registers": { + "MMCCR": { + "description": "Ethernet MMC control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CR": { + "description": "CR", + "offset": 0, + "size": 1 + }, + "CSR": { + "description": "CSR", + "offset": 1, + "size": 1 + }, + "ROR": { + "description": "ROR", + "offset": 2, + "size": 1 + }, + "MCF": { + "description": "MCF", + "offset": 3, + "size": 1 + }, + "MCP": { + "description": "MCP", + "offset": 4, + "size": 1 + }, + "MCFHP": { + "description": "MCFHP", + "offset": 5, + "size": 1 + } + } + } + }, + "MMCRIR": { + "description": "Ethernet MMC receive interrupt\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCES": { + "description": "RFCES", + "offset": 5, + "size": 1 + }, + "RFAES": { + "description": "RFAES", + "offset": 6, + "size": 1 + }, + "RGUFS": { + "description": "RGUFS", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIR": { + "description": "Ethernet MMC transmit interrupt\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFSCS": { + "description": "TGFSCS", + "offset": 14, + "size": 1 + }, + "TGFMSCS": { + "description": "TGFMSCS", + "offset": 15, + "size": 1 + }, + "TGFS": { + "description": "TGFS", + "offset": 21, + "size": 1 + } + } + } + }, + "MMCRIMR": { + "description": "Ethernet MMC receive interrupt mask\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCEM": { + "description": "RFCEM", + "offset": 5, + "size": 1 + }, + "RFAEM": { + "description": "RFAEM", + "offset": 6, + "size": 1 + }, + "RGUFM": { + "description": "RGUFM", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIMR": { + "description": "Ethernet MMC transmit interrupt mask\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TGFSCM": { + "description": "TGFSCM", + "offset": 14, + "size": 1 + }, + "TGFMSCM": { + "description": "TGFMSCM", + "offset": 15, + "size": 1 + }, + "TGFM": { + "description": "TGFM", + "offset": 16, + "size": 1 + } + } + } + }, + "MMCTGFSCCR": { + "description": "Ethernet MMC transmitted good frames after a\n single collision counter", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFSCC": { + "description": "TGFSCC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFMSCCR": { + "description": "Ethernet MMC transmitted good frames after\n more than a single collision", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFMSCC": { + "description": "TGFMSCC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFCR": { + "description": "Ethernet MMC transmitted good frames counter\n register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFC": { + "description": "HTL", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFCECR": { + "description": "Ethernet MMC received frames with CRC error\n counter register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFCFC": { + "description": "RFCFC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFAECR": { + "description": "Ethernet MMC received frames with alignment\n error counter register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFAEC": { + "description": "RFAEC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRGUFCR": { + "description": "MMC received good unicast frames counter\n register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RGUFC": { + "description": "RGUFC", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "TIM5": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "TIM5 option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IT4_RMP": { + "description": "Timer Input 4 remap", + "offset": 6, + "size": 2 + } + } + } + } + } + } + }, + "TIM9": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 3 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 3 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "Ethernet_MAC": { + "description": "Ethernet: media access control\n (MAC)", + "children": { + "registers": { + "MACCR": { + "description": "Ethernet MAC configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "RE": { + "description": "RE", + "offset": 2, + "size": 1 + }, + "TE": { + "description": "TE", + "offset": 3, + "size": 1 + }, + "DC": { + "description": "DC", + "offset": 4, + "size": 1 + }, + "BL": { + "description": "BL", + "offset": 5, + "size": 2 + }, + "APCS": { + "description": "APCS", + "offset": 7, + "size": 1 + }, + "RD": { + "description": "RD", + "offset": 9, + "size": 1 + }, + "IPCO": { + "description": "IPCO", + "offset": 10, + "size": 1 + }, + "DM": { + "description": "DM", + "offset": 11, + "size": 1 + }, + "LM": { + "description": "LM", + "offset": 12, + "size": 1 + }, + "ROD": { + "description": "ROD", + "offset": 13, + "size": 1 + }, + "FES": { + "description": "FES", + "offset": 14, + "size": 1 + }, + "CSD": { + "description": "CSD", + "offset": 16, + "size": 1 + }, + "IFG": { + "description": "IFG", + "offset": 17, + "size": 3 + }, + "JD": { + "description": "JD", + "offset": 22, + "size": 1 + }, + "WD": { + "description": "WD", + "offset": 23, + "size": 1 + }, + "CSTF": { + "description": "CSTF", + "offset": 25, + "size": 1 + } + } + } + }, + "MACFFR": { + "description": "Ethernet MAC frame filter\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "PM", + "offset": 0, + "size": 1 + }, + "HU": { + "description": "HU", + "offset": 1, + "size": 1 + }, + "HM": { + "description": "HM", + "offset": 2, + "size": 1 + }, + "DAIF": { + "description": "DAIF", + "offset": 3, + "size": 1 + }, + "RAM": { + "description": "RAM", + "offset": 4, + "size": 1 + }, + "BFD": { + "description": "BFD", + "offset": 5, + "size": 1 + }, + "PCF": { + "description": "PCF", + "offset": 6, + "size": 1 + }, + "SAIF": { + "description": "SAIF", + "offset": 7, + "size": 1 + }, + "SAF": { + "description": "SAF", + "offset": 8, + "size": 1 + }, + "HPF": { + "description": "HPF", + "offset": 9, + "size": 1 + }, + "RA": { + "description": "RA", + "offset": 31, + "size": 1 + } + } + } + }, + "MACHTHR": { + "description": "Ethernet MAC hash table high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTH": { + "description": "HTH", + "offset": 0, + "size": 32 + } + } + } + }, + "MACHTLR": { + "description": "Ethernet MAC hash table low\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTL": { + "description": "HTL", + "offset": 0, + "size": 32 + } + } + } + }, + "MACMIIAR": { + "description": "Ethernet MAC MII address\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MB": { + "description": "MB", + "offset": 0, + "size": 1 + }, + "MW": { + "description": "MW", + "offset": 1, + "size": 1 + }, + "CR": { + "description": "CR", + "offset": 2, + "size": 3 + }, + "MR": { + "description": "MR", + "offset": 6, + "size": 5 + }, + "PA": { + "description": "PA", + "offset": 11, + "size": 5 + } + } + } + }, + "MACMIIDR": { + "description": "Ethernet MAC MII data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TD": { + "description": "TD", + "offset": 0, + "size": 16 + } + } + } + }, + "MACFCR": { + "description": "Ethernet MAC flow control\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FCB": { + "description": "FCB", + "offset": 0, + "size": 1 + }, + "TFCE": { + "description": "TFCE", + "offset": 1, + "size": 1 + }, + "RFCE": { + "description": "RFCE", + "offset": 2, + "size": 1 + }, + "UPFD": { + "description": "UPFD", + "offset": 3, + "size": 1 + }, + "PLT": { + "description": "PLT", + "offset": 4, + "size": 2 + }, + "ZQPD": { + "description": "ZQPD", + "offset": 7, + "size": 1 + }, + "PT": { + "description": "PT", + "offset": 16, + "size": 16 + } + } + } + }, + "MACVLANTR": { + "description": "Ethernet MAC VLAN tag register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VLANTI": { + "description": "VLANTI", + "offset": 0, + "size": 16 + }, + "VLANTC": { + "description": "VLANTC", + "offset": 16, + "size": 1 + } + } + } + }, + "MACPMTCSR": { + "description": "Ethernet MAC PMT control and status\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PD": { + "description": "PD", + "offset": 0, + "size": 1 + }, + "MPE": { + "description": "MPE", + "offset": 1, + "size": 1 + }, + "WFE": { + "description": "WFE", + "offset": 2, + "size": 1 + }, + "MPR": { + "description": "MPR", + "offset": 5, + "size": 1 + }, + "WFR": { + "description": "WFR", + "offset": 6, + "size": 1 + }, + "GU": { + "description": "GU", + "offset": 9, + "size": 1 + }, + "WFFRPR": { + "description": "WFFRPR", + "offset": 31, + "size": 1 + } + } + } + }, + "MACDBGR": { + "description": "Ethernet MAC debug register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CR": { + "description": "CR", + "offset": 0, + "size": 1 + }, + "CSR": { + "description": "CSR", + "offset": 1, + "size": 1 + }, + "ROR": { + "description": "ROR", + "offset": 2, + "size": 1 + }, + "MCF": { + "description": "MCF", + "offset": 3, + "size": 1 + }, + "MCP": { + "description": "MCP", + "offset": 4, + "size": 1 + }, + "MCFHP": { + "description": "MCFHP", + "offset": 5, + "size": 1 + } + } + } + }, + "MACSR": { + "description": "Ethernet MAC interrupt status\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTS": { + "description": "PMTS", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "MMCS": { + "description": "MMCS", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "MMCRS": { + "description": "MMCRS", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "MMCTS": { + "description": "MMCTS", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "TSTS": { + "description": "TSTS", + "offset": 9, + "size": 1 + } + } + } + }, + "MACIMR": { + "description": "Ethernet MAC interrupt mask\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTIM": { + "description": "PMTIM", + "offset": 3, + "size": 1 + }, + "TSTIM": { + "description": "TSTIM", + "offset": 9, + "size": 1 + } + } + } + }, + "MACA0HR": { + "description": "Ethernet MAC address 0 high\n register", + "offset": 64, + "size": 32, + "reset_value": 1114111, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0H": { + "description": "MAC address0 high", + "offset": 0, + "size": 16 + }, + "MO": { + "description": "Always 1", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "MACA0LR": { + "description": "Ethernet MAC address 0 low\n register", + "offset": 68, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0L": { + "description": "0", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA1HR": { + "description": "Ethernet MAC address 1 high\n register", + "offset": 72, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1H": { + "description": "MACA1H", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA1LR": { + "description": "Ethernet MAC address1 low\n register", + "offset": 76, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1LR": { + "description": "MACA1LR", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA2HR": { + "description": "Ethernet MAC address 2 high\n register", + "offset": 80, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAC2AH": { + "description": "MAC2AH", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA2LR": { + "description": "Ethernet MAC address 2 low\n register", + "offset": 84, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA2L": { + "description": "MACA2L", + "offset": 0, + "size": 31 + } + } + } + }, + "MACA3HR": { + "description": "Ethernet MAC address 3 high\n register", + "offset": 88, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA3H": { + "description": "MACA3H", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA3LR": { + "description": "Ethernet MAC address 3 low\n register", + "offset": 92, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MBCA3L": { + "description": "MBCA3L", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "TIM10": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "TIM11": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RMP": { + "description": "Input 1 remapping\n capability", + "offset": 0, + "size": 2 + } + } + } + } + } + } + } + } + }, + "devices": { + "STM32F407": { + "arch": "cortex_m4", + "description": "STM32F407", + "properties": { + "cpu.nvic_prio_bits": "3", + "cpu.mpu": "false", + "cpu.fpu": "false", + "cpu.revision": "r1p0", + "cpu.vendor_systick_config": "false", + "cpu.endian": "little", + "cpu.name": "CM4" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "FPU": { + "index": 81, + "description": "Floating point unit interrupt" + }, + "DCMI": { + "index": 78, + "description": "DCMI global interrupt" + }, + "FSMC": { + "index": 48, + "description": "FSMC global interrupt" + }, + "DMA2_Stream0": { + "index": 56, + "description": "DMA2 Stream0 global interrupt" + }, + "DMA1_Stream0": { + "index": 11, + "description": "DMA1 Stream0 global interrupt" + }, + "RCC": { + "index": 5, + "description": "RCC global interrupt" + }, + "SPI1": { + "index": 35, + "description": "SPI1 global interrupt" + }, + "SPI2": { + "index": 36, + "description": "SPI2 global interrupt" + }, + "SPI3": { + "index": 51, + "description": "SPI3 global interrupt" + }, + "SDIO": { + "index": 49, + "description": "SDIO global interrupt" + }, + "ADC": { + "index": 18, + "description": "ADC3 global interrupts" + }, + "USART6": { + "index": 71, + "description": "USART6 global interrupt" + }, + "USART1": { + "index": 37, + "description": "USART1 global interrupt" + }, + "USART2": { + "index": 38, + "description": "USART2 global interrupt" + }, + "USART3": { + "index": 39, + "description": "USART3 global interrupt" + }, + "TIM6_DAC": { + "index": 54, + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n error interrupt" + }, + "PVD": { + "index": 1, + "description": "PVD through EXTI line detection\n interrupt" + }, + "I2C3_EV": { + "index": 72, + "description": "I2C3 event interrupt" + }, + "I2C2_EV": { + "index": 33, + "description": "I2C2 event interrupt" + }, + "I2C1_EV": { + "index": 31, + "description": "I2C1 event interrupt" + }, + "WWDG": { + "index": 0, + "description": "Window Watchdog interrupt" + }, + "RTC_WKUP": { + "index": 3, + "description": "RTC Wakeup interrupt through the EXTI\n line" + }, + "UART4": { + "index": 52, + "description": "UART4 global interrupt" + }, + "UART5": { + "index": 53, + "description": "UART5 global interrupt" + }, + "TIM1_BRK_TIM9": { + "index": 24, + "description": "TIM1 Break interrupt and TIM9 global\n interrupt" + }, + "TIM8_BRK_TIM12": { + "index": 43, + "description": "TIM8 Break interrupt and TIM12 global\n interrupt" + }, + "TIM2": { + "index": 28, + "description": "TIM2 global interrupt" + }, + "TIM3": { + "index": 29, + "description": "TIM3 global interrupt" + }, + "TIM4": { + "index": 30, + "description": "TIM4 global interrupt" + }, + "TIM5": { + "index": 50, + "description": "TIM5 global interrupt" + }, + "TIM1_UP_TIM10": { + "index": 25, + "description": "TIM1 Update interrupt and TIM10 global\n interrupt" + }, + "TIM8_UP_TIM13": { + "index": 44, + "description": "TIM8 Update interrupt and TIM13 global\n interrupt" + }, + "TIM8_TRG_COM_TIM14": { + "index": 45, + "description": "TIM8 Trigger and Commutation interrupts and\n TIM14 global interrupt" + }, + "TIM1_TRG_COM_TIM11": { + "index": 26, + "description": "TIM1 Trigger and Commutation interrupts and\n TIM11 global interrupt" + }, + "TIM7": { + "index": 55, + "description": "TIM7 global interrupt" + }, + "ETH": { + "index": 61, + "description": "Ethernet global interrupt" + }, + "OTG_FS_WKUP": { + "index": 42, + "description": "USB On-The-Go FS Wakeup through EXTI line\n interrupt" + }, + "CAN1_TX": { + "index": 19, + "description": "CAN1 TX interrupts" + }, + "CAN2_TX": { + "index": 63, + "description": "CAN2 TX interrupts" + }, + "TAMP_STAMP": { + "index": 2, + "description": "Tamper and TimeStamp interrupts through the\n EXTI line" + }, + "OTG_HS_EP1_OUT": { + "index": 74, + "description": "USB On The Go HS End Point 1 Out global\n interrupt" + }, + "LCD_TFT": { + "index": 88, + "description": "LTDC global interrupt" + }, + "HASH_RNG": { + "index": 80, + "description": "Hash and Rng global interrupt" + }, + "CRYP": { + "index": 79, + "description": "CRYP crypto global interrupt" + } + }, + "peripheral_instances": { + "RNG": { + "description": "Random number generator", + "offset": 1342572544, + "type": "types.peripherals.RNG" + }, + "DCMI": { + "description": "Digital camera interface", + "offset": 1342504960, + "type": "types.peripherals.DCMI" + }, + "FSMC": { + "description": "Flexible static memory controller", + "offset": 2684354560, + "type": "types.peripherals.FSMC" + }, + "DBG": { + "description": "Debug support", + "offset": 3758366720, + "type": "types.peripherals.DBG" + }, + "DMA2": { + "description": "DMA controller", + "offset": 1073898496, + "type": "types.peripherals.DMA2" + }, + "DMA1": { + "offset": 1073897472, + "type": "types.peripherals.DMA2" + }, + "RCC": { + "description": "Reset and clock control", + "offset": 1073887232, + "type": "types.peripherals.RCC" + }, + "GPIOI": { + "description": "General-purpose I/Os", + "offset": 1073881088, + "type": "types.peripherals.GPIOI" + }, + "GPIOH": { + "offset": 1073880064, + "type": "types.peripherals.GPIOI" + }, + "GPIOG": { + "offset": 1073879040, + "type": "types.peripherals.GPIOI" + }, + "GPIOF": { + "offset": 1073878016, + "type": "types.peripherals.GPIOI" + }, + "GPIOE": { + "offset": 1073876992, + "type": "types.peripherals.GPIOI" + }, + "GPIOD": { + "offset": 1073875968, + "type": "types.peripherals.GPIOI" + }, + "GPIOC": { + "offset": 1073874944, + "type": "types.peripherals.GPIOI" + }, + "GPIOJ": { + "offset": 1073882112, + "type": "types.peripherals.GPIOI" + }, + "GPIOK": { + "offset": 1073883136, + "type": "types.peripherals.GPIOI" + }, + "GPIOB": { + "description": "General-purpose I/Os", + "offset": 1073873920, + "type": "types.peripherals.GPIOB" + }, + "GPIOA": { + "description": "General-purpose I/Os", + "offset": 1073872896, + "type": "types.peripherals.GPIOA" + }, + "SYSCFG": { + "description": "System configuration controller", + "offset": 1073821696, + "type": "types.peripherals.SYSCFG" + }, + "SPI1": { + "description": "Serial peripheral interface", + "offset": 1073819648, + "type": "types.peripherals.SPI1" + }, + "SPI2": { + "offset": 1073756160, + "type": "types.peripherals.SPI1" + }, + "SPI3": { + "offset": 1073757184, + "type": "types.peripherals.SPI1" + }, + "I2S2ext": { + "offset": 1073755136, + "type": "types.peripherals.SPI1" + }, + "I2S3ext": { + "offset": 1073758208, + "type": "types.peripherals.SPI1" + }, + "SPI4": { + "offset": 1073820672, + "type": "types.peripherals.SPI1" + }, + "SPI5": { + "offset": 1073827840, + "type": "types.peripherals.SPI1" + }, + "SPI6": { + "offset": 1073828864, + "type": "types.peripherals.SPI1" + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "offset": 1073818624, + "type": "types.peripherals.SDIO" + }, + "ADC1": { + "description": "Analog-to-digital converter", + "offset": 1073815552, + "type": "types.peripherals.ADC1" + }, + "ADC2": { + "offset": 1073815808, + "type": "types.peripherals.ADC1" + }, + "ADC3": { + "offset": 1073816064, + "type": "types.peripherals.ADC1" + }, + "USART6": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073812480, + "type": "types.peripherals.USART6" + }, + "USART1": { + "offset": 1073811456, + "type": "types.peripherals.USART6" + }, + "USART2": { + "offset": 1073759232, + "type": "types.peripherals.USART6" + }, + "USART3": { + "offset": 1073760256, + "type": "types.peripherals.USART6" + }, + "DAC": { + "description": "Digital-to-analog converter", + "offset": 1073771520, + "type": "types.peripherals.DAC" + }, + "PWR": { + "description": "Power control", + "offset": 1073770496, + "type": "types.peripherals.PWR" + }, + "I2C3": { + "description": "Inter-integrated circuit", + "offset": 1073765376, + "type": "types.peripherals.I2C3" + }, + "I2C2": { + "offset": 1073764352, + "type": "types.peripherals.I2C3" + }, + "I2C1": { + "offset": 1073763328, + "type": "types.peripherals.I2C3" + }, + "IWDG": { + "description": "Independent watchdog", + "offset": 1073754112, + "type": "types.peripherals.IWDG" + }, + "WWDG": { + "description": "Window watchdog", + "offset": 1073753088, + "type": "types.peripherals.WWDG" + }, + "RTC": { + "description": "Real-time clock", + "offset": 1073752064, + "type": "types.peripherals.RTC" + }, + "UART4": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073761280, + "type": "types.peripherals.UART4" + }, + "UART5": { + "offset": 1073762304, + "type": "types.peripherals.UART4" + }, + "UART7": { + "offset": 1073772544, + "type": "types.peripherals.UART4" + }, + "UART8": { + "offset": 1073773568, + "type": "types.peripherals.UART4" + }, + "C_ADC": { + "description": "Common ADC registers", + "offset": 1073816320, + "type": "types.peripherals.C_ADC" + }, + "TIM1": { + "description": "Advanced-timers", + "offset": 1073807360, + "type": "types.peripherals.TIM1" + }, + "TIM8": { + "offset": 1073808384, + "type": "types.peripherals.TIM1" + }, + "TIM2": { + "description": "General purpose timers", + "offset": 1073741824, + "type": "types.peripherals.TIM2" + }, + "TIM3": { + "description": "General purpose timers", + "offset": 1073742848, + "type": "types.peripherals.TIM3" + }, + "TIM4": { + "offset": 1073743872, + "type": "types.peripherals.TIM3" + }, + "TIM5": { + "description": "General-purpose-timers", + "offset": 1073744896, + "type": "types.peripherals.TIM5" + }, + "TIM9": { + "description": "General purpose timers", + "offset": 1073823744, + "type": "types.peripherals.TIM9" + }, + "TIM12": { + "offset": 1073747968, + "type": "types.peripherals.TIM9" + }, + "TIM10": { + "description": "General-purpose-timers", + "offset": 1073824768, + "type": "types.peripherals.TIM10" + }, + "TIM13": { + "offset": 1073748992, + "type": "types.peripherals.TIM10" + }, + "TIM14": { + "offset": 1073750016, + "type": "types.peripherals.TIM10" + }, + "TIM11": { + "description": "General-purpose-timers", + "offset": 1073825792, + "type": "types.peripherals.TIM11" + }, + "TIM6": { + "description": "Basic timers", + "offset": 1073745920, + "type": "types.peripherals.TIM6" + }, + "TIM7": { + "offset": 1073746944, + "type": "types.peripherals.TIM6" + }, + "Ethernet_MAC": { + "description": "Ethernet: media access control\n (MAC)", + "offset": 1073905664, + "type": "types.peripherals.Ethernet_MAC" + }, + "Ethernet_MMC": { + "description": "Ethernet: MAC management counters", + "offset": 1073905920, + "type": "types.peripherals.Ethernet_MMC" + }, + "Ethernet_PTP": { + "description": "Ethernet: Precision time protocol", + "offset": 1073907456, + "type": "types.peripherals.Ethernet_PTP" + }, + "Ethernet_DMA": { + "description": "Ethernet: DMA controller operation", + "offset": 1073909760, + "type": "types.peripherals.Ethernet_DMA" + }, + "CRC": { + "description": "Cryptographic processor", + "offset": 1073885184, + "type": "types.peripherals.CRC" + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "offset": 1342177280, + "type": "types.peripherals.OTG_FS_GLOBAL" + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "offset": 1342178304, + "type": "types.peripherals.OTG_FS_HOST" + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "offset": 1342179328, + "type": "types.peripherals.OTG_FS_DEVICE" + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "offset": 1342180864, + "type": "types.peripherals.OTG_FS_PWRCLK" + }, + "CAN1": { + "description": "Controller area network", + "offset": 1073767424, + "type": "types.peripherals.CAN1" + }, + "CAN2": { + "offset": 1073768448, + "type": "types.peripherals.CAN1" + }, + "FLASH": { + "description": "FLASH", + "offset": 1073888256, + "type": "types.peripherals.FLASH" + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "offset": 1073822720, + "type": "types.peripherals.EXTI" + }, + "OTG_HS_GLOBAL": { + "description": "USB on the go high speed", + "offset": 1074003968, + "type": "types.peripherals.OTG_HS_GLOBAL" + }, + "OTG_HS_HOST": { + "description": "USB on the go high speed", + "offset": 1074004992, + "type": "types.peripherals.OTG_HS_HOST" + }, + "OTG_HS_DEVICE": { + "description": "USB on the go high speed", + "offset": 1074006016, + "type": "types.peripherals.OTG_HS_DEVICE" + }, + "OTG_HS_PWRCLK": { + "description": "USB on the go high speed", + "offset": 1074007552, + "type": "types.peripherals.OTG_HS_PWRCLK" + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "offset": 3758153984, + "type": "types.peripherals.NVIC" + }, + "SAI1": { + "description": "Serial audio interface", + "offset": 1073829888, + "type": "types.peripherals.SAI1" + }, + "LTDC": { + "description": "LCD-TFT Controller", + "offset": 1073833984, + "type": "types.peripherals.LTDC" + }, + "HASH": { + "description": "Hash processor", + "offset": 1342571520, + "type": "types.peripherals.HASH" + }, + "CRYP": { + "description": "Cryptographic processor", + "offset": 1342570496, + "type": "types.peripherals.CRYP" + }, + "FPU": { + "description": "Floting point unit", + "offset": 3758157620, + "type": "types.peripherals.FPU" + }, + "MPU": { + "description": "Memory protection unit", + "offset": 3758157200, + "type": "types.peripherals.MPU" + }, + "STK": { + "description": "SysTick timer", + "offset": 3758153744, + "type": "types.peripherals.STK" + }, + "SCB": { + "description": "System control block", + "offset": 3758157056, + "type": "types.peripherals.SCB" + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "offset": 3758157568, + "type": "types.peripherals.NVIC_STIR" + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "offset": 3758157192, + "type": "types.peripherals.FPU_CPACR" + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "offset": 3758153736, + "type": "types.peripherals.SCB_ACTRL" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/STM32F407.zig b/src/chips/STM32F407.zig new file mode 100644 index 0000000..bf7ea69 --- /dev/null +++ b/src/chips/STM32F407.zig @@ -0,0 +1,20004 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// STM32F407 + pub const STM32F407 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "3"; + pub const @"cpu.mpu" = "false"; + pub const @"cpu.fpu" = "false"; + pub const @"cpu.revision" = "r1p0"; + pub const @"cpu.vendor_systick_config" = "false"; + pub const @"cpu.endian" = "little"; + pub const @"cpu.name" = "CM4"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + /// Window Watchdog interrupt + WWDG: Handler = unhandled, + /// PVD through EXTI line detection interrupt + PVD: Handler = unhandled, + /// Tamper and TimeStamp interrupts through the EXTI line + TAMP_STAMP: Handler = unhandled, + /// RTC Wakeup interrupt through the EXTI line + RTC_WKUP: Handler = unhandled, + reserved18: [1]u32 = undefined, + /// RCC global interrupt + RCC: Handler = unhandled, + reserved20: [5]u32 = undefined, + /// DMA1 Stream0 global interrupt + DMA1_Stream0: Handler = unhandled, + reserved26: [6]u32 = undefined, + /// ADC1 global interrupt + ADC: Handler = unhandled, + /// CAN1 TX interrupts + CAN1_TX: Handler = unhandled, + reserved34: [4]u32 = undefined, + /// TIM1 Break interrupt and TIM9 global interrupt + TIM1_BRK_TIM9: Handler = unhandled, + /// TIM1 Update interrupt and TIM10 global interrupt + TIM1_UP_TIM10: Handler = unhandled, + /// TIM1 Trigger and Commutation interrupts and TIM11 global interrupt + TIM1_TRG_COM_TIM11: Handler = unhandled, + reserved41: [1]u32 = undefined, + /// TIM2 global interrupt + TIM2: Handler = unhandled, + /// TIM3 global interrupt + TIM3: Handler = unhandled, + /// TIM4 global interrupt + TIM4: Handler = unhandled, + /// I2C1 event interrupt + I2C1_EV: Handler = unhandled, + reserved46: [1]u32 = undefined, + /// I2C2 event interrupt + I2C2_EV: Handler = unhandled, + reserved48: [1]u32 = undefined, + /// SPI1 global interrupt + SPI1: Handler = unhandled, + /// SPI2 global interrupt + SPI2: Handler = unhandled, + /// USART1 global interrupt + USART1: Handler = unhandled, + /// USART2 global interrupt + USART2: Handler = unhandled, + /// USART3 global interrupt + USART3: Handler = unhandled, + reserved54: [2]u32 = undefined, + /// USB On-The-Go FS Wakeup through EXTI line interrupt + OTG_FS_WKUP: Handler = unhandled, + /// TIM8 Break interrupt and TIM12 global interrupt + TIM8_BRK_TIM12: Handler = unhandled, + /// TIM8 Update interrupt and TIM13 global interrupt + TIM8_UP_TIM13: Handler = unhandled, + /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt + TIM8_TRG_COM_TIM14: Handler = unhandled, + reserved60: [2]u32 = undefined, + /// FSMC global interrupt + FSMC: Handler = unhandled, + /// SDIO global interrupt + SDIO: Handler = unhandled, + /// TIM5 global interrupt + TIM5: Handler = unhandled, + /// SPI3 global interrupt + SPI3: Handler = unhandled, + /// UART4 global interrupt + UART4: Handler = unhandled, + /// UART5 global interrupt + UART5: Handler = unhandled, + /// TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt + TIM6_DAC: Handler = unhandled, + /// TIM7 global interrupt + TIM7: Handler = unhandled, + /// DMA2 Stream0 global interrupt + DMA2_Stream0: Handler = unhandled, + reserved71: [4]u32 = undefined, + /// Ethernet global interrupt + ETH: Handler = unhandled, + reserved76: [1]u32 = undefined, + /// CAN2 TX interrupts + CAN2_TX: Handler = unhandled, + reserved78: [7]u32 = undefined, + /// USART6 global interrupt + USART6: Handler = unhandled, + /// I2C3 event interrupt + I2C3_EV: Handler = unhandled, + reserved87: [1]u32 = undefined, + /// USB On The Go HS End Point 1 Out global interrupt + OTG_HS_EP1_OUT: Handler = unhandled, + reserved89: [3]u32 = undefined, + /// DCMI global interrupt + DCMI: Handler = unhandled, + /// CRYP crypto global interrupt + CRYP: Handler = unhandled, + /// Hash and Rng global interrupt + HASH_RNG: Handler = unhandled, + /// FPU interrupt + FPU: Handler = unhandled, + reserved96: [6]u32 = undefined, + /// LTDC global interrupt + LCD_TFT: Handler = unhandled, + }; + + pub const peripherals = struct { + /// General purpose timers + pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000); + /// General purpose timers + pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400); + /// General purpose timers + pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800); + /// General-purpose-timers + pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00); + /// Basic timers + pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000); + /// Basic timers + pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400); + /// General purpose timers + pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800); + /// General-purpose-timers + pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00); + /// General-purpose-timers + pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000); + /// Real-time clock + pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800); + /// Window watchdog + pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00); + /// Independent watchdog + pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000); + /// Serial peripheral interface + pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400); + /// Serial peripheral interface + pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800); + /// Serial peripheral interface + pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00); + /// Serial peripheral interface + pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800); + /// Universal synchronous asynchronous receiver transmitter + pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00); + /// Universal synchronous asynchronous receiver transmitter + pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000); + /// Inter-integrated circuit + pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400); + /// Inter-integrated circuit + pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800); + /// Inter-integrated circuit + pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00); + /// Controller area network + pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400); + /// Controller area network + pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800); + /// Power control + pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000); + /// Digital-to-analog converter + pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400); + /// Universal synchronous asynchronous receiver transmitter + pub const UART7 = @ptrCast(*volatile types.UART4, 0x40007800); + /// Universal synchronous asynchronous receiver transmitter + pub const UART8 = @ptrCast(*volatile types.UART4, 0x40007c00); + /// Advanced-timers + pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000); + /// Advanced-timers + pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400); + /// Analog-to-digital converter + pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000); + /// Analog-to-digital converter + pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100); + /// Analog-to-digital converter + pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200); + /// Common ADC registers + pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300); + /// Secure digital input/output interface + pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00); + /// Serial peripheral interface + pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000); + /// Serial peripheral interface + pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400); + /// System configuration controller + pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800); + /// External interrupt/event controller + pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00); + /// General purpose timers + pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000); + /// General-purpose-timers + pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400); + /// General-purpose-timers + pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800); + /// Serial peripheral interface + pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000); + /// Serial peripheral interface + pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400); + /// Serial audio interface + pub const SAI1 = @ptrCast(*volatile types.SAI1, 0x40015800); + /// LCD-TFT Controller + pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800); + /// General-purpose I/Os + pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000); + /// General-purpose I/Os + pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400); + /// General-purpose I/Os + pub const GPIOC = @ptrCast(*volatile types.GPIOI, 0x40020800); + /// General-purpose I/Os + pub const GPIOD = @ptrCast(*volatile types.GPIOI, 0x40020c00); + /// General-purpose I/Os + pub const GPIOE = @ptrCast(*volatile types.GPIOI, 0x40021000); + /// General-purpose I/Os + pub const GPIOF = @ptrCast(*volatile types.GPIOI, 0x40021400); + /// General-purpose I/Os + pub const GPIOG = @ptrCast(*volatile types.GPIOI, 0x40021800); + /// General-purpose I/Os + pub const GPIOH = @ptrCast(*volatile types.GPIOI, 0x40021c00); + /// General-purpose I/Os + pub const GPIOI = @ptrCast(*volatile types.GPIOI, 0x40022000); + /// General-purpose I/Os + pub const GPIOJ = @ptrCast(*volatile types.GPIOI, 0x40022400); + /// General-purpose I/Os + pub const GPIOK = @ptrCast(*volatile types.GPIOI, 0x40022800); + /// Cryptographic processor + pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000); + /// Reset and clock control + pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800); + /// FLASH + pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00); + /// DMA controller + pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000); + /// DMA controller + pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400); + /// Ethernet: media access control (MAC) + pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000); + /// Ethernet: MAC management counters + pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100); + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700); + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000); + /// USB on the go high speed + pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000); + /// USB on the go high speed + pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400); + /// USB on the go high speed + pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800); + /// USB on the go high speed + pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00); + /// USB on the go full speed + pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000); + /// USB on the go full speed + pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400); + /// USB on the go full speed + pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800); + /// USB on the go full speed + pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00); + /// Digital camera interface + pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000); + /// Cryptographic processor + pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000); + /// Hash processor + pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400); + /// Random number generator + pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800); + /// Flexible static memory controller + pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000); + /// System control block ACTLR + pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008); + /// SysTick timer + pub const STK = @ptrCast(*volatile types.STK, 0xe000e010); + /// Nested Vectored Interrupt Controller + pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100); + /// System control block + pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00); + /// Floating point unit CPACR + pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88); + /// Memory protection unit + pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90); + /// Nested vectored interrupt controller + pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00); + /// Floting point unit + pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34); + /// Debug support + pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000); + }; + }; +}; + +pub const types = struct { + /// Random number generator + pub const RNG = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Random number generator enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + padding: u28, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved5: u2, + /// Clock error interrupt status + CEIS: u1, + /// Seed error interrupt status + SEIS: u1, + padding: u25, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Random data + RNDATA: u32, + }), + }; + + /// Digital camera interface + pub const DCMI = extern struct { + /// control register 1 + CR: mmio.Mmio(packed struct(u32) { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization polarity + HSPOL: u1, + /// Vertical synchronization polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved14: u2, + /// DCMI enable + ENABLE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding: u29, + }), + /// raw interrupt status register + RIS: mmio.Mmio(packed struct(u32) { + /// Capture complete raw interrupt status + FRAME_RIS: u1, + /// Overrun raw interrupt status + OVR_RIS: u1, + /// Synchronization error raw interrupt status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding: u27, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding: u27, + }), + /// masked interrupt status register + MIS: mmio.Mmio(packed struct(u32) { + /// Capture complete masked interrupt status + FRAME_MIS: u1, + /// Overrun masked interrupt status + OVR_MIS: u1, + /// Synchronization error masked interrupt status + ERR_MIS: u1, + /// VSYNC masked interrupt status + VSYNC_MIS: u1, + /// Line masked interrupt status + LINE_MIS: u1, + padding: u27, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt status clear + FRAME_ISC: u1, + /// Overrun interrupt status clear + OVR_ISC: u1, + /// Synchronization error interrupt status clear + ERR_ISC: u1, + /// Vertical synch interrupt status clear + VSYNC_ISC: u1, + /// line interrupt status clear + LINE_ISC: u1, + padding: u27, + }), + /// embedded synchronization code register + ESCR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), + /// embedded synchronization unmask register + ESUR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter unmask + FSU: u8, + /// Line start delimiter unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), + /// crop window start + CWSTRT: mmio.Mmio(packed struct(u32) { + /// Horizontal offset count + HOFFCNT: u14, + reserved16: u2, + /// Vertical start line count + VST: u13, + padding: u3, + }), + /// crop window size + CWSIZE: mmio.Mmio(packed struct(u32) { + /// Capture count + CAPCNT: u14, + reserved16: u2, + /// Vertical line count + VLINE: u14, + padding: u2, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), + }; + + /// Flexible static memory controller + pub const FSMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved11: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 1 + BTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2 + BCR2: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 2 + BTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 3 + BCR3: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 3 + BTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 4 + BCR4: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 4 + BTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved96: [64]u8, + /// PC Card/NAND Flash control register 2 + PCR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 2 + PMEM2: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 2 + PATT2: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved116: [4]u8, + /// ECC result register 2 + ECCR2: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved128: [8]u8, + /// PC Card/NAND Flash control register 3 + PCR3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 3 + SR3: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 3 + PMEM3: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 3 + PATT3: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved148: [4]u8, + /// ECC result register 3 + ECCR3: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved160: [8]u8, + /// PC Card/NAND Flash control register 4 + PCR4: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 4 + SR4: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 4 + PMEM4: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 4 + PATT4: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1 + BWTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved268: [4]u8, + /// SRAM/NOR-Flash write timing registers 2 + BWTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved276: [4]u8, + /// SRAM/NOR-Flash write timing registers 3 + BWTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved284: [4]u8, + /// SRAM/NOR-Flash write timing registers 4 + BWTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + }; + + /// Debug support + pub const DBG = extern struct { + /// IDCODE + DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, + }), + /// Control Register + DBGMCU_CR: mmio.Mmio(packed struct(u32) { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + reserved16: u8, + /// DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT: u1, + /// DBG_TIM8_STOP + DBG_TIM8_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + padding: u11, + }), + /// Debug MCU APB1 Freeze registe + DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) { + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3 _STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_TIM12_STOP + DBG_TIM12_STOP: u1, + /// DBG_TIM13_STOP + DBG_TIM13_STOP: u1, + /// DBG_TIM14_STOP + DBG_TIM14_STOP: u1, + reserved11: u2, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_IWDEG_STOP + DBG_IWDEG_STOP: u1, + reserved21: u8, + /// DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT: u1, + /// DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT: u1, + /// DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT: u1, + reserved25: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding: u5, + }), + /// Debug MCU APB2 Freeze registe + DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) { + /// TIM1 counter stopped when core is halted + DBG_TIM1_STOP: u1, + /// TIM8 counter stopped when core is halted + DBG_TIM8_STOP: u1, + reserved16: u14, + /// TIM9 counter stopped when core is halted + DBG_TIM9_STOP: u1, + /// TIM10 counter stopped when core is halted + DBG_TIM10_STOP: u1, + /// TIM11 counter stopped when core is halted + DBG_TIM11_STOP: u1, + padding: u13, + }), + }; + + /// DMA controller + pub const DMA2 = extern struct { + /// low interrupt status register + LISR: mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF0: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF1: u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF1: u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF2: u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF3: u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF3: u1, + padding: u4, + }), + /// high interrupt status register + HISR: mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF4: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF5: u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF5: u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF6: u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF7: u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF7: u1, + padding: u4, + }), + /// low interrupt flag clear register + LIFCR: mmio.Mmio(packed struct(u32) { + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF0: u1, + reserved2: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF1: u1, + reserved8: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF1: u1, + reserved16: u4, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF2: u1, + reserved18: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF3: u1, + reserved24: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF3: u1, + padding: u4, + }), + /// high interrupt flag clear register + HIFCR: mmio.Mmio(packed struct(u32) { + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF4: u1, + reserved2: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF5: u1, + reserved8: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF5: u1, + reserved16: u4, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF6: u1, + reserved18: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF7: u1, + reserved24: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF7: u1, + padding: u4, + }), + /// stream x configuration register + S0CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + reserved21: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S0NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S0PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S0M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S0M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S0FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S1CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S1NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S1PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S1M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S1M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S1FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S2CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S2NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S2PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S2M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S2M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S2FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S3CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S3NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S3PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S3M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S3M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S3FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S4CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S4NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S4PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S4M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S4M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S4FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S5CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S5NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S5PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S5M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S5M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S5FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S6CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S6NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S6PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S6M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S6M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S6FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S7CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S7NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S7PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S7M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S7M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S7FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + }; + + /// System control block ACTLR + pub const SCB_ACTRL = extern struct { + /// Auxiliary control register + ACTRL: mmio.Mmio(packed struct(u32) { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved8: u5, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding: u22, + }), + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding: u4, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM0: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM1: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM2: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM3: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM4: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM5: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN0: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN1: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN2: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN3: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN4: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN5: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN6: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN7: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN8: u1, + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP0: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP1: u1, + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: u1, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ0: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ1: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ2: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ3: u1, + padding: u4, + }), + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW0: u1, + /// System clock switch + SW1: u1, + /// System clock switch status + SWS0: u1, + /// System clock switch status + SWS1: u1, + /// AHB prescaler + HPRE: u4, + reserved10: u2, + /// APB Low speed prescaler (APB1) + PPRE1: u3, + /// APB high-speed prescaler (APB2) + PPRE2: u3, + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1: u2, + /// I2S clock selection + I2SSRC: u1, + /// MCO1 prescaler + MCO1PRE: u3, + /// MCO2 prescaler + MCO2PRE: u3, + /// Microcontroller clock output 2 + MCO2: u2, + }), + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt flag + PLLRDYF: u1, + /// PLLI2S ready interrupt flag + PLLI2SRDYF: u1, + reserved7: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt enable + PLLI2SRDYIE: u1, + reserved16: u2, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt clear + PLLRDYC: u1, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved25: u2, + /// Ethernet MAC reset + ETHMACRST: u1, + reserved29: u3, + /// USB OTG HS module reset + OTGHSRST: u1, + padding: u2, + }), + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// Camera interface reset + DCMIRST: u1, + reserved6: u5, + /// Random number generator module reset + RNGRST: u1, + /// USB OTG FS module reset + OTGFSRST: u1, + padding: u24, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module reset + FSMCRST: u1, + padding: u31, + }), + reserved32: [4]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved25: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding: u2, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved4: u2, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved8: u2, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved11: u2, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding: u13, + }), + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved18: u5, + /// Backup SRAM interface clock enable + BKPSRAMEN: u1, + reserved21: u2, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved25: u2, + /// Ethernet MAC clock enable + ETHMACEN: u1, + /// Ethernet Transmission clock enable + ETHMACTXEN: u1, + /// Ethernet Reception clock enable + ETHMACRXEN: u1, + /// Ethernet PTP clock enable + ETHMACPTPEN: u1, + /// USB OTG HS clock enable + OTGHSEN: u1, + /// USB OTG HSULPI clock enable + OTGHSULPIEN: u1, + padding: u1, + }), + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable + DCMIEN: u1, + reserved6: u5, + /// Random number generator clock enable + RNGEN: u1, + /// USB OTG FS clock enable + OTGFSEN: u1, + padding: u24, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable + FSMCEN: u1, + padding: u31, + }), + reserved64: [4]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved25: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved8: u2, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved16: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + padding: u13, + }), + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep mode + GPIOILPEN: u1, + reserved12: u3, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + reserved15: u2, + /// Flash interface clock enable during Sleep mode + FLITFLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable during Sleep mode + BKPSRAMLPEN: u1, + reserved21: u2, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + reserved25: u2, + /// Ethernet MAC clock enable during Sleep mode + ETHMACLPEN: u1, + /// Ethernet transmission clock enable during Sleep mode + ETHMACTXLPEN: u1, + /// Ethernet reception clock enable during Sleep mode + ETHMACRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep mode + ETHMACPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep mode + OTGHSLPEN: u1, + /// USB OTG HS ULPI clock enable during Sleep mode + OTGHSULPILPEN: u1, + padding: u1, + }), + /// AHB2 peripheral clock enable in low power mode register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable during Sleep mode + DCMILPEN: u1, + reserved6: u5, + /// Random number generator clock enable during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep mode + OTGFSLPEN: u1, + padding: u24, + }), + /// AHB3 peripheral clock enable in low power mode register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// Flexible static memory controller module clock enable during Sleep mode + FSMCLPEN: u1, + padding: u31, + }), + reserved96: [4]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during Sleep mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep mode + TIM14LPEN: u1, + reserved11: u2, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 clock enable during Sleep mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep mode + SPI3LPEN: u1, + reserved17: u1, + /// USART2 clock enable during Sleep mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep mode + I2C3LPEN: u1, + reserved25: u1, + /// CAN 1 clock enable during Sleep mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep mode + CAN2LPEN: u1, + reserved28: u1, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + padding: u2, + }), + /// APB2 peripheral clock enabled in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable during Sleep mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + reserved8: u2, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + reserved14: u1, + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + reserved16: u1, + /// TIM9 clock enable during sleep mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + padding: u13, + }), + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL0: u1, + /// RTC clock source selection + RTCSEL1: u1, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// clock control & status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: u1, + /// Spread spectrum modulation enable + SSCGEN: u1, + }), + /// PLLI2S configuration register + PLLI2SCFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLLI2S multiplication factor for VCO + PLLI2SNx: u9, + reserved28: u13, + /// PLLI2S division factor for I2S clocks + PLLI2SRx: u3, + padding: u1, + }), + }; + + /// General-purpose I/Os + pub const GPIOI = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = extern struct { + /// Coprocessor access control register + CPACR: mmio.Mmio(packed struct(u32) { + reserved20: u20, + /// CP + CP: u4, + padding: u8, + }), + }; + + /// Nested vectored interrupt controller + pub const NVIC_STIR = extern struct { + /// Software trigger interrupt register + STIR: mmio.Mmio(packed struct(u32) { + /// Software generated interrupt ID + INTID: u9, + padding: u23, + }), + }; + + /// System control block + pub const SCB = extern struct { + /// CPUID base register + CPUID: mmio.Mmio(packed struct(u32) { + /// Revision number + Revision: u4, + /// Part number of the processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), + /// Interrupt control and state register + ICSR: mmio.Mmio(packed struct(u32) { + /// Active vector + VECTACTIVE: u9, + reserved11: u2, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved22: u3, + /// Interrupt pending flag + ISRPENDING: u1, + reserved25: u2, + /// SysTick exception clear-pending bit + PENDSTCLR: u1, + /// SysTick exception set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved31: u2, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), + /// Vector table offset register + VTOR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// Vector table base offset field + TBLOFF: u21, + padding: u2, + }), + /// Application interrupt and reset control register + AIRCR: mmio.Mmio(packed struct(u32) { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved8: u5, + /// PRIGROUP + PRIGROUP: u3, + reserved15: u4, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), + /// System control register + SCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved4: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding: u27, + }), + /// Configuration and control register + CCR: mmio.Mmio(packed struct(u32) { + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved3: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved8: u3, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding: u22, + }), + /// System handler priority registers + SHPR1: mmio.Mmio(packed struct(u32) { + /// Priority of system handler 4 + PRI_4: u8, + /// Priority of system handler 5 + PRI_5: u8, + /// Priority of system handler 6 + PRI_6: u8, + padding: u8, + }), + /// System handler priority registers + SHPR2: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// Priority of system handler 11 + PRI_11: u8, + }), + /// System handler priority registers + SHPR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Priority of system handler 14 + PRI_14: u8, + /// Priority of system handler 15 + PRI_15: u8, + }), + /// System handler control and state register + SHCRS: mmio.Mmio(packed struct(u32) { + /// Memory management fault exception active bit + MEMFAULTACT: u1, + /// Bus fault exception active bit + BUSFAULTACT: u1, + reserved3: u1, + /// Usage fault exception active bit + USGFAULTACT: u1, + reserved7: u3, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved10: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// Usage fault exception pending bit + USGFAULTPENDED: u1, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding: u13, + }), + /// Configurable fault status register + CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Instruction access violation flag + IACCVIOL: u1, + reserved3: u1, + /// Memory manager fault on unstacking for a return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved7: u1, + /// Memory Management Fault Address Register (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception entry + STKERR: u1, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1, + reserved15: u1, + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1, + /// Undefined instruction usage fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage fault + INVPC: u1, + /// No coprocessor usage fault. + NOCP: u1, + reserved24: u4, + /// Unaligned access usage fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding: u6, + }), + /// Hard fault status register + HFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved30: u28, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), + reserved52: [4]u8, + /// Memory management fault address register + MMFAR: mmio.Mmio(packed struct(u32) { + /// Memory management fault address + MMFAR: u32, + }), + /// Bus fault address register + BFAR: mmio.Mmio(packed struct(u32) { + /// Bus fault address + BFAR: u32, + }), + /// Auxiliary fault status register + AFSR: mmio.Mmio(packed struct(u32) { + /// Implementation defined + IMPDEF: u32, + }), + }; + + /// SysTick timer + pub const STK = extern struct { + /// SysTick control and status register + CTRL: mmio.Mmio(packed struct(u32) { + /// Counter enable + ENABLE: u1, + /// SysTick exception request enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved16: u13, + /// COUNTFLAG + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick reload value register + LOAD: mmio.Mmio(packed struct(u32) { + /// RELOAD value + RELOAD: u24, + padding: u8, + }), + /// SysTick current value register + VAL: mmio.Mmio(packed struct(u32) { + /// Current counter value + CURRENT: u24, + padding: u8, + }), + /// SysTick calibration value register + CALIB: mmio.Mmio(packed struct(u32) { + /// Calibration value + TENMS: u24, + reserved30: u6, + /// SKEW flag: Indicates whether the TENMS value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), + }; + + /// Memory protection unit + pub const MPU = extern struct { + /// MPU type register + MPU_TYPER: mmio.Mmio(packed struct(u32) { + /// Separate flag + SEPARATE: u1, + reserved8: u7, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction regions + IREGION: u8, + padding: u8, + }), + /// MPU control register + MPU_CTRL: mmio.Mmio(packed struct(u32) { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1, + padding: u29, + }), + /// MPU region number register + MPU_RNR: mmio.Mmio(packed struct(u32) { + /// MPU region + REGION: u8, + padding: u24, + }), + /// MPU region base address register + MPU_RBAR: mmio.Mmio(packed struct(u32) { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), + /// MPU region attribute and size register + MPU_RASR: mmio.Mmio(packed struct(u32) { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection region + SIZE: u5, + reserved8: u2, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved24: u2, + /// Access permission + AP: u3, + reserved28: u1, + /// Instruction access disable bit + XN: u1, + padding: u3, + }), + }; + + /// Floting point unit + pub const FPU = extern struct { + /// Floating-point context control register + FPCCR: mmio.Mmio(packed struct(u32) { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved3: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved8: u1, + /// MONRDY + MONRDY: u1, + reserved30: u21, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), + /// Floating-point context address register + FPCAR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Location of unpopulated floating-point + ADDRESS: u29, + }), + /// Floating-point status control register + FPSCR: mmio.Mmio(packed struct(u32) { + /// Invalid operation cumulative exception bit + IOC: u1, + /// Division by zero cumulative exception bit. + DZC: u1, + /// Overflow cumulative exception bit + OFC: u1, + /// Underflow cumulative exception bit + UFC: u1, + /// Inexact cumulative exception bit + IXC: u1, + reserved7: u2, + /// Input denormal cumulative exception bit. + IDC: u1, + reserved22: u14, + /// Rounding Mode control field + RMode: u2, + /// Flush-to-zero mode control bit: + FZ: u1, + /// Default NaN mode control bit + DN: u1, + /// Alternative half-precision control bit + AHP: u1, + reserved28: u1, + /// Overflow condition code flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code flag + N: u1, + }), + }; + + /// Cryptographic processor + pub const CRYP = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction + ALGODIR: u1, + /// Algorithm mode + ALGOMODE0: u3, + /// Data type selection + DATATYPE: u2, + /// Key size selection (AES mode only) + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush + FFLUSH: u1, + /// Cryptographic processor enable + CRYPEN: u1, + /// GCM_CCMPH + GCM_CCMPH: u2, + reserved19: u1, + /// ALGOMODE + ALGOMODE3: u1, + padding: u12, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty + IFEM: u1, + /// Input FIFO not full + IFNF: u1, + /// Output FIFO not empty + OFNE: u1, + /// Output FIFO full + OFFU: u1, + /// Busy bit + BUSY: u1, + padding: u27, + }), + /// data input register + DIN: mmio.Mmio(packed struct(u32) { + /// Data input + DATAIN: u32, + }), + /// data output register + DOUT: mmio.Mmio(packed struct(u32) { + /// Data output + DATAOUT: u32, + }), + /// DMA control register + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable + DIEN: u1, + /// DMA output enable + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask + INIM: u1, + /// Output FIFO service interrupt mask + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status + INRIS: u1, + /// Output FIFO service raw interrupt status + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status + INMIS: u1, + /// Output FIFO service masked interrupt status + OUTMIS: u1, + padding: u30, + }), + /// key registers + K0LR: mmio.Mmio(packed struct(u32) { + /// b224 + b224: u1, + /// b225 + b225: u1, + /// b226 + b226: u1, + /// b227 + b227: u1, + /// b228 + b228: u1, + /// b229 + b229: u1, + /// b230 + b230: u1, + /// b231 + b231: u1, + /// b232 + b232: u1, + /// b233 + b233: u1, + /// b234 + b234: u1, + /// b235 + b235: u1, + /// b236 + b236: u1, + /// b237 + b237: u1, + /// b238 + b238: u1, + /// b239 + b239: u1, + /// b240 + b240: u1, + /// b241 + b241: u1, + /// b242 + b242: u1, + /// b243 + b243: u1, + /// b244 + b244: u1, + /// b245 + b245: u1, + /// b246 + b246: u1, + /// b247 + b247: u1, + /// b248 + b248: u1, + /// b249 + b249: u1, + /// b250 + b250: u1, + /// b251 + b251: u1, + /// b252 + b252: u1, + /// b253 + b253: u1, + /// b254 + b254: u1, + /// b255 + b255: u1, + }), + /// key registers + K0RR: mmio.Mmio(packed struct(u32) { + /// b192 + b192: u1, + /// b193 + b193: u1, + /// b194 + b194: u1, + /// b195 + b195: u1, + /// b196 + b196: u1, + /// b197 + b197: u1, + /// b198 + b198: u1, + /// b199 + b199: u1, + /// b200 + b200: u1, + /// b201 + b201: u1, + /// b202 + b202: u1, + /// b203 + b203: u1, + /// b204 + b204: u1, + /// b205 + b205: u1, + /// b206 + b206: u1, + /// b207 + b207: u1, + /// b208 + b208: u1, + /// b209 + b209: u1, + /// b210 + b210: u1, + /// b211 + b211: u1, + /// b212 + b212: u1, + /// b213 + b213: u1, + /// b214 + b214: u1, + /// b215 + b215: u1, + /// b216 + b216: u1, + /// b217 + b217: u1, + /// b218 + b218: u1, + /// b219 + b219: u1, + /// b220 + b220: u1, + /// b221 + b221: u1, + /// b222 + b222: u1, + /// b223 + b223: u1, + }), + /// key registers + K1LR: mmio.Mmio(packed struct(u32) { + /// b160 + b160: u1, + /// b161 + b161: u1, + /// b162 + b162: u1, + /// b163 + b163: u1, + /// b164 + b164: u1, + /// b165 + b165: u1, + /// b166 + b166: u1, + /// b167 + b167: u1, + /// b168 + b168: u1, + /// b169 + b169: u1, + /// b170 + b170: u1, + /// b171 + b171: u1, + /// b172 + b172: u1, + /// b173 + b173: u1, + /// b174 + b174: u1, + /// b175 + b175: u1, + /// b176 + b176: u1, + /// b177 + b177: u1, + /// b178 + b178: u1, + /// b179 + b179: u1, + /// b180 + b180: u1, + /// b181 + b181: u1, + /// b182 + b182: u1, + /// b183 + b183: u1, + /// b184 + b184: u1, + /// b185 + b185: u1, + /// b186 + b186: u1, + /// b187 + b187: u1, + /// b188 + b188: u1, + /// b189 + b189: u1, + /// b190 + b190: u1, + /// b191 + b191: u1, + }), + /// key registers + K1RR: mmio.Mmio(packed struct(u32) { + /// b128 + b128: u1, + /// b129 + b129: u1, + /// b130 + b130: u1, + /// b131 + b131: u1, + /// b132 + b132: u1, + /// b133 + b133: u1, + /// b134 + b134: u1, + /// b135 + b135: u1, + /// b136 + b136: u1, + /// b137 + b137: u1, + /// b138 + b138: u1, + /// b139 + b139: u1, + /// b140 + b140: u1, + /// b141 + b141: u1, + /// b142 + b142: u1, + /// b143 + b143: u1, + /// b144 + b144: u1, + /// b145 + b145: u1, + /// b146 + b146: u1, + /// b147 + b147: u1, + /// b148 + b148: u1, + /// b149 + b149: u1, + /// b150 + b150: u1, + /// b151 + b151: u1, + /// b152 + b152: u1, + /// b153 + b153: u1, + /// b154 + b154: u1, + /// b155 + b155: u1, + /// b156 + b156: u1, + /// b157 + b157: u1, + /// b158 + b158: u1, + /// b159 + b159: u1, + }), + /// key registers + K2LR: mmio.Mmio(packed struct(u32) { + /// b96 + b96: u1, + /// b97 + b97: u1, + /// b98 + b98: u1, + /// b99 + b99: u1, + /// b100 + b100: u1, + /// b101 + b101: u1, + /// b102 + b102: u1, + /// b103 + b103: u1, + /// b104 + b104: u1, + /// b105 + b105: u1, + /// b106 + b106: u1, + /// b107 + b107: u1, + /// b108 + b108: u1, + /// b109 + b109: u1, + /// b110 + b110: u1, + /// b111 + b111: u1, + /// b112 + b112: u1, + /// b113 + b113: u1, + /// b114 + b114: u1, + /// b115 + b115: u1, + /// b116 + b116: u1, + /// b117 + b117: u1, + /// b118 + b118: u1, + /// b119 + b119: u1, + /// b120 + b120: u1, + /// b121 + b121: u1, + /// b122 + b122: u1, + /// b123 + b123: u1, + /// b124 + b124: u1, + /// b125 + b125: u1, + /// b126 + b126: u1, + /// b127 + b127: u1, + }), + /// key registers + K2RR: mmio.Mmio(packed struct(u32) { + /// b64 + b64: u1, + /// b65 + b65: u1, + /// b66 + b66: u1, + /// b67 + b67: u1, + /// b68 + b68: u1, + /// b69 + b69: u1, + /// b70 + b70: u1, + /// b71 + b71: u1, + /// b72 + b72: u1, + /// b73 + b73: u1, + /// b74 + b74: u1, + /// b75 + b75: u1, + /// b76 + b76: u1, + /// b77 + b77: u1, + /// b78 + b78: u1, + /// b79 + b79: u1, + /// b80 + b80: u1, + /// b81 + b81: u1, + /// b82 + b82: u1, + /// b83 + b83: u1, + /// b84 + b84: u1, + /// b85 + b85: u1, + /// b86 + b86: u1, + /// b87 + b87: u1, + /// b88 + b88: u1, + /// b89 + b89: u1, + /// b90 + b90: u1, + /// b91 + b91: u1, + /// b92 + b92: u1, + /// b93 + b93: u1, + /// b94 + b94: u1, + /// b95 + b95: u1, + }), + /// key registers + K3LR: mmio.Mmio(packed struct(u32) { + /// b32 + b32: u1, + /// b33 + b33: u1, + /// b34 + b34: u1, + /// b35 + b35: u1, + /// b36 + b36: u1, + /// b37 + b37: u1, + /// b38 + b38: u1, + /// b39 + b39: u1, + /// b40 + b40: u1, + /// b41 + b41: u1, + /// b42 + b42: u1, + /// b43 + b43: u1, + /// b44 + b44: u1, + /// b45 + b45: u1, + /// b46 + b46: u1, + /// b47 + b47: u1, + /// b48 + b48: u1, + /// b49 + b49: u1, + /// b50 + b50: u1, + /// b51 + b51: u1, + /// b52 + b52: u1, + /// b53 + b53: u1, + /// b54 + b54: u1, + /// b55 + b55: u1, + /// b56 + b56: u1, + /// b57 + b57: u1, + /// b58 + b58: u1, + /// b59 + b59: u1, + /// b60 + b60: u1, + /// b61 + b61: u1, + /// b62 + b62: u1, + /// b63 + b63: u1, + }), + /// key registers + K3RR: mmio.Mmio(packed struct(u32) { + /// b0 + b0: u1, + /// b1 + b1: u1, + /// b2 + b2: u1, + /// b3 + b3: u1, + /// b4 + b4: u1, + /// b5 + b5: u1, + /// b6 + b6: u1, + /// b7 + b7: u1, + /// b8 + b8: u1, + /// b9 + b9: u1, + /// b10 + b10: u1, + /// b11 + b11: u1, + /// b12 + b12: u1, + /// b13 + b13: u1, + /// b14 + b14: u1, + /// b15 + b15: u1, + /// b16 + b16: u1, + /// b17 + b17: u1, + /// b18 + b18: u1, + /// b19 + b19: u1, + /// b20 + b20: u1, + /// b21 + b21: u1, + /// b22 + b22: u1, + /// b23 + b23: u1, + /// b24 + b24: u1, + /// b25 + b25: u1, + /// b26 + b26: u1, + /// b27 + b27: u1, + /// b28 + b28: u1, + /// b29 + b29: u1, + /// b30 + b30: u1, + /// b31 + b31: u1, + }), + /// initialization vector registers + IV0LR: mmio.Mmio(packed struct(u32) { + /// IV31 + IV31: u1, + /// IV30 + IV30: u1, + /// IV29 + IV29: u1, + /// IV28 + IV28: u1, + /// IV27 + IV27: u1, + /// IV26 + IV26: u1, + /// IV25 + IV25: u1, + /// IV24 + IV24: u1, + /// IV23 + IV23: u1, + /// IV22 + IV22: u1, + /// IV21 + IV21: u1, + /// IV20 + IV20: u1, + /// IV19 + IV19: u1, + /// IV18 + IV18: u1, + /// IV17 + IV17: u1, + /// IV16 + IV16: u1, + /// IV15 + IV15: u1, + /// IV14 + IV14: u1, + /// IV13 + IV13: u1, + /// IV12 + IV12: u1, + /// IV11 + IV11: u1, + /// IV10 + IV10: u1, + /// IV9 + IV9: u1, + /// IV8 + IV8: u1, + /// IV7 + IV7: u1, + /// IV6 + IV6: u1, + /// IV5 + IV5: u1, + /// IV4 + IV4: u1, + /// IV3 + IV3: u1, + /// IV2 + IV2: u1, + /// IV1 + IV1: u1, + /// IV0 + IV0: u1, + }), + /// initialization vector registers + IV0RR: mmio.Mmio(packed struct(u32) { + /// IV63 + IV63: u1, + /// IV62 + IV62: u1, + /// IV61 + IV61: u1, + /// IV60 + IV60: u1, + /// IV59 + IV59: u1, + /// IV58 + IV58: u1, + /// IV57 + IV57: u1, + /// IV56 + IV56: u1, + /// IV55 + IV55: u1, + /// IV54 + IV54: u1, + /// IV53 + IV53: u1, + /// IV52 + IV52: u1, + /// IV51 + IV51: u1, + /// IV50 + IV50: u1, + /// IV49 + IV49: u1, + /// IV48 + IV48: u1, + /// IV47 + IV47: u1, + /// IV46 + IV46: u1, + /// IV45 + IV45: u1, + /// IV44 + IV44: u1, + /// IV43 + IV43: u1, + /// IV42 + IV42: u1, + /// IV41 + IV41: u1, + /// IV40 + IV40: u1, + /// IV39 + IV39: u1, + /// IV38 + IV38: u1, + /// IV37 + IV37: u1, + /// IV36 + IV36: u1, + /// IV35 + IV35: u1, + /// IV34 + IV34: u1, + /// IV33 + IV33: u1, + /// IV32 + IV32: u1, + }), + /// initialization vector registers + IV1LR: mmio.Mmio(packed struct(u32) { + /// IV95 + IV95: u1, + /// IV94 + IV94: u1, + /// IV93 + IV93: u1, + /// IV92 + IV92: u1, + /// IV91 + IV91: u1, + /// IV90 + IV90: u1, + /// IV89 + IV89: u1, + /// IV88 + IV88: u1, + /// IV87 + IV87: u1, + /// IV86 + IV86: u1, + /// IV85 + IV85: u1, + /// IV84 + IV84: u1, + /// IV83 + IV83: u1, + /// IV82 + IV82: u1, + /// IV81 + IV81: u1, + /// IV80 + IV80: u1, + /// IV79 + IV79: u1, + /// IV78 + IV78: u1, + /// IV77 + IV77: u1, + /// IV76 + IV76: u1, + /// IV75 + IV75: u1, + /// IV74 + IV74: u1, + /// IV73 + IV73: u1, + /// IV72 + IV72: u1, + /// IV71 + IV71: u1, + /// IV70 + IV70: u1, + /// IV69 + IV69: u1, + /// IV68 + IV68: u1, + /// IV67 + IV67: u1, + /// IV66 + IV66: u1, + /// IV65 + IV65: u1, + /// IV64 + IV64: u1, + }), + /// initialization vector registers + IV1RR: mmio.Mmio(packed struct(u32) { + /// IV127 + IV127: u1, + /// IV126 + IV126: u1, + /// IV125 + IV125: u1, + /// IV124 + IV124: u1, + /// IV123 + IV123: u1, + /// IV122 + IV122: u1, + /// IV121 + IV121: u1, + /// IV120 + IV120: u1, + /// IV119 + IV119: u1, + /// IV118 + IV118: u1, + /// IV117 + IV117: u1, + /// IV116 + IV116: u1, + /// IV115 + IV115: u1, + /// IV114 + IV114: u1, + /// IV113 + IV113: u1, + /// IV112 + IV112: u1, + /// IV111 + IV111: u1, + /// IV110 + IV110: u1, + /// IV109 + IV109: u1, + /// IV108 + IV108: u1, + /// IV107 + IV107: u1, + /// IV106 + IV106: u1, + /// IV105 + IV105: u1, + /// IV104 + IV104: u1, + /// IV103 + IV103: u1, + /// IV102 + IV102: u1, + /// IV101 + IV101: u1, + /// IV100 + IV100: u1, + /// IV99 + IV99: u1, + /// IV98 + IV98: u1, + /// IV97 + IV97: u1, + /// IV96 + IV96: u1, + }), + /// context swap register + CSGCMCCM0R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM0R + CSGCMCCM0R: u32, + }), + /// context swap register + CSGCMCCM1R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM1R + CSGCMCCM1R: u32, + }), + /// context swap register + CSGCMCCM2R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM2R + CSGCMCCM2R: u32, + }), + /// context swap register + CSGCMCCM3R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM3R + CSGCMCCM3R: u32, + }), + /// context swap register + CSGCMCCM4R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM4R + CSGCMCCM4R: u32, + }), + /// context swap register + CSGCMCCM5R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM5R + CSGCMCCM5R: u32, + }), + /// context swap register + CSGCMCCM6R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM6R + CSGCMCCM6R: u32, + }), + /// context swap register + CSGCMCCM7R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM7R + CSGCMCCM7R: u32, + }), + /// context swap register + CSGCM0R: mmio.Mmio(packed struct(u32) { + /// CSGCM0R + CSGCM0R: u32, + }), + /// context swap register + CSGCM1R: mmio.Mmio(packed struct(u32) { + /// CSGCM1R + CSGCM1R: u32, + }), + /// context swap register + CSGCM2R: mmio.Mmio(packed struct(u32) { + /// CSGCM2R + CSGCM2R: u32, + }), + /// context swap register + CSGCM3R: mmio.Mmio(packed struct(u32) { + /// CSGCM3R + CSGCM3R: u32, + }), + /// context swap register + CSGCM4R: mmio.Mmio(packed struct(u32) { + /// CSGCM4R + CSGCM4R: u32, + }), + /// context swap register + CSGCM5R: mmio.Mmio(packed struct(u32) { + /// CSGCM5R + CSGCM5R: u32, + }), + /// context swap register + CSGCM6R: mmio.Mmio(packed struct(u32) { + /// CSGCM6R + CSGCM6R: u32, + }), + /// context swap register + CSGCM7R: mmio.Mmio(packed struct(u32) { + /// CSGCM7R + CSGCM7R: u32, + }), + }; + + /// Hash processor + pub const HASH = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation + INIT: u1, + /// DMA enable + DMAE: u1, + /// Data type selection + DATATYPE: u2, + /// Mode selection + MODE: u1, + /// Algorithm selection + ALGO0: u1, + /// Number of words already pushed + NBW: u4, + /// DIN not empty + DINNE: u1, + /// Multiple DMA Transfers + MDMAT: u1, + reserved16: u2, + /// Long key selection + LKEY: u1, + reserved18: u1, + /// ALGO + ALGO1: u1, + padding: u13, + }), + /// data input register + DIN: mmio.Mmio(packed struct(u32) { + /// Data input + DATAIN: u32, + }), + /// start register + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message + NBLW: u5, + reserved8: u3, + /// Digest calculation + DCAL: u1, + padding: u23, + }), + /// digest registers + HR0: mmio.Mmio(packed struct(u32) { + /// H0 + H0: u32, + }), + /// digest registers + HR1: mmio.Mmio(packed struct(u32) { + /// H1 + H1: u32, + }), + /// digest registers + HR2: mmio.Mmio(packed struct(u32) { + /// H2 + H2: u32, + }), + /// digest registers + HR3: mmio.Mmio(packed struct(u32) { + /// H3 + H3: u32, + }), + /// digest registers + HR4: mmio.Mmio(packed struct(u32) { + /// H4 + H4: u32, + }), + /// interrupt enable register + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable + DINIE: u1, + /// Digest calculation completion interrupt enable + DCIE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status + DINIS: u1, + /// Digest calculation completion interrupt status + DCIS: u1, + /// DMA Status + DMAS: u1, + /// Busy bit + BUSY: u1, + padding: u28, + }), + reserved248: [208]u8, + /// context swap registers + CSR0: mmio.Mmio(packed struct(u32) { + /// CSR0 + CSR0: u32, + }), + /// context swap registers + CSR1: mmio.Mmio(packed struct(u32) { + /// CSR1 + CSR1: u32, + }), + /// context swap registers + CSR2: mmio.Mmio(packed struct(u32) { + /// CSR2 + CSR2: u32, + }), + /// context swap registers + CSR3: mmio.Mmio(packed struct(u32) { + /// CSR3 + CSR3: u32, + }), + /// context swap registers + CSR4: mmio.Mmio(packed struct(u32) { + /// CSR4 + CSR4: u32, + }), + /// context swap registers + CSR5: mmio.Mmio(packed struct(u32) { + /// CSR5 + CSR5: u32, + }), + /// context swap registers + CSR6: mmio.Mmio(packed struct(u32) { + /// CSR6 + CSR6: u32, + }), + /// context swap registers + CSR7: mmio.Mmio(packed struct(u32) { + /// CSR7 + CSR7: u32, + }), + /// context swap registers + CSR8: mmio.Mmio(packed struct(u32) { + /// CSR8 + CSR8: u32, + }), + /// context swap registers + CSR9: mmio.Mmio(packed struct(u32) { + /// CSR9 + CSR9: u32, + }), + /// context swap registers + CSR10: mmio.Mmio(packed struct(u32) { + /// CSR10 + CSR10: u32, + }), + /// context swap registers + CSR11: mmio.Mmio(packed struct(u32) { + /// CSR11 + CSR11: u32, + }), + /// context swap registers + CSR12: mmio.Mmio(packed struct(u32) { + /// CSR12 + CSR12: u32, + }), + /// context swap registers + CSR13: mmio.Mmio(packed struct(u32) { + /// CSR13 + CSR13: u32, + }), + /// context swap registers + CSR14: mmio.Mmio(packed struct(u32) { + /// CSR14 + CSR14: u32, + }), + /// context swap registers + CSR15: mmio.Mmio(packed struct(u32) { + /// CSR15 + CSR15: u32, + }), + /// context swap registers + CSR16: mmio.Mmio(packed struct(u32) { + /// CSR16 + CSR16: u32, + }), + /// context swap registers + CSR17: mmio.Mmio(packed struct(u32) { + /// CSR17 + CSR17: u32, + }), + /// context swap registers + CSR18: mmio.Mmio(packed struct(u32) { + /// CSR18 + CSR18: u32, + }), + /// context swap registers + CSR19: mmio.Mmio(packed struct(u32) { + /// CSR19 + CSR19: u32, + }), + /// context swap registers + CSR20: mmio.Mmio(packed struct(u32) { + /// CSR20 + CSR20: u32, + }), + /// context swap registers + CSR21: mmio.Mmio(packed struct(u32) { + /// CSR21 + CSR21: u32, + }), + /// context swap registers + CSR22: mmio.Mmio(packed struct(u32) { + /// CSR22 + CSR22: u32, + }), + /// context swap registers + CSR23: mmio.Mmio(packed struct(u32) { + /// CSR23 + CSR23: u32, + }), + /// context swap registers + CSR24: mmio.Mmio(packed struct(u32) { + /// CSR24 + CSR24: u32, + }), + /// context swap registers + CSR25: mmio.Mmio(packed struct(u32) { + /// CSR25 + CSR25: u32, + }), + /// context swap registers + CSR26: mmio.Mmio(packed struct(u32) { + /// CSR26 + CSR26: u32, + }), + /// context swap registers + CSR27: mmio.Mmio(packed struct(u32) { + /// CSR27 + CSR27: u32, + }), + /// context swap registers + CSR28: mmio.Mmio(packed struct(u32) { + /// CSR28 + CSR28: u32, + }), + /// context swap registers + CSR29: mmio.Mmio(packed struct(u32) { + /// CSR29 + CSR29: u32, + }), + /// context swap registers + CSR30: mmio.Mmio(packed struct(u32) { + /// CSR30 + CSR30: u32, + }), + /// context swap registers + CSR31: mmio.Mmio(packed struct(u32) { + /// CSR31 + CSR31: u32, + }), + /// context swap registers + CSR32: mmio.Mmio(packed struct(u32) { + /// CSR32 + CSR32: u32, + }), + /// context swap registers + CSR33: mmio.Mmio(packed struct(u32) { + /// CSR33 + CSR33: u32, + }), + /// context swap registers + CSR34: mmio.Mmio(packed struct(u32) { + /// CSR34 + CSR34: u32, + }), + /// context swap registers + CSR35: mmio.Mmio(packed struct(u32) { + /// CSR35 + CSR35: u32, + }), + /// context swap registers + CSR36: mmio.Mmio(packed struct(u32) { + /// CSR36 + CSR36: u32, + }), + /// context swap registers + CSR37: mmio.Mmio(packed struct(u32) { + /// CSR37 + CSR37: u32, + }), + /// context swap registers + CSR38: mmio.Mmio(packed struct(u32) { + /// CSR38 + CSR38: u32, + }), + /// context swap registers + CSR39: mmio.Mmio(packed struct(u32) { + /// CSR39 + CSR39: u32, + }), + /// context swap registers + CSR40: mmio.Mmio(packed struct(u32) { + /// CSR40 + CSR40: u32, + }), + /// context swap registers + CSR41: mmio.Mmio(packed struct(u32) { + /// CSR41 + CSR41: u32, + }), + /// context swap registers + CSR42: mmio.Mmio(packed struct(u32) { + /// CSR42 + CSR42: u32, + }), + /// context swap registers + CSR43: mmio.Mmio(packed struct(u32) { + /// CSR43 + CSR43: u32, + }), + /// context swap registers + CSR44: mmio.Mmio(packed struct(u32) { + /// CSR44 + CSR44: u32, + }), + /// context swap registers + CSR45: mmio.Mmio(packed struct(u32) { + /// CSR45 + CSR45: u32, + }), + /// context swap registers + CSR46: mmio.Mmio(packed struct(u32) { + /// CSR46 + CSR46: u32, + }), + /// context swap registers + CSR47: mmio.Mmio(packed struct(u32) { + /// CSR47 + CSR47: u32, + }), + /// context swap registers + CSR48: mmio.Mmio(packed struct(u32) { + /// CSR48 + CSR48: u32, + }), + /// context swap registers + CSR49: mmio.Mmio(packed struct(u32) { + /// CSR49 + CSR49: u32, + }), + /// context swap registers + CSR50: mmio.Mmio(packed struct(u32) { + /// CSR50 + CSR50: u32, + }), + /// context swap registers + CSR51: mmio.Mmio(packed struct(u32) { + /// CSR51 + CSR51: u32, + }), + /// context swap registers + CSR52: mmio.Mmio(packed struct(u32) { + /// CSR52 + CSR52: u32, + }), + /// context swap registers + CSR53: mmio.Mmio(packed struct(u32) { + /// CSR53 + CSR53: u32, + }), + reserved784: [320]u8, + /// HASH digest register + HASH_HR0: mmio.Mmio(packed struct(u32) { + /// H0 + H0: u32, + }), + /// read-only + HASH_HR1: mmio.Mmio(packed struct(u32) { + /// H1 + H1: u32, + }), + /// read-only + HASH_HR2: mmio.Mmio(packed struct(u32) { + /// H2 + H2: u32, + }), + /// read-only + HASH_HR3: mmio.Mmio(packed struct(u32) { + /// H3 + H3: u32, + }), + /// read-only + HASH_HR4: mmio.Mmio(packed struct(u32) { + /// H4 + H4: u32, + }), + /// read-only + HASH_HR5: mmio.Mmio(packed struct(u32) { + /// H5 + H5: u32, + }), + /// read-only + HASH_HR6: mmio.Mmio(packed struct(u32) { + /// H6 + H6: u32, + }), + /// read-only + HASH_HR7: mmio.Mmio(packed struct(u32) { + /// H7 + H7: u32, + }), + }; + + /// General-purpose I/Os + pub const GPIOB = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// General-purpose I/Os + pub const GPIOA = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRM: mmio.Mmio(packed struct(u32) { + /// MEM_MODE + MEM_MODE: u2, + padding: u30, + }), + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + reserved23: u23, + /// Ethernet PHY interface selection + MII_RMII_SEL: u1, + padding: u8, + }), + /// external interrupt configuration register 1 + EXTICR1: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 0 to 3) + EXTI0: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI1: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI2: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI3: u4, + padding: u16, + }), + /// external interrupt configuration register 2 + EXTICR2: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 4 to 7) + EXTI4: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI5: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI6: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI7: u4, + padding: u16, + }), + /// external interrupt configuration register 3 + EXTICR3: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 8 to 11) + EXTI8: u4, + /// EXTI x configuration (x = 8 to 11) + EXTI9: u4, + /// EXTI10 + EXTI10: u4, + /// EXTI x configuration (x = 8 to 11) + EXTI11: u4, + padding: u16, + }), + /// external interrupt configuration register 4 + EXTICR4: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 12 to 15) + EXTI12: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI13: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI14: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI15: u4, + padding: u16, + }), + reserved32: [8]u8, + /// Compensation cell control register + CMPCR: mmio.Mmio(packed struct(u32) { + /// Compensation cell power-down + CMP_PD: u1, + reserved8: u7, + /// READY + READY: u1, + padding: u23, + }), + }; + + /// Serial peripheral interface + pub const SPI1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Output enable in bidirectional mode + BIDIOE: u1, + /// Bidirectional data mode enable + BIDIMODE: u1, + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved4: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + padding: u24, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding: u23, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, + padding: u16, + }), + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, + }), + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, + }), + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, + }), + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: u1, + /// Data length to be transferred + DATLEN: u2, + /// Steady state clock polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding: u22, + }), + }; + + /// LCD-TFT Controller + pub const LTDC = extern struct { + reserved8: [8]u8, + /// Synchronization Size Configuration Register + SSCR: mmio.Mmio(packed struct(u32) { + /// Vertical Synchronization Height (in units of horizontal scan line) + VSH: u11, + reserved16: u5, + /// Horizontal Synchronization Width (in units of pixel clock period) + HSW: u10, + padding: u6, + }), + /// Back Porch Configuration Register + BPCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Vertical back porch (in units of horizontal scan line) + AVBP: u11, + reserved16: u5, + /// Accumulated Horizontal back porch (in units of pixel clock period) + AHBP: u10, + padding: u6, + }), + /// Active Width Configuration Register + AWCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Active Height (in units of horizontal scan line) + AAH: u11, + reserved16: u5, + /// AAV + AAV: u10, + padding: u6, + }), + /// Total Width Configuration Register + TWCR: mmio.Mmio(packed struct(u32) { + /// Total Height (in units of horizontal scan line) + TOTALH: u11, + reserved16: u5, + /// Total Width (in units of pixel clock period) + TOTALW: u10, + padding: u6, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// LCD-TFT controller enable bit + LTDCEN: u1, + reserved4: u3, + /// Dither Blue Width + DBW: u3, + reserved8: u1, + /// Dither Green Width + DGW: u3, + reserved12: u1, + /// Dither Red Width + DRW: u3, + reserved16: u1, + /// Dither Enable + DEN: u1, + reserved28: u11, + /// Pixel Clock Polarity + PCPOL: u1, + /// Data Enable Polarity + DEPOL: u1, + /// Vertical Synchronization Polarity + VSPOL: u1, + /// Horizontal Synchronization Polarity + HSPOL: u1, + }), + reserved36: [8]u8, + /// Shadow Reload Configuration Register + SRCR: mmio.Mmio(packed struct(u32) { + /// Immediate Reload + IMR: u1, + /// Vertical Blanking Reload + VBR: u1, + padding: u30, + }), + reserved44: [4]u8, + /// Background Color Configuration Register + BCCR: mmio.Mmio(packed struct(u32) { + /// Background Color Red value + BC: u24, + padding: u8, + }), + reserved52: [4]u8, + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt Enable + FUIE: u1, + /// Transfer Error Interrupt Enable + TERRIE: u1, + /// Register Reload interrupt enable + RRIE: u1, + padding: u28, + }), + /// Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt flag + FUIF: u1, + /// Transfer Error interrupt flag + TERRIF: u1, + /// Register Reload Interrupt Flag + RRIF: u1, + padding: u28, + }), + /// Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Clears the Line Interrupt Flag + CLIF: u1, + /// Clears the FIFO Underrun Interrupt flag + CFUIF: u1, + /// Clears the Transfer Error Interrupt Flag + CTERRIF: u1, + /// Clears Register Reload Interrupt Flag + CRRIF: u1, + padding: u28, + }), + /// Line Interrupt Position Configuration Register + LIPCR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Position + LIPOS: u11, + padding: u21, + }), + /// Current Position Status Register + CPSR: mmio.Mmio(packed struct(u32) { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, + }), + /// Current Display Status Register + CDSR: mmio.Mmio(packed struct(u32) { + /// Vertical Data Enable display Status + VDES: u1, + /// Horizontal Data Enable display Status + HDES: u1, + /// Vertical Synchronization display Status + VSYNCS: u1, + /// Horizontal Synchronization display Status + HSYNCS: u1, + padding: u28, + }), + reserved132: [56]u8, + /// Layerx Control Register + L1CR: mmio.Mmio(packed struct(u32) { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved4: u2, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding: u27, + }), + /// Layerx Window Horizontal Position Configuration Register + L1WHPCR: mmio.Mmio(packed struct(u32) { + /// Window Horizontal Start Position + WHSTPOS: u12, + reserved16: u4, + /// Window Horizontal Stop Position + WHSPPOS: u12, + padding: u4, + }), + /// Layerx Window Vertical Position Configuration Register + L1WVPCR: mmio.Mmio(packed struct(u32) { + /// Window Vertical Start Position + WVSTPOS: u11, + reserved16: u5, + /// Window Vertical Stop Position + WVSPPOS: u11, + padding: u5, + }), + /// Layerx Color Keying Configuration Register + L1CKCR: mmio.Mmio(packed struct(u32) { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, + padding: u8, + }), + /// Layerx Pixel Format Configuration Register + L1PFCR: mmio.Mmio(packed struct(u32) { + /// Pixel Format + PF: u3, + padding: u29, + }), + /// Layerx Constant Alpha Configuration Register + L1CACR: mmio.Mmio(packed struct(u32) { + /// Constant Alpha + CONSTA: u8, + padding: u24, + }), + /// Layerx Default Color Configuration Register + L1DCCR: mmio.Mmio(packed struct(u32) { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), + /// Layerx Blending Factors Configuration Register + L1BFCR: mmio.Mmio(packed struct(u32) { + /// Blending Factor 2 + BF2: u3, + reserved8: u5, + /// Blending Factor 1 + BF1: u3, + padding: u21, + }), + reserved172: [8]u8, + /// Layerx Color Frame Buffer Address Register + L1CFBAR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Start Address + CFBADD: u32, + }), + /// Layerx Color Frame Buffer Length Register + L1CFBLR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Line Length + CFBLL: u13, + reserved16: u3, + /// Color Frame Buffer Pitch in bytes + CFBP: u13, + padding: u3, + }), + /// Layerx ColorFrame Buffer Line Number Register + L1CFBLNR: mmio.Mmio(packed struct(u32) { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding: u21, + }), + reserved196: [12]u8, + /// Layerx CLUT Write Register + L1CLUTWR: mmio.Mmio(packed struct(u32) { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), + reserved260: [60]u8, + /// Layerx Control Register + L2CR: mmio.Mmio(packed struct(u32) { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved4: u2, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding: u27, + }), + /// Layerx Window Horizontal Position Configuration Register + L2WHPCR: mmio.Mmio(packed struct(u32) { + /// Window Horizontal Start Position + WHSTPOS: u12, + reserved16: u4, + /// Window Horizontal Stop Position + WHSPPOS: u12, + padding: u4, + }), + /// Layerx Window Vertical Position Configuration Register + L2WVPCR: mmio.Mmio(packed struct(u32) { + /// Window Vertical Start Position + WVSTPOS: u11, + reserved16: u5, + /// Window Vertical Stop Position + WVSPPOS: u11, + padding: u5, + }), + /// Layerx Color Keying Configuration Register + L2CKCR: mmio.Mmio(packed struct(u32) { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u7, + /// Color Key Red value + CKRED: u9, + padding: u8, + }), + /// Layerx Pixel Format Configuration Register + L2PFCR: mmio.Mmio(packed struct(u32) { + /// Pixel Format + PF: u3, + padding: u29, + }), + /// Layerx Constant Alpha Configuration Register + L2CACR: mmio.Mmio(packed struct(u32) { + /// Constant Alpha + CONSTA: u8, + padding: u24, + }), + /// Layerx Default Color Configuration Register + L2DCCR: mmio.Mmio(packed struct(u32) { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), + /// Layerx Blending Factors Configuration Register + L2BFCR: mmio.Mmio(packed struct(u32) { + /// Blending Factor 2 + BF2: u3, + reserved8: u5, + /// Blending Factor 1 + BF1: u3, + padding: u21, + }), + reserved300: [8]u8, + /// Layerx Color Frame Buffer Address Register + L2CFBAR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Start Address + CFBADD: u32, + }), + /// Layerx Color Frame Buffer Length Register + L2CFBLR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Line Length + CFBLL: u13, + reserved16: u3, + /// Color Frame Buffer Pitch in bytes + CFBP: u13, + padding: u3, + }), + /// Layerx ColorFrame Buffer Line Number Register + L2CFBLNR: mmio.Mmio(packed struct(u32) { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding: u21, + }), + reserved324: [12]u8, + /// Layerx CLUT Write Register + L2CLUTWR: mmio.Mmio(packed struct(u32) { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), + }; + + /// Serial audio interface + pub const SAI1 = extern struct { + reserved4: [4]u8, + /// SAI AConfiguration register 1 + SAI_ACR1: mmio.Mmio(packed struct(u32) { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved5: u1, + /// Data size + DS: u3, + /// Least significant bit first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OUTDRIV: u1, + reserved16: u2, + /// Audio block enable + SAIAEN: u1, + /// DMA enable + DMAEN: u1, + reserved19: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCKDIV: u4, + padding: u8, + }), + /// SAI AConfiguration register 2 + SAI_ACR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUSH: u1, + /// Tristate management on data line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECNT: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding: u16, + }), + /// SAI AFrame configuration register + SAI_AFRCR: mmio.Mmio(packed struct(u32) { + /// Frame length + FRL: u8, + /// Frame synchronization active level length + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition + FSDEF: u1, + /// Frame synchronization polarity + FSPOL: u1, + /// Frame synchronization offset + FSOFF: u1, + padding: u13, + }), + /// SAI ASlot register + SAI_ASLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset + FBOFF: u5, + reserved6: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio frame + NBSLOT: u4, + reserved16: u4, + /// Slot enable + SLOTEN: u16, + }), + /// SAI AInterrupt mask register2 + SAI_AIM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable + OVRUDRIE: u1, + /// Mute detection interrupt enable + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable + WCKCFGIE: u1, + /// FIFO request interrupt enable + FREQIE: u1, + /// Codec not ready interrupt enable + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable + LFSDETIE: u1, + padding: u25, + }), + /// SAI AStatus register + SAI_ASR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization detection + AFSDET: u1, + /// Late frame synchronization detection + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold + FLTH: u3, + padding: u13, + }), + /// SAI AClear flag register + SAI_ACLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun + COVRUDR: u1, + /// Mute detection flag + CMUTEDET: u1, + /// Clear wrong clock configuration flag + CWCKCFG: u1, + reserved4: u1, + /// Clear codec not ready flag + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag + CAFSDET: u1, + /// Clear late frame synchronization detection flag + CLFSDET: u1, + padding: u25, + }), + /// SAI AData register + SAI_ADR: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, + }), + /// SAI BConfiguration register 1 + SAI_BCR1: mmio.Mmio(packed struct(u32) { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved5: u1, + /// Data size + DS: u3, + /// Least significant bit first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OUTDRIV: u1, + reserved16: u2, + /// Audio block enable + SAIBEN: u1, + /// DMA enable + DMAEN: u1, + reserved19: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCKDIV: u4, + padding: u8, + }), + /// SAI BConfiguration register 2 + SAI_BCR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUSH: u1, + /// Tristate management on data line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECNT: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding: u16, + }), + /// SAI BFrame configuration register + SAI_BFRCR: mmio.Mmio(packed struct(u32) { + /// Frame length + FRL: u8, + /// Frame synchronization active level length + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition + FSDEF: u1, + /// Frame synchronization polarity + FSPOL: u1, + /// Frame synchronization offset + FSOFF: u1, + padding: u13, + }), + /// SAI BSlot register + SAI_BSLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset + FBOFF: u5, + reserved6: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio frame + NBSLOT: u4, + reserved16: u4, + /// Slot enable + SLOTEN: u16, + }), + /// SAI BInterrupt mask register2 + SAI_BIM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable + OVRUDRIE: u1, + /// Mute detection interrupt enable + MUTEDETIE: u1, + /// Wrong clock configuration interrupt enable + WCKCFGIE: u1, + /// FIFO request interrupt enable + FREQIE: u1, + /// Codec not ready interrupt enable + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable + LFSDETIE: u1, + padding: u25, + }), + /// SAI BStatus register + SAI_BSR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization detection + AFSDET: u1, + /// Late frame synchronization detection + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold + FLTH: u3, + padding: u13, + }), + /// SAI BClear flag register + SAI_BCLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun + COVRUDR: u1, + /// Mute detection flag + CMUTEDET: u1, + /// Clear wrong clock configuration flag + CWCKCFG: u1, + reserved4: u1, + /// Clear codec not ready flag + CCNRDY: u1, + /// Clear anticipated frame synchronization detection flag + CAFSDET: u1, + /// Clear late frame synchronization detection flag + CLFSDET: u1, + padding: u25, + }), + /// SAI BData register + SAI_BDR: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, + }), + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = extern struct { + /// Interrupt Set-Enable Register + ISER0: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER1: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER2: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + reserved128: [116]u8, + /// Interrupt Clear-Enable Register + ICER0: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER1: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER2: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + reserved256: [116]u8, + /// Interrupt Set-Pending Register + ISPR0: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR1: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR2: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + reserved384: [116]u8, + /// Interrupt Clear-Pending Register + ICPR0: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR1: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR2: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + reserved512: [116]u8, + /// Interrupt Active Bit Register + IABR0: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR1: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR2: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + reserved768: [244]u8, + /// Interrupt Priority Register + IPR0: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR1: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR2: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR3: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR4: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR5: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR6: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR7: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR8: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR9: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR10: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR11: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR12: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR13: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR14: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR15: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR16: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR17: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR18: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR19: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_PWRCLK = extern struct { + /// Power and clock gating control register + OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY suspended + PHYSUSP: u1, + padding: u27, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_DEVICE = extern struct { + /// OTG_HS device configuration register + OTG_HS_DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: u2, + /// Nonzero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic (micro)frame interval + PFIVL: u2, + reserved24: u11, + /// Periodic scheduling interval + PERSCHIVL: u2, + padding: u6, + }), + /// OTG_HS device control register + OTG_HS_DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, + }), + /// OTG_HS device status register + OTG_HS_DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// OTG_HS device IN endpoint common interrupt mask register + OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (nonisochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + padding: u22, + }), + /// OTG_HS device OUT endpoint common interrupt mask register + OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + reserved6: u1, + /// Back-to-back SETUP packets received mask + B2BSTUP: u1, + reserved8: u1, + /// OUT packet error mask + OPEM: u1, + /// BNA interrupt mask + BOIM: u1, + padding: u22, + }), + /// OTG_HS device all endpoints interrupt register + OTG_HS_DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + /// OTG_HS all endpoints interrupt mask register + OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, + }), + reserved40: [8]u8, + /// OTG_HS device VBUS discharge time register + OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, + }), + /// OTG_HS device VBUS pulsing time register + OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + /// OTG_HS Device threshold control register + OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) { + /// Nonisochronous IN endpoints threshold enable + NONISOTHREN: u1, + /// ISO IN endpoint threshold enable + ISOTHREN: u1, + /// Transmit threshold length + TXTHRLEN: u9, + reserved16: u5, + /// Receive threshold enable + RXTHREN: u1, + /// Receive threshold length + RXTHRLEN: u9, + reserved27: u1, + /// Arbiter parking enable + ARPEN: u1, + padding: u4, + }), + /// OTG_HS device IN endpoint FIFO empty interrupt mask register + OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + /// OTG_HS device each endpoint interrupt register + OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// IN endpoint 1interrupt bit + IEP1INT: u1, + reserved17: u15, + /// OUT endpoint 1 interrupt bit + OEP1INT: u1, + padding: u14, + }), + /// OTG_HS device each endpoint interrupt register mask + OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// IN Endpoint 1 interrupt mask bit + IEP1INTM: u1, + reserved17: u15, + /// OUT Endpoint 1 interrupt mask bit + OEP1INTM: u1, + padding: u14, + }), + /// OTG_HS device each in endpoint-1 interrupt register + OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (nonisochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved13: u3, + /// NAK interrupt mask + NAKM: u1, + padding: u18, + }), + reserved128: [60]u8, + /// OTG_HS device each OUT endpoint-1 interrupt register + OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// OUT packet error mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved12: u2, + /// Bubble error interrupt mask + BERRM: u1, + /// NAK interrupt mask + NAKM: u1, + /// NYET interrupt mask + NYETM: u1, + padding: u17, + }), + reserved256: [124]u8, + /// OTG device endpoint-0 control register + OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved264: [4]u8, + /// OTG device endpoint-0 interrupt register + OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved272: [4]u8, + /// OTG_HS device IN endpoint 0 transfer size register + OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u2, + padding: u11, + }), + /// OTG_HS device endpoint-1 DMA address register + OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved288: [4]u8, + /// OTG device endpoint-1 control register + OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved296: [4]u8, + /// OTG device endpoint-1 interrupt register + OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved304: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-2 DMA address register + OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved320: [4]u8, + /// OTG device endpoint-2 control register + OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved328: [4]u8, + /// OTG device endpoint-2 interrupt register + OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved336: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-3 DMA address register + OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved352: [4]u8, + /// OTG device endpoint-3 control register + OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved360: [4]u8, + /// OTG device endpoint-3 interrupt register + OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved368: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-4 DMA address register + OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved384: [4]u8, + /// OTG device endpoint-4 control register + OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved392: [4]u8, + /// OTG device endpoint-4 interrupt register + OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved400: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-5 DMA address register + OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved416: [4]u8, + /// OTG device endpoint-5 control register + OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved424: [4]u8, + /// OTG device endpoint-5 interrupt register + OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved432: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved440: [4]u8, + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved448: [4]u8, + /// OTG device endpoint-6 control register + OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved456: [4]u8, + /// OTG device endpoint-6 interrupt register + OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved480: [20]u8, + /// OTG device endpoint-7 control register + OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved488: [4]u8, + /// OTG device endpoint-7 interrupt register + OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved768: [276]u8, + /// OTG_HS device control OUT endpoint 0 control register + OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u2, + reserved15: u13, + /// USB active endpoint + USBAEP: u1, + reserved17: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved776: [4]u8, + /// OTG_HS device endpoint-0 interrupt register + OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved784: [4]u8, + /// OTG_HS device endpoint-1 transfer size register + OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u1, + reserved29: u9, + /// SETUP packet count + STUPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// OTG device endpoint-1 control register + OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved808: [4]u8, + /// OTG_HS device endpoint-1 interrupt register + OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved816: [4]u8, + /// OTG_HS device endpoint-2 transfer size register + OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved832: [12]u8, + /// OTG device endpoint-2 control register + OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved840: [4]u8, + /// OTG_HS device endpoint-2 interrupt register + OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved848: [4]u8, + /// OTG_HS device endpoint-3 transfer size register + OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved864: [12]u8, + /// OTG device endpoint-3 control register + OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved872: [4]u8, + /// OTG_HS device endpoint-3 interrupt register + OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved880: [4]u8, + /// OTG_HS device endpoint-4 transfer size register + OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved904: [20]u8, + /// OTG_HS device endpoint-4 interrupt register + OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved912: [4]u8, + /// OTG_HS device endpoint-5 transfer size register + OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved936: [20]u8, + /// OTG_HS device endpoint-5 interrupt register + OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved968: [28]u8, + /// OTG_HS device endpoint-6 interrupt register + OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved1000: [28]u8, + /// OTG_HS device endpoint-7 interrupt register + OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_HOST = extern struct { + /// OTG_HS host configuration register + OTG_HS_HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, + }), + /// OTG_HS Host frame interval register + OTG_HS_HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, + }), + /// OTG_HS host frame number/frame time remaining register + OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), + reserved16: [4]u8, + /// OTG_HS_Host periodic transmit FIFO/queue status register + OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, + }), + /// OTG_HS Host all channels interrupt register + OTG_HS_HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, + }), + /// OTG_HS host all channels interrupt mask register + OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, + }), + reserved64: [36]u8, + /// OTG_HS host port control and status register + OTG_HS_HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, + }), + reserved256: [188]u8, + /// OTG_HS host channel-0 characteristics register + OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-0 split control register + OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-11 interrupt register + OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-11 interrupt mask register + OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-11 transfer size register + OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-0 DMA address register + OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved288: [8]u8, + /// OTG_HS host channel-1 characteristics register + OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-1 split control register + OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-1 interrupt register + OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-1 interrupt mask register + OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-1 transfer size register + OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-1 DMA address register + OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved320: [8]u8, + /// OTG_HS host channel-2 characteristics register + OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-2 split control register + OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-2 interrupt register + OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-2 interrupt mask register + OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-2 transfer size register + OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-2 DMA address register + OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved352: [8]u8, + /// OTG_HS host channel-3 characteristics register + OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-3 split control register + OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-3 interrupt register + OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-3 interrupt mask register + OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-3 transfer size register + OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-3 DMA address register + OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved384: [8]u8, + /// OTG_HS host channel-4 characteristics register + OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-4 split control register + OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-4 interrupt register + OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-4 interrupt mask register + OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-4 transfer size register + OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-4 DMA address register + OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved416: [8]u8, + /// OTG_HS host channel-5 characteristics register + OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-5 split control register + OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-5 interrupt register + OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-5 interrupt mask register + OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-5 transfer size register + OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-5 DMA address register + OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved448: [8]u8, + /// OTG_HS host channel-6 characteristics register + OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-6 split control register + OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-6 interrupt register + OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-6 interrupt mask register + OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-6 transfer size register + OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-6 DMA address register + OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved480: [8]u8, + /// OTG_HS host channel-7 characteristics register + OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-7 split control register + OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-7 interrupt register + OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-7 interrupt mask register + OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-7 transfer size register + OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-7 DMA address register + OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved512: [8]u8, + /// OTG_HS host channel-8 characteristics register + OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-8 split control register + OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-8 interrupt register + OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-8 interrupt mask register + OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-8 transfer size register + OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-8 DMA address register + OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved544: [8]u8, + /// OTG_HS host channel-9 characteristics register + OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-9 split control register + OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-9 interrupt register + OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-9 interrupt mask register + OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-9 transfer size register + OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-9 DMA address register + OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved576: [8]u8, + /// OTG_HS host channel-10 characteristics register + OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-10 split control register + OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-10 interrupt register + OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-10 interrupt mask register + OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-10 transfer size register + OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-10 DMA address register + OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved608: [8]u8, + /// OTG_HS host channel-11 characteristics register + OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-11 split control register + OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-11 interrupt register + OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-11 interrupt mask register + OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-11 transfer size register + OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-11 DMA address register + OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_GLOBAL = extern struct { + /// OTG_HS control and status register + OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved8: u6, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, + }), + /// OTG_HS interrupt register + OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding: u12, + }), + /// OTG_HS AHB configuration register + OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved7: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, + }), + /// OTG_HS USB configuration register + OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved15: u1, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved17: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect disable + ULPIIPD: u1, + reserved29: u3, + /// Forced host mode + FHMOD: u1, + /// Forced peripheral mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), + /// OTG_HS reset register + OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved30: u19, + /// DMA request signal + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, + }), + /// OTG_HS core interrupt register + OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO nonempty + RXFLVL: u1, + /// Nonperiodic TxFIFO empty + NPTXFE: u1, + /// Global IN nonperiodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + BOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer + PXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved24: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUINT: u1, + }), + /// OTG_HS interrupt mask register + OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO nonempty mask + RXFLVLM: u1, + /// Nonperiodic TxFIFO empty mask + NPTXFEM: u1, + /// Global nonperiodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask + PXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + reserved24: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved28: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, + }), + /// OTG_HS Receive status debug read register (host mode) + OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding: u11, + }), + /// OTG_HS status read and pop register (host mode) + OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding: u11, + }), + /// OTG_HS Receive FIFO size register + OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, + }), + /// OTG_HS nonperiodic transmit FIFO size register (host mode) + OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) { + /// Nonperiodic transmit RAM start address + NPTXFSA: u16, + /// Nonperiodic TxFIFO depth + NPTXFD: u16, + }), + /// OTG_HS nonperiodic transmit FIFO/queue status register + OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Nonperiodic TxFIFO space available + NPTXFSAV: u16, + /// Nonperiodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the nonperiodic transmit request queue + NPTXQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// OTG_HS general core configuration register + OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + /// Enable I2C bus connection for the external I2C PHY interface + I2CPADEN: u1, + /// Enable the VBUS sensing device + VBUSASEN: u1, + /// Enable the VBUS sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable option + NOVBUSSENS: u1, + padding: u10, + }), + /// OTG_HS core ID register + OTG_HS_CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, + }), + reserved256: [192]u8, + /// OTG_HS Host periodic transmit FIFO size register + OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + reserved284: [16]u8, + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + }; + + /// Secure digital input/output interface + pub const SDIO = extern struct { + /// power control register + POWER: mmio.Mmio(packed struct(u32) { + /// PWRCTRL + PWRCTRL: u2, + padding: u30, + }), + /// SDI clock control register + CLKCR: mmio.Mmio(packed struct(u32) { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration bit + PWRSAV: u1, + /// Clock divider bypass enable bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding: u17, + }), + /// argument register + ARG: mmio.Mmio(packed struct(u32) { + /// Command argument + CMDARG: u32, + }), + /// command register + CMD: mmio.Mmio(packed struct(u32) { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt request + WAITINT: u1, + /// CPSM Waits for ends of data transfer (CmdPend internal signal). + WAITPEND: u1, + /// Command path state machine (CPSM) Enable bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + /// Enable CMD completion + ENCMDcompl: u1, + /// not Interrupt Enable + nIEN: u1, + /// CE-ATA command + CE_ATACMD: u1, + padding: u17, + }), + /// command response register + RESPCMD: mmio.Mmio(packed struct(u32) { + /// Response command index + RESPCMD: u6, + padding: u26, + }), + /// response 1..4 register + RESP1: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS1: u32, + }), + /// response 1..4 register + RESP2: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS2: u32, + }), + /// response 1..4 register + RESP3: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS3: u32, + }), + /// response 1..4 register + RESP4: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS4: u32, + }), + /// data timer register + DTIMER: mmio.Mmio(packed struct(u32) { + /// Data timeout period + DATATIME: u32, + }), + /// data length register + DLEN: mmio.Mmio(packed struct(u32) { + /// Data length value + DATALENGTH: u25, + padding: u7, + }), + /// data control register + DCTRL: mmio.Mmio(packed struct(u32) { + /// DTEN + DTEN: u1, + /// Data transfer direction selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding: u20, + }), + /// data counter register + DCOUNT: mmio.Mmio(packed struct(u32) { + /// Data count value + DATACOUNT: u25, + padding: u7, + }), + /// status register + STA: mmio.Mmio(packed struct(u32) { + /// Command response received (CRC check failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun error + TXUNDERR: u1, + /// Received FIFO overrun error + RXOVERR: u1, + /// Command response received (CRC check passed) + CMDREND: u1, + /// Command sent (no response required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is zero) + DATAEND: u1, + /// Start bit not detected on all data signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check passed) + DBCKEND: u1, + /// Command transfer in progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit FIFO + TXDAVL: u1, + /// Data available in receive FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + /// CE-ATA command completion signal received for CMD61 + CEATAEND: u1, + padding: u8, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved22: u11, + /// SDIOIT flag clear bit + SDIOITC: u1, + /// CEATAEND flag clear bit + CEATAENDC: u1, + padding: u8, + }), + /// mask register + MASK: mmio.Mmio(packed struct(u32) { + /// Command CRC fail interrupt enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt enable + DCRCFAILIE: u1, + /// Command timeout interrupt enable + CTIMEOUTIE: u1, + /// Data timeout interrupt enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt enable + RXOVERRIE: u1, + /// Command response received interrupt enable + CMDRENDIE: u1, + /// Command sent interrupt enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// Start bit error interrupt enable + STBITERRIE: u1, + /// Data block end interrupt enable + DBCKENDIE: u1, + /// Command acting interrupt enable + CMDACTIE: u1, + /// Data transmit acting interrupt enable + TXACTIE: u1, + /// Data receive acting interrupt enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt enable + SDIOITIE: u1, + /// CE-ATA command completion signal received interrupt enable + CEATAENDIE: u1, + padding: u8, + }), + reserved72: [8]u8, + /// FIFO counter register + FIFOCNT: mmio.Mmio(packed struct(u32) { + /// Remaining number of words to be written to or read from the FIFO. + FIFOCOUNT: u24, + padding: u8, + }), + reserved128: [52]u8, + /// data FIFO register + FIFO: mmio.Mmio(packed struct(u32) { + /// Receive and transmit FIFO data + FIFOData: u32, + }), + }; + + /// Analog-to-digital converter + pub const ADC1 = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding: u26, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + reserved22: u6, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding: u5, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved8: u6, + /// Direct memory access mode (for single ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC mode) + DDS: u1, + /// End of conversion selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved16: u4, + /// External event select for injected group + JEXTSEL: u4, + /// External trigger enable for injected channels + JEXTEN: u2, + /// Start conversion of injected channels + JSWSTART: u1, + reserved24: u1, + /// External event select for regular group + EXTSEL: u4, + /// External trigger enable for regular channels + EXTEN: u2, + /// Start conversion of regular channels + SWSTART: u1, + padding: u1, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Sample time bits + SMPx_x: u32, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Sample time bits + SMPx_x: u32, + }), + /// injected channel data offset register x + JOFR1: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR2: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR3: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR4: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ13: u5, + /// 14th conversion in regular sequence + SQ14: u5, + /// 15th conversion in regular sequence + SQ15: u5, + /// 16th conversion in regular sequence + SQ16: u5, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ7: u5, + /// 8th conversion in regular sequence + SQ8: u5, + /// 9th conversion in regular sequence + SQ9: u5, + /// 10th conversion in regular sequence + SQ10: u5, + /// 11th conversion in regular sequence + SQ11: u5, + /// 12th conversion in regular sequence + SQ12: u5, + padding: u2, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ1: u5, + /// 2nd conversion in regular sequence + SQ2: u5, + /// 3rd conversion in regular sequence + SQ3: u5, + /// 4th conversion in regular sequence + SQ4: u5, + /// 5th conversion in regular sequence + SQ5: u5, + /// 6th conversion in regular sequence + SQ6: u5, + padding: u2, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + padding: u16, + }), + }; + + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Interrupt mask register (EXTI_IMR) + IMR: mmio.Mmio(packed struct(u32) { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + padding: u9, + }), + /// Event mask register (EXTI_EMR) + EMR: mmio.Mmio(packed struct(u32) { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + padding: u9, + }), + /// Rising Trigger selection register (EXTI_RTSR) + RTSR: mmio.Mmio(packed struct(u32) { + /// Rising trigger event configuration of line 0 + TR0: u1, + /// Rising trigger event configuration of line 1 + TR1: u1, + /// Rising trigger event configuration of line 2 + TR2: u1, + /// Rising trigger event configuration of line 3 + TR3: u1, + /// Rising trigger event configuration of line 4 + TR4: u1, + /// Rising trigger event configuration of line 5 + TR5: u1, + /// Rising trigger event configuration of line 6 + TR6: u1, + /// Rising trigger event configuration of line 7 + TR7: u1, + /// Rising trigger event configuration of line 8 + TR8: u1, + /// Rising trigger event configuration of line 9 + TR9: u1, + /// Rising trigger event configuration of line 10 + TR10: u1, + /// Rising trigger event configuration of line 11 + TR11: u1, + /// Rising trigger event configuration of line 12 + TR12: u1, + /// Rising trigger event configuration of line 13 + TR13: u1, + /// Rising trigger event configuration of line 14 + TR14: u1, + /// Rising trigger event configuration of line 15 + TR15: u1, + /// Rising trigger event configuration of line 16 + TR16: u1, + /// Rising trigger event configuration of line 17 + TR17: u1, + /// Rising trigger event configuration of line 18 + TR18: u1, + /// Rising trigger event configuration of line 19 + TR19: u1, + /// Rising trigger event configuration of line 20 + TR20: u1, + /// Rising trigger event configuration of line 21 + TR21: u1, + /// Rising trigger event configuration of line 22 + TR22: u1, + padding: u9, + }), + /// Falling Trigger selection register (EXTI_FTSR) + FTSR: mmio.Mmio(packed struct(u32) { + /// Falling trigger event configuration of line 0 + TR0: u1, + /// Falling trigger event configuration of line 1 + TR1: u1, + /// Falling trigger event configuration of line 2 + TR2: u1, + /// Falling trigger event configuration of line 3 + TR3: u1, + /// Falling trigger event configuration of line 4 + TR4: u1, + /// Falling trigger event configuration of line 5 + TR5: u1, + /// Falling trigger event configuration of line 6 + TR6: u1, + /// Falling trigger event configuration of line 7 + TR7: u1, + /// Falling trigger event configuration of line 8 + TR8: u1, + /// Falling trigger event configuration of line 9 + TR9: u1, + /// Falling trigger event configuration of line 10 + TR10: u1, + /// Falling trigger event configuration of line 11 + TR11: u1, + /// Falling trigger event configuration of line 12 + TR12: u1, + /// Falling trigger event configuration of line 13 + TR13: u1, + /// Falling trigger event configuration of line 14 + TR14: u1, + /// Falling trigger event configuration of line 15 + TR15: u1, + /// Falling trigger event configuration of line 16 + TR16: u1, + /// Falling trigger event configuration of line 17 + TR17: u1, + /// Falling trigger event configuration of line 18 + TR18: u1, + /// Falling trigger event configuration of line 19 + TR19: u1, + /// Falling trigger event configuration of line 20 + TR20: u1, + /// Falling trigger event configuration of line 21 + TR21: u1, + /// Falling trigger event configuration of line 22 + TR22: u1, + padding: u9, + }), + /// Software interrupt event register (EXTI_SWIER) + SWIER: mmio.Mmio(packed struct(u32) { + /// Software Interrupt on line 0 + SWIER0: u1, + /// Software Interrupt on line 1 + SWIER1: u1, + /// Software Interrupt on line 2 + SWIER2: u1, + /// Software Interrupt on line 3 + SWIER3: u1, + /// Software Interrupt on line 4 + SWIER4: u1, + /// Software Interrupt on line 5 + SWIER5: u1, + /// Software Interrupt on line 6 + SWIER6: u1, + /// Software Interrupt on line 7 + SWIER7: u1, + /// Software Interrupt on line 8 + SWIER8: u1, + /// Software Interrupt on line 9 + SWIER9: u1, + /// Software Interrupt on line 10 + SWIER10: u1, + /// Software Interrupt on line 11 + SWIER11: u1, + /// Software Interrupt on line 12 + SWIER12: u1, + /// Software Interrupt on line 13 + SWIER13: u1, + /// Software Interrupt on line 14 + SWIER14: u1, + /// Software Interrupt on line 15 + SWIER15: u1, + /// Software Interrupt on line 16 + SWIER16: u1, + /// Software Interrupt on line 17 + SWIER17: u1, + /// Software Interrupt on line 18 + SWIER18: u1, + /// Software Interrupt on line 19 + SWIER19: u1, + /// Software Interrupt on line 20 + SWIER20: u1, + /// Software Interrupt on line 21 + SWIER21: u1, + /// Software Interrupt on line 22 + SWIER22: u1, + padding: u9, + }), + /// Pending register (EXTI_PR) + PR: mmio.Mmio(packed struct(u32) { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + padding: u9, + }), + }; + + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: u3, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding: u19, + }), + /// Flash key register + KEYR: mmio.Mmio(packed struct(u32) { + /// FPEC key + KEY: u32, + }), + /// Flash option key register + OPTKEYR: mmio.Mmio(packed struct(u32) { + /// Option byte key + OPTKEY: u32, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved4: u2, + /// Write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Programming parallelism error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved16: u8, + /// Busy + BSY: u1, + padding: u15, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase + MER: u1, + /// Sector number + SNB: u4, + reserved8: u1, + /// Program size + PSIZE: u2, + reserved16: u6, + /// Start + STRT: u1, + reserved24: u7, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved31: u5, + /// Lock + LOCK: u1, + }), + /// Flash option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved5: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option bytes + nRST_STOP: u1, + /// nRST_STDBY User option bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding: u4, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART6 = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + padding: u20, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + }; + + /// Basic timers + pub const TIM6 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + padding: u24, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// Controller area network + pub const CAN1 = extern struct { + /// master control register + MCR: mmio.Mmio(packed struct(u32) { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved15: u7, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding: u15, + }), + /// master status register + MSR: mmio.Mmio(packed struct(u32) { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved8: u3, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding: u20, + }), + /// transmit status register + TSR: mmio.Mmio(packed struct(u32) { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved7: u3, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved15: u3, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved23: u3, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox 0 + TME0: u1, + /// Lowest priority flag for mailbox 1 + TME1: u1, + /// Lowest priority flag for mailbox 2 + TME2: u1, + /// Lowest priority flag for mailbox 0 + LOW0: u1, + /// Lowest priority flag for mailbox 1 + LOW1: u1, + /// Lowest priority flag for mailbox 2 + LOW2: u1, + }), + /// receive FIFO 0 register + RF0R: mmio.Mmio(packed struct(u32) { + /// FMP0 + FMP0: u2, + reserved3: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding: u26, + }), + /// receive FIFO 1 register + RF1R: mmio.Mmio(packed struct(u32) { + /// FMP1 + FMP1: u2, + reserved3: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding: u26, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved8: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved15: u3, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding: u14, + }), + /// interrupt enable register + ESR: mmio.Mmio(packed struct(u32) { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved4: u1, + /// LEC + LEC: u3, + reserved16: u9, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), + /// bit timing register + BTR: mmio.Mmio(packed struct(u32) { + /// BRP + BRP: u10, + reserved16: u6, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved24: u1, + /// SJW + SJW: u2, + reserved30: u4, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), + reserved384: [352]u8, + /// TX mailbox identifier register + TI0R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox identifier register + TI1R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox identifier register + TI2R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT2R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL2R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH2R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// receive FIFO mailbox identifier register + RI0R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data high register + RDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// mailbox data high register + RDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// receive FIFO mailbox data high register + RDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox data high register + RI1R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data high register + RDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// mailbox data high register + RDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + RDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + reserved512: [48]u8, + /// filter master register + FMR: mmio.Mmio(packed struct(u32) { + /// FINIT + FINIT: u1, + reserved8: u7, + /// CAN2SB + CAN2SB: u6, + padding: u18, + }), + /// filter mode register + FM1R: mmio.Mmio(packed struct(u32) { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding: u4, + }), + reserved524: [4]u8, + /// filter scale register + FS1R: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding: u4, + }), + reserved532: [4]u8, + /// filter FIFO assignment register + FFA1R: mmio.Mmio(packed struct(u32) { + /// Filter FIFO assignment for filter 0 + FFA0: u1, + /// Filter FIFO assignment for filter 1 + FFA1: u1, + /// Filter FIFO assignment for filter 2 + FFA2: u1, + /// Filter FIFO assignment for filter 3 + FFA3: u1, + /// Filter FIFO assignment for filter 4 + FFA4: u1, + /// Filter FIFO assignment for filter 5 + FFA5: u1, + /// Filter FIFO assignment for filter 6 + FFA6: u1, + /// Filter FIFO assignment for filter 7 + FFA7: u1, + /// Filter FIFO assignment for filter 8 + FFA8: u1, + /// Filter FIFO assignment for filter 9 + FFA9: u1, + /// Filter FIFO assignment for filter 10 + FFA10: u1, + /// Filter FIFO assignment for filter 11 + FFA11: u1, + /// Filter FIFO assignment for filter 12 + FFA12: u1, + /// Filter FIFO assignment for filter 13 + FFA13: u1, + /// Filter FIFO assignment for filter 14 + FFA14: u1, + /// Filter FIFO assignment for filter 15 + FFA15: u1, + /// Filter FIFO assignment for filter 16 + FFA16: u1, + /// Filter FIFO assignment for filter 17 + FFA17: u1, + /// Filter FIFO assignment for filter 18 + FFA18: u1, + /// Filter FIFO assignment for filter 19 + FFA19: u1, + /// Filter FIFO assignment for filter 20 + FFA20: u1, + /// Filter FIFO assignment for filter 21 + FFA21: u1, + /// Filter FIFO assignment for filter 22 + FFA22: u1, + /// Filter FIFO assignment for filter 23 + FFA23: u1, + /// Filter FIFO assignment for filter 24 + FFA24: u1, + /// Filter FIFO assignment for filter 25 + FFA25: u1, + /// Filter FIFO assignment for filter 26 + FFA26: u1, + /// Filter FIFO assignment for filter 27 + FFA27: u1, + padding: u4, + }), + reserved540: [4]u8, + /// filter activation register + FA1R: mmio.Mmio(packed struct(u32) { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding: u4, + }), + reserved576: [32]u8, + /// Filter bank 0 register 1 + F0R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 0 register 2 + F0R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 1 + F1R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 2 + F1R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 1 + F2R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 2 + F2R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 1 + F3R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 2 + F3R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F4R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 2 + F4R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 1 + F5R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 2 + F5R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 1 + F6R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 2 + F6R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 1 + F7R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 2 + F7R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 1 + F8R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 2 + F8R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 1 + F9R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 2 + F9R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 1 + F10R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 2 + F10R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 1 + F11R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 2 + F11R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F12R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 12 register 2 + F12R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 1 + F13R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 2 + F13R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 1 + F14R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 2 + F14R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 1 + F15R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 2 + F15R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 1 + F16R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 2 + F16R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 1 + F17R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 2 + F17R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 1 + F18R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 2 + F18R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 1 + F19R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 2 + F19R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 1 + F20R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 2 + F20R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 1 + F21R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 2 + F21R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 1 + F22R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 2 + F22R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 1 + F23R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 2 + F23R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 1 + F24R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 2 + F24R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 1 + F25R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 2 + F25R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 1 + F26R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 2 + F26R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 1 + F27R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 2 + F27R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = extern struct { + /// OTG_FS power and clock gating control register + FS_PCGCCTL: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY Suspended + PHYSUSP: u1, + padding: u27, + }), + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer disable + BOFF1: u1, + /// DAC channel1 trigger enable + TEN1: u1, + /// DAC channel1 trigger selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt enable + DMAUDRIE1: u1, + reserved16: u2, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer disable + BOFF2: u1, + /// DAC channel2 trigger enable + TEN2: u1, + /// DAC channel2 trigger selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt enable + DMAUDRIE2: u1, + padding: u2, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 software trigger + SWTRIG1: u1, + /// DAC channel2 software trigger + SWTRIG2: u1, + padding: u30, + }), + /// channel1 12-bit right-aligned data holding register + DHR12R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + padding: u20, + }), + /// channel1 12-bit left aligned data holding register + DHR12L1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + padding: u16, + }), + /// channel1 8-bit right aligned data holding register + DHR8R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + padding: u24, + }), + /// channel2 12-bit right aligned data holding register + DHR12R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u20, + }), + /// channel2 12-bit left aligned data holding register + DHR12L2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + padding: u16, + }), + /// channel2 8-bit right-aligned data holding register + DHR8R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u24, + }), + /// Dual DAC 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + reserved16: u4, + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u4, + }), + /// DUAL DAC 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + reserved20: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + }), + /// DUAL DAC 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u16, + }), + /// channel1 data output register + DOR1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 data output + DACC1DOR: u12, + padding: u20, + }), + /// channel2 data output register + DOR2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 data output + DACC2DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// DAC channel1 DMA underrun flag + DMAUDR1: u1, + reserved29: u15, + /// DAC channel2 DMA underrun flag + DMAUDR2: u1, + padding: u2, + }), + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Flash power down in Stop mode + FPDS: u1, + padding: u22, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved8: u4, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved14: u4, + /// Regulator voltage scaling output selection ready bit + VOSRDY: u1, + padding: u17, + }), + }; + + /// Inter-integrated circuit + pub const I2C3 = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved3: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Software reset + SWRST: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Peripheral clock frequency + FREQ: u6, + reserved8: u2, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding: u19, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved15: u5, + /// Addressing mode (slave mode) + ADDMODE: u1, + padding: u16, + }), + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + /// Dual addressing mode enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding: u24, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// 8-bit data register + DR: u8, + padding: u24, + }), + /// Status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master mode) + ADD10: u1, + /// Stop detection (slave mode) + STOPF: u1, + reserved6: u1, + /// Data register not empty (receivers) + RxNE: u1, + /// Data register empty (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved14: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding: u16, + }), + /// Status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved4: u1, + /// General call address (Slave mode) + GENCALL: u1, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking register + PEC: u8, + padding: u16, + }), + /// Clock control register + CCR: mmio.Mmio(packed struct(u32) { + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12, + reserved14: u2, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding: u16, + }), + /// TRISE register + TRISE: mmio.Mmio(packed struct(u32) { + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6, + padding: u26, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = extern struct { + /// OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding: u19, + }), + /// OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, + }), + /// OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + FS_DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (Non-isochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + padding: u25, + }), + /// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + FS_DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + padding: u27, + }), + /// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + /// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + reserved40: [8]u8, + /// OTG_FS device VBUS discharge time register + DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, + }), + /// OTG_FS device VBUS pulsing time register + DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + reserved52: [4]u8, + /// OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + reserved256: [200]u8, + /// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + FS_DIEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u2, + reserved15: u13, + /// USB active endpoint + USBAEP: u1, + reserved17: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved264: [4]u8, + /// device endpoint-x interrupt register + DIEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved272: [4]u8, + /// device endpoint-0 transfer size register + DIEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u2, + padding: u11, + }), + reserved280: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved288: [4]u8, + /// OTG device endpoint-1 control register + DIEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved296: [4]u8, + /// device endpoint-1 interrupt register + DIEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved304: [4]u8, + /// device endpoint-1 transfer size register + DIEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved312: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved320: [4]u8, + /// OTG device endpoint-2 control register + DIEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved328: [4]u8, + /// device endpoint-2 interrupt register + DIEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved336: [4]u8, + /// device endpoint-2 transfer size register + DIEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved344: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved352: [4]u8, + /// OTG device endpoint-3 control register + DIEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved360: [4]u8, + /// device endpoint-3 interrupt register + DIEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved368: [4]u8, + /// device endpoint-3 transfer size register + DIEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved376: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved768: [388]u8, + /// device endpoint-0 control register + DOEPCTL0: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u2, + reserved15: u13, + /// USBAEP + USBAEP: u1, + reserved17: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved30: u2, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved776: [4]u8, + /// device endpoint-0 interrupt register + DOEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved784: [4]u8, + /// device OUT endpoint-0 transfer size register + DOEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u1, + reserved29: u9, + /// SETUP packet count + STUPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// device endpoint-1 control register + DOEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved808: [4]u8, + /// device endpoint-1 interrupt register + DOEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved816: [4]u8, + /// device OUT endpoint-1 transfer size register + DOEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved832: [12]u8, + /// device endpoint-2 control register + DOEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved840: [4]u8, + /// device endpoint-2 interrupt register + DOEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved848: [4]u8, + /// device OUT endpoint-2 transfer size register + DOEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved864: [12]u8, + /// device endpoint-3 control register + DOEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved872: [4]u8, + /// device endpoint-3 interrupt register + DOEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved880: [4]u8, + /// device OUT endpoint-3 transfer size register + DOEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = extern struct { + /// OTG_FS host configuration register (OTG_FS_HCFG) + FS_HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, + }), + /// OTG_FS Host frame interval register + HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, + }), + /// OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + FS_HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), + reserved16: [4]u8, + /// OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + FS_HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, + }), + /// OTG_FS Host all channels interrupt register + HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, + }), + /// OTG_FS host all channels interrupt mask register + HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, + }), + reserved64: [36]u8, + /// OTG_FS host port control and status register (OTG_FS_HPRT) + FS_HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, + }), + reserved256: [188]u8, + /// OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + FS_HCCHAR0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved264: [4]u8, + /// OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + FS_HCINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + FS_HCINTMSK0: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-0 transfer size register + FS_HCTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved288: [12]u8, + /// OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) + FS_HCCHAR1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved296: [4]u8, + /// OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) + FS_HCINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) + FS_HCINTMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-1 transfer size register + FS_HCTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved320: [12]u8, + /// OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) + FS_HCCHAR2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved328: [4]u8, + /// OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) + FS_HCINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) + FS_HCINTMSK2: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-2 transfer size register + FS_HCTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved352: [12]u8, + /// OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) + FS_HCCHAR3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved360: [4]u8, + /// OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) + FS_HCINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) + FS_HCINTMSK3: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-3 transfer size register + FS_HCTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved384: [12]u8, + /// OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) + FS_HCCHAR4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved392: [4]u8, + /// OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) + FS_HCINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) + FS_HCINTMSK4: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-x transfer size register + FS_HCTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved416: [12]u8, + /// OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) + FS_HCCHAR5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved424: [4]u8, + /// OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) + FS_HCINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) + FS_HCINTMSK5: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-5 transfer size register + FS_HCTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved448: [12]u8, + /// OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) + FS_HCCHAR6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved456: [4]u8, + /// OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) + FS_HCINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) + FS_HCINTMSK6: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-6 transfer size register + FS_HCTSIZ6: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved480: [12]u8, + /// OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) + FS_HCCHAR7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved488: [4]u8, + /// OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) + FS_HCINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) + FS_HCINTMSK7: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-7 transfer size register + FS_HCTSIZ7: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + }; + + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value (write only, read 0000h) + KEY: u16, + padding: u16, + }), + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: u3, + padding: u29, + }), + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + padding: u30, + }), + }; + + /// Window watchdog + pub const WWDG = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding: u24, + }), + /// Configuration register + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB0: u1, + /// Timer base + WDGTB1: u1, + /// Early wakeup interrupt + EWI: u1, + padding: u22, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, + }), + }; + + /// Real-time clock + pub const RTC = extern struct { + /// time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, + }), + /// date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active edge + TSEDGE: u1, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + reserved6: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration enable + DCE: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Time-stamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved20: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// TAMPER2 detection flag + TAMP2F: u1, + reserved16: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding: u15, + }), + /// prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + /// calibration register + CALIBR: mmio.Mmio(packed struct(u32) { + /// Digital calibration + DC: u5, + reserved7: u2, + /// Digital calibration sign + DCS: u1, + padding: u24, + }), + /// alarm A register + ALRMAR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), + /// alarm B register + ALRMBR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), + /// write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// time stamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + reserved16: u13, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// time stamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, + }), + /// timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: u1, + /// Use an 8-second calibration cycle period + CALW8: u1, + /// Increase frequency of RTC by 488.5 ppm + CALP: u1, + padding: u16, + }), + /// tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + reserved7: u2, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// alarm A sub second register + ALRMASSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + /// alarm B sub second register + ALRMBSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [4]u8, + /// backup register + BKP0R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP1R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP2R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP3R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP4R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP5R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP6R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP7R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP8R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP9R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP10R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP11R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP12R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP13R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP14R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP15R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP16R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP17R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP18R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP19R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const UART4 = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding: u23, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved6: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved11: u3, + /// One sample bit method enable + ONEBIT: u1, + padding: u20, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = extern struct { + /// OTG_FS control and status register (OTG_FS_GOTGCTL) + FS_GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved8: u6, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, + }), + /// OTG_FS interrupt register (OTG_FS_GOTGINT) + FS_GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding: u12, + }), + /// OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + FS_GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + reserved7: u6, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, + }), + /// OTG_FS USB configuration register (OTG_FS_GUSBCFG) + FS_GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// Full Speed serial transceiver select + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved29: u15, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), + /// OTG_FS reset register (OTG_FS_GRSTCTL) + FS_GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved31: u20, + /// AHB master idle + AHBIDL: u1, + }), + /// OTG_FS core interrupt register (OTG_FS_GINTSTS) + FS_GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + IPXFR_INCOMPISOOUT: u1, + reserved24: u2, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUPINT: u1, + }), + /// OTG_FS interrupt mask register (OTG_FS_GINTMSK) + FS_GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM: u1, + reserved24: u2, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved28: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, + }), + /// OTG_FS Receive status debug read(Device mode) + FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding: u7, + }), + reserved36: [4]u8, + /// OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + FS_GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, + }), + /// OTG_FS non-periodic transmit FIFO size register (Device mode) + FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint 0 transmit RAM start address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), + /// OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + FS_GNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Non-periodic TxFIFO space available + NPTXFSAV: u16, + /// Non-periodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request queue + NPTXQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// OTG_FS general core configuration register (OTG_FS_GCCFG) + FS_GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + reserved18: u1, + /// Enable the VBUS sensing device + VBUSASEN: u1, + /// Enable the VBUS sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding: u11, + }), + /// core ID register + FS_CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, + }), + reserved256: [192]u8, + /// OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + FS_DIEPTXF1: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO2 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + FS_DIEPTXF2: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO3 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + FS_DIEPTXF3: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO4 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + }; + + /// Cryptographic processor + pub const CRC = extern struct { + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data Register + DR: u32, + }), + /// Independent Data register + IDR: mmio.Mmio(packed struct(u32) { + /// Independent Data register + IDR: u8, + padding: u24, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Control regidter + CR: u1, + padding: u31, + }), + }; + + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = extern struct { + /// Ethernet DMA bus mode register + DMABMR: mmio.Mmio(packed struct(u32) { + /// SR + SR: u1, + /// DA + DA: u1, + /// DSL + DSL: u5, + /// EDFE + EDFE: u1, + /// PBL + PBL: u6, + /// RTPR + RTPR: u2, + /// FB + FB: u1, + /// RDP + RDP: u6, + /// USP + USP: u1, + /// FPM + FPM: u1, + /// AAB + AAB: u1, + /// MB + MB: u1, + padding: u5, + }), + /// Ethernet DMA transmit poll demand register + DMATPDR: mmio.Mmio(packed struct(u32) { + /// TPD + TPD: u32, + }), + /// EHERNET DMA receive poll demand register + DMARPDR: mmio.Mmio(packed struct(u32) { + /// RPD + RPD: u32, + }), + /// Ethernet DMA receive descriptor list address register + DMARDLAR: mmio.Mmio(packed struct(u32) { + /// SRL + SRL: u32, + }), + /// Ethernet DMA transmit descriptor list address register + DMATDLAR: mmio.Mmio(packed struct(u32) { + /// STL + STL: u32, + }), + /// Ethernet DMA status register + DMASR: mmio.Mmio(packed struct(u32) { + /// TS + TS: u1, + /// TPSS + TPSS: u1, + /// TBUS + TBUS: u1, + /// TJTS + TJTS: u1, + /// ROS + ROS: u1, + /// TUS + TUS: u1, + /// RS + RS: u1, + /// RBUS + RBUS: u1, + /// RPSS + RPSS: u1, + /// PWTS + PWTS: u1, + /// ETS + ETS: u1, + reserved13: u2, + /// FBES + FBES: u1, + /// ERS + ERS: u1, + /// AIS + AIS: u1, + /// NIS + NIS: u1, + /// RPS + RPS: u3, + /// TPS + TPS: u3, + /// EBS + EBS: u3, + reserved27: u1, + /// MMCS + MMCS: u1, + /// PMTS + PMTS: u1, + /// TSTS + TSTS: u1, + padding: u2, + }), + /// Ethernet DMA operation mode register + DMAOMR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved6: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved13: u5, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved20: u3, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved24: u2, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding: u5, + }), + /// Ethernet DMA interrupt enable register + DMAIER: mmio.Mmio(packed struct(u32) { + /// TIE + TIE: u1, + /// TPSIE + TPSIE: u1, + /// TBUIE + TBUIE: u1, + /// TJTIE + TJTIE: u1, + /// ROIE + ROIE: u1, + /// TUIE + TUIE: u1, + /// RIE + RIE: u1, + /// RBUIE + RBUIE: u1, + /// RPSIE + RPSIE: u1, + /// RWTIE + RWTIE: u1, + /// ETIE + ETIE: u1, + reserved13: u2, + /// FBEIE + FBEIE: u1, + /// ERIE + ERIE: u1, + /// AISE + AISE: u1, + /// NISE + NISE: u1, + padding: u15, + }), + /// Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR: mmio.Mmio(packed struct(u32) { + /// MFC + MFC: u16, + /// OMFC + OMFC: u1, + /// MFA + MFA: u11, + /// OFOC + OFOC: u1, + padding: u3, + }), + /// Ethernet DMA receive status watchdog timer register + DMARSWTR: mmio.Mmio(packed struct(u32) { + /// RSWTC + RSWTC: u8, + padding: u24, + }), + reserved72: [32]u8, + /// Ethernet DMA current host transmit descriptor register + DMACHTDR: mmio.Mmio(packed struct(u32) { + /// HTDAP + HTDAP: u32, + }), + /// Ethernet DMA current host receive descriptor register + DMACHRDR: mmio.Mmio(packed struct(u32) { + /// HRDAP + HRDAP: u32, + }), + /// Ethernet DMA current host transmit buffer address register + DMACHTBAR: mmio.Mmio(packed struct(u32) { + /// HTBAP + HTBAP: u32, + }), + /// Ethernet DMA current host receive buffer address register + DMACHRBAR: mmio.Mmio(packed struct(u32) { + /// HRBAP + HRBAP: u32, + }), + }; + + /// Common ADC registers + pub const C_ADC = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag of ADC 1 + AWD1: u1, + /// End of conversion of ADC 1 + EOC1: u1, + /// Injected channel end of conversion of ADC 1 + JEOC1: u1, + /// Injected channel Start flag of ADC 1 + JSTRT1: u1, + /// Regular channel Start flag of ADC 1 + STRT1: u1, + /// Overrun flag of ADC 1 + OVR1: u1, + reserved8: u2, + /// Analog watchdog flag of ADC 2 + AWD2: u1, + /// End of conversion of ADC 2 + EOC2: u1, + /// Injected channel end of conversion of ADC 2 + JEOC2: u1, + /// Injected channel Start flag of ADC 2 + JSTRT2: u1, + /// Regular channel Start flag of ADC 2 + STRT2: u1, + /// Overrun flag of ADC 2 + OVR2: u1, + reserved16: u2, + /// Analog watchdog flag of ADC 3 + AWD3: u1, + /// End of conversion of ADC 3 + EOC3: u1, + /// Injected channel end of conversion of ADC 3 + JEOC3: u1, + /// Injected channel Start flag of ADC 3 + JSTRT3: u1, + /// Regular channel Start flag of ADC 3 + STRT3: u1, + /// Overrun flag of ADC3 + OVR3: u1, + padding: u10, + }), + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Multi ADC mode selection + MULT: u5, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// DMA disable selection for multi-ADC mode + DDS: u1, + /// Direct memory access mode for multi ADC mode + DMA: u2, + /// ADC prescaler + ADCPRE: u2, + reserved22: u4, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, + }), + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// 1st data item of a pair of regular conversions + DATA1: u16, + /// 2nd data item of a pair of regular conversions + DATA2: u16, + }), + }; + + /// Advanced-timers + pub const TIM1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding: u17, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear enable + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + OC4CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output enable + CC2NE: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output enable + CC3NE: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + padding: u18, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR4: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding: u16, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = extern struct { + /// Ethernet PTP time stamp control register + PTPTSCR: mmio.Mmio(packed struct(u32) { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved8: u2, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding: u13, + }), + /// Ethernet PTP subsecond increment register + PTPSSIR: mmio.Mmio(packed struct(u32) { + /// STSSI + STSSI: u8, + padding: u24, + }), + /// Ethernet PTP time stamp high register + PTPTSHR: mmio.Mmio(packed struct(u32) { + /// STS + STS: u32, + }), + /// Ethernet PTP time stamp low register + PTPTSLR: mmio.Mmio(packed struct(u32) { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, + }), + /// Ethernet PTP time stamp high update register + PTPTSHUR: mmio.Mmio(packed struct(u32) { + /// TSUS + TSUS: u32, + }), + /// Ethernet PTP time stamp low update register + PTPTSLUR: mmio.Mmio(packed struct(u32) { + /// TSUSS + TSUSS: u31, + /// TSUPNS + TSUPNS: u1, + }), + /// Ethernet PTP time stamp addend register + PTPTSAR: mmio.Mmio(packed struct(u32) { + /// TSA + TSA: u32, + }), + /// Ethernet PTP target time high register + PTPTTHR: mmio.Mmio(packed struct(u32) { + /// 0 + TTSH: u32, + }), + /// Ethernet PTP target time low register + PTPTTLR: mmio.Mmio(packed struct(u32) { + /// TTSL + TTSL: u32, + }), + reserved40: [4]u8, + /// Ethernet PTP time stamp status register + PTPTSSR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding: u30, + }), + /// Ethernet PTP PPS control register + PTPPPSCR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding: u30, + }), + }; + + /// General purpose timers + pub const TIM2 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// TIM5 option register + OR: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// Timer Input 4 remap + ITR1_RMP: u2, + padding: u20, + }), + }; + + /// General purpose timers + pub const TIM3 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// Ethernet: MAC management counters + pub const Ethernet_MMC = extern struct { + /// Ethernet MMC control register + MMCCR: mmio.Mmio(packed struct(u32) { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding: u26, + }), + /// Ethernet MMC receive interrupt register + MMCRIR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// RFCES + RFCES: u1, + /// RFAES + RFAES: u1, + reserved17: u10, + /// RGUFS + RGUFS: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt register + MMCTIR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// TGFSCS + TGFSCS: u1, + /// TGFMSCS + TGFMSCS: u1, + reserved21: u5, + /// TGFS + TGFS: u1, + padding: u10, + }), + /// Ethernet MMC receive interrupt mask register + MMCRIMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// RFCEM + RFCEM: u1, + /// RFAEM + RFAEM: u1, + reserved17: u10, + /// RGUFM + RGUFM: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt mask register + MMCTIMR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// TGFSCM + TGFSCM: u1, + /// TGFMSCM + TGFMSCM: u1, + /// TGFM + TGFM: u1, + padding: u15, + }), + reserved76: [56]u8, + /// Ethernet MMC transmitted good frames after a single collision counter + MMCTGFSCCR: mmio.Mmio(packed struct(u32) { + /// TGFSCC + TGFSCC: u32, + }), + /// Ethernet MMC transmitted good frames after more than a single collision + MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { + /// TGFMSCC + TGFMSCC: u32, + }), + reserved104: [20]u8, + /// Ethernet MMC transmitted good frames counter register + MMCTGFCR: mmio.Mmio(packed struct(u32) { + /// HTL + TGFC: u32, + }), + reserved148: [40]u8, + /// Ethernet MMC received frames with CRC error counter register + MMCRFCECR: mmio.Mmio(packed struct(u32) { + /// RFCFC + RFCFC: u32, + }), + /// Ethernet MMC received frames with alignment error counter register + MMCRFAECR: mmio.Mmio(packed struct(u32) { + /// RFAEC + RFAEC: u32, + }), + reserved196: [40]u8, + /// MMC received good unicast frames counter register + MMCRGUFCR: mmio.Mmio(packed struct(u32) { + /// RGUFC + RGUFC: u32, + }), + }; + + /// General-purpose-timers + pub const TIM5 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// TIM5 option register + OR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// Timer Input 4 remap + IT4_RMP: u2, + padding: u24, + }), + }; + + /// General purpose timers + pub const TIM9 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding: u24, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + reserved6: u3, + /// Trigger interrupt enable + TIE: u1, + padding: u25, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + reserved6: u3, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + padding: u21, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + reserved6: u3, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved8: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding: u17, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + padding: u24, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + }; + + /// Ethernet: media access control (MAC) + pub const Ethernet_MAC = extern struct { + /// Ethernet MAC configuration register + MACCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// RE + RE: u1, + /// TE + TE: u1, + /// DC + DC: u1, + /// BL + BL: u2, + /// APCS + APCS: u1, + reserved9: u1, + /// RD + RD: u1, + /// IPCO + IPCO: u1, + /// DM + DM: u1, + /// LM + LM: u1, + /// ROD + ROD: u1, + /// FES + FES: u1, + reserved16: u1, + /// CSD + CSD: u1, + /// IFG + IFG: u3, + reserved22: u2, + /// JD + JD: u1, + /// WD + WD: u1, + reserved25: u1, + /// CSTF + CSTF: u1, + padding: u6, + }), + /// Ethernet MAC frame filter register + MACFFR: mmio.Mmio(packed struct(u32) { + /// PM + PM: u1, + /// HU + HU: u1, + /// HM + HM: u1, + /// DAIF + DAIF: u1, + /// RAM + RAM: u1, + /// BFD + BFD: u1, + /// PCF + PCF: u1, + /// SAIF + SAIF: u1, + /// SAF + SAF: u1, + /// HPF + HPF: u1, + reserved31: u21, + /// RA + RA: u1, + }), + /// Ethernet MAC hash table high register + MACHTHR: mmio.Mmio(packed struct(u32) { + /// HTH + HTH: u32, + }), + /// Ethernet MAC hash table low register + MACHTLR: mmio.Mmio(packed struct(u32) { + /// HTL + HTL: u32, + }), + /// Ethernet MAC MII address register + MACMIIAR: mmio.Mmio(packed struct(u32) { + /// MB + MB: u1, + /// MW + MW: u1, + /// CR + CR: u3, + reserved6: u1, + /// MR + MR: u5, + /// PA + PA: u5, + padding: u16, + }), + /// Ethernet MAC MII data register + MACMIIDR: mmio.Mmio(packed struct(u32) { + /// TD + TD: u16, + padding: u16, + }), + /// Ethernet MAC flow control register + MACFCR: mmio.Mmio(packed struct(u32) { + /// FCB + FCB: u1, + /// TFCE + TFCE: u1, + /// RFCE + RFCE: u1, + /// UPFD + UPFD: u1, + /// PLT + PLT: u2, + reserved7: u1, + /// ZQPD + ZQPD: u1, + reserved16: u8, + /// PT + PT: u16, + }), + /// Ethernet MAC VLAN tag register + MACVLANTR: mmio.Mmio(packed struct(u32) { + /// VLANTI + VLANTI: u16, + /// VLANTC + VLANTC: u1, + padding: u15, + }), + reserved44: [12]u8, + /// Ethernet MAC PMT control and status register + MACPMTCSR: mmio.Mmio(packed struct(u32) { + /// PD + PD: u1, + /// MPE + MPE: u1, + /// WFE + WFE: u1, + reserved5: u2, + /// MPR + MPR: u1, + /// WFR + WFR: u1, + reserved9: u2, + /// GU + GU: u1, + reserved31: u21, + /// WFFRPR + WFFRPR: u1, + }), + reserved52: [4]u8, + /// Ethernet MAC debug register + MACDBGR: mmio.Mmio(packed struct(u32) { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding: u26, + }), + /// Ethernet MAC interrupt status register + MACSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMTS + PMTS: u1, + /// MMCS + MMCS: u1, + /// MMCRS + MMCRS: u1, + /// MMCTS + MMCTS: u1, + reserved9: u2, + /// TSTS + TSTS: u1, + padding: u22, + }), + /// Ethernet MAC interrupt mask register + MACIMR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMTIM + PMTIM: u1, + reserved9: u5, + /// TSTIM + TSTIM: u1, + padding: u22, + }), + /// Ethernet MAC address 0 high register + MACA0HR: mmio.Mmio(packed struct(u32) { + /// MAC address0 high + MACA0H: u16, + reserved31: u15, + /// Always 1 + MO: u1, + }), + /// Ethernet MAC address 0 low register + MACA0LR: mmio.Mmio(packed struct(u32) { + /// 0 + MACA0L: u32, + }), + /// Ethernet MAC address 1 high register + MACA1HR: mmio.Mmio(packed struct(u32) { + /// MACA1H + MACA1H: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address1 low register + MACA1LR: mmio.Mmio(packed struct(u32) { + /// MACA1LR + MACA1LR: u32, + }), + /// Ethernet MAC address 2 high register + MACA2HR: mmio.Mmio(packed struct(u32) { + /// MAC2AH + MAC2AH: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address 2 low register + MACA2LR: mmio.Mmio(packed struct(u32) { + /// MACA2L + MACA2L: u31, + padding: u1, + }), + /// Ethernet MAC address 3 high register + MACA3HR: mmio.Mmio(packed struct(u32) { + /// MACA3H + MACA3H: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address 3 low register + MACA3LR: mmio.Mmio(packed struct(u32) { + /// MBCA3L + MBCA3L: u32, + }), + }; + + /// General-purpose-timers + pub const TIM10 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved7: u4, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved9: u7, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + padding: u30, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding: u25, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + }; + + /// General-purpose-timers + pub const TIM11 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved7: u4, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved9: u7, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + padding: u30, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding: u25, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + reserved80: [24]u8, + /// option register + OR: mmio.Mmio(packed struct(u32) { + /// Input 1 remapping capability + RMP: u2, + padding: u30, + }), + }; +}; diff --git a/src/chips/STM32F429.json b/src/chips/STM32F429.json new file mode 100644 index 0000000..efbd775 --- /dev/null +++ b/src/chips/STM32F429.json @@ -0,0 +1,52094 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "RNG": { + "description": "Random number generator", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "Interrupt enable", + "offset": 3, + "size": 1 + }, + "RNGEN": { + "description": "Random number generator\n enable", + "offset": 2, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEIS": { + "description": "Seed error interrupt\n status", + "offset": 6, + "size": 1 + }, + "CEIS": { + "description": "Clock error interrupt\n status", + "offset": 5, + "size": 1 + }, + "SECS": { + "description": "Seed error current status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "CECS": { + "description": "Clock error current status", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "DRDY": { + "description": "Data ready", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RNDATA": { + "description": "Random data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "HASH": { + "description": "Hash processor", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INIT": { + "description": "Initialize message digest\n calculation", + "offset": 2, + "size": 1, + "access": "write-only" + }, + "DMAE": { + "description": "DMA enable", + "offset": 3, + "size": 1 + }, + "DATATYPE": { + "description": "Data type selection", + "offset": 4, + "size": 2 + }, + "MODE": { + "description": "Mode selection", + "offset": 6, + "size": 1 + }, + "ALGO0": { + "description": "Algorithm selection", + "offset": 7, + "size": 1 + }, + "NBW": { + "description": "Number of words already\n pushed", + "offset": 8, + "size": 4, + "access": "read-only" + }, + "DINNE": { + "description": "DIN not empty", + "offset": 12, + "size": 1, + "access": "read-only" + }, + "MDMAT": { + "description": "Multiple DMA Transfers", + "offset": 13, + "size": 1 + }, + "LKEY": { + "description": "Long key selection", + "offset": 16, + "size": 1 + }, + "ALGO1": { + "description": "ALGO", + "offset": 18, + "size": 1 + } + } + } + }, + "DIN": { + "description": "data input register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAIN": { + "description": "Data input", + "offset": 0, + "size": 32 + } + } + } + }, + "STR": { + "description": "start register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCAL": { + "description": "Digest calculation", + "offset": 8, + "size": 1, + "access": "write-only" + }, + "NBLW": { + "description": "Number of valid bits in the last word of\n the message", + "offset": 0, + "size": 5 + } + } + } + }, + "HR0": { + "description": "digest registers", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H0": { + "description": "H0", + "offset": 0, + "size": 32 + } + } + } + }, + "HR1": { + "description": "digest registers", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H1": { + "description": "H1", + "offset": 0, + "size": 32 + } + } + } + }, + "HR2": { + "description": "digest registers", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H2": { + "description": "H2", + "offset": 0, + "size": 32 + } + } + } + }, + "HR3": { + "description": "digest registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H3": { + "description": "H3", + "offset": 0, + "size": 32 + } + } + } + }, + "HR4": { + "description": "digest registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H4": { + "description": "H4", + "offset": 0, + "size": 32 + } + } + } + }, + "IMR": { + "description": "interrupt enable register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCIE": { + "description": "Digest calculation completion interrupt\n enable", + "offset": 1, + "size": 1 + }, + "DINIE": { + "description": "Data input interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 36, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "BUSY": { + "description": "Busy bit", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "DMAS": { + "description": "DMA Status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "DCIS": { + "description": "Digest calculation completion interrupt\n status", + "offset": 1, + "size": 1 + }, + "DINIS": { + "description": "Data input interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "CSR0": { + "description": "context swap registers", + "offset": 248, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR0": { + "description": "CSR0", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR1": { + "description": "context swap registers", + "offset": 252, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR1": { + "description": "CSR1", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR2": { + "description": "context swap registers", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR2": { + "description": "CSR2", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR3": { + "description": "context swap registers", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR3": { + "description": "CSR3", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR4": { + "description": "context swap registers", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR4": { + "description": "CSR4", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR5": { + "description": "context swap registers", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR5": { + "description": "CSR5", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR6": { + "description": "context swap registers", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR6": { + "description": "CSR6", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR7": { + "description": "context swap registers", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR7": { + "description": "CSR7", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR8": { + "description": "context swap registers", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR8": { + "description": "CSR8", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR9": { + "description": "context swap registers", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR9": { + "description": "CSR9", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR10": { + "description": "context swap registers", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR10": { + "description": "CSR10", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR11": { + "description": "context swap registers", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR11": { + "description": "CSR11", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR12": { + "description": "context swap registers", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR12": { + "description": "CSR12", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR13": { + "description": "context swap registers", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR13": { + "description": "CSR13", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR14": { + "description": "context swap registers", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR14": { + "description": "CSR14", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR15": { + "description": "context swap registers", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR15": { + "description": "CSR15", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR16": { + "description": "context swap registers", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR16": { + "description": "CSR16", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR17": { + "description": "context swap registers", + "offset": 316, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR17": { + "description": "CSR17", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR18": { + "description": "context swap registers", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR18": { + "description": "CSR18", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR19": { + "description": "context swap registers", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR19": { + "description": "CSR19", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR20": { + "description": "context swap registers", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR20": { + "description": "CSR20", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR21": { + "description": "context swap registers", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR21": { + "description": "CSR21", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR22": { + "description": "context swap registers", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR22": { + "description": "CSR22", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR23": { + "description": "context swap registers", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR23": { + "description": "CSR23", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR24": { + "description": "context swap registers", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR24": { + "description": "CSR24", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR25": { + "description": "context swap registers", + "offset": 348, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR25": { + "description": "CSR25", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR26": { + "description": "context swap registers", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR26": { + "description": "CSR26", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR27": { + "description": "context swap registers", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR27": { + "description": "CSR27", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR28": { + "description": "context swap registers", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR28": { + "description": "CSR28", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR29": { + "description": "context swap registers", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR29": { + "description": "CSR29", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR30": { + "description": "context swap registers", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR30": { + "description": "CSR30", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR31": { + "description": "context swap registers", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR31": { + "description": "CSR31", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR32": { + "description": "context swap registers", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR32": { + "description": "CSR32", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR33": { + "description": "context swap registers", + "offset": 380, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR33": { + "description": "CSR33", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR34": { + "description": "context swap registers", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR34": { + "description": "CSR34", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR35": { + "description": "context swap registers", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR35": { + "description": "CSR35", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR36": { + "description": "context swap registers", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR36": { + "description": "CSR36", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR37": { + "description": "context swap registers", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR37": { + "description": "CSR37", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR38": { + "description": "context swap registers", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR38": { + "description": "CSR38", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR39": { + "description": "context swap registers", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR39": { + "description": "CSR39", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR40": { + "description": "context swap registers", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR40": { + "description": "CSR40", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR41": { + "description": "context swap registers", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR41": { + "description": "CSR41", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR42": { + "description": "context swap registers", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR42": { + "description": "CSR42", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR43": { + "description": "context swap registers", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR43": { + "description": "CSR43", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR44": { + "description": "context swap registers", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR44": { + "description": "CSR44", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR45": { + "description": "context swap registers", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR45": { + "description": "CSR45", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR46": { + "description": "context swap registers", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR46": { + "description": "CSR46", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR47": { + "description": "context swap registers", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR47": { + "description": "CSR47", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR48": { + "description": "context swap registers", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR48": { + "description": "CSR48", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR49": { + "description": "context swap registers", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR49": { + "description": "CSR49", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR50": { + "description": "context swap registers", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR50": { + "description": "CSR50", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR51": { + "description": "context swap registers", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR51": { + "description": "CSR51", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR52": { + "description": "context swap registers", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR52": { + "description": "CSR52", + "offset": 0, + "size": 32 + } + } + } + }, + "CSR53": { + "description": "context swap registers", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSR53": { + "description": "CSR53", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR0": { + "description": "HASH digest register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H0": { + "description": "H0", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR1": { + "description": "read-only", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H1": { + "description": "H1", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR2": { + "description": "read-only", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H2": { + "description": "H2", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR3": { + "description": "read-only", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H3": { + "description": "H3", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR4": { + "description": "read-only", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H4": { + "description": "H4", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR5": { + "description": "read-only", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H5": { + "description": "H5", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR6": { + "description": "read-only", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H6": { + "description": "H6", + "offset": 0, + "size": 32 + } + } + } + }, + "HASH_HR7": { + "description": "read-only", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "H7": { + "description": "H7", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "CRYP": { + "description": "Cryptographic processor", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALGODIR": { + "description": "Algorithm direction", + "offset": 2, + "size": 1 + }, + "ALGOMODE0": { + "description": "Algorithm mode", + "offset": 3, + "size": 3 + }, + "DATATYPE": { + "description": "Data type selection", + "offset": 6, + "size": 2 + }, + "KEYSIZE": { + "description": "Key size selection (AES mode\n only)", + "offset": 8, + "size": 2 + }, + "FFLUSH": { + "description": "FIFO flush", + "offset": 14, + "size": 1, + "access": "write-only" + }, + "CRYPEN": { + "description": "Cryptographic processor\n enable", + "offset": 15, + "size": 1 + }, + "GCM_CCMPH": { + "description": "GCM_CCMPH", + "offset": 16, + "size": 2 + }, + "ALGOMODE3": { + "description": "ALGOMODE", + "offset": 19, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 3, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "BUSY": { + "description": "Busy bit", + "offset": 4, + "size": 1 + }, + "OFFU": { + "description": "Output FIFO full", + "offset": 3, + "size": 1 + }, + "OFNE": { + "description": "Output FIFO not empty", + "offset": 2, + "size": 1 + }, + "IFNF": { + "description": "Input FIFO not full", + "offset": 1, + "size": 1 + }, + "IFEM": { + "description": "Input FIFO empty", + "offset": 0, + "size": 1 + } + } + } + }, + "DIN": { + "description": "data input register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATAIN": { + "description": "Data input", + "offset": 0, + "size": 32 + } + } + } + }, + "DOUT": { + "description": "data output register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATAOUT": { + "description": "Data output", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACR": { + "description": "DMA control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DOEN": { + "description": "DMA output enable", + "offset": 1, + "size": 1 + }, + "DIEN": { + "description": "DMA input enable", + "offset": 0, + "size": 1 + } + } + } + }, + "IMSCR": { + "description": "interrupt mask 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"IV25": { + "description": "IV25", + "offset": 6, + "size": 1 + }, + "IV24": { + "description": "IV24", + "offset": 7, + "size": 1 + }, + "IV23": { + "description": "IV23", + "offset": 8, + "size": 1 + }, + "IV22": { + "description": "IV22", + "offset": 9, + "size": 1 + }, + "IV21": { + "description": "IV21", + "offset": 10, + "size": 1 + }, + "IV20": { + "description": "IV20", + "offset": 11, + "size": 1 + }, + "IV19": { + "description": "IV19", + "offset": 12, + "size": 1 + }, + "IV18": { + "description": "IV18", + "offset": 13, + "size": 1 + }, + "IV17": { + "description": "IV17", + "offset": 14, + "size": 1 + }, + "IV16": { + "description": "IV16", + "offset": 15, + "size": 1 + }, + "IV15": { + "description": "IV15", + "offset": 16, + "size": 1 + }, + "IV14": { + "description": "IV14", + "offset": 17, + "size": 1 + }, + "IV13": { + "description": "IV13", + "offset": 18, + "size": 1 + }, + "IV12": { + "description": "IV12", + "offset": 19, + "size": 1 + }, + "IV11": { + "description": "IV11", + "offset": 20, + "size": 1 + }, + "IV10": { + "description": "IV10", + "offset": 21, + "size": 1 + }, + "IV9": { + "description": "IV9", + "offset": 22, + "size": 1 + }, + "IV8": { + "description": "IV8", + "offset": 23, + "size": 1 + }, + "IV7": { + "description": "IV7", + "offset": 24, + "size": 1 + }, + "IV6": { + "description": "IV6", + "offset": 25, + "size": 1 + }, + "IV5": { + "description": "IV5", + "offset": 26, + "size": 1 + }, + "IV4": { + "description": "IV4", + "offset": 27, + "size": 1 + }, + "IV3": { + "description": "IV3", + "offset": 28, + "size": 1 + }, + "IV2": { + "description": "IV2", + "offset": 29, + "size": 1 + }, + "IV1": { + "description": "IV1", + "offset": 30, + "size": 1 + }, + "IV0": { + "description": "IV0", + "offset": 31, + "size": 1 + } + } + } + }, + "IV0RR": { + "description": "initialization vector\n registers", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IV63": { + "description": "IV63", + "offset": 0, + "size": 1 + }, + "IV62": { + "description": "IV62", + "offset": 1, + "size": 1 + }, + "IV61": { + "description": "IV61", + "offset": 2, + "size": 1 + }, + "IV60": { + "description": "IV60", + "offset": 3, + "size": 1 + }, + "IV59": { + "description": "IV59", + "offset": 4, + "size": 1 + }, + "IV58": { + "description": "IV58", + "offset": 5, + "size": 1 + }, + "IV57": { + "description": "IV57", + "offset": 6, + "size": 1 + }, + "IV56": { + "description": "IV56", + "offset": 7, + "size": 1 + }, + "IV55": { + "description": "IV55", + "offset": 8, + "size": 1 + }, + "IV54": { + "description": "IV54", + "offset": 9, + "size": 1 + }, + "IV53": { + "description": "IV53", + "offset": 10, + "size": 1 + }, + "IV52": { + "description": "IV52", + "offset": 11, + "size": 1 + }, + "IV51": { + "description": "IV51", + "offset": 12, + "size": 1 + }, + "IV50": { + "description": "IV50", + "offset": 13, + "size": 1 + }, + "IV49": { + "description": "IV49", + "offset": 14, + "size": 1 + }, + "IV48": { + "description": "IV48", + "offset": 15, + "size": 1 + }, + "IV47": { + "description": "IV47", + "offset": 16, + "size": 1 + }, + "IV46": { + "description": "IV46", + "offset": 17, + "size": 1 + }, + "IV45": { + "description": "IV45", + "offset": 18, + "size": 1 + }, + "IV44": { + "description": "IV44", + "offset": 19, + "size": 1 + }, + "IV43": { + "description": "IV43", + "offset": 20, + "size": 1 + }, + "IV42": { + "description": "IV42", + "offset": 21, + "size": 1 + }, + "IV41": { + "description": "IV41", + "offset": 22, + "size": 1 + }, + "IV40": { + "description": "IV40", + "offset": 23, + "size": 1 + }, + "IV39": { + "description": "IV39", + "offset": 24, + "size": 1 + }, + "IV38": { + "description": "IV38", + "offset": 25, + "size": 1 + }, + "IV37": { + "description": "IV37", + "offset": 26, + "size": 1 + }, + "IV36": { + "description": "IV36", + "offset": 27, + "size": 1 + }, + "IV35": { + "description": "IV35", + "offset": 28, + "size": 1 + }, + "IV34": { + "description": "IV34", + "offset": 29, + "size": 1 + }, + "IV33": { + "description": "IV33", + "offset": 30, + "size": 1 + }, + "IV32": { + "description": "IV32", + "offset": 31, + "size": 1 + } + } + } + }, + "IV1LR": { + "description": "initialization vector\n registers", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IV95": { + "description": "IV95", + "offset": 0, + "size": 1 + }, + "IV94": { + "description": "IV94", + "offset": 1, + "size": 1 + }, + "IV93": { + "description": "IV93", + "offset": 2, + "size": 1 + }, + "IV92": { + "description": "IV92", + "offset": 3, + "size": 1 + }, + "IV91": { + "description": "IV91", + "offset": 4, + "size": 1 + }, + "IV90": { + "description": "IV90", + "offset": 5, + "size": 1 + }, + "IV89": { + "description": "IV89", + "offset": 6, + "size": 1 + }, + "IV88": { + "description": "IV88", + "offset": 7, + "size": 1 + }, + "IV87": { + "description": "IV87", + "offset": 8, + "size": 1 + }, + "IV86": { + "description": "IV86", + "offset": 9, + "size": 1 + }, + "IV85": { + "description": "IV85", + "offset": 10, + "size": 1 + }, + "IV84": { + "description": "IV84", + "offset": 11, + "size": 1 + }, + "IV83": { + "description": "IV83", + "offset": 12, + "size": 1 + }, + "IV82": { + "description": "IV82", + "offset": 13, + "size": 1 + }, + "IV81": { + "description": "IV81", + "offset": 14, + "size": 1 + }, + "IV80": { + "description": "IV80", + "offset": 15, + "size": 1 + }, + "IV79": { + "description": "IV79", + "offset": 16, + "size": 1 + }, + "IV78": { + "description": "IV78", + "offset": 17, + "size": 1 + }, + "IV77": { + "description": "IV77", + "offset": 18, + "size": 1 + }, + "IV76": { + "description": "IV76", + "offset": 19, + "size": 1 + }, + "IV75": { + "description": "IV75", + "offset": 20, + "size": 1 + }, + "IV74": { + "description": "IV74", + "offset": 21, + "size": 1 + }, + "IV73": { + "description": "IV73", + "offset": 22, + "size": 1 + }, + "IV72": { + "description": "IV72", + "offset": 23, + "size": 1 + }, + "IV71": { + "description": "IV71", + "offset": 24, + "size": 1 + }, + "IV70": { + "description": "IV70", + "offset": 25, + "size": 1 + }, + "IV69": { + "description": "IV69", + "offset": 26, + "size": 1 + }, + "IV68": { + "description": "IV68", + "offset": 27, + "size": 1 + }, + "IV67": { + "description": "IV67", + "offset": 28, + "size": 1 + }, + "IV66": { + "description": "IV66", + "offset": 29, + "size": 1 + }, + "IV65": { + "description": "IV65", + "offset": 30, + "size": 1 + }, + "IV64": { + "description": "IV64", + "offset": 31, + "size": 1 + } + } + } + }, + "IV1RR": { + "description": "initialization vector\n registers", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IV127": { + "description": "IV127", + "offset": 0, + "size": 1 + }, + "IV126": { + "description": "IV126", + "offset": 1, + "size": 1 + }, + "IV125": { + "description": "IV125", + "offset": 2, + "size": 1 + }, + "IV124": { + "description": "IV124", + "offset": 3, + "size": 1 + }, + "IV123": { + "description": "IV123", + "offset": 4, + "size": 1 + }, + "IV122": { + "description": "IV122", + "offset": 5, + "size": 1 + }, + "IV121": { + "description": "IV121", + "offset": 6, + "size": 1 + }, + "IV120": { + "description": "IV120", + "offset": 7, + "size": 1 + }, + "IV119": { + "description": "IV119", + "offset": 8, + "size": 1 + }, + "IV118": { + "description": "IV118", + "offset": 9, + "size": 1 + }, + "IV117": { + "description": "IV117", + "offset": 10, + "size": 1 + }, + "IV116": { + "description": "IV116", + "offset": 11, + "size": 1 + }, + "IV115": { + "description": "IV115", + "offset": 12, + "size": 1 + }, + "IV114": { + "description": "IV114", + "offset": 13, + "size": 1 + }, + "IV113": { + "description": "IV113", + "offset": 14, + "size": 1 + }, + "IV112": { + "description": "IV112", + "offset": 15, + "size": 1 + }, + "IV111": { + "description": "IV111", + "offset": 16, + "size": 1 + }, + "IV110": { + "description": "IV110", + "offset": 17, + "size": 1 + }, + "IV109": { + "description": "IV109", + "offset": 18, + "size": 1 + }, + "IV108": { + "description": "IV108", + "offset": 19, + "size": 1 + }, + "IV107": { + "description": "IV107", + "offset": 20, + "size": 1 + }, + "IV106": { + "description": "IV106", + "offset": 21, + "size": 1 + }, + "IV105": { + "description": "IV105", + "offset": 22, + "size": 1 + }, + "IV104": { + "description": "IV104", + "offset": 23, + "size": 1 + }, + "IV103": { + "description": "IV103", + "offset": 24, + "size": 1 + }, + "IV102": { + "description": "IV102", + "offset": 25, + "size": 1 + }, + "IV101": { + "description": "IV101", + "offset": 26, + "size": 1 + }, + "IV100": { + "description": "IV100", + "offset": 27, + "size": 1 + }, + "IV99": { + "description": "IV99", + "offset": 28, + "size": 1 + }, + "IV98": { + "description": "IV98", + "offset": 29, + "size": 1 + }, + "IV97": { + "description": "IV97", + "offset": 30, + "size": 1 + }, + "IV96": { + "description": "IV96", + "offset": 31, + "size": 1 + } + } + } + }, + "CSGCMCCM0R": { + "description": "context swap register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM0R": { + "description": "CSGCMCCM0R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM1R": { + "description": "context swap register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM1R": { + "description": "CSGCMCCM1R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM2R": { + "description": "context swap register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM2R": { + "description": "CSGCMCCM2R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM3R": { + "description": "context swap register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM3R": { + "description": "CSGCMCCM3R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM4R": { + "description": "context swap register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM4R": { + "description": "CSGCMCCM4R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM5R": { + "description": "context swap register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM5R": { + "description": "CSGCMCCM5R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM6R": { + "description": "context swap register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM6R": { + "description": "CSGCMCCM6R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCMCCM7R": { + "description": "context swap register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCMCCM7R": { + "description": "CSGCMCCM7R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM0R": { + "description": "context swap register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM0R": { + "description": "CSGCM0R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM1R": { + "description": "context swap register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM1R": { + "description": "CSGCM1R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM2R": { + "description": "context swap register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM2R": { + "description": "CSGCM2R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM3R": { + "description": "context swap register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM3R": { + "description": "CSGCM3R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM4R": { + "description": "context swap register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM4R": { + "description": "CSGCM4R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM5R": { + "description": "context swap register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM5R": { + "description": "CSGCM5R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM6R": { + "description": "context swap register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM6R": { + "description": "CSGCM6R", + "offset": 0, + "size": 32 + } + } + } + }, + "CSGCM7R": { + "description": "context swap register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSGCM7R": { + "description": "CSGCM7R", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "DCMI": { + "description": "Digital camera interface", + "children": { + "registers": { + "CR": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "DCMI enable", + "offset": 14, + "size": 1 + }, + "EDM": { + "description": "Extended data mode", + "offset": 10, + "size": 2 + }, + "FCRC": { + "description": "Frame capture rate control", + "offset": 8, + "size": 2 + }, + "VSPOL": { + "description": "Vertical synchronization\n polarity", + "offset": 7, + "size": 1 + }, + "HSPOL": { + "description": "Horizontal synchronization\n polarity", + "offset": 6, + "size": 1 + }, + "PCKPOL": { + "description": "Pixel clock polarity", + "offset": 5, + "size": 1 + }, + "ESS": { + "description": "Embedded synchronization\n select", + "offset": 4, + "size": 1 + }, + "JPEG": { + "description": "JPEG format", + "offset": 3, + "size": 1 + }, + "CROP": { + "description": "Crop feature", + "offset": 2, + "size": 1 + }, + "CM": { + "description": "Capture mode", + "offset": 1, + "size": 1 + }, + "CAPTURE": { + "description": "Capture enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FNE": { + "description": "FIFO not empty", + "offset": 2, + "size": 1 + }, + "VSYNC": { + "description": "VSYNC", + "offset": 1, + "size": 1 + }, + "HSYNC": { + "description": "HSYNC", + "offset": 0, + "size": 1 + } + } + } + }, + "RIS": { + "description": "raw interrupt status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "LINE_RIS": { + "description": "Line raw interrupt status", + "offset": 4, + "size": 1 + }, + "VSYNC_RIS": { + "description": "VSYNC raw interrupt status", + "offset": 3, + "size": 1 + }, + "ERR_RIS": { + "description": "Synchronization error raw interrupt\n status", + "offset": 2, + "size": 1 + }, + "OVR_RIS": { + "description": "Overrun raw interrupt\n status", + "offset": 1, + "size": 1 + }, + "FRAME_RIS": { + "description": "Capture complete raw interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINE_IE": { + "description": "Line interrupt enable", + "offset": 4, + "size": 1 + }, + "VSYNC_IE": { + "description": "VSYNC interrupt enable", + "offset": 3, + "size": 1 + }, + "ERR_IE": { + "description": "Synchronization error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "OVR_IE": { + "description": "Overrun interrupt enable", + "offset": 1, + "size": 1 + }, + "FRAME_IE": { + "description": "Capture complete interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "MIS": { + "description": "masked interrupt status\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "LINE_MIS": { + "description": "Line masked interrupt\n status", + "offset": 4, + "size": 1 + }, + "VSYNC_MIS": { + "description": "VSYNC masked interrupt\n status", + "offset": 3, + "size": 1 + }, + "ERR_MIS": { + "description": "Synchronization error masked interrupt\n status", + "offset": 2, + "size": 1 + }, + "OVR_MIS": { + "description": "Overrun masked interrupt\n status", + "offset": 1, + "size": 1 + }, + "FRAME_MIS": { + "description": "Capture complete masked interrupt\n status", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "interrupt clear register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "LINE_ISC": { + "description": "line interrupt status\n clear", + "offset": 4, + "size": 1 + }, + "VSYNC_ISC": { + "description": "Vertical synch interrupt status\n clear", + "offset": 3, + "size": 1 + }, + "ERR_ISC": { + "description": "Synchronization error interrupt status\n clear", + "offset": 2, + "size": 1 + }, + "OVR_ISC": { + "description": "Overrun interrupt status\n clear", + "offset": 1, + "size": 1 + }, + "FRAME_ISC": { + "description": "Capture complete interrupt status\n clear", + "offset": 0, + "size": 1 + } + } + } + }, + "ESCR": { + "description": "embedded synchronization code\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEC": { + "description": "Frame end delimiter code", + "offset": 24, + "size": 8 + }, + "LEC": { + "description": "Line end delimiter code", + "offset": 16, + "size": 8 + }, + "LSC": { + "description": "Line start delimiter code", + "offset": 8, + "size": 8 + }, + "FSC": { + "description": "Frame start delimiter code", + "offset": 0, + "size": 8 + } + } + } + }, + "ESUR": { + "description": "embedded synchronization unmask\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEU": { + "description": "Frame end delimiter unmask", + "offset": 24, + "size": 8 + }, + "LEU": { + "description": "Line end delimiter unmask", + "offset": 16, + "size": 8 + }, + "LSU": { + "description": "Line start delimiter\n unmask", + "offset": 8, + "size": 8 + }, + "FSU": { + "description": "Frame start delimiter\n unmask", + "offset": 0, + "size": 8 + } + } + } + }, + "CWSTRT": { + "description": "crop window start", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VST": { + "description": "Vertical start line count", + "offset": 16, + "size": 13 + }, + "HOFFCNT": { + "description": "Horizontal offset count", + "offset": 0, + "size": 14 + } + } + } + }, + "CWSIZE": { + "description": "crop window size", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VLINE": { + "description": "Vertical line count", + "offset": 16, + "size": 14 + }, + "CAPCNT": { + "description": "Capture count", + "offset": 0, + "size": 14 + } + } + } + }, + "DR": { + "description": "data register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Byte3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "Byte2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "Byte1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "Byte0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "FMC": { + "description": "Flexible memory controller", + "children": { + "registers": { + "BCR1": { + "description": "SRAM/NOR-Flash chip-select control register\n 1", + "offset": 0, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCLKEN": { + "description": "CCLKEN", + "offset": 20, + "size": 1 + }, + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR1": { + "description": "SRAM/NOR-Flash chip-select timing register\n 1", + "offset": 4, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR2": { + "description": "SRAM/NOR-Flash chip-select control register\n 2", + "offset": 8, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR2": { + "description": "SRAM/NOR-Flash chip-select timing register\n 2", + "offset": 12, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR3": { + "description": "SRAM/NOR-Flash chip-select control register\n 3", + "offset": 16, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR3": { + "description": "SRAM/NOR-Flash chip-select timing register\n 3", + "offset": 20, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BCR4": { + "description": "SRAM/NOR-Flash chip-select control register\n 4", + "offset": 24, + "size": 32, + "reset_value": 12496, + "reset_mask": 4294967295, + "children": { + "fields": { + "CBURSTRW": { + "description": "CBURSTRW", + "offset": 19, + "size": 1 + }, + "ASYNCWAIT": { + "description": "ASYNCWAIT", + "offset": 15, + "size": 1 + }, + "EXTMOD": { + "description": "EXTMOD", + "offset": 14, + "size": 1 + }, + "WAITEN": { + "description": "WAITEN", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "WREN", + "offset": 12, + "size": 1 + }, + "WAITCFG": { + "description": "WAITCFG", + "offset": 11, + "size": 1 + }, + "WRAPMOD": { + "description": "WRAPMOD", + "offset": 10, + "size": 1 + }, + "WAITPOL": { + "description": "WAITPOL", + "offset": 9, + "size": 1 + }, + "BURSTEN": { + "description": "BURSTEN", + "offset": 8, + "size": 1 + }, + "FACCEN": { + "description": "FACCEN", + "offset": 6, + "size": 1 + }, + "MWID": { + "description": "MWID", + "offset": 4, + "size": 2 + }, + "MTYP": { + "description": "MTYP", + "offset": 2, + "size": 2 + }, + "MUXEN": { + "description": "MUXEN", + "offset": 1, + "size": 1 + }, + "MBKEN": { + "description": "MBKEN", + "offset": 0, + "size": 1 + } + } + } + }, + "BTR4": { + "description": "SRAM/NOR-Flash chip-select timing register\n 4", + "offset": 28, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "BUSTURN": { + "description": "BUSTURN", + "offset": 16, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "PCR2": { + "description": "PC Card/NAND Flash control register\n 2", + "offset": 96, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR2": { + "description": "FIFO status and interrupt register\n 2", + "offset": 100, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM2": { + "description": "Common memory space timing register\n 2", + "offset": 104, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT2": { + "description": "Attribute memory space timing register\n 2", + "offset": 108, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR2": { + "description": "ECC result register 2", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECCx", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR3": { + "description": "PC Card/NAND Flash control register\n 3", + "offset": 128, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR3": { + "description": "FIFO status and interrupt register\n 3", + "offset": 132, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM3": { + "description": "Common memory space timing register\n 3", + "offset": 136, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT3": { + "description": "Attribute memory space timing register\n 3", + "offset": 140, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "ECCR3": { + "description": "ECC result register 3", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ECCx": { + "description": "ECCx", + "offset": 0, + "size": 32 + } + } + } + }, + "PCR4": { + "description": "PC Card/NAND Flash control register\n 4", + "offset": 160, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "ECCPS": { + "description": "ECCPS", + "offset": 17, + "size": 3 + }, + "TAR": { + "description": "TAR", + "offset": 13, + "size": 4 + }, + "TCLR": { + "description": "TCLR", + "offset": 9, + "size": 4 + }, + "ECCEN": { + "description": "ECCEN", + "offset": 6, + "size": 1 + }, + "PWID": { + "description": "PWID", + "offset": 4, + "size": 2 + }, + "PTYP": { + "description": "PTYP", + "offset": 3, + "size": 1 + }, + "PBKEN": { + "description": "PBKEN", + "offset": 2, + "size": 1 + }, + "PWAITEN": { + "description": "PWAITEN", + "offset": 1, + "size": 1 + } + } + } + }, + "SR4": { + "description": "FIFO status and interrupt register\n 4", + "offset": 164, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEMPT": { + "description": "FEMPT", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "IFEN": { + "description": "IFEN", + "offset": 5, + "size": 1 + }, + "ILEN": { + "description": "ILEN", + "offset": 4, + "size": 1 + }, + "IREN": { + "description": "IREN", + "offset": 3, + "size": 1 + }, + "IFS": { + "description": "IFS", + "offset": 2, + "size": 1 + }, + "ILS": { + "description": "ILS", + "offset": 1, + "size": 1 + }, + "IRS": { + "description": "IRS", + "offset": 0, + "size": 1 + } + } + } + }, + "PMEM4": { + "description": "Common memory space timing register\n 4", + "offset": 168, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMHIZx": { + "description": "MEMHIZx", + "offset": 24, + "size": 8 + }, + "MEMHOLDx": { + "description": "MEMHOLDx", + "offset": 16, + "size": 8 + }, + "MEMWAITx": { + "description": "MEMWAITx", + "offset": 8, + "size": 8 + }, + "MEMSETx": { + "description": "MEMSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PATT4": { + "description": "Attribute memory space timing register\n 4", + "offset": 172, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "ATTHIZx": { + "description": "ATTHIZx", + "offset": 24, + "size": 8 + }, + "ATTHOLDx": { + "description": "ATTHOLDx", + "offset": 16, + "size": 8 + }, + "ATTWAITx": { + "description": "ATTWAITx", + "offset": 8, + "size": 8 + }, + "ATTSETx": { + "description": "ATTSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "PIO4": { + "description": "I/O space timing register 4", + "offset": 176, + "size": 32, + "reset_value": 4244438268, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOHIZx": { + "description": "IOHIZx", + "offset": 24, + "size": 8 + }, + "IOHOLDx": { + "description": "IOHOLDx", + "offset": 16, + "size": 8 + }, + "IOWAITx": { + "description": "IOWAITx", + "offset": 8, + "size": 8 + }, + "IOSETx": { + "description": "IOSETx", + "offset": 0, + "size": 8 + } + } + } + }, + "BWTR1": { + "description": "SRAM/NOR-Flash write timing registers\n 1", + "offset": 260, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR2": { + "description": "SRAM/NOR-Flash write timing registers\n 2", + "offset": 268, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR3": { + "description": "SRAM/NOR-Flash write timing registers\n 3", + "offset": 260, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "BWTR4": { + "description": "SRAM/NOR-Flash write timing registers\n 4", + "offset": 268, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "ACCMOD": { + "description": "ACCMOD", + "offset": 28, + "size": 2 + }, + "DATLAT": { + "description": "DATLAT", + "offset": 24, + "size": 4 + }, + "CLKDIV": { + "description": "CLKDIV", + "offset": 20, + "size": 4 + }, + "DATAST": { + "description": "DATAST", + "offset": 8, + "size": 8 + }, + "ADDHLD": { + "description": "ADDHLD", + "offset": 4, + "size": 4 + }, + "ADDSET": { + "description": "ADDSET", + "offset": 0, + "size": 4 + } + } + } + }, + "SDCR1": { + "description": "SDRAM Control Register 1", + "offset": 320, + "size": 32, + "reset_value": 720, + "reset_mask": 4294967295, + "children": { + "fields": { + "NC": { + "description": "Number of column address\n bits", + "offset": 0, + "size": 2 + }, + "NR": { + "description": "Number of row address bits", + "offset": 2, + "size": 2 + }, + "MWID": { + "description": "Memory data bus width", + "offset": 4, + "size": 2 + }, + "NB": { + "description": "Number of internal banks", + "offset": 6, + "size": 1 + }, + "CAS": { + "description": "CAS latency", + "offset": 7, + "size": 2 + }, + "WP": { + "description": "Write protection", + "offset": 9, + "size": 1 + }, + "SDCLK": { + "description": "SDRAM clock configuration", + "offset": 10, + "size": 2 + }, + "RBURST": { + "description": "Burst read", + "offset": 12, + "size": 1 + }, + "RPIPE": { + "description": "Read pipe", + "offset": 13, + "size": 2 + } + } + } + }, + "SDCR2": { + "description": "SDRAM Control Register 2", + "offset": 324, + "size": 32, + "reset_value": 720, + "reset_mask": 4294967295, + "children": { + "fields": { + "NC": { + "description": "Number of column address\n bits", + "offset": 0, + "size": 2 + }, + "NR": { + "description": "Number of row address bits", + "offset": 2, + "size": 2 + }, + "MWID": { + "description": "Memory data bus width", + "offset": 4, + "size": 2 + }, + "NB": { + "description": "Number of internal banks", + "offset": 6, + "size": 1 + }, + "CAS": { + "description": "CAS latency", + "offset": 7, + "size": 2 + }, + "WP": { + "description": "Write protection", + "offset": 9, + "size": 1 + }, + "SDCLK": { + "description": "SDRAM clock configuration", + "offset": 10, + "size": 2 + }, + "RBURST": { + "description": "Burst read", + "offset": 12, + "size": 1 + }, + "RPIPE": { + "description": "Read pipe", + "offset": 13, + "size": 2 + } + } + } + }, + "SDTR1": { + "description": "SDRAM Timing register 1", + "offset": 328, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "TMRD": { + "description": "Load Mode Register to\n Active", + "offset": 0, + "size": 4 + }, + "TXSR": { + "description": "Exit self-refresh delay", + "offset": 4, + "size": 4 + }, + "TRAS": { + "description": "Self refresh time", + "offset": 8, + "size": 4 + }, + "TRC": { + "description": "Row cycle delay", + "offset": 12, + "size": 4 + }, + "TWR": { + "description": "Recovery delay", + "offset": 16, + "size": 4 + }, + "TRP": { + "description": "Row precharge delay", + "offset": 20, + "size": 4 + }, + "TRCD": { + "description": "Row to column delay", + "offset": 24, + "size": 4 + } + } + } + }, + "SDTR2": { + "description": "SDRAM Timing register 2", + "offset": 332, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "TMRD": { + "description": "Load Mode Register to\n Active", + "offset": 0, + "size": 4 + }, + "TXSR": { + "description": "Exit self-refresh delay", + "offset": 4, + "size": 4 + }, + "TRAS": { + "description": "Self refresh time", + "offset": 8, + "size": 4 + }, + "TRC": { + "description": "Row cycle delay", + "offset": 12, + "size": 4 + }, + "TWR": { + "description": "Recovery delay", + "offset": 16, + "size": 4 + }, + "TRP": { + "description": "Row precharge delay", + "offset": 20, + "size": 4 + }, + "TRCD": { + "description": "Row to column delay", + "offset": 24, + "size": 4 + } + } + } + }, + "SDCMR": { + "description": "SDRAM Command Mode register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "Command mode", + "offset": 0, + "size": 3, + "access": "write-only" + }, + "CTB2": { + "description": "Command target bank 2", + "offset": 3, + "size": 1, + "access": "write-only" + }, + "CTB1": { + "description": "Command target bank 1", + "offset": 4, + "size": 1, + "access": "write-only" + }, + "NRFS": { + "description": "Number of Auto-refresh", + "offset": 5, + "size": 4 + }, + "MRD": { + "description": "Mode Register definition", + "offset": 9, + "size": 13 + } + } + } + }, + "SDRTR": { + "description": "SDRAM Refresh Timer register", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRE": { + "description": "Clear Refresh error flag", + "offset": 0, + "size": 1, + "access": "write-only" + }, + "COUNT": { + "description": "Refresh Timer Count", + "offset": 1, + "size": 13 + }, + "REIE": { + "description": "RES Interrupt Enable", + "offset": 14, + "size": 1 + } + } + } + }, + "SDSR": { + "description": "SDRAM Status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RE": { + "description": "Refresh error flag", + "offset": 0, + "size": 1 + }, + "MODES1": { + "description": "Status Mode for Bank 1", + "offset": 1, + "size": 2 + }, + "MODES2": { + "description": "Status Mode for Bank 2", + "offset": 3, + "size": 2 + }, + "BUSY": { + "description": "Busy status", + "offset": 5, + "size": 1 + } + } + } + } + } + } + }, + "DBG": { + "description": "Debug support", + "children": { + "registers": { + "DBGMCU_IDCODE": { + "description": "IDCODE", + "offset": 0, + "size": 32, + "reset_value": 268461073, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DEV_ID": { + "description": "DEV_ID", + "offset": 0, + "size": 12 + }, + "REV_ID": { + "description": "REV_ID", + "offset": 16, + "size": 16 + } + } + } + }, + "DBGMCU_CR": { + "description": "Control Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_SLEEP": { + "description": "DBG_SLEEP", + "offset": 0, + "size": 1 + }, + "DBG_STOP": { + "description": "DBG_STOP", + "offset": 1, + "size": 1 + }, + "DBG_STANDBY": { + "description": "DBG_STANDBY", + "offset": 2, + "size": 1 + }, + "TRACE_IOEN": { + "description": "TRACE_IOEN", + "offset": 5, + "size": 1 + }, + "TRACE_MODE": { + "description": "TRACE_MODE", + "offset": 6, + "size": 2 + } + } + } + }, + "DBGMCU_APB1_FZ": { + "description": "Debug MCU APB1 Freeze registe", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM2_STOP": { + "description": "DBG_TIM2_STOP", + "offset": 0, + "size": 1 + }, + "DBG_TIM3_STOP": { + "description": "DBG_TIM3 _STOP", + "offset": 1, + "size": 1 + }, + "DBG_TIM4_STOP": { + "description": "DBG_TIM4_STOP", + "offset": 2, + "size": 1 + }, + "DBG_TIM5_STOP": { + "description": "DBG_TIM5_STOP", + "offset": 3, + "size": 1 + }, + "DBG_TIM6_STOP": { + "description": "DBG_TIM6_STOP", + "offset": 4, + "size": 1 + }, + "DBG_TIM7_STOP": { + "description": "DBG_TIM7_STOP", + "offset": 5, + "size": 1 + }, + "DBG_TIM12_STOP": { + "description": "DBG_TIM12_STOP", + "offset": 6, + "size": 1 + }, + "DBG_TIM13_STOP": { + "description": "DBG_TIM13_STOP", + "offset": 7, + "size": 1 + }, + "DBG_TIM14_STOP": { + "description": "DBG_TIM14_STOP", + "offset": 8, + "size": 1 + }, + "DBG_WWDG_STOP": { + "description": "DBG_WWDG_STOP", + "offset": 11, + "size": 1 + }, + "DBG_IWDEG_STOP": { + "description": "DBG_IWDEG_STOP", + "offset": 12, + "size": 1 + }, + "DBG_J2C1_SMBUS_TIMEOUT": { + "description": "DBG_J2C1_SMBUS_TIMEOUT", + "offset": 21, + "size": 1 + }, + "DBG_J2C2_SMBUS_TIMEOUT": { + "description": "DBG_J2C2_SMBUS_TIMEOUT", + "offset": 22, + "size": 1 + }, + "DBG_J2C3SMBUS_TIMEOUT": { + "description": "DBG_J2C3SMBUS_TIMEOUT", + "offset": 23, + "size": 1 + }, + "DBG_CAN1_STOP": { + "description": "DBG_CAN1_STOP", + "offset": 25, + "size": 1 + }, + "DBG_CAN2_STOP": { + "description": "DBG_CAN2_STOP", + "offset": 26, + "size": 1 + } + } + } + }, + "DBGMCU_APB2_FZ": { + "description": "Debug MCU APB2 Freeze registe", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBG_TIM1_STOP": { + "description": "TIM1 counter stopped when core is\n halted", + "offset": 0, + "size": 1 + }, + "DBG_TIM8_STOP": { + "description": "TIM8 counter stopped when core is\n halted", + "offset": 1, + "size": 1 + }, + "DBG_TIM9_STOP": { + "description": "TIM9 counter stopped when core is\n halted", + "offset": 16, + "size": 1 + }, + "DBG_TIM10_STOP": { + "description": "TIM10 counter stopped when core is\n halted", + "offset": 17, + "size": 1 + }, + "DBG_TIM11_STOP": { + "description": "TIM11 counter stopped when core is\n halted", + "offset": 18, + "size": 1 + } + } + } + } + } + } + }, + "DMA2": { + "description": "DMA controller", + "children": { + "registers": { + "LISR": { + "description": "low interrupt status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TCIF3": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 27, + "size": 1 + }, + "HTIF3": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 26, + "size": 1 + }, + "TEIF3": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 25, + "size": 1 + }, + "DMEIF3": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 24, + "size": 1 + }, + "FEIF3": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 22, + "size": 1 + }, + "TCIF2": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 21, + "size": 1 + }, + "HTIF2": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 20, + "size": 1 + }, + "TEIF2": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 19, + "size": 1 + }, + "DMEIF2": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 18, + "size": 1 + }, + "FEIF2": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 16, + "size": 1 + }, + "TCIF1": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 11, + "size": 1 + }, + "HTIF1": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 10, + "size": 1 + }, + "TEIF1": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 9, + "size": 1 + }, + "DMEIF1": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 8, + "size": 1 + }, + "FEIF1": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 6, + "size": 1 + }, + "TCIF0": { + "description": "Stream x transfer complete interrupt\n flag (x = 3..0)", + "offset": 5, + "size": 1 + }, + "HTIF0": { + "description": "Stream x half transfer interrupt flag\n (x=3..0)", + "offset": 4, + "size": 1 + }, + "TEIF0": { + "description": "Stream x transfer error interrupt flag\n (x=3..0)", + "offset": 3, + "size": 1 + }, + "DMEIF0": { + "description": "Stream x direct mode error interrupt\n flag (x=3..0)", + "offset": 2, + "size": 1 + }, + "FEIF0": { + "description": "Stream x FIFO error interrupt flag\n (x=3..0)", + "offset": 0, + "size": 1 + } + } + } + }, + "HISR": { + "description": "high interrupt status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TCIF7": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 27, + "size": 1 + }, + "HTIF7": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 26, + "size": 1 + }, + "TEIF7": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 25, + "size": 1 + }, + "DMEIF7": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 24, + "size": 1 + }, + "FEIF7": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 22, + "size": 1 + }, + "TCIF6": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 21, + "size": 1 + }, + "HTIF6": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 20, + "size": 1 + }, + "TEIF6": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 19, + "size": 1 + }, + "DMEIF6": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 18, + "size": 1 + }, + "FEIF6": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 16, + "size": 1 + }, + "TCIF5": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 11, + "size": 1 + }, + "HTIF5": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 10, + "size": 1 + }, + "TEIF5": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 9, + "size": 1 + }, + "DMEIF5": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 8, + "size": 1 + }, + "FEIF5": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 6, + "size": 1 + }, + "TCIF4": { + "description": "Stream x transfer complete interrupt\n flag (x=7..4)", + "offset": 5, + "size": 1 + }, + "HTIF4": { + "description": "Stream x half transfer interrupt flag\n (x=7..4)", + "offset": 4, + "size": 1 + }, + "TEIF4": { + "description": "Stream x transfer error interrupt flag\n (x=7..4)", + "offset": 3, + "size": 1 + }, + "DMEIF4": { + "description": "Stream x direct mode error interrupt\n flag (x=7..4)", + "offset": 2, + "size": 1 + }, + "FEIF4": { + "description": "Stream x FIFO error interrupt flag\n (x=7..4)", + "offset": 0, + "size": 1 + } + } + } + }, + "LIFCR": { + "description": "low interrupt flag clear\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTCIF3": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 27, + "size": 1 + }, + "CHTIF3": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 26, + "size": 1 + }, + "CTEIF3": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 25, + "size": 1 + }, + "CDMEIF3": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 24, + "size": 1 + }, + "CFEIF3": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 22, + "size": 1 + }, + "CTCIF2": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 21, + "size": 1 + }, + "CHTIF2": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 20, + "size": 1 + }, + "CTEIF2": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 19, + "size": 1 + }, + "CDMEIF2": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 18, + "size": 1 + }, + "CFEIF2": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 16, + "size": 1 + }, + "CTCIF1": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 11, + "size": 1 + }, + "CHTIF1": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 10, + "size": 1 + }, + "CTEIF1": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 9, + "size": 1 + }, + "CDMEIF1": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 8, + "size": 1 + }, + "CFEIF1": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 6, + "size": 1 + }, + "CTCIF0": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 3..0)", + "offset": 5, + "size": 1 + }, + "CHTIF0": { + "description": "Stream x clear half transfer interrupt\n flag (x = 3..0)", + "offset": 4, + "size": 1 + }, + "CTEIF0": { + "description": "Stream x clear transfer error interrupt\n flag (x = 3..0)", + "offset": 3, + "size": 1 + }, + "CDMEIF0": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 3..0)", + "offset": 2, + "size": 1 + }, + "CFEIF0": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 3..0)", + "offset": 0, + "size": 1 + } + } + } + }, + "HIFCR": { + "description": "high interrupt flag clear\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTCIF7": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 27, + "size": 1 + }, + "CHTIF7": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 26, + "size": 1 + }, + "CTEIF7": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 25, + "size": 1 + }, + "CDMEIF7": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 24, + "size": 1 + }, + "CFEIF7": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 22, + "size": 1 + }, + "CTCIF6": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 21, + "size": 1 + }, + "CHTIF6": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 20, + "size": 1 + }, + "CTEIF6": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 19, + "size": 1 + }, + "CDMEIF6": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 18, + "size": 1 + }, + "CFEIF6": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 16, + "size": 1 + }, + "CTCIF5": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 11, + "size": 1 + }, + "CHTIF5": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 10, + "size": 1 + }, + "CTEIF5": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 9, + "size": 1 + }, + "CDMEIF5": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 8, + "size": 1 + }, + "CFEIF5": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 6, + "size": 1 + }, + "CTCIF4": { + "description": "Stream x clear transfer complete\n interrupt flag (x = 7..4)", + "offset": 5, + "size": 1 + }, + "CHTIF4": { + "description": "Stream x clear half transfer interrupt\n flag (x = 7..4)", + "offset": 4, + "size": 1 + }, + "CTEIF4": { + "description": "Stream x clear transfer error interrupt\n flag (x = 7..4)", + "offset": 3, + "size": 1 + }, + "CDMEIF4": { + "description": "Stream x clear direct mode error\n interrupt flag (x = 7..4)", + "offset": 2, + "size": 1 + }, + "CFEIF4": { + "description": "Stream x clear FIFO error interrupt flag\n (x = 7..4)", + "offset": 0, + "size": 1 + } + } + } + }, + "S0CR": { + "description": "stream x configuration\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S0NDTR": { + "description": "stream x number of data\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S0PAR": { + "description": "stream x peripheral address\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S0M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S0M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S0FCR": { + "description": "stream x FIFO control register", + "offset": 36, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S1CR": { + "description": "stream x configuration\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S1NDTR": { + "description": "stream x number of data\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S1PAR": { + "description": "stream x peripheral address\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S1M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S1M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S1FCR": { + "description": "stream x FIFO control register", + "offset": 60, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S2CR": { + "description": "stream x configuration\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S2NDTR": { + "description": "stream x number of data\n register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S2PAR": { + "description": "stream x peripheral address\n register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S2M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S2M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S2FCR": { + "description": "stream x FIFO control register", + "offset": 84, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S3CR": { + "description": "stream x configuration\n register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S3NDTR": { + "description": "stream x number of data\n register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S3PAR": { + "description": "stream x peripheral address\n register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S3M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S3M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S3FCR": { + "description": "stream x FIFO control register", + "offset": 108, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S4CR": { + "description": "stream x configuration\n register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S4NDTR": { + "description": "stream x number of data\n register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S4PAR": { + "description": "stream x peripheral address\n register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S4M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S4M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S4FCR": { + "description": "stream x FIFO control register", + "offset": 132, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S5CR": { + "description": "stream x configuration\n register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S5NDTR": { + "description": "stream x number of data\n register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S5PAR": { + "description": "stream x peripheral address\n register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S5M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S5M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S5FCR": { + "description": "stream x FIFO control register", + "offset": 156, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S6CR": { + "description": "stream x configuration\n register", + "offset": 160, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S6NDTR": { + "description": "stream x number of data\n register", + "offset": 164, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S6PAR": { + "description": "stream x peripheral address\n register", + "offset": 168, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S6M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S6M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S6FCR": { + "description": "stream x FIFO control register", + "offset": 180, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + }, + "S7CR": { + "description": "stream x configuration\n register", + "offset": 184, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHSEL": { + "description": "Channel selection", + "offset": 25, + "size": 3 + }, + "MBURST": { + "description": "Memory burst transfer\n configuration", + "offset": 23, + "size": 2 + }, + "PBURST": { + "description": "Peripheral burst transfer\n configuration", + "offset": 21, + "size": 2 + }, + "ACK": { + "description": "ACK", + "offset": 20, + "size": 1 + }, + "CT": { + "description": "Current target (only in double buffer\n mode)", + "offset": 19, + "size": 1 + }, + "DBM": { + "description": "Double buffer mode", + "offset": 18, + "size": 1 + }, + "PL": { + "description": "Priority level", + "offset": 16, + "size": 2 + }, + "PINCOS": { + "description": "Peripheral increment offset\n size", + "offset": 15, + "size": 1 + }, + "MSIZE": { + "description": "Memory data size", + "offset": 13, + "size": 2 + }, + "PSIZE": { + "description": "Peripheral data size", + "offset": 11, + "size": 2 + }, + "MINC": { + "description": "Memory increment mode", + "offset": 10, + "size": 1 + }, + "PINC": { + "description": "Peripheral increment mode", + "offset": 9, + "size": 1 + }, + "CIRC": { + "description": "Circular mode", + "offset": 8, + "size": 1 + }, + "DIR": { + "description": "Data transfer direction", + "offset": 6, + "size": 2 + }, + "PFCTRL": { + "description": "Peripheral flow controller", + "offset": 5, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 4, + "size": 1 + }, + "HTIE": { + "description": "Half transfer interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DMEIE": { + "description": "Direct mode error interrupt\n enable", + "offset": 1, + "size": 1 + }, + "EN": { + "description": "Stream enable / flag stream ready when\n read low", + "offset": 0, + "size": 1 + } + } + } + }, + "S7NDTR": { + "description": "stream x number of data\n register", + "offset": 188, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NDT": { + "description": "Number of data items to\n transfer", + "offset": 0, + "size": 16 + } + } + } + }, + "S7PAR": { + "description": "stream x peripheral address\n register", + "offset": 192, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PA": { + "description": "Peripheral address", + "offset": 0, + "size": 32 + } + } + } + }, + "S7M0AR": { + "description": "stream x memory 0 address\n register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M0A": { + "description": "Memory 0 address", + "offset": 0, + "size": 32 + } + } + } + }, + "S7M1AR": { + "description": "stream x memory 1 address\n register", + "offset": 200, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "M1A": { + "description": "Memory 1 address (used in case of Double\n buffer mode)", + "offset": 0, + "size": 32 + } + } + } + }, + "S7FCR": { + "description": "stream x FIFO control register", + "offset": 204, + "size": 32, + "reset_value": 33, + "reset_mask": 4294967295, + "children": { + "fields": { + "FEIE": { + "description": "FIFO error interrupt\n enable", + "offset": 7, + "size": 1 + }, + "FS": { + "description": "FIFO status", + "offset": 3, + "size": 3, + "access": "read-only" + }, + "DMDIS": { + "description": "Direct mode disable", + "offset": 2, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold selection", + "offset": 0, + "size": 2 + } + } + } + } + } + } + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "children": { + "registers": { + "ACTRL": { + "description": "Auxiliary control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DISMCYCINT": { + "description": "DISMCYCINT", + "offset": 0, + "size": 1 + }, + "DISDEFWBUF": { + "description": "DISDEFWBUF", + "offset": 1, + "size": 1 + }, + "DISFOLD": { + "description": "DISFOLD", + "offset": 2, + "size": 1 + }, + "DISFPCA": { + "description": "DISFPCA", + "offset": 8, + "size": 1 + }, + "DISOOFP": { + "description": "DISOOFP", + "offset": 9, + "size": 1 + } + } + } + } + } + } + }, + "RCC": { + "description": "Reset and clock control", + "children": { + "registers": { + "CR": { + "description": "clock control register", + "offset": 0, + "size": 32, + "reset_value": 131, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLI2SRDY": { + "description": "PLLI2S clock ready flag", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PLLI2SON": { + "description": "PLLI2S enable", + "offset": 26, + "size": 1 + }, + "PLLRDY": { + "description": "Main PLL (PLL) clock ready\n flag", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PLLON": { + "description": "Main PLL (PLL) enable", + "offset": 24, + "size": 1 + }, + "CSSON": { + "description": "Clock security system\n enable", + "offset": 19, + "size": 1 + }, + "HSEBYP": { + "description": "HSE clock bypass", + "offset": 18, + "size": 1 + }, + "HSERDY": { + "description": "HSE clock ready flag", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "HSEON": { + "description": "HSE clock enable", + "offset": 16, + "size": 1 + }, + "HSICAL": { + "description": "Internal high-speed clock\n calibration", + "offset": 8, + "size": 8, + "access": "read-only" + }, + "HSITRIM": { + "description": "Internal high-speed clock\n trimming", + "offset": 3, + "size": 5 + }, + "HSIRDY": { + "description": "Internal high-speed clock ready\n flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "HSION": { + "description": "Internal high-speed clock\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "PLLCFGR": { + "description": "PLL configuration register", + "offset": 4, + "size": 32, + "reset_value": 603992080, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLQ3": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 27, + "size": 1 + }, + "PLLQ2": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 26, + "size": 1 + }, + "PLLQ1": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 25, + "size": 1 + }, + "PLLQ0": { + "description": "Main PLL (PLL) division factor for USB\n OTG FS, SDIO and random number generator\n clocks", + "offset": 24, + "size": 1 + }, + "PLLSRC": { + "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n entry clock source", + "offset": 22, + "size": 1 + }, + "PLLP1": { + "description": "Main PLL (PLL) division factor for main\n system clock", + "offset": 17, + "size": 1 + }, + "PLLP0": { + "description": "Main PLL (PLL) division factor for main\n system clock", + "offset": 16, + "size": 1 + }, + "PLLN8": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 14, + "size": 1 + }, + "PLLN7": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 13, + "size": 1 + }, + "PLLN6": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 12, + "size": 1 + }, + "PLLN5": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 11, + "size": 1 + }, + "PLLN4": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 10, + "size": 1 + }, + "PLLN3": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 9, + "size": 1 + }, + "PLLN2": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 8, + "size": 1 + }, + "PLLN1": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 7, + "size": 1 + }, + "PLLN0": { + "description": "Main PLL (PLL) multiplication factor for\n VCO", + "offset": 6, + "size": 1 + }, + "PLLM5": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 5, + "size": 1 + }, + "PLLM4": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 4, + "size": 1 + }, + "PLLM3": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 3, + "size": 1 + }, + "PLLM2": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 2, + "size": 1 + }, + "PLLM1": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 1, + "size": 1 + }, + "PLLM0": { + "description": "Division factor for the main PLL (PLL)\n and audio PLL (PLLI2S) input clock", + "offset": 0, + "size": 1 + } + } + } + }, + "CFGR": { + "description": "clock configuration register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCO2": { + "description": "Microcontroller clock output\n 2", + "offset": 30, + "size": 2 + }, + "MCO2PRE": { + "description": "MCO2 prescaler", + "offset": 27, + "size": 3 + }, + "MCO1PRE": { + "description": "MCO1 prescaler", + "offset": 24, + "size": 3 + }, + "I2SSRC": { + "description": "I2S clock selection", + "offset": 23, + "size": 1 + }, + "MCO1": { + "description": "Microcontroller clock output\n 1", + "offset": 21, + "size": 2 + }, + "RTCPRE": { + "description": "HSE division factor for RTC\n clock", + "offset": 16, + "size": 5 + }, + "PPRE2": { + "description": "APB high-speed prescaler\n (APB2)", + "offset": 13, + "size": 3 + }, + "PPRE1": { + "description": "APB Low speed prescaler\n (APB1)", + "offset": 10, + "size": 3 + }, + "HPRE": { + "description": "AHB prescaler", + "offset": 4, + "size": 4 + }, + "SWS1": { + "description": "System clock switch status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "SWS0": { + "description": "System clock switch status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SW1": { + "description": "System clock switch", + "offset": 1, + "size": 1 + }, + "SW0": { + "description": "System clock switch", + "offset": 0, + "size": 1 + } + } + } + }, + "CIR": { + "description": "clock interrupt register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSSC": { + "description": "Clock security system interrupt\n clear", + "offset": 23, + "size": 1, + "access": "write-only" + }, + "PLLI2SRDYC": { + "description": "PLLI2S ready interrupt\n clear", + "offset": 21, + "size": 1, + "access": "write-only" + }, + "PLLRDYC": { + "description": "Main PLL(PLL) ready interrupt\n clear", + "offset": 20, + "size": 1, + "access": "write-only" + }, + "HSERDYC": { + "description": "HSE ready interrupt clear", + "offset": 19, + "size": 1, + "access": "write-only" + }, + "HSIRDYC": { + "description": "HSI ready interrupt clear", + "offset": 18, + "size": 1, + "access": "write-only" + }, + "LSERDYC": { + "description": "LSE ready interrupt clear", + "offset": 17, + "size": 1, + "access": "write-only" + }, + "LSIRDYC": { + "description": "LSI ready interrupt clear", + "offset": 16, + "size": 1, + "access": "write-only" + }, + "PLLI2SRDYIE": { + "description": "PLLI2S ready interrupt\n enable", + "offset": 13, + "size": 1 + }, + "PLLRDYIE": { + "description": "Main PLL (PLL) ready interrupt\n enable", + "offset": 12, + "size": 1 + }, + "HSERDYIE": { + "description": "HSE ready interrupt enable", + "offset": 11, + "size": 1 + }, + "HSIRDYIE": { + "description": "HSI ready interrupt enable", + "offset": 10, + "size": 1 + }, + "LSERDYIE": { + "description": "LSE ready interrupt enable", + "offset": 9, + "size": 1 + }, + "LSIRDYIE": { + "description": "LSI ready interrupt enable", + "offset": 8, + "size": 1 + }, + "CSSF": { + "description": "Clock security system interrupt\n flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "PLLI2SRDYF": { + "description": "PLLI2S ready interrupt\n flag", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "PLLRDYF": { + "description": "Main PLL (PLL) ready interrupt\n flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "HSERDYF": { + "description": "HSE ready interrupt flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "HSIRDYF": { + "description": "HSI ready interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "LSERDYF": { + "description": "LSE ready interrupt flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSIRDYF": { + "description": "LSI ready interrupt flag", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "AHB1RSTR": { + "description": "AHB1 peripheral reset register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGHSRST": { + "description": "USB OTG HS module reset", + "offset": 29, + "size": 1 + }, + "ETHMACRST": { + "description": "Ethernet MAC reset", + "offset": 25, + "size": 1 + }, + "DMA2RST": { + "description": "DMA2 reset", + "offset": 22, + "size": 1 + }, + "DMA1RST": { + "description": "DMA2 reset", + "offset": 21, + "size": 1 + }, + "CRCRST": { + "description": "CRC reset", + "offset": 12, + "size": 1 + }, + "GPIOIRST": { + "description": "IO port I reset", + "offset": 8, + "size": 1 + }, + "GPIOHRST": { + "description": "IO port H reset", + "offset": 7, + "size": 1 + }, + "GPIOGRST": { + "description": "IO port G reset", + "offset": 6, + "size": 1 + }, + "GPIOFRST": { + "description": "IO port F reset", + "offset": 5, + "size": 1 + }, + "GPIOERST": { + "description": "IO port E reset", + "offset": 4, + "size": 1 + }, + "GPIODRST": { + "description": "IO port D reset", + "offset": 3, + "size": 1 + }, + "GPIOCRST": { + "description": "IO port C reset", + "offset": 2, + "size": 1 + }, + "GPIOBRST": { + "description": "IO port B reset", + "offset": 1, + "size": 1 + }, + "GPIOARST": { + "description": "IO port A reset", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB2RSTR": { + "description": "AHB2 peripheral reset register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSRST": { + "description": "USB OTG FS module reset", + "offset": 7, + "size": 1 + }, + "RNGRST": { + "description": "Random number generator module\n reset", + "offset": 6, + "size": 1 + }, + "HSAHRST": { + "description": "Hash module reset", + "offset": 5, + "size": 1 + }, + "CRYPRST": { + "description": "Cryptographic module reset", + "offset": 4, + "size": 1 + }, + "DCMIRST": { + "description": "Camera interface reset", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3RSTR": { + "description": "AHB3 peripheral reset register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FMCRST": { + "description": "Flexible memory controller module\n reset", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1RSTR": { + "description": "APB1 peripheral reset register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2RST": { + "description": "TIM2 reset", + "offset": 0, + "size": 1 + }, + "TIM3RST": { + "description": "TIM3 reset", + "offset": 1, + "size": 1 + }, + "TIM4RST": { + "description": "TIM4 reset", + "offset": 2, + "size": 1 + }, + "TIM5RST": { + "description": "TIM5 reset", + "offset": 3, + "size": 1 + }, + "TIM6RST": { + "description": "TIM6 reset", + "offset": 4, + "size": 1 + }, + "TIM7RST": { + "description": "TIM7 reset", + "offset": 5, + "size": 1 + }, + "TIM12RST": { + "description": "TIM12 reset", + "offset": 6, + "size": 1 + }, + "TIM13RST": { + "description": "TIM13 reset", + "offset": 7, + "size": 1 + }, + "TIM14RST": { + "description": "TIM14 reset", + "offset": 8, + "size": 1 + }, + "WWDGRST": { + "description": "Window watchdog reset", + "offset": 11, + "size": 1 + }, + "SPI2RST": { + "description": "SPI 2 reset", + "offset": 14, + "size": 1 + }, + "SPI3RST": { + "description": "SPI 3 reset", + "offset": 15, + "size": 1 + }, + "UART2RST": { + "description": "USART 2 reset", + "offset": 17, + "size": 1 + }, + "UART3RST": { + "description": "USART 3 reset", + "offset": 18, + "size": 1 + }, + "UART4RST": { + "description": "USART 4 reset", + "offset": 19, + "size": 1 + }, + "UART5RST": { + "description": "USART 5 reset", + "offset": 20, + "size": 1 + }, + "I2C1RST": { + "description": "I2C 1 reset", + "offset": 21, + "size": 1 + }, + "I2C2RST": { + "description": "I2C 2 reset", + "offset": 22, + "size": 1 + }, + "I2C3RST": { + "description": "I2C3 reset", + "offset": 23, + "size": 1 + }, + "CAN1RST": { + "description": "CAN1 reset", + "offset": 25, + "size": 1 + }, + "CAN2RST": { + "description": "CAN2 reset", + "offset": 26, + "size": 1 + }, + "PWRRST": { + "description": "Power interface reset", + "offset": 28, + "size": 1 + }, + "DACRST": { + "description": "DAC reset", + "offset": 29, + "size": 1 + } + } + } + }, + "APB2RSTR": { + "description": "APB2 peripheral reset register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM1RST": { + "description": "TIM1 reset", + "offset": 0, + "size": 1 + }, + "TIM8RST": { + "description": "TIM8 reset", + "offset": 1, + "size": 1 + }, + "USART1RST": { + "description": "USART1 reset", + "offset": 4, + "size": 1 + }, + "USART6RST": { + "description": "USART6 reset", + "offset": 5, + "size": 1 + }, + "ADCRST": { + "description": "ADC interface reset (common to all\n ADCs)", + "offset": 8, + "size": 1 + }, + "SDIORST": { + "description": "SDIO reset", + "offset": 11, + "size": 1 + }, + "SPI1RST": { + "description": "SPI 1 reset", + "offset": 12, + "size": 1 + }, + "SYSCFGRST": { + "description": "System configuration controller\n reset", + "offset": 14, + "size": 1 + }, + "TIM9RST": { + "description": "TIM9 reset", + "offset": 16, + "size": 1 + }, + "TIM10RST": { + "description": "TIM10 reset", + "offset": 17, + "size": 1 + }, + "TIM11RST": { + "description": "TIM11 reset", + "offset": 18, + "size": 1 + } + } + } + }, + "AHB1ENR": { + "description": "AHB1 peripheral clock register", + "offset": 48, + "size": 32, + "reset_value": 1048576, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGHSULPIEN": { + "description": "USB OTG HSULPI clock\n enable", + "offset": 30, + "size": 1 + }, + "OTGHSEN": { + "description": "USB OTG HS clock enable", + "offset": 29, + "size": 1 + }, + "ETHMACPTPEN": { + "description": "Ethernet PTP clock enable", + "offset": 28, + "size": 1 + }, + "ETHMACRXEN": { + "description": "Ethernet Reception clock\n enable", + "offset": 27, + "size": 1 + }, + "ETHMACTXEN": { + "description": "Ethernet Transmission clock\n enable", + "offset": 26, + "size": 1 + }, + "ETHMACEN": { + "description": "Ethernet MAC clock enable", + "offset": 25, + "size": 1 + }, + "DMA2EN": { + "description": "DMA2 clock enable", + "offset": 22, + "size": 1 + }, + "DMA1EN": { + "description": "DMA1 clock enable", + "offset": 21, + "size": 1 + }, + "CCMDATARAMEN": { + "description": "CCM data RAM clock enable", + "offset": 20, + "size": 1 + }, + "BKPSRAMEN": { + "description": "Backup SRAM interface clock\n enable", + "offset": 18, + "size": 1 + }, + "CRCEN": { + "description": "CRC clock enable", + "offset": 12, + "size": 1 + }, + "GPIOIEN": { + "description": "IO port I clock enable", + "offset": 8, + "size": 1 + }, + "GPIOHEN": { + "description": "IO port H clock enable", + "offset": 7, + "size": 1 + }, + "GPIOGEN": { + "description": "IO port G clock enable", + "offset": 6, + "size": 1 + }, + "GPIOFEN": { + "description": "IO port F clock enable", + "offset": 5, + "size": 1 + }, + "GPIOEEN": { + "description": "IO port E clock enable", + "offset": 4, + "size": 1 + }, + "GPIODEN": { + "description": "IO port D clock enable", + "offset": 3, + "size": 1 + }, + "GPIOCEN": { + "description": "IO port C clock enable", + "offset": 2, + "size": 1 + }, + "GPIOBEN": { + "description": "IO port B clock enable", + "offset": 1, + "size": 1 + }, + "GPIOAEN": { + "description": "IO port A clock enable", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB2ENR": { + "description": "AHB2 peripheral clock enable\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSEN": { + "description": "USB OTG FS clock enable", + "offset": 7, + "size": 1 + }, + "RNGEN": { + "description": "Random number generator clock\n enable", + "offset": 6, + "size": 1 + }, + "HASHEN": { + "description": "Hash modules clock enable", + "offset": 5, + "size": 1 + }, + "CRYPEN": { + "description": "Cryptographic modules clock\n enable", + "offset": 4, + "size": 1 + }, + "DCMIEN": { + "description": "Camera interface enable", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3ENR": { + "description": "AHB3 peripheral clock enable\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FMCEN": { + "description": "Flexible memory controller module clock\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1ENR": { + "description": "APB1 peripheral clock enable\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2EN": { + "description": "TIM2 clock enable", + "offset": 0, + "size": 1 + }, + "TIM3EN": { + "description": "TIM3 clock enable", + "offset": 1, + "size": 1 + }, + "TIM4EN": { + "description": "TIM4 clock enable", + "offset": 2, + "size": 1 + }, + "TIM5EN": { + "description": "TIM5 clock enable", + "offset": 3, + "size": 1 + }, + "TIM6EN": { + "description": "TIM6 clock enable", + "offset": 4, + "size": 1 + }, + "TIM7EN": { + "description": "TIM7 clock enable", + "offset": 5, + "size": 1 + }, + "TIM12EN": { + "description": "TIM12 clock enable", + "offset": 6, + "size": 1 + }, + "TIM13EN": { + "description": "TIM13 clock enable", + "offset": 7, + "size": 1 + }, + "TIM14EN": { + "description": "TIM14 clock enable", + "offset": 8, + "size": 1 + }, + "WWDGEN": { + "description": "Window watchdog clock\n enable", + "offset": 11, + "size": 1 + }, + "SPI2EN": { + "description": "SPI2 clock enable", + "offset": 14, + "size": 1 + }, + "SPI3EN": { + "description": "SPI3 clock enable", + "offset": 15, + "size": 1 + }, + "USART2EN": { + "description": "USART 2 clock enable", + "offset": 17, + "size": 1 + }, + "USART3EN": { + "description": "USART3 clock enable", + "offset": 18, + "size": 1 + }, + "UART4EN": { + "description": "UART4 clock enable", + "offset": 19, + "size": 1 + }, + "UART5EN": { + "description": "UART5 clock enable", + "offset": 20, + "size": 1 + }, + "I2C1EN": { + "description": "I2C1 clock enable", + "offset": 21, + "size": 1 + }, + "I2C2EN": { + "description": "I2C2 clock enable", + "offset": 22, + "size": 1 + }, + "I2C3EN": { + "description": "I2C3 clock enable", + "offset": 23, + "size": 1 + }, + "CAN1EN": { + "description": "CAN 1 clock enable", + "offset": 25, + "size": 1 + }, + "CAN2EN": { + "description": "CAN 2 clock enable", + "offset": 26, + "size": 1 + }, + "PWREN": { + "description": "Power interface clock\n enable", + "offset": 28, + "size": 1 + }, + "DACEN": { + "description": "DAC interface clock enable", + "offset": 29, + "size": 1 + } + } + } + }, + "APB2ENR": { + "description": "APB2 peripheral clock enable\n register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM1EN": { + "description": "TIM1 clock enable", + "offset": 0, + "size": 1 + }, + "TIM8EN": { + "description": "TIM8 clock enable", + "offset": 1, + "size": 1 + }, + "USART1EN": { + "description": "USART1 clock enable", + "offset": 4, + "size": 1 + }, + "USART6EN": { + "description": "USART6 clock enable", + "offset": 5, + "size": 1 + }, + "ADC1EN": { + "description": "ADC1 clock enable", + "offset": 8, + "size": 1 + }, + "ADC2EN": { + "description": "ADC2 clock enable", + "offset": 9, + "size": 1 + }, + "ADC3EN": { + "description": "ADC3 clock enable", + "offset": 10, + "size": 1 + }, + "SDIOEN": { + "description": "SDIO clock enable", + "offset": 11, + "size": 1 + }, + "SPI1EN": { + "description": "SPI1 clock enable", + "offset": 12, + "size": 1 + }, + "SYSCFGEN": { + "description": "System configuration controller clock\n enable", + "offset": 14, + "size": 1 + }, + "TIM9EN": { + "description": "TIM9 clock enable", + "offset": 16, + "size": 1 + }, + "TIM10EN": { + "description": "TIM10 clock enable", + "offset": 17, + "size": 1 + }, + "TIM11EN": { + "description": "TIM11 clock enable", + "offset": 18, + "size": 1 + } + } + } + }, + "AHB1LPENR": { + "description": "AHB1 peripheral clock enable in low power\n mode register", + "offset": 80, + "size": 32, + "reset_value": 2120716799, + "reset_mask": 4294967295, + "children": { + "fields": { + "GPIOALPEN": { + "description": "IO port A clock enable during sleep\n mode", + "offset": 0, + "size": 1 + }, + "GPIOBLPEN": { + "description": "IO port B clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "GPIOCLPEN": { + "description": "IO port C clock enable during Sleep\n mode", + "offset": 2, + "size": 1 + }, + "GPIODLPEN": { + "description": "IO port D clock enable during Sleep\n mode", + "offset": 3, + "size": 1 + }, + "GPIOELPEN": { + "description": "IO port E clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "GPIOFLPEN": { + "description": "IO port F clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "GPIOGLPEN": { + "description": "IO port G clock enable during Sleep\n mode", + "offset": 6, + "size": 1 + }, + "GPIOHLPEN": { + "description": "IO port H clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "GPIOILPEN": { + "description": "IO port I clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "CRCLPEN": { + "description": "CRC clock enable during Sleep\n mode", + "offset": 12, + "size": 1 + }, + "FLITFLPEN": { + "description": "Flash interface clock enable during\n Sleep mode", + "offset": 15, + "size": 1 + }, + "SRAM1LPEN": { + "description": "SRAM 1interface clock enable during\n Sleep mode", + "offset": 16, + "size": 1 + }, + "SRAM2LPEN": { + "description": "SRAM 2 interface clock enable during\n Sleep mode", + "offset": 17, + "size": 1 + }, + "BKPSRAMLPEN": { + "description": "Backup SRAM interface clock enable\n during Sleep mode", + "offset": 18, + "size": 1 + }, + "DMA1LPEN": { + "description": "DMA1 clock enable during Sleep\n mode", + "offset": 21, + "size": 1 + }, + "DMA2LPEN": { + "description": "DMA2 clock enable during Sleep\n mode", + "offset": 22, + "size": 1 + }, + "ETHMACLPEN": { + "description": "Ethernet MAC clock enable during Sleep\n mode", + "offset": 25, + "size": 1 + }, + "ETHMACTXLPEN": { + "description": "Ethernet transmission clock enable\n during Sleep mode", + "offset": 26, + "size": 1 + }, + "ETHMACRXLPEN": { + "description": "Ethernet reception clock enable during\n Sleep mode", + "offset": 27, + "size": 1 + }, + "ETHMACPTPLPEN": { + "description": "Ethernet PTP clock enable during Sleep\n mode", + "offset": 28, + "size": 1 + }, + "OTGHSLPEN": { + "description": "USB OTG HS clock enable during Sleep\n mode", + "offset": 29, + "size": 1 + }, + "OTGHSULPILPEN": { + "description": "USB OTG HS ULPI clock enable during\n Sleep mode", + "offset": 30, + "size": 1 + } + } + } + }, + "AHB2LPENR": { + "description": "AHB2 peripheral clock enable in low power\n mode register", + "offset": 84, + "size": 32, + "reset_value": 241, + "reset_mask": 4294967295, + "children": { + "fields": { + "OTGFSLPEN": { + "description": "USB OTG FS clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "RNGLPEN": { + "description": "Random number generator clock enable\n during Sleep mode", + "offset": 6, + "size": 1 + }, + "HASHLPEN": { + "description": "Hash modules clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "CRYPLPEN": { + "description": "Cryptography modules clock enable during\n Sleep mode", + "offset": 4, + "size": 1 + }, + "DCMILPEN": { + "description": "Camera interface enable during Sleep\n mode", + "offset": 0, + "size": 1 + } + } + } + }, + "AHB3LPENR": { + "description": "AHB3 peripheral clock enable in low power\n mode register", + "offset": 88, + "size": 32, + "reset_value": 1, + "reset_mask": 4294967295, + "children": { + "fields": { + "FMCLPEN": { + "description": "Flexible memory controller module clock\n enable during Sleep mode", + "offset": 0, + "size": 1 + } + } + } + }, + "APB1LPENR": { + "description": "APB1 peripheral clock enable in low power\n mode register", + "offset": 96, + "size": 32, + "reset_value": 922667519, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM2LPEN": { + "description": "TIM2 clock enable during Sleep\n mode", + "offset": 0, + "size": 1 + }, + "TIM3LPEN": { + "description": "TIM3 clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "TIM4LPEN": { + "description": "TIM4 clock enable during Sleep\n mode", + "offset": 2, + "size": 1 + }, + "TIM5LPEN": { + "description": "TIM5 clock enable during Sleep\n mode", + "offset": 3, + "size": 1 + }, + "TIM6LPEN": { + "description": "TIM6 clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "TIM7LPEN": { + "description": "TIM7 clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "TIM12LPEN": { + "description": "TIM12 clock enable during Sleep\n mode", + "offset": 6, + "size": 1 + }, + "TIM13LPEN": { + "description": "TIM13 clock enable during Sleep\n mode", + "offset": 7, + "size": 1 + }, + "TIM14LPEN": { + "description": "TIM14 clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "WWDGLPEN": { + "description": "Window watchdog clock enable during\n Sleep mode", + "offset": 11, + "size": 1 + }, + "SPI2LPEN": { + "description": "SPI2 clock enable during Sleep\n mode", + "offset": 14, + "size": 1 + }, + "SPI3LPEN": { + "description": "SPI3 clock enable during Sleep\n mode", + "offset": 15, + "size": 1 + }, + "USART2LPEN": { + "description": "USART2 clock enable during Sleep\n mode", + "offset": 17, + "size": 1 + }, + "USART3LPEN": { + "description": "USART3 clock enable during Sleep\n mode", + "offset": 18, + "size": 1 + }, + "UART4LPEN": { + "description": "UART4 clock enable during Sleep\n mode", + "offset": 19, + "size": 1 + }, + "UART5LPEN": { + "description": "UART5 clock enable during Sleep\n mode", + "offset": 20, + "size": 1 + }, + "I2C1LPEN": { + "description": "I2C1 clock enable during Sleep\n mode", + "offset": 21, + "size": 1 + }, + "I2C2LPEN": { + "description": "I2C2 clock enable during Sleep\n mode", + "offset": 22, + "size": 1 + }, + "I2C3LPEN": { + "description": "I2C3 clock enable during Sleep\n mode", + "offset": 23, + "size": 1 + }, + "CAN1LPEN": { + "description": "CAN 1 clock enable during Sleep\n mode", + "offset": 25, + "size": 1 + }, + "CAN2LPEN": { + "description": "CAN 2 clock enable during Sleep\n mode", + "offset": 26, + "size": 1 + }, + "PWRLPEN": { + "description": "Power interface clock enable during\n Sleep mode", + "offset": 28, + "size": 1 + }, + "DACLPEN": { + "description": "DAC interface clock enable during Sleep\n mode", + "offset": 29, + "size": 1 + } + } + } + }, + "APB2LPENR": { + "description": "APB2 peripheral clock enabled in low power\n mode register", + "offset": 100, + "size": 32, + "reset_value": 483123, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIM1LPEN": { + "description": "TIM1 clock enable during Sleep\n mode", + "offset": 0, + "size": 1 + }, + "TIM8LPEN": { + "description": "TIM8 clock enable during Sleep\n mode", + "offset": 1, + "size": 1 + }, + "USART1LPEN": { + "description": "USART1 clock enable during Sleep\n mode", + "offset": 4, + "size": 1 + }, + "USART6LPEN": { + "description": "USART6 clock enable during Sleep\n mode", + "offset": 5, + "size": 1 + }, + "ADC1LPEN": { + "description": "ADC1 clock enable during Sleep\n mode", + "offset": 8, + "size": 1 + }, + "ADC2LPEN": { + "description": "ADC2 clock enable during Sleep\n mode", + "offset": 9, + "size": 1 + }, + "ADC3LPEN": { + "description": "ADC 3 clock enable during Sleep\n mode", + "offset": 10, + "size": 1 + }, + "SDIOLPEN": { + "description": "SDIO clock enable during Sleep\n mode", + "offset": 11, + "size": 1 + }, + "SPI1LPEN": { + "description": "SPI 1 clock enable during Sleep\n mode", + "offset": 12, + "size": 1 + }, + "SYSCFGLPEN": { + "description": "System configuration controller clock\n enable during Sleep mode", + "offset": 14, + "size": 1 + }, + "TIM9LPEN": { + "description": "TIM9 clock enable during sleep\n mode", + "offset": 16, + "size": 1 + }, + "TIM10LPEN": { + "description": "TIM10 clock enable during Sleep\n mode", + "offset": 17, + "size": 1 + }, + "TIM11LPEN": { + "description": "TIM11 clock enable during Sleep\n mode", + "offset": 18, + "size": 1 + } + } + } + }, + "BDCR": { + "description": "Backup domain control register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BDRST": { + "description": "Backup domain software\n reset", + "offset": 16, + "size": 1 + }, + "RTCEN": { + "description": "RTC clock enable", + "offset": 15, + "size": 1 + }, + "RTCSEL1": { + "description": "RTC clock source selection", + "offset": 9, + "size": 1 + }, + "RTCSEL0": { + "description": "RTC clock source selection", + "offset": 8, + "size": 1 + }, + "LSEBYP": { + "description": "External low-speed oscillator\n bypass", + "offset": 2, + "size": 1 + }, + "LSERDY": { + "description": "External low-speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSEON": { + "description": "External low-speed oscillator\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CSR": { + "description": "clock control & status\n register", + "offset": 116, + "size": 32, + "reset_value": 234881024, + "reset_mask": 4294967295, + "children": { + "fields": { + "LPWRRSTF": { + "description": "Low-power reset flag", + "offset": 31, + "size": 1 + }, + "WWDGRSTF": { + "description": "Window watchdog reset flag", + "offset": 30, + "size": 1 + }, + "WDGRSTF": { + "description": "Independent watchdog reset\n flag", + "offset": 29, + "size": 1 + }, + "SFTRSTF": { + "description": "Software reset flag", + "offset": 28, + "size": 1 + }, + "PORRSTF": { + "description": "POR/PDR reset flag", + "offset": 27, + "size": 1 + }, + "PADRSTF": { + "description": "PIN reset flag", + "offset": 26, + "size": 1 + }, + "BORRSTF": { + "description": "BOR reset flag", + "offset": 25, + "size": 1 + }, + "RMVF": { + "description": "Remove reset flag", + "offset": 24, + "size": 1 + }, + "LSIRDY": { + "description": "Internal low-speed oscillator\n ready", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LSION": { + "description": "Internal low-speed oscillator\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SSCGR": { + "description": "spread spectrum clock generation\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SSCGEN": { + "description": "Spread spectrum modulation\n enable", + "offset": 31, + "size": 1 + }, + "SPREADSEL": { + "description": "Spread Select", + "offset": 30, + "size": 1 + }, + "INCSTEP": { + "description": "Incrementation step", + "offset": 13, + "size": 15 + }, + "MODPER": { + "description": "Modulation period", + "offset": 0, + "size": 13 + } + } + } + }, + "PLLI2SCFGR": { + "description": "PLLI2S configuration register", + "offset": 132, + "size": 32, + "reset_value": 536883200, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLI2SR": { + "description": "PLLI2S division factor for I2S\n clocks", + "offset": 28, + "size": 3 + }, + "PLLI2SQ": { + "description": "PLLI2S division factor for SAI1\n clock", + "offset": 24, + "size": 4 + }, + "PLLI2SN": { + "description": "PLLI2S multiplication factor for\n VCO", + "offset": 6, + "size": 9 + } + } + } + }, + "DCKCFGR": { + "description": "RCC Dedicated Clock Configuration\n Register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLI2SDIVQ": { + "description": "PLLI2S division factor for SAI1\n clock", + "offset": 0, + "size": 5 + }, + "PLLSAIDIVQ": { + "description": "PLLSAI division factor for SAI1\n clock", + "offset": 8, + "size": 5 + }, + "PLLSAIDIVR": { + "description": "division factor for\n LCD_CLK", + "offset": 16, + "size": 2 + }, + "SAI1ASRC": { + "description": "SAI1-A clock source\n selection", + "offset": 20, + "size": 2 + }, + "SAI1BSRC": { + "description": "SAI1-B clock source\n selection", + "offset": 22, + "size": 2 + }, + "TIMPRE": { + "description": "Timers clocks prescalers\n selection", + "offset": 24, + "size": 1 + } + } + } + }, + "PLLSAICFGR": { + "description": "RCC PLL configuration register", + "offset": 136, + "size": 32, + "reset_value": 603992064, + "reset_mask": 4294967295, + "children": { + "fields": { + "PLLSAIR": { + "description": "PLLSAI division factor for LCD\n clock", + "offset": 28, + "size": 3 + }, + "PLLSAIQ": { + "description": "PLLSAI division factor for SAI1\n clock", + "offset": 24, + "size": 4 + }, + "PLLSAIN": { + "description": "PLLSAI division factor for\n VCO", + "offset": 6, + "size": 9 + } + } + } + } + } + } + }, + "GPIOK": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "children": { + "registers": { + "CPACR": { + "description": "Coprocessor access control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CP": { + "description": "CP", + "offset": 20, + "size": 4 + } + } + } + } + } + } + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "children": { + "registers": { + "STIR": { + "description": "Software trigger interrupt\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTID": { + "description": "Software generated interrupt\n ID", + "offset": 0, + "size": 9 + } + } + } + } + } + } + }, + "SCB": { + "description": "System control block", + "children": { + "registers": { + "CPUID": { + "description": "CPUID base register", + "offset": 0, + "size": 32, + "reset_value": 1091551809, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "Revision": { + "description": "Revision number", + "offset": 0, + "size": 4 + }, + "PartNo": { + "description": "Part number of the\n processor", + "offset": 4, + "size": 12 + }, + "Constant": { + "description": "Reads as 0xF", + "offset": 16, + "size": 4 + }, + "Variant": { + "description": "Variant number", + "offset": 20, + "size": 4 + }, + "Implementer": { + "description": "Implementer code", + "offset": 24, + "size": 8 + } + } + } + }, + "ICSR": { + "description": "Interrupt control and state\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTACTIVE": { + "description": "Active vector", + "offset": 0, + "size": 9 + }, + "RETTOBASE": { + "description": "Return to base level", + "offset": 11, + "size": 1 + }, + "VECTPENDING": { + "description": "Pending vector", + "offset": 12, + "size": 7 + }, + "ISRPENDING": { + "description": "Interrupt pending flag", + "offset": 22, + "size": 1 + }, + "PENDSTCLR": { + "description": "SysTick exception clear-pending\n bit", + "offset": 25, + "size": 1 + }, + "PENDSTSET": { + "description": "SysTick exception set-pending\n bit", + "offset": 26, + "size": 1 + }, + "PENDSVCLR": { + "description": "PendSV clear-pending bit", + "offset": 27, + "size": 1 + }, + "PENDSVSET": { + "description": "PendSV set-pending bit", + "offset": 28, + "size": 1 + }, + "NMIPENDSET": { + "description": "NMI set-pending bit.", + "offset": 31, + "size": 1 + } + } + } + }, + "VTOR": { + "description": "Vector table offset register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TBLOFF": { + "description": "Vector table base offset\n field", + "offset": 9, + "size": 21 + } + } + } + }, + "AIRCR": { + "description": "Application interrupt and reset control\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTRESET": { + "description": "VECTRESET", + "offset": 0, + "size": 1 + }, + "VECTCLRACTIVE": { + "description": "VECTCLRACTIVE", + "offset": 1, + "size": 1 + }, + "SYSRESETREQ": { + "description": "SYSRESETREQ", + "offset": 2, + "size": 1 + }, + "PRIGROUP": { + "description": "PRIGROUP", + "offset": 8, + "size": 3 + }, + "ENDIANESS": { + "description": "ENDIANESS", + "offset": 15, + "size": 1 + }, + "VECTKEYSTAT": { + "description": "Register key", + "offset": 16, + "size": 16 + } + } + } + }, + "SCR": { + "description": "System control register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLEEPONEXIT": { + "description": "SLEEPONEXIT", + "offset": 1, + "size": 1 + }, + "SLEEPDEEP": { + "description": "SLEEPDEEP", + "offset": 2, + "size": 1 + }, + "SEVEONPEND": { + "description": "Send Event on Pending bit", + "offset": 4, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Configuration and control\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONBASETHRDENA": { + "description": "Configures how the processor enters\n Thread mode", + "offset": 0, + "size": 1 + }, + "USERSETMPEND": { + "description": "USERSETMPEND", + "offset": 1, + "size": 1 + }, + "UNALIGN__TRP": { + "description": "UNALIGN_ TRP", + "offset": 3, + "size": 1 + }, + "DIV_0_TRP": { + "description": "DIV_0_TRP", + "offset": 4, + "size": 1 + }, + "BFHFNMIGN": { + "description": "BFHFNMIGN", + "offset": 8, + "size": 1 + }, + "STKALIGN": { + "description": "STKALIGN", + "offset": 9, + "size": 1 + } + } + } + }, + "SHPR1": { + "description": "System handler priority\n registers", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_4": { + "description": "Priority of system handler\n 4", + "offset": 0, + "size": 8 + }, + "PRI_5": { + "description": "Priority of system handler\n 5", + "offset": 8, + "size": 8 + }, + "PRI_6": { + "description": "Priority of system handler\n 6", + "offset": 16, + "size": 8 + } + } + } + }, + "SHPR2": { + "description": "System handler priority\n registers", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_11": { + "description": "Priority of system handler\n 11", + "offset": 24, + "size": 8 + } + } + } + }, + "SHPR3": { + "description": "System handler priority\n registers", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRI_14": { + "description": "Priority of system handler\n 14", + "offset": 16, + "size": 8 + }, + "PRI_15": { + "description": "Priority of system handler\n 15", + "offset": 24, + "size": 8 + } + } + } + }, + "SHCRS": { + "description": "System handler control and state\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEMFAULTACT": { + "description": "Memory management fault exception active\n bit", + "offset": 0, + "size": 1 + }, + "BUSFAULTACT": { + "description": "Bus fault exception active\n bit", + "offset": 1, + "size": 1 + }, + "USGFAULTACT": { + "description": "Usage fault exception active\n bit", + "offset": 3, + "size": 1 + }, + "SVCALLACT": { + "description": "SVC call active bit", + "offset": 7, + "size": 1 + }, + "MONITORACT": { + "description": "Debug monitor active bit", + "offset": 8, + "size": 1 + }, + "PENDSVACT": { + "description": "PendSV exception active\n bit", + "offset": 10, + "size": 1 + }, + "SYSTICKACT": { + "description": "SysTick exception active\n bit", + "offset": 11, + "size": 1 + }, + "USGFAULTPENDED": { + "description": "Usage fault exception pending\n bit", + "offset": 12, + "size": 1 + }, + "MEMFAULTPENDED": { + "description": "Memory management fault exception\n pending bit", + "offset": 13, + "size": 1 + }, + "BUSFAULTPENDED": { + "description": "Bus fault exception pending\n bit", + "offset": 14, + "size": 1 + }, + "SVCALLPENDED": { + "description": "SVC call pending bit", + "offset": 15, + "size": 1 + }, + "MEMFAULTENA": { + "description": "Memory management fault enable\n bit", + "offset": 16, + "size": 1 + }, + "BUSFAULTENA": { + "description": "Bus fault enable bit", + "offset": 17, + "size": 1 + }, + "USGFAULTENA": { + "description": "Usage fault enable bit", + "offset": 18, + "size": 1 + } + } + } + }, + "CFSR_UFSR_BFSR_MMFSR": { + "description": "Configurable fault status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IACCVIOL": { + "description": "Instruction access violation\n flag", + "offset": 1, + "size": 1 + }, + "MUNSTKERR": { + "description": "Memory manager fault on unstacking for a\n return from exception", + "offset": 3, + "size": 1 + }, + "MSTKERR": { + "description": "Memory manager fault on stacking for\n exception entry.", + "offset": 4, + "size": 1 + }, + "MLSPERR": { + "description": "MLSPERR", + "offset": 5, + "size": 1 + }, + "MMARVALID": { + "description": "Memory Management Fault Address Register\n (MMAR) valid flag", + "offset": 7, + "size": 1 + }, + "IBUSERR": { + "description": "Instruction bus error", + "offset": 8, + "size": 1 + }, + "PRECISERR": { + "description": "Precise data bus error", + "offset": 9, + "size": 1 + }, + "IMPRECISERR": { + "description": "Imprecise data bus error", + "offset": 10, + "size": 1 + }, + "UNSTKERR": { + "description": "Bus fault on unstacking for a return\n from exception", + "offset": 11, + "size": 1 + }, + "STKERR": { + "description": "Bus fault on stacking for exception\n entry", + "offset": 12, + "size": 1 + }, + "LSPERR": { + "description": "Bus fault on floating-point lazy state\n preservation", + "offset": 13, + "size": 1 + }, + "BFARVALID": { + "description": "Bus Fault Address Register (BFAR) valid\n flag", + "offset": 15, + "size": 1 + }, + "UNDEFINSTR": { + "description": "Undefined instruction usage\n fault", + "offset": 16, + "size": 1 + }, + "INVSTATE": { + "description": "Invalid state usage fault", + "offset": 17, + "size": 1 + }, + "INVPC": { + "description": "Invalid PC load usage\n fault", + "offset": 18, + "size": 1 + }, + "NOCP": { + "description": "No coprocessor usage\n fault.", + "offset": 19, + "size": 1 + }, + "UNALIGNED": { + "description": "Unaligned access usage\n fault", + "offset": 24, + "size": 1 + }, + "DIVBYZERO": { + "description": "Divide by zero usage fault", + "offset": 25, + "size": 1 + } + } + } + }, + "HFSR": { + "description": "Hard fault status register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VECTTBL": { + "description": "Vector table hard fault", + "offset": 1, + "size": 1 + }, + "FORCED": { + "description": "Forced hard fault", + "offset": 30, + "size": 1 + }, + "DEBUG_VT": { + "description": "Reserved for Debug use", + "offset": 31, + "size": 1 + } + } + } + }, + "MMFAR": { + "description": "Memory management fault address\n register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMFAR": { + "description": "Memory management fault\n address", + "offset": 0, + "size": 32 + } + } + } + }, + "BFAR": { + "description": "Bus fault address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BFAR": { + "description": "Bus fault address", + "offset": 0, + "size": 32 + } + } + } + }, + "AFSR": { + "description": "Auxiliary fault status\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IMPDEF": { + "description": "Implementation defined", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "STK": { + "description": "SysTick timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Counter enable", + "offset": 0, + "size": 1 + }, + "TICKINT": { + "description": "SysTick exception request\n enable", + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "description": "Clock source selection", + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "description": "COUNTFLAG", + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick reload value register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RELOAD": { + "description": "RELOAD value", + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick current value register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CURRENT": { + "description": "Current counter value", + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick calibration value\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TENMS": { + "description": "Calibration value", + "offset": 0, + "size": 24 + }, + "SKEW": { + "description": "SKEW flag: Indicates whether the TENMS\n value is exact", + "offset": 30, + "size": 1 + }, + "NOREF": { + "description": "NOREF flag. Reads as zero", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "MPU": { + "description": "Memory protection unit", + "children": { + "registers": { + "MPU_TYPER": { + "description": "MPU type register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SEPARATE": { + "description": "Separate flag", + "offset": 0, + "size": 1 + }, + "DREGION": { + "description": "Number of MPU data regions", + "offset": 8, + "size": 8 + }, + "IREGION": { + "description": "Number of MPU instruction\n regions", + "offset": 16, + "size": 8 + } + } + } + }, + "MPU_CTRL": { + "description": "MPU control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ENABLE": { + "description": "Enables the MPU", + "offset": 0, + "size": 1 + }, + "HFNMIENA": { + "description": "Enables the operation of MPU during hard\n fault", + "offset": 1, + "size": 1 + }, + "PRIVDEFENA": { + "description": "Enable priviliged software access to\n default memory map", + "offset": 2, + "size": 1 + } + } + } + }, + "MPU_RNR": { + "description": "MPU region number register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region", + "offset": 0, + "size": 8 + } + } + } + }, + "MPU_RBAR": { + "description": "MPU region base address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REGION": { + "description": "MPU region field", + "offset": 0, + "size": 4 + }, + "VALID": { + "description": "MPU region number valid", + "offset": 4, + "size": 1 + }, + "ADDR": { + "description": "Region base address field", + "offset": 5, + "size": 27 + } + } + } + }, + "MPU_RASR": { + "description": "MPU region attribute and size\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENABLE": { + "description": "Region enable bit.", + "offset": 0, + "size": 1 + }, + "SIZE": { + "description": "Size of the MPU protection\n region", + "offset": 1, + "size": 5 + }, + "SRD": { + "description": "Subregion disable bits", + "offset": 8, + "size": 8 + }, + "B": { + "description": "memory attribute", + "offset": 16, + "size": 1 + }, + "C": { + "description": "memory attribute", + "offset": 17, + "size": 1 + }, + "S": { + "description": "Shareable memory attribute", + "offset": 18, + "size": 1 + }, + "TEX": { + "description": "memory attribute", + "offset": 19, + "size": 3 + }, + "AP": { + "description": "Access permission", + "offset": 24, + "size": 3 + }, + "XN": { + "description": "Instruction access disable\n bit", + "offset": 28, + "size": 1 + } + } + } + } + } + } + }, + "FPU": { + "description": "Floting point unit", + "children": { + "registers": { + "FPCCR": { + "description": "Floating-point context control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LSPACT": { + "description": "LSPACT", + "offset": 0, + "size": 1 + }, + "USER": { + "description": "USER", + "offset": 1, + "size": 1 + }, + "THREAD": { + "description": "THREAD", + "offset": 3, + "size": 1 + }, + "HFRDY": { + "description": "HFRDY", + "offset": 4, + "size": 1 + }, + "MMRDY": { + "description": "MMRDY", + "offset": 5, + "size": 1 + }, + "BFRDY": { + "description": "BFRDY", + "offset": 6, + "size": 1 + }, + "MONRDY": { + "description": "MONRDY", + "offset": 8, + "size": 1 + }, + "LSPEN": { + "description": "LSPEN", + "offset": 30, + "size": 1 + }, + "ASPEN": { + "description": "ASPEN", + "offset": 31, + "size": 1 + } + } + } + }, + "FPCAR": { + "description": "Floating-point context address\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS": { + "description": "Location of unpopulated\n floating-point", + "offset": 3, + "size": 29 + } + } + } + }, + "FPSCR": { + "description": "Floating-point status control\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOC": { + "description": "Invalid operation cumulative exception\n bit", + "offset": 0, + "size": 1 + }, + "DZC": { + "description": "Division by zero cumulative exception\n bit.", + "offset": 1, + "size": 1 + }, + "OFC": { + "description": "Overflow cumulative exception\n bit", + "offset": 2, + "size": 1 + }, + "UFC": { + "description": "Underflow cumulative exception\n bit", + "offset": 3, + "size": 1 + }, + "IXC": { + "description": "Inexact cumulative exception\n bit", + "offset": 4, + "size": 1 + }, + "IDC": { + "description": "Input denormal cumulative exception\n bit.", + "offset": 7, + "size": 1 + }, + "RMode": { + "description": "Rounding Mode control\n field", + "offset": 22, + "size": 2 + }, + "FZ": { + "description": "Flush-to-zero mode control\n bit:", + "offset": 24, + "size": 1 + }, + "DN": { + "description": "Default NaN mode control\n bit", + "offset": 25, + "size": 1 + }, + "AHP": { + "description": "Alternative half-precision control\n bit", + "offset": 26, + "size": 1 + }, + "V": { + "description": "Overflow condition code\n flag", + "offset": 28, + "size": 1 + }, + "C": { + "description": "Carry condition code flag", + "offset": 29, + "size": 1 + }, + "Z": { + "description": "Zero condition code flag", + "offset": 30, + "size": 1 + }, + "N": { + "description": "Negative condition code\n flag", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "TIM6": { + "description": "Basic timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "Ethernet_MMC": { + "description": "Ethernet: MAC management counters", + "children": { + "registers": { + "MMCCR": { + "description": "Ethernet MMC control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CR": { + "description": "CR", + "offset": 0, + "size": 1 + }, + "CSR": { + "description": "CSR", + "offset": 1, + "size": 1 + }, + "ROR": { + "description": "ROR", + "offset": 2, + "size": 1 + }, + "MCF": { + "description": "MCF", + "offset": 3, + "size": 1 + }, + "MCP": { + "description": "MCP", + "offset": 4, + "size": 1 + }, + "MCFHP": { + "description": "MCFHP", + "offset": 5, + "size": 1 + } + } + } + }, + "MMCRIR": { + "description": "Ethernet MMC receive interrupt\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCES": { + "description": "RFCES", + "offset": 5, + "size": 1 + }, + "RFAES": { + "description": "RFAES", + "offset": 6, + "size": 1 + }, + "RGUFS": { + "description": "RGUFS", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIR": { + "description": "Ethernet MMC transmit interrupt\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFSCS": { + "description": "TGFSCS", + "offset": 14, + "size": 1 + }, + "TGFMSCS": { + "description": "TGFMSCS", + "offset": 15, + "size": 1 + }, + "TGFS": { + "description": "TGFS", + "offset": 21, + "size": 1 + } + } + } + }, + "MMCRIMR": { + "description": "Ethernet MMC receive interrupt mask\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFCEM": { + "description": "RFCEM", + "offset": 5, + "size": 1 + }, + "RFAEM": { + "description": "RFAEM", + "offset": 6, + "size": 1 + }, + "RGUFM": { + "description": "RGUFM", + "offset": 17, + "size": 1 + } + } + } + }, + "MMCTIMR": { + "description": "Ethernet MMC transmit interrupt mask\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TGFSCM": { + "description": "TGFSCM", + "offset": 14, + "size": 1 + }, + "TGFMSCM": { + "description": "TGFMSCM", + "offset": 15, + "size": 1 + }, + "TGFM": { + "description": "TGFM", + "offset": 16, + "size": 1 + } + } + } + }, + "MMCTGFSCCR": { + "description": "Ethernet MMC transmitted good frames after a\n single collision counter", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFSCC": { + "description": "TGFSCC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFMSCCR": { + "description": "Ethernet MMC transmitted good frames after\n more than a single collision", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFMSCC": { + "description": "TGFMSCC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCTGFCR": { + "description": "Ethernet MMC transmitted good frames counter\n register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TGFC": { + "description": "HTL", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFCECR": { + "description": "Ethernet MMC received frames with CRC error\n counter register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFCFC": { + "description": "RFCFC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRFAECR": { + "description": "Ethernet MMC received frames with alignment\n error counter register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RFAEC": { + "description": "RFAEC", + "offset": 0, + "size": 32 + } + } + } + }, + "MMCRGUFCR": { + "description": "MMC received good unicast frames counter\n register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RGUFC": { + "description": "RGUFC", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "GPIOB": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 640, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 256, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "GPIOA": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "MODER": { + "description": "GPIO port mode register", + "offset": 0, + "size": 32, + "reset_value": 2818572288, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODER15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "MODER14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "MODER13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "MODER12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "MODER11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "MODER10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "MODER9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "MODER8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "MODER7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "MODER6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "MODER5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "MODER4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "MODER3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "MODER2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "MODER1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "MODER0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "OTYPER": { + "description": "GPIO port output type register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OT15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "OT14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "OT13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "OT12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "OT11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "OT10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "OT9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "OT8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "OT7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "OT6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "OT5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "OT4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "OT3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "OT2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "OT1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "OT0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "OSPEEDR": { + "description": "GPIO port output speed\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OSPEEDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "OSPEEDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "OSPEEDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "OSPEEDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "OSPEEDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "OSPEEDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "OSPEEDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "OSPEEDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "OSPEEDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "OSPEEDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "OSPEEDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "OSPEEDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "OSPEEDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "OSPEEDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "OSPEEDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "OSPEEDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "PUPDR": { + "description": "GPIO port pull-up/pull-down\n register", + "offset": 12, + "size": 32, + "reset_value": 1677721600, + "reset_mask": 4294967295, + "children": { + "fields": { + "PUPDR15": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 30, + "size": 2 + }, + "PUPDR14": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 28, + "size": 2 + }, + "PUPDR13": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 26, + "size": 2 + }, + "PUPDR12": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 24, + "size": 2 + }, + "PUPDR11": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 22, + "size": 2 + }, + "PUPDR10": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 20, + "size": 2 + }, + "PUPDR9": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 18, + "size": 2 + }, + "PUPDR8": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 16, + "size": 2 + }, + "PUPDR7": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 14, + "size": 2 + }, + "PUPDR6": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 12, + "size": 2 + }, + "PUPDR5": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 10, + "size": 2 + }, + "PUPDR4": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 8, + "size": 2 + }, + "PUPDR3": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 6, + "size": 2 + }, + "PUPDR2": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 4, + "size": 2 + }, + "PUPDR1": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 2, + "size": 2 + }, + "PUPDR0": { + "description": "Port x configuration bits (y =\n 0..15)", + "offset": 0, + "size": 2 + } + } + } + }, + "IDR": { + "description": "GPIO port input data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDR15": { + "description": "Port input data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "IDR14": { + "description": "Port input data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "IDR13": { + "description": "Port input data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "IDR12": { + "description": "Port input data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "IDR11": { + "description": "Port input data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "IDR10": { + "description": "Port input data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "IDR9": { + "description": "Port input data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "IDR8": { + "description": "Port input data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "IDR7": { + "description": "Port input data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "IDR6": { + "description": "Port input data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "IDR5": { + "description": "Port input data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "IDR4": { + "description": "Port input data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "IDR3": { + "description": "Port input data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "IDR2": { + "description": "Port input data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "IDR1": { + "description": "Port input data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "IDR0": { + "description": "Port input data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "ODR": { + "description": "GPIO port output data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ODR15": { + "description": "Port output data (y =\n 0..15)", + "offset": 15, + "size": 1 + }, + "ODR14": { + "description": "Port output data (y =\n 0..15)", + "offset": 14, + "size": 1 + }, + "ODR13": { + "description": "Port output data (y =\n 0..15)", + "offset": 13, + "size": 1 + }, + "ODR12": { + "description": "Port output data (y =\n 0..15)", + "offset": 12, + "size": 1 + }, + "ODR11": { + "description": "Port output data (y =\n 0..15)", + "offset": 11, + "size": 1 + }, + "ODR10": { + "description": "Port output data (y =\n 0..15)", + "offset": 10, + "size": 1 + }, + "ODR9": { + "description": "Port output data (y =\n 0..15)", + "offset": 9, + "size": 1 + }, + "ODR8": { + "description": "Port output data (y =\n 0..15)", + "offset": 8, + "size": 1 + }, + "ODR7": { + "description": "Port output data (y =\n 0..15)", + "offset": 7, + "size": 1 + }, + "ODR6": { + "description": "Port output data (y =\n 0..15)", + "offset": 6, + "size": 1 + }, + "ODR5": { + "description": "Port output data (y =\n 0..15)", + "offset": 5, + "size": 1 + }, + "ODR4": { + "description": "Port output data (y =\n 0..15)", + "offset": 4, + "size": 1 + }, + "ODR3": { + "description": "Port output data (y =\n 0..15)", + "offset": 3, + "size": 1 + }, + "ODR2": { + "description": "Port output data (y =\n 0..15)", + "offset": 2, + "size": 1 + }, + "ODR1": { + "description": "Port output data (y =\n 0..15)", + "offset": 1, + "size": 1 + }, + "ODR0": { + "description": "Port output data (y =\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "BSRR": { + "description": "GPIO port bit set/reset\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BR15": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 31, + "size": 1 + }, + "BR14": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 30, + "size": 1 + }, + "BR13": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 29, + "size": 1 + }, + "BR12": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 28, + "size": 1 + }, + "BR11": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 27, + "size": 1 + }, + "BR10": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 26, + "size": 1 + }, + "BR9": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 25, + "size": 1 + }, + "BR8": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 24, + "size": 1 + }, + "BR7": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 23, + "size": 1 + }, + "BR6": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 22, + "size": 1 + }, + "BR5": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 21, + "size": 1 + }, + "BR4": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 20, + "size": 1 + }, + "BR3": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 19, + "size": 1 + }, + "BR2": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 18, + "size": 1 + }, + "BR1": { + "description": "Port x reset bit y (y =\n 0..15)", + "offset": 17, + "size": 1 + }, + "BR0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "BS15": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "BS14": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "BS13": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "BS12": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "BS11": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "BS10": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "BS9": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "BS8": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "BS7": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "BS6": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "BS5": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "BS4": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "BS3": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "BS2": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "BS1": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "BS0": { + "description": "Port x set bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "LCKR": { + "description": "GPIO port configuration lock\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LCKK": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 16, + "size": 1 + }, + "LCK15": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 15, + "size": 1 + }, + "LCK14": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 14, + "size": 1 + }, + "LCK13": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 13, + "size": 1 + }, + "LCK12": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 12, + "size": 1 + }, + "LCK11": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 11, + "size": 1 + }, + "LCK10": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 10, + "size": 1 + }, + "LCK9": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 9, + "size": 1 + }, + "LCK8": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 8, + "size": 1 + }, + "LCK7": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 7, + "size": 1 + }, + "LCK6": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 6, + "size": 1 + }, + "LCK5": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 5, + "size": 1 + }, + "LCK4": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 4, + "size": 1 + }, + "LCK3": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 3, + "size": 1 + }, + "LCK2": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 2, + "size": 1 + }, + "LCK1": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 1, + "size": 1 + }, + "LCK0": { + "description": "Port x lock bit y (y=\n 0..15)", + "offset": 0, + "size": 1 + } + } + } + }, + "AFRL": { + "description": "GPIO alternate function low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRL7": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 28, + "size": 4 + }, + "AFRL6": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 24, + "size": 4 + }, + "AFRL5": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 20, + "size": 4 + }, + "AFRL4": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 16, + "size": 4 + }, + "AFRL3": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 12, + "size": 4 + }, + "AFRL2": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 8, + "size": 4 + }, + "AFRL1": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 4, + "size": 4 + }, + "AFRL0": { + "description": "Alternate function selection for port x\n bit y (y = 0..7)", + "offset": 0, + "size": 4 + } + } + } + }, + "AFRH": { + "description": "GPIO alternate function high\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRH15": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 28, + "size": 4 + }, + "AFRH14": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 24, + "size": 4 + }, + "AFRH13": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 20, + "size": 4 + }, + "AFRH12": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 16, + "size": 4 + }, + "AFRH11": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 12, + "size": 4 + }, + "AFRH10": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 8, + "size": 4 + }, + "AFRH9": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 4, + "size": 4 + }, + "AFRH8": { + "description": "Alternate function selection for port x\n bit y (y = 8..15)", + "offset": 0, + "size": 4 + } + } + } + } + } + } + }, + "SYSCFG": { + "description": "System configuration controller", + "children": { + "registers": { + "MEMRM": { + "description": "memory remap register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MEM_MODE": { + "description": "Memory mapping selection", + "offset": 0, + "size": 3 + }, + "FB_MODE": { + "description": "Flash bank mode selection", + "offset": 8, + "size": 1 + }, + "SWP_FMC": { + "description": "FMC memory mapping swap", + "offset": 10, + "size": 2 + } + } + } + }, + "PMC": { + "description": "peripheral mode configuration\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MII_RMII_SEL": { + "description": "Ethernet PHY interface\n selection", + "offset": 23, + "size": 1 + }, + "ADC1DC2": { + "description": "ADC1DC2", + "offset": 16, + "size": 1 + }, + "ADC2DC2": { + "description": "ADC2DC2", + "offset": 17, + "size": 1 + }, + "ADC3DC2": { + "description": "ADC3DC2", + "offset": 18, + "size": 1 + } + } + } + }, + "EXTICR1": { + "description": "external interrupt configuration register\n 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI3": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 12, + "size": 4 + }, + "EXTI2": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 8, + "size": 4 + }, + "EXTI1": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 4, + "size": 4 + }, + "EXTI0": { + "description": "EXTI x configuration (x = 0 to\n 3)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR2": { + "description": "external interrupt configuration register\n 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI7": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 12, + "size": 4 + }, + "EXTI6": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 8, + "size": 4 + }, + "EXTI5": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 4, + "size": 4 + }, + "EXTI4": { + "description": "EXTI x configuration (x = 4 to\n 7)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR3": { + "description": "external interrupt configuration register\n 3", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI11": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 12, + "size": 4 + }, + "EXTI10": { + "description": "EXTI10", + "offset": 8, + "size": 4 + }, + "EXTI9": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 4, + "size": 4 + }, + "EXTI8": { + "description": "EXTI x configuration (x = 8 to\n 11)", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTICR4": { + "description": "external interrupt configuration register\n 4", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI15": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 12, + "size": 4 + }, + "EXTI14": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 8, + "size": 4 + }, + "EXTI13": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 4, + "size": 4 + }, + "EXTI12": { + "description": "EXTI x configuration (x = 12 to\n 15)", + "offset": 0, + "size": 4 + } + } + } + }, + "CMPCR": { + "description": "Compensation cell control\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "READY": { + "description": "READY", + "offset": 8, + "size": 1 + }, + "CMP_PD": { + "description": "Compensation cell\n power-down", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "SPI1": { + "description": "Serial peripheral interface", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BIDIMODE": { + "description": "Bidirectional data mode\n enable", + "offset": 15, + "size": 1 + }, + "BIDIOE": { + "description": "Output enable in bidirectional\n mode", + "offset": 14, + "size": 1 + }, + "CRCEN": { + "description": "Hardware CRC calculation\n enable", + "offset": 13, + "size": 1 + }, + "CRCNEXT": { + "description": "CRC transfer next", + "offset": 12, + "size": 1 + }, + "DFF": { + "description": "Data frame format", + "offset": 11, + "size": 1 + }, + "RXONLY": { + "description": "Receive only", + "offset": 10, + "size": 1 + }, + "SSM": { + "description": "Software slave management", + "offset": 9, + "size": 1 + }, + "SSI": { + "description": "Internal slave select", + "offset": 8, + "size": 1 + }, + "LSBFIRST": { + "description": "Frame format", + "offset": 7, + "size": 1 + }, + "SPE": { + "description": "SPI enable", + "offset": 6, + "size": 1 + }, + "BR": { + "description": "Baud rate control", + "offset": 3, + "size": 3 + }, + "MSTR": { + "description": "Master selection", + "offset": 2, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 1, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXEIE": { + "description": "Tx buffer empty interrupt\n enable", + "offset": 7, + "size": 1 + }, + "RXNEIE": { + "description": "RX buffer not empty interrupt\n enable", + "offset": 6, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 5, + "size": 1 + }, + "FRF": { + "description": "Frame format", + "offset": 4, + "size": 1 + }, + "SSOE": { + "description": "SS output enable", + "offset": 2, + "size": 1 + }, + "TXDMAEN": { + "description": "Tx buffer DMA enable", + "offset": 1, + "size": 1 + }, + "RXDMAEN": { + "description": "Rx buffer DMA enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 8, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIFRFE": { + "description": "TI frame format error", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "BSY": { + "description": "Busy flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "OVR": { + "description": "Overrun flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "MODF": { + "description": "Mode fault", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "CRCERR": { + "description": "CRC error flag", + "offset": 4, + "size": 1 + }, + "UDR": { + "description": "Underrun flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "CHSIDE": { + "description": "Channel side", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "TXE": { + "description": "Transmit buffer empty", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RXNE": { + "description": "Receive buffer not empty", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "data register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 16 + } + } + } + }, + "CRCPR": { + "description": "CRC polynomial register", + "offset": 16, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial register", + "offset": 0, + "size": 16 + } + } + } + }, + "RXCRCR": { + "description": "RX CRC register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RxCRC": { + "description": "Rx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "TXCRCR": { + "description": "TX CRC register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TxCRC": { + "description": "Tx CRC register", + "offset": 0, + "size": 16 + } + } + } + }, + "I2SCFGR": { + "description": "I2S configuration register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "I2SMOD": { + "description": "I2S mode selection", + "offset": 11, + "size": 1 + }, + "I2SE": { + "description": "I2S Enable", + "offset": 10, + "size": 1 + }, + "I2SCFG": { + "description": "I2S configuration mode", + "offset": 8, + "size": 2 + }, + "PCMSYNC": { + "description": "PCM frame synchronization", + "offset": 7, + "size": 1 + }, + "I2SSTD": { + "description": "I2S standard selection", + "offset": 4, + "size": 2 + }, + "CKPOL": { + "description": "Steady state clock\n polarity", + "offset": 3, + "size": 1 + }, + "DATLEN": { + "description": "Data length to be\n transferred", + "offset": 1, + "size": 2 + }, + "CHLEN": { + "description": "Channel length (number of bits per audio\n channel)", + "offset": 0, + "size": 1 + } + } + } + }, + "I2SPR": { + "description": "I2S prescaler register", + "offset": 32, + "size": 32, + "reset_value": 10, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKOE": { + "description": "Master clock output enable", + "offset": 9, + "size": 1 + }, + "ODD": { + "description": "Odd factor for the\n prescaler", + "offset": 8, + "size": 1 + }, + "I2SDIV": { + "description": "I2S Linear prescaler", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "I2C3": { + "description": "Inter-integrated circuit", + "children": { + "registers": { + "CR1": { + "description": "Control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWRST": { + "description": "Software reset", + "offset": 15, + "size": 1 + }, + "ALERT": { + "description": "SMBus alert", + "offset": 13, + "size": 1 + }, + "PEC": { + "description": "Packet error checking", + "offset": 12, + "size": 1 + }, + "POS": { + "description": "Acknowledge/PEC Position (for data\n reception)", + "offset": 11, + "size": 1 + }, + "ACK": { + "description": "Acknowledge enable", + "offset": 10, + "size": 1 + }, + "STOP": { + "description": "Stop generation", + "offset": 9, + "size": 1 + }, + "START": { + "description": "Start generation", + "offset": 8, + "size": 1 + }, + "NOSTRETCH": { + "description": "Clock stretching disable (Slave\n mode)", + "offset": 7, + "size": 1 + }, + "ENGC": { + "description": "General call enable", + "offset": 6, + "size": 1 + }, + "ENPEC": { + "description": "PEC enable", + "offset": 5, + "size": 1 + }, + "ENARP": { + "description": "ARP enable", + "offset": 4, + "size": 1 + }, + "SMBTYPE": { + "description": "SMBus type", + "offset": 3, + "size": 1 + }, + "SMBUS": { + "description": "SMBus mode", + "offset": 1, + "size": 1 + }, + "PE": { + "description": "Peripheral enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LAST": { + "description": "DMA last transfer", + "offset": 12, + "size": 1 + }, + "DMAEN": { + "description": "DMA requests enable", + "offset": 11, + "size": 1 + }, + "ITBUFEN": { + "description": "Buffer interrupt enable", + "offset": 10, + "size": 1 + }, + "ITEVTEN": { + "description": "Event interrupt enable", + "offset": 9, + "size": 1 + }, + "ITERREN": { + "description": "Error interrupt enable", + "offset": 8, + "size": 1 + }, + "FREQ": { + "description": "Peripheral clock frequency", + "offset": 0, + "size": 6 + } + } + } + }, + "OAR1": { + "description": "Own address register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDMODE": { + "description": "Addressing mode (slave\n mode)", + "offset": 15, + "size": 1 + }, + "ADD10": { + "description": "Interface address", + "offset": 8, + "size": 2 + }, + "ADD7": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ADD0": { + "description": "Interface address", + "offset": 0, + "size": 1 + } + } + } + }, + "OAR2": { + "description": "Own address register 2", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADD2": { + "description": "Interface address", + "offset": 1, + "size": 7 + }, + "ENDUAL": { + "description": "Dual addressing mode\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "8-bit data register", + "offset": 0, + "size": 8 + } + } + } + }, + "SR1": { + "description": "Status register 1", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMBALERT": { + "description": "SMBus alert", + "offset": 15, + "size": 1 + }, + "TIMEOUT": { + "description": "Timeout or Tlow error", + "offset": 14, + "size": 1 + }, + "PECERR": { + "description": "PEC Error in reception", + "offset": 12, + "size": 1 + }, + "OVR": { + "description": "Overrun/Underrun", + "offset": 11, + "size": 1 + }, + "AF": { + "description": "Acknowledge failure", + "offset": 10, + "size": 1 + }, + "ARLO": { + "description": "Arbitration lost (master\n mode)", + "offset": 9, + "size": 1 + }, + "BERR": { + "description": "Bus error", + "offset": 8, + "size": 1 + }, + "TxE": { + "description": "Data register empty\n (transmitters)", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "RxNE": { + "description": "Data register not empty\n (receivers)", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "STOPF": { + "description": "Stop detection (slave\n mode)", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ADD10": { + "description": "10-bit header sent (Master\n mode)", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "BTF": { + "description": "Byte transfer finished", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ADDR": { + "description": "Address sent (master mode)/matched\n (slave mode)", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "SB": { + "description": "Start bit (Master mode)", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "SR2": { + "description": "Status register 2", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PEC": { + "description": "acket error checking\n register", + "offset": 8, + "size": 8 + }, + "DUALF": { + "description": "Dual flag (Slave mode)", + "offset": 7, + "size": 1 + }, + "SMBHOST": { + "description": "SMBus host header (Slave\n mode)", + "offset": 6, + "size": 1 + }, + "SMBDEFAULT": { + "description": "SMBus device default address (Slave\n mode)", + "offset": 5, + "size": 1 + }, + "GENCALL": { + "description": "General call address (Slave\n mode)", + "offset": 4, + "size": 1 + }, + "TRA": { + "description": "Transmitter/receiver", + "offset": 2, + "size": 1 + }, + "BUSY": { + "description": "Bus busy", + "offset": 1, + "size": 1 + }, + "MSL": { + "description": "Master/slave", + "offset": 0, + "size": 1 + } + } + } + }, + "CCR": { + "description": "Clock control register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "F_S": { + "description": "I2C master mode selection", + "offset": 15, + "size": 1 + }, + "DUTY": { + "description": "Fast mode duty cycle", + "offset": 14, + "size": 1 + }, + "CCR": { + "description": "Clock control register in Fast/Standard\n mode (Master mode)", + "offset": 0, + "size": 12 + } + } + } + }, + "TRISE": { + "description": "TRISE register", + "offset": 32, + "size": 32, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRISE": { + "description": "Maximum rise time in Fast/Standard mode\n (Master mode)", + "offset": 0, + "size": 6 + } + } + } + }, + "FLTR": { + "description": "I2C FLTR register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DNF": { + "description": "Digital noise filter", + "offset": 0, + "size": 4 + }, + "ANOFF": { + "description": "Analog noise filter OFF", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "DMA2D": { + "description": "DMA2D controller", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MODE": { + "description": "DMA2D mode", + "offset": 16, + "size": 2 + }, + "CEIE": { + "description": "Configuration Error Interrupt\n Enable", + "offset": 13, + "size": 1 + }, + "CTCIE": { + "description": "CLUT transfer complete interrupt\n enable", + "offset": 12, + "size": 1 + }, + "CAEIE": { + "description": "CLUT access error interrupt\n enable", + "offset": 11, + "size": 1 + }, + "TWIE": { + "description": "Transfer watermark interrupt\n enable", + "offset": 10, + "size": 1 + }, + "TCIE": { + "description": "Transfer complete interrupt\n enable", + "offset": 9, + "size": 1 + }, + "TEIE": { + "description": "Transfer error interrupt\n enable", + "offset": 8, + "size": 1 + }, + "ABORT": { + "description": "Abort", + "offset": 2, + "size": 1 + }, + "SUSP": { + "description": "Suspend", + "offset": 1, + "size": 1 + }, + "START": { + "description": "Start", + "offset": 0, + "size": 1 + } + } + } + }, + "ISR": { + "description": "Interrupt Status Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CEIF": { + "description": "Configuration error interrupt\n flag", + "offset": 5, + "size": 1 + }, + "CTCIF": { + "description": "CLUT transfer complete interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CAEIF": { + "description": "CLUT access error interrupt\n flag", + "offset": 3, + "size": 1 + }, + "TWIF": { + "description": "Transfer watermark interrupt\n flag", + "offset": 2, + "size": 1 + }, + "TCIF": { + "description": "Transfer complete interrupt\n flag", + "offset": 1, + "size": 1 + }, + "TEIF": { + "description": "Transfer error interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + }, + "IFCR": { + "description": "interrupt flag clear register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCEIF": { + "description": "Clear configuration error interrupt\n flag", + "offset": 5, + "size": 1 + }, + "CCTCIF": { + "description": "Clear CLUT transfer complete interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CAECIF": { + "description": "Clear CLUT access error interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CTWIF": { + "description": "Clear transfer watermark interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CTCIF": { + "description": "Clear transfer complete interrupt\n flag", + "offset": 1, + "size": 1 + }, + "CTEIF": { + "description": "Clear Transfer error interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + }, + "FGMAR": { + "description": "foreground memory address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "FGOR": { + "description": "foreground offset register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LO": { + "description": "Line offset", + "offset": 0, + "size": 14 + } + } + } + }, + "BGMAR": { + "description": "background memory address\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "BGOR": { + "description": "background offset register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LO": { + "description": "Line offset", + "offset": 0, + "size": 14 + } + } + } + }, + "FGPFCCR": { + "description": "foreground PFC control\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALPHA": { + "description": "Alpha value", + "offset": 24, + "size": 8 + }, + "AM": { + "description": "Alpha mode", + "offset": 16, + "size": 2 + }, + "CS": { + "description": "CLUT size", + "offset": 8, + "size": 8 + }, + "START": { + "description": "Start", + "offset": 5, + "size": 1 + }, + "CCM": { + "description": "CLUT color mode", + "offset": 4, + "size": 1 + }, + "CM": { + "description": "Color mode", + "offset": 0, + "size": 4 + } + } + } + }, + "FGCOLR": { + "description": "foreground color register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RED": { + "description": "Red Value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green Value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue Value", + "offset": 0, + "size": 8 + } + } + } + }, + "BGPFCCR": { + "description": "background PFC control\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALPHA": { + "description": "Alpha value", + "offset": 24, + "size": 8 + }, + "AM": { + "description": "Alpha mode", + "offset": 16, + "size": 2 + }, + "CS": { + "description": "CLUT size", + "offset": 8, + "size": 8 + }, + "START": { + "description": "Start", + "offset": 5, + "size": 1 + }, + "CCM": { + "description": "CLUT Color mode", + "offset": 4, + "size": 1 + }, + "CM": { + "description": "Color mode", + "offset": 0, + "size": 4 + } + } + } + }, + "BGCOLR": { + "description": "background color register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RED": { + "description": "Red Value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green Value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue Value", + "offset": 0, + "size": 8 + } + } + } + }, + "FGCMAR": { + "description": "foreground CLUT memory address\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory Address", + "offset": 0, + "size": 32 + } + } + } + }, + "BGCMAR": { + "description": "background CLUT memory address\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory address", + "offset": 0, + "size": 32 + } + } + } + }, + "OPFCCR": { + "description": "output PFC control register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CM": { + "description": "Color mode", + "offset": 0, + "size": 3 + } + } + } + }, + "OCOLR": { + "description": "output color register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "APLHA": { + "description": "Alpha Channel Value", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "Red Value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green Value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue Value", + "offset": 0, + "size": 8 + } + } + } + }, + "OMAR": { + "description": "output memory address register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MA": { + "description": "Memory Address", + "offset": 0, + "size": 32 + } + } + } + }, + "OOR": { + "description": "output offset register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LO": { + "description": "Line Offset", + "offset": 0, + "size": 14 + } + } + } + }, + "NLR": { + "description": "number of line register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PL": { + "description": "Pixel per lines", + "offset": 16, + "size": 14 + }, + "NL": { + "description": "Number of lines", + "offset": 0, + "size": 16 + } + } + } + }, + "LWR": { + "description": "line watermark register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LW": { + "description": "Line watermark", + "offset": 0, + "size": 16 + } + } + } + }, + "AMTCR": { + "description": "AHB master timer configuration\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DT": { + "description": "Dead Time", + "offset": 8, + "size": 8 + }, + "EN": { + "description": "Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "FGCLUT": { + "description": "FGCLUT", + "offset": 1024, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "APLHA": { + "description": "APLHA", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "RED", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "GREEN", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "BLUE", + "offset": 0, + "size": 8 + } + } + } + }, + "BGCLUT": { + "description": "BGCLUT", + "offset": 2048, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "APLHA": { + "description": "APLHA", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "RED", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "GREEN", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "BLUE", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "SAI": { + "description": "Serial audio interface", + "children": { + "registers": { + "BCR1": { + "description": "BConfiguration register 1", + "offset": 36, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCJDIV": { + "description": "Master clock divider", + "offset": 20, + "size": 4 + }, + "NODIV": { + "description": "No divider", + "offset": 19, + "size": 1 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 17, + "size": 1 + }, + "SAIBEN": { + "description": "Audio block B enable", + "offset": 16, + "size": 1 + }, + "OutDri": { + "description": "Output drive", + "offset": 13, + "size": 1 + }, + "MONO": { + "description": "Mono mode", + "offset": 12, + "size": 1 + }, + "SYNCEN": { + "description": "Synchronization enable", + "offset": 10, + "size": 2 + }, + "CKSTR": { + "description": "Clock strobing edge", + "offset": 9, + "size": 1 + }, + "LSBFIRST": { + "description": "Least significant bit\n first", + "offset": 8, + "size": 1 + }, + "DS": { + "description": "Data size", + "offset": 5, + "size": 3 + }, + "PRTCFG": { + "description": "Protocol configuration", + "offset": 2, + "size": 2 + }, + "MODE": { + "description": "Audio block mode", + "offset": 0, + "size": 2 + } + } + } + }, + "BCR2": { + "description": "BConfiguration register 2", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP": { + "description": "Companding mode", + "offset": 14, + "size": 2 + }, + "CPL": { + "description": "Complement bit", + "offset": 13, + "size": 1 + }, + "MUTECN": { + "description": "Mute counter", + "offset": 7, + "size": 6 + }, + "MUTEVAL": { + "description": "Mute value", + "offset": 6, + "size": 1 + }, + "MUTE": { + "description": "Mute", + "offset": 5, + "size": 1 + }, + "TRIS": { + "description": "Tristate management on data\n line", + "offset": 4, + "size": 1 + }, + "FFLUS": { + "description": "FIFO flush", + "offset": 3, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold", + "offset": 0, + "size": 3 + } + } + } + }, + "BFRCR": { + "description": "BFRCR", + "offset": 44, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSOFF": { + "description": "Frame synchronization\n offset", + "offset": 18, + "size": 1 + }, + "FSPOL": { + "description": "Frame synchronization\n polarity", + "offset": 17, + "size": 1 + }, + "FSDEF": { + "description": "Frame synchronization\n definition", + "offset": 16, + "size": 1 + }, + "FSALL": { + "description": "Frame synchronization active level\n length", + "offset": 8, + "size": 7 + }, + "FRL": { + "description": "Frame length", + "offset": 0, + "size": 8 + } + } + } + }, + "BSLOTR": { + "description": "BSlot register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLOTEN": { + "description": "Slot enable", + "offset": 16, + "size": 16 + }, + "NBSLOT": { + "description": "Number of slots in an audio\n frame", + "offset": 8, + "size": 4 + }, + "SLOTSZ": { + "description": "Slot size", + "offset": 6, + "size": 2 + }, + "FBOFF": { + "description": "First bit offset", + "offset": 0, + "size": 5 + } + } + } + }, + "BIM": { + "description": "BInterrupt mask register2", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LFSDETIE": { + "description": "Late frame synchronization detection\n interrupt enable", + "offset": 6, + "size": 1 + }, + "AFSDETIE": { + "description": "Anticipated frame synchronization\n detection interrupt enable", + "offset": 5, + "size": 1 + }, + "CNRDYIE": { + "description": "Codec not ready interrupt\n enable", + "offset": 4, + "size": 1 + }, + "FREQIE": { + "description": "FIFO request interrupt\n enable", + "offset": 3, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration interrupt\n enable", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection interrupt\n enable", + "offset": 1, + "size": 1 + }, + "OVRUDRIE": { + "description": "Overrun/underrun interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "BSR": { + "description": "BStatus register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FLVL": { + "description": "FIFO level threshold", + "offset": 16, + "size": 3 + }, + "LFSDET": { + "description": "Late frame synchronization\n detection", + "offset": 6, + "size": 1 + }, + "AFSDET": { + "description": "Anticipated frame synchronization\n detection", + "offset": 5, + "size": 1 + }, + "CNRDY": { + "description": "Codec not ready", + "offset": 4, + "size": 1 + }, + "FREQ": { + "description": "FIFO request", + "offset": 3, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection", + "offset": 1, + "size": 1 + }, + "OVRUDR": { + "description": "Overrun / underrun", + "offset": 0, + "size": 1 + } + } + } + }, + "BCLRFR": { + "description": "BClear flag register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "LFSDET": { + "description": "Clear late frame synchronization\n detection flag", + "offset": 6, + "size": 1 + }, + "CAFSDET": { + "description": "Clear anticipated frame synchronization\n detection flag", + "offset": 5, + "size": 1 + }, + "CNRDY": { + "description": "Clear codec not ready flag", + "offset": 4, + "size": 1 + }, + "WCKCFG": { + "description": "Clear wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection flag", + "offset": 1, + "size": 1 + }, + "OVRUDR": { + "description": "Clear overrun / underrun", + "offset": 0, + "size": 1 + } + } + } + }, + "BDR": { + "description": "BData register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Data", + "offset": 0, + "size": 32 + } + } + } + }, + "ACR1": { + "description": "AConfiguration register 1", + "offset": 4, + "size": 32, + "reset_value": 64, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCJDIV": { + "description": "Master clock divider", + "offset": 20, + "size": 4 + }, + "NODIV": { + "description": "No divider", + "offset": 19, + "size": 1 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 17, + "size": 1 + }, + "SAIAEN": { + "description": "Audio block A enable", + "offset": 16, + "size": 1 + }, + "OutDri": { + "description": "Output drive", + "offset": 13, + "size": 1 + }, + "MONO": { + "description": "Mono mode", + "offset": 12, + "size": 1 + }, + "SYNCEN": { + "description": "Synchronization enable", + "offset": 10, + "size": 2 + }, + "CKSTR": { + "description": "Clock strobing edge", + "offset": 9, + "size": 1 + }, + "LSBFIRST": { + "description": "Least significant bit\n first", + "offset": 8, + "size": 1 + }, + "DS": { + "description": "Data size", + "offset": 5, + "size": 3 + }, + "PRTCFG": { + "description": "Protocol configuration", + "offset": 2, + "size": 2 + }, + "MODE": { + "description": "Audio block mode", + "offset": 0, + "size": 2 + } + } + } + }, + "ACR2": { + "description": "AConfiguration register 2", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COMP": { + "description": "Companding mode", + "offset": 14, + "size": 2 + }, + "CPL": { + "description": "Complement bit", + "offset": 13, + "size": 1 + }, + "MUTECN": { + "description": "Mute counter", + "offset": 7, + "size": 6 + }, + "MUTEVAL": { + "description": "Mute value", + "offset": 6, + "size": 1 + }, + "MUTE": { + "description": "Mute", + "offset": 5, + "size": 1 + }, + "TRIS": { + "description": "Tristate management on data\n line", + "offset": 4, + "size": 1 + }, + "FFLUS": { + "description": "FIFO flush", + "offset": 3, + "size": 1 + }, + "FTH": { + "description": "FIFO threshold", + "offset": 0, + "size": 3 + } + } + } + }, + "AFRCR": { + "description": "AFRCR", + "offset": 12, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSOFF": { + "description": "Frame synchronization\n offset", + "offset": 18, + "size": 1 + }, + "FSPOL": { + "description": "Frame synchronization\n polarity", + "offset": 17, + "size": 1 + }, + "FSDEF": { + "description": "Frame synchronization\n definition", + "offset": 16, + "size": 1 + }, + "FSALL": { + "description": "Frame synchronization active level\n length", + "offset": 8, + "size": 7 + }, + "FRL": { + "description": "Frame length", + "offset": 0, + "size": 8 + } + } + } + }, + "ASLOTR": { + "description": "ASlot register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLOTEN": { + "description": "Slot enable", + "offset": 16, + "size": 16 + }, + "NBSLOT": { + "description": "Number of slots in an audio\n frame", + "offset": 8, + "size": 4 + }, + "SLOTSZ": { + "description": "Slot size", + "offset": 6, + "size": 2 + }, + "FBOFF": { + "description": "First bit offset", + "offset": 0, + "size": 5 + } + } + } + }, + "AIM": { + "description": "AInterrupt mask register2", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LFSDET": { + "description": "Late frame synchronization detection\n interrupt enable", + "offset": 6, + "size": 1 + }, + "AFSDETIE": { + "description": "Anticipated frame synchronization\n detection interrupt enable", + "offset": 5, + "size": 1 + }, + "CNRDYIE": { + "description": "Codec not ready interrupt\n enable", + "offset": 4, + "size": 1 + }, + "FREQIE": { + "description": "FIFO request interrupt\n enable", + "offset": 3, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration interrupt\n enable", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection interrupt\n enable", + "offset": 1, + "size": 1 + }, + "OVRUDRIE": { + "description": "Overrun/underrun interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ASR": { + "description": "AStatus register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FLVL": { + "description": "FIFO level threshold", + "offset": 16, + "size": 3 + }, + "LFSDET": { + "description": "Late frame synchronization\n detection", + "offset": 6, + "size": 1 + }, + "AFSDET": { + "description": "Anticipated frame synchronization\n detection", + "offset": 5, + "size": 1 + }, + "CNRDY": { + "description": "Codec not ready", + "offset": 4, + "size": 1 + }, + "FREQ": { + "description": "FIFO request", + "offset": 3, + "size": 1 + }, + "WCKCFG": { + "description": "Wrong clock configuration flag. This bit\n is read only.", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection", + "offset": 1, + "size": 1 + }, + "OVRUDR": { + "description": "Overrun / underrun", + "offset": 0, + "size": 1 + } + } + } + }, + "ACLRFR": { + "description": "AClear flag register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LFSDET": { + "description": "Clear late frame synchronization\n detection flag", + "offset": 6, + "size": 1 + }, + "CAFSDET": { + "description": "Clear anticipated frame synchronization\n detection flag.", + "offset": 5, + "size": 1 + }, + "CNRDY": { + "description": "Clear codec not ready flag", + "offset": 4, + "size": 1 + }, + "WCKCFG": { + "description": "Clear wrong clock configuration\n flag", + "offset": 2, + "size": 1 + }, + "MUTEDET": { + "description": "Mute detection flag", + "offset": 1, + "size": 1 + }, + "OVRUDR": { + "description": "Clear overrun / underrun", + "offset": 0, + "size": 1 + } + } + } + }, + "ADR": { + "description": "AData register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "LTDC": { + "description": "LCD-TFT Controller", + "children": { + "registers": { + "SSCR": { + "description": "Synchronization Size Configuration\n Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSW": { + "description": "Horizontal Synchronization Width (in\n units of pixel clock period)", + "offset": 16, + "size": 10 + }, + "VSH": { + "description": "Vertical Synchronization Height (in\n units of horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "BPCR": { + "description": "Back Porch Configuration\n Register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AHBP": { + "description": "Accumulated Horizontal back porch (in\n units of pixel clock period)", + "offset": 16, + "size": 10 + }, + "AVBP": { + "description": "Accumulated Vertical back porch (in\n units of horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "AWCR": { + "description": "Active Width Configuration\n Register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AAV": { + "description": "AAV", + "offset": 16, + "size": 10 + }, + "AAH": { + "description": "Accumulated Active Height (in units of\n horizontal scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "TWCR": { + "description": "Total Width Configuration\n Register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOTALW": { + "description": "Total Width (in units of pixel clock\n period)", + "offset": 16, + "size": 10 + }, + "TOTALH": { + "description": "Total Height (in units of horizontal\n scan line)", + "offset": 0, + "size": 11 + } + } + } + }, + "GCR": { + "description": "Global Control Register", + "offset": 24, + "size": 32, + "reset_value": 8736, + "reset_mask": 4294967295, + "children": { + "fields": { + "HSPOL": { + "description": "Horizontal Synchronization\n Polarity", + "offset": 31, + "size": 1 + }, + "VSPOL": { + "description": "Vertical Synchronization\n Polarity", + "offset": 30, + "size": 1 + }, + "DEPOL": { + "description": "Data Enable Polarity", + "offset": 29, + "size": 1 + }, + "PCPOL": { + "description": "Pixel Clock Polarity", + "offset": 28, + "size": 1 + }, + "DEN": { + "description": "Dither Enable", + "offset": 16, + "size": 1 + }, + "DRW": { + "description": "Dither Red Width", + "offset": 12, + "size": 3, + "access": "read-only" + }, + "DGW": { + "description": "Dither Green Width", + "offset": 8, + "size": 3, + "access": "read-only" + }, + "DBW": { + "description": "Dither Blue Width", + "offset": 4, + "size": 3, + "access": "read-only" + }, + "LTDCEN": { + "description": "LCD-TFT controller enable\n bit", + "offset": 0, + "size": 1 + } + } + } + }, + "SRCR": { + "description": "Shadow Reload Configuration\n Register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBR": { + "description": "Vertical Blanking Reload", + "offset": 1, + "size": 1 + }, + "IMR": { + "description": "Immediate Reload", + "offset": 0, + "size": 1 + } + } + } + }, + "BCCR": { + "description": "Background Color Configuration\n Register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BC": { + "description": "Background Color Red value", + "offset": 0, + "size": 24 + } + } + } + }, + "IER": { + "description": "Interrupt Enable Register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RRIE": { + "description": "Register Reload interrupt\n enable", + "offset": 3, + "size": 1 + }, + "TERRIE": { + "description": "Transfer Error Interrupt\n Enable", + "offset": 2, + "size": 1 + }, + "FUIE": { + "description": "FIFO Underrun Interrupt\n Enable", + "offset": 1, + "size": 1 + }, + "LIE": { + "description": "Line Interrupt Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ISR": { + "description": "Interrupt Status Register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RRIF": { + "description": "Register Reload Interrupt\n Flag", + "offset": 3, + "size": 1 + }, + "TERRIF": { + "description": "Transfer Error interrupt\n flag", + "offset": 2, + "size": 1 + }, + "FUIF": { + "description": "FIFO Underrun Interrupt\n flag", + "offset": 1, + "size": 1 + }, + "LIF": { + "description": "Line Interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "Interrupt Clear Register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CRRIF": { + "description": "Clears Register Reload Interrupt\n Flag", + "offset": 3, + "size": 1 + }, + "CTERRIF": { + "description": "Clears the Transfer Error Interrupt\n Flag", + "offset": 2, + "size": 1 + }, + "CFUIF": { + "description": "Clears the FIFO Underrun Interrupt\n flag", + "offset": 1, + "size": 1 + }, + "CLIF": { + "description": "Clears the Line Interrupt\n Flag", + "offset": 0, + "size": 1 + } + } + } + }, + "LIPCR": { + "description": "Line Interrupt Position Configuration\n Register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LIPOS": { + "description": "Line Interrupt Position", + "offset": 0, + "size": 11 + } + } + } + }, + "CPSR": { + "description": "Current Position Status\n Register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CXPOS": { + "description": "Current X Position", + "offset": 16, + "size": 16 + }, + "CYPOS": { + "description": "Current Y Position", + "offset": 0, + "size": 16 + } + } + } + }, + "CDSR": { + "description": "Current Display Status\n Register", + "offset": 72, + "size": 32, + "reset_value": 15, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HSYNCS": { + "description": "Horizontal Synchronization display\n Status", + "offset": 3, + "size": 1 + }, + "VSYNCS": { + "description": "Vertical Synchronization display\n Status", + "offset": 2, + "size": 1 + }, + "HDES": { + "description": "Horizontal Data Enable display\n Status", + "offset": 1, + "size": 1 + }, + "VDES": { + "description": "Vertical Data Enable display\n Status", + "offset": 0, + "size": 1 + } + } + } + }, + "L1CR": { + "description": "Layerx Control Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLUTEN": { + "description": "Color Look-Up Table Enable", + "offset": 4, + "size": 1 + }, + "COLKEN": { + "description": "Color Keying Enable", + "offset": 1, + "size": 1 + }, + "LEN": { + "description": "Layer Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "L1WHPCR": { + "description": "Layerx Window Horizontal Position\n Configuration Register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WHSPPOS": { + "description": "Window Horizontal Stop\n Position", + "offset": 16, + "size": 12 + }, + "WHSTPOS": { + "description": "Window Horizontal Start\n Position", + "offset": 0, + "size": 12 + } + } + } + }, + "L1WVPCR": { + "description": "Layerx Window Vertical Position\n Configuration Register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WVSPPOS": { + "description": "Window Vertical Stop\n Position", + "offset": 16, + "size": 11 + }, + "WVSTPOS": { + "description": "Window Vertical Start\n Position", + "offset": 0, + "size": 11 + } + } + } + }, + "L1CKCR": { + "description": "Layerx Color Keying Configuration\n Register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKRED": { + "description": "Color Key Red value", + "offset": 16, + "size": 8 + }, + "CKGREEN": { + "description": "Color Key Green value", + "offset": 8, + "size": 8 + }, + "CKBLUE": { + "description": "Color Key Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L1PFCR": { + "description": "Layerx Pixel Format Configuration\n Register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PF": { + "description": "Pixel Format", + "offset": 0, + "size": 3 + } + } + } + }, + "L1CACR": { + "description": "Layerx Constant Alpha Configuration\n Register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CONSTA": { + "description": "Constant Alpha", + "offset": 0, + "size": 8 + } + } + } + }, + "L1DCCR": { + "description": "Layerx Default Color Configuration\n Register", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCALPHA": { + "description": "Default Color Alpha", + "offset": 24, + "size": 8 + }, + "DCRED": { + "description": "Default Color Red", + "offset": 16, + "size": 8 + }, + "DCGREEN": { + "description": "Default Color Green", + "offset": 8, + "size": 8 + }, + "DCBLUE": { + "description": "Default Color Blue", + "offset": 0, + "size": 8 + } + } + } + }, + "L1BFCR": { + "description": "Layerx Blending Factors Configuration\n Register", + "offset": 160, + "size": 32, + "reset_value": 1543, + "reset_mask": 4294967295, + "children": { + "fields": { + "BF1": { + "description": "Blending Factor 1", + "offset": 8, + "size": 3 + }, + "BF2": { + "description": "Blending Factor 2", + "offset": 0, + "size": 3 + } + } + } + }, + "L1CFBAR": { + "description": "Layerx Color Frame Buffer Address\n Register", + "offset": 172, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBADD": { + "description": "Color Frame Buffer Start\n Address", + "offset": 0, + "size": 32 + } + } + } + }, + "L1CFBLR": { + "description": "Layerx Color Frame Buffer Length\n Register", + "offset": 176, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBP": { + "description": "Color Frame Buffer Pitch in\n bytes", + "offset": 16, + "size": 13 + }, + "CFBLL": { + "description": "Color Frame Buffer Line\n Length", + "offset": 0, + "size": 13 + } + } + } + }, + "L1CFBLNR": { + "description": "Layerx ColorFrame Buffer Line Number\n Register", + "offset": 180, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBLNBR": { + "description": "Frame Buffer Line Number", + "offset": 0, + "size": 11 + } + } + } + }, + "L1CLUTWR": { + "description": "Layerx CLUT Write Register", + "offset": 196, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CLUTADD": { + "description": "CLUT Address", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "Red value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L2CR": { + "description": "Layerx Control Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLUTEN": { + "description": "Color Look-Up Table Enable", + "offset": 4, + "size": 1 + }, + "COLKEN": { + "description": "Color Keying Enable", + "offset": 1, + "size": 1 + }, + "LEN": { + "description": "Layer Enable", + "offset": 0, + "size": 1 + } + } + } + }, + "L2WHPCR": { + "description": "Layerx Window Horizontal Position\n Configuration Register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WHSPPOS": { + "description": "Window Horizontal Stop\n Position", + "offset": 16, + "size": 12 + }, + "WHSTPOS": { + "description": "Window Horizontal Start\n Position", + "offset": 0, + "size": 12 + } + } + } + }, + "L2WVPCR": { + "description": "Layerx Window Vertical Position\n Configuration Register", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WVSPPOS": { + "description": "Window Vertical Stop\n Position", + "offset": 16, + "size": 11 + }, + "WVSTPOS": { + "description": "Window Vertical Start\n Position", + "offset": 0, + "size": 11 + } + } + } + }, + "L2CKCR": { + "description": "Layerx Color Keying Configuration\n Register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKRED": { + "description": "Color Key Red value", + "offset": 15, + "size": 9 + }, + "CKGREEN": { + "description": "Color Key Green value", + "offset": 8, + "size": 7 + }, + "CKBLUE": { + "description": "Color Key Blue value", + "offset": 0, + "size": 8 + } + } + } + }, + "L2PFCR": { + "description": "Layerx Pixel Format Configuration\n Register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PF": { + "description": "Pixel Format", + "offset": 0, + "size": 3 + } + } + } + }, + "L2CACR": { + "description": "Layerx Constant Alpha Configuration\n Register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CONSTA": { + "description": "Constant Alpha", + "offset": 0, + "size": 8 + } + } + } + }, + "L2DCCR": { + "description": "Layerx Default Color Configuration\n Register", + "offset": 284, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCALPHA": { + "description": "Default Color Alpha", + "offset": 24, + "size": 8 + }, + "DCRED": { + "description": "Default Color Red", + "offset": 16, + "size": 8 + }, + "DCGREEN": { + "description": "Default Color Green", + "offset": 8, + "size": 8 + }, + "DCBLUE": { + "description": "Default Color Blue", + "offset": 0, + "size": 8 + } + } + } + }, + "L2BFCR": { + "description": "Layerx Blending Factors Configuration\n Register", + "offset": 288, + "size": 32, + "reset_value": 1543, + "reset_mask": 4294967295, + "children": { + "fields": { + "BF1": { + "description": "Blending Factor 1", + "offset": 8, + "size": 3 + }, + "BF2": { + "description": "Blending Factor 2", + "offset": 0, + "size": 3 + } + } + } + }, + "L2CFBAR": { + "description": "Layerx Color Frame Buffer Address\n Register", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBADD": { + "description": "Color Frame Buffer Start\n Address", + "offset": 0, + "size": 32 + } + } + } + }, + "L2CFBLR": { + "description": "Layerx Color Frame Buffer Length\n Register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBP": { + "description": "Color Frame Buffer Pitch in\n bytes", + "offset": 16, + "size": 13 + }, + "CFBLL": { + "description": "Color Frame Buffer Line\n Length", + "offset": 0, + "size": 13 + } + } + } + }, + "L2CFBLNR": { + "description": "Layerx ColorFrame Buffer Line Number\n Register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CFBLNBR": { + "description": "Frame Buffer Line Number", + "offset": 0, + "size": 11 + } + } + } + }, + "L2CLUTWR": { + "description": "Layerx CLUT Write Register", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CLUTADD": { + "description": "CLUT Address", + "offset": 24, + "size": 8 + }, + "RED": { + "description": "Red value", + "offset": 16, + "size": 8 + }, + "GREEN": { + "description": "Green value", + "offset": 8, + "size": 8 + }, + "BLUE": { + "description": "Blue value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "OTG_HS_PWRCLK": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_PCGCR": { + "description": "Power and clock gating control\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPPCLK": { + "description": "Stop PHY clock", + "offset": 0, + "size": 1 + }, + "GATEHCLK": { + "description": "Gate HCLK", + "offset": 1, + "size": 1 + }, + "PHYSUSP": { + "description": "PHY suspended", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "OTG_HS_DEVICE": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_DCFG": { + "description": "OTG_HS device configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 35651584, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSPD": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOHSK": { + "description": "Nonzero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAD": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "PFIVL": { + "description": "Periodic (micro)frame\n interval", + "offset": 11, + "size": 2 + }, + "PERSCHIVL": { + "description": "Periodic scheduling\n interval", + "offset": 24, + "size": 2 + } + } + } + }, + "OTG_HS_DCTL": { + "description": "OTG_HS device control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWUSIG": { + "description": "Remote wakeup signaling", + "offset": 0, + "size": 1 + }, + "SDIS": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINSTS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONSTS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "TCTL": { + "description": "Test control", + "offset": 4, + "size": 3 + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1, + "access": "write-only" + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1, + "access": "write-only" + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1, + "access": "write-only" + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1, + "access": "write-only" + }, + "POPRGDNE": { + "description": "Power-on programming done", + "offset": 11, + "size": 1 + } + } + } + }, + "OTG_HS_DSTS": { + "description": "OTG_HS device status register", + "offset": 8, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SUSPSTS": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ENUMSPD": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "EERR": { + "description": "Erratic error", + "offset": 3, + "size": 1 + }, + "FNSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "OTG_HS_DIEPMSK": { + "description": "OTG_HS device IN endpoint common interrupt\n mask register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (nonisochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "FIFO underrun mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPMSK": { + "description": "OTG_HS device OUT endpoint common interrupt\n mask register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "STUPM": { + "description": "SETUP phase done mask", + "offset": 3, + "size": 1 + }, + "OTEPDM": { + "description": "OUT token received when endpoint\n disabled mask", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets received\n mask", + "offset": 6, + "size": 1 + }, + "OPEM": { + "description": "OUT packet error mask", + "offset": 8, + "size": 1 + }, + "BOIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + } + } + } + }, + "OTG_HS_DAINT": { + "description": "OTG_HS device all endpoints interrupt\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPINT": { + "description": "IN endpoint interrupt bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DAINTMSK": { + "description": "OTG_HS all endpoints interrupt mask\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPM": { + "description": "IN EP interrupt mask bits", + "offset": 0, + "size": 16 + }, + "OEPM": { + "description": "OUT EP interrupt mask bits", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DVBUSDIS": { + "description": "OTG_HS device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DVBUSPULSE": { + "description": "OTG_HS device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSP": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "OTG_HS_DTHRCTL": { + "description": "OTG_HS Device threshold control\n register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NONISOTHREN": { + "description": "Nonisochronous IN endpoints threshold\n enable", + "offset": 0, + "size": 1 + }, + "ISOTHREN": { + "description": "ISO IN endpoint threshold\n enable", + "offset": 1, + "size": 1 + }, + "TXTHRLEN": { + "description": "Transmit threshold length", + "offset": 2, + "size": 9 + }, + "RXTHREN": { + "description": "Receive threshold enable", + "offset": 16, + "size": 1 + }, + "RXTHRLEN": { + "description": "Receive threshold length", + "offset": 17, + "size": 9 + }, + "ARPEN": { + "description": "Arbiter parking enable", + "offset": 27, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPEMPMSK": { + "description": "OTG_HS device IN endpoint FIFO empty\n interrupt mask register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXFEM": { + "description": "IN EP Tx FIFO empty interrupt mask\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DEACHINT": { + "description": "OTG_HS device each endpoint interrupt\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEP1INT": { + "description": "IN endpoint 1interrupt bit", + "offset": 1, + "size": 1 + }, + "OEP1INT": { + "description": "OUT endpoint 1 interrupt\n bit", + "offset": 17, + "size": 1 + } + } + } + }, + "OTG_HS_DEACHINTMSK": { + "description": "OTG_HS device each endpoint interrupt\n register mask", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEP1INTM": { + "description": "IN Endpoint 1 interrupt mask\n bit", + "offset": 1, + "size": 1 + }, + "OEP1INTM": { + "description": "OUT Endpoint 1 interrupt mask\n bit", + "offset": 17, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPEACHMSK1": { + "description": "OTG_HS device each in endpoint-1 interrupt\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (nonisochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "FIFO underrun mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + }, + "NAKM": { + "description": "NAK interrupt mask", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPEACHMSK1": { + "description": "OTG_HS device each OUT endpoint-1 interrupt\n register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "TXFURM": { + "description": "OUT packet error mask", + "offset": 8, + "size": 1 + }, + "BIM": { + "description": "BNA interrupt mask", + "offset": 9, + "size": 1 + }, + "BERRM": { + "description": "Bubble error interrupt\n mask", + "offset": 12, + "size": 1 + }, + "NAKM": { + "description": "NAK interrupt mask", + "offset": 13, + "size": 1 + }, + "NYETM": { + "description": "NYET interrupt mask", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL0": { + "description": "OTG device endpoint-0 control\n register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL4": { + "description": "OTG device endpoint-4 control\n register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL5": { + "description": "OTG device endpoint-5 control\n register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL6": { + "description": "OTG device endpoint-6 control\n register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPCTL7": { + "description": "OTG device endpoint-7 control\n register", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even/odd frame", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT0": { + "description": "OTG device endpoint-0 interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT1": { + "description": "OTG device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT2": { + "description": "OTG device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT3": { + "description": "OTG device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT4": { + "description": "OTG device endpoint-4 interrupt\n register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT5": { + "description": "OTG device endpoint-5 interrupt\n register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT6": { + "description": "OTG device endpoint-6 interrupt\n register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPINT7": { + "description": "OTG device endpoint-7 interrupt\n register", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "TOC": { + "description": "Timeout condition", + "offset": 3, + "size": 1 + }, + "ITTXFE": { + "description": "IN token received when TxFIFO is\n empty", + "offset": 4, + "size": 1 + }, + "INEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TXFIFOUDRN": { + "description": "Transmit Fifo Underrun", + "offset": 8, + "size": 1 + }, + "BNA": { + "description": "Buffer not available\n interrupt", + "offset": 9, + "size": 1 + }, + "PKTDRPSTS": { + "description": "Packet dropped status", + "offset": 11, + "size": 1 + }, + "BERR": { + "description": "Babble error interrupt", + "offset": 12, + "size": 1 + }, + "NAK": { + "description": "NAK interrupt", + "offset": 13, + "size": 1 + } + } + } + }, + "OTG_HS_DIEPTSIZ0": { + "description": "OTG_HS device IN endpoint 0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPDMA1": { + "description": "OTG_HS device endpoint-1 DMA address\n register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA2": { + "description": "OTG_HS device endpoint-2 DMA address\n register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA3": { + "description": "OTG_HS device endpoint-3 DMA address\n register", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA4": { + "description": "OTG_HS device endpoint-4 DMA address\n register", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DIEPDMA5": { + "description": "OTG_HS device endpoint-5 DMA address\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_DTXFSTS0": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS1": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS2": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS3": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS4": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DTXFSTS5": { + "description": "OTG_HS device IN endpoint transmit FIFO\n status register", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n avail", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTSIZ1": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ2": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ3": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ4": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DIEPTSIZ5": { + "description": "OTG_HS device endpoint transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPCTL0": { + "description": "OTG_HS device control OUT endpoint 0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 2, + "access": "read-only" + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1, + "access": "write-only" + } + } + } + }, + "OTG_HS_DOEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1 + }, + "EONUM_DPID": { + "description": "Even odd frame/Endpoint data\n PID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "SNPM": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "Stall": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "Set DATA0 PID/Set even\n frame", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SODDFRM": { + "description": "Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT0": { + "description": "OTG_HS device endpoint-0 interrupt\n register", + "offset": 776, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT1": { + "description": "OTG_HS device endpoint-1 interrupt\n register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT2": { + "description": "OTG_HS device endpoint-2 interrupt\n register", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT3": { + "description": "OTG_HS device endpoint-3 interrupt\n register", + "offset": 872, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT4": { + "description": "OTG_HS device endpoint-4 interrupt\n register", + "offset": 904, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT5": { + "description": "OTG_HS device endpoint-5 interrupt\n register", + "offset": 936, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT6": { + "description": "OTG_HS device endpoint-6 interrupt\n register", + "offset": 968, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPINT7": { + "description": "OTG_HS device endpoint-7 interrupt\n register", + "offset": 1000, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed\n interrupt", + "offset": 0, + "size": 1 + }, + "EPDISD": { + "description": "Endpoint disabled\n interrupt", + "offset": 1, + "size": 1 + }, + "STUP": { + "description": "SETUP phase done", + "offset": 3, + "size": 1 + }, + "OTEPDIS": { + "description": "OUT token received when endpoint\n disabled", + "offset": 4, + "size": 1 + }, + "B2BSTUP": { + "description": "Back-to-back SETUP packets\n received", + "offset": 6, + "size": 1 + }, + "NYET": { + "description": "NYET interrupt", + "offset": 14, + "size": 1 + } + } + } + }, + "OTG_HS_DOEPTSIZ0": { + "description": "OTG_HS device endpoint-1 transfer size\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "STUPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ1": { + "description": "OTG_HS device endpoint-2 transfer size\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ2": { + "description": "OTG_HS device endpoint-3 transfer size\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ3": { + "description": "OTG_HS device endpoint-4 transfer size\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_DOEPTSIZ4": { + "description": "OTG_HS device endpoint-5 transfer size\n register", + "offset": 912, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "OTG_HS_HOST": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_HCFG": { + "description": "OTG_HS host configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSLSPCS": { + "description": "FS/LS PHY clock select", + "offset": 0, + "size": 2 + }, + "FSLSS": { + "description": "FS- and LS-only support", + "offset": 2, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_HFIR": { + "description": "OTG_HS Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 60000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRIVL": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HFNUM": { + "description": "OTG_HS host frame number/frame time\n remaining register", + "offset": 8, + "size": 32, + "reset_value": 16383, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FTREM": { + "description": "Frame time remaining", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_HPTXSTS": { + "description": "OTG_HS_Host periodic transmit FIFO/queue\n status register", + "offset": 16, + "size": 32, + "reset_value": 524544, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFSAVL": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16 + }, + "PTXQSAV": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXQTOP": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "OTG_HS_HAINT": { + "description": "OTG_HS Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HAINT": { + "description": "Channel interrupts", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HAINTMSK": { + "description": "OTG_HS host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HAINTM": { + "description": "Channel interrupt mask", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_HPRT": { + "description": "OTG_HS host port control and status\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCSTS": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCDET": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PENA": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PENCHNG": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "POCA": { + "description": "Port overcurrent active", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "POCCHNG": { + "description": "Port overcurrent change", + "offset": 5, + "size": 1 + }, + "PRES": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSUSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLSTS": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PPWR": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PTCTL": { + "description": "Port test control", + "offset": 13, + "size": 4 + }, + "PSPD": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "OTG_HS_HCCHAR0": { + "description": "OTG_HS host channel-0 characteristics\n register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR1": { + "description": "OTG_HS host channel-1 characteristics\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR2": { + "description": "OTG_HS host channel-2 characteristics\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR3": { + "description": "OTG_HS host channel-3 characteristics\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR4": { + "description": "OTG_HS host channel-4 characteristics\n register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR5": { + "description": "OTG_HS host channel-5 characteristics\n register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR6": { + "description": "OTG_HS host channel-6 characteristics\n register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR7": { + "description": "OTG_HS host channel-7 characteristics\n register", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR8": { + "description": "OTG_HS host channel-8 characteristics\n register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR9": { + "description": "OTG_HS host channel-9 characteristics\n register", + "offset": 544, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR10": { + "description": "OTG_HS host channel-10 characteristics\n register", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCCHAR11": { + "description": "OTG_HS host channel-11 characteristics\n register", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MC": { + "description": "Multi Count (MC) / Error Count\n (EC)", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT0": { + "description": "OTG_HS host channel-0 split control\n register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT1": { + "description": "OTG_HS host channel-1 split control\n register", + "offset": 292, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT2": { + "description": "OTG_HS host channel-2 split control\n register", + "offset": 324, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT3": { + "description": "OTG_HS host channel-3 split control\n register", + "offset": 356, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT4": { + "description": "OTG_HS host channel-4 split control\n register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT5": { + "description": "OTG_HS host channel-5 split control\n register", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT6": { + "description": "OTG_HS host channel-6 split control\n register", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT7": { + "description": "OTG_HS host channel-7 split control\n register", + "offset": 484, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT8": { + "description": "OTG_HS host channel-8 split control\n register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT9": { + "description": "OTG_HS host channel-9 split control\n register", + "offset": 548, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT10": { + "description": "OTG_HS host channel-10 split control\n register", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCSPLT11": { + "description": "OTG_HS host channel-11 split control\n register", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRTADDR": { + "description": "Port address", + "offset": 0, + "size": 7 + }, + "HUBADDR": { + "description": "Hub address", + "offset": 7, + "size": 7 + }, + "XACTPOS": { + "description": "XACTPOS", + "offset": 14, + "size": 2 + }, + "COMPLSPLT": { + "description": "Do complete split", + "offset": 16, + "size": 1 + }, + "SPLITEN": { + "description": "Split enable", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT0": { + "description": "OTG_HS host channel-11 interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT1": { + "description": "OTG_HS host channel-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT2": { + "description": "OTG_HS host channel-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT3": { + "description": "OTG_HS host channel-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT4": { + "description": "OTG_HS host channel-4 interrupt\n register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT5": { + "description": "OTG_HS host channel-5 interrupt\n register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT6": { + "description": "OTG_HS host channel-6 interrupt\n register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT7": { + "description": "OTG_HS host channel-7 interrupt\n register", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT8": { + "description": "OTG_HS host channel-8 interrupt\n register", + "offset": 520, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT9": { + "description": "OTG_HS host channel-9 interrupt\n register", + "offset": 552, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT10": { + "description": "OTG_HS host channel-10 interrupt\n register", + "offset": 584, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINT11": { + "description": "OTG_HS host channel-11 interrupt\n register", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "Response received\n interrupt", + "offset": 6, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK0": { + "description": "OTG_HS host channel-11 interrupt mask\n register", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK1": { + "description": "OTG_HS host channel-1 interrupt mask\n register", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK2": { + "description": "OTG_HS host channel-2 interrupt mask\n register", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK3": { + "description": "OTG_HS host channel-3 interrupt mask\n register", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK4": { + "description": "OTG_HS host channel-4 interrupt mask\n register", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK5": { + "description": "OTG_HS host channel-5 interrupt mask\n register", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK6": { + "description": "OTG_HS host channel-6 interrupt mask\n register", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK7": { + "description": "OTG_HS host channel-7 interrupt mask\n register", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK8": { + "description": "OTG_HS host channel-8 interrupt mask\n register", + "offset": 524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK9": { + "description": "OTG_HS host channel-9 interrupt mask\n register", + "offset": 556, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK10": { + "description": "OTG_HS host channel-10 interrupt mask\n register", + "offset": 588, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCINTMSK11": { + "description": "OTG_HS host channel-11 interrupt mask\n register", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "AHBERR": { + "description": "AHB error", + "offset": 2, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "OTG_HS_HCTSIZ0": { + "description": "OTG_HS host channel-11 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ1": { + "description": "OTG_HS host channel-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ2": { + "description": "OTG_HS host channel-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ3": { + "description": "OTG_HS host channel-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ4": { + "description": "OTG_HS host channel-4 transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ5": { + "description": "OTG_HS host channel-5 transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ6": { + "description": "OTG_HS host channel-6 transfer size\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ7": { + "description": "OTG_HS host channel-7 transfer size\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ8": { + "description": "OTG_HS host channel-8 transfer size\n register", + "offset": 528, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ9": { + "description": "OTG_HS host channel-9 transfer size\n register", + "offset": 560, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ10": { + "description": "OTG_HS host channel-10 transfer size\n register", + "offset": 592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCTSIZ11": { + "description": "OTG_HS host channel-11 transfer size\n register", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "OTG_HS_HCDMA0": { + "description": "OTG_HS host channel-0 DMA address\n register", + "offset": 276, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA1": { + "description": "OTG_HS host channel-1 DMA address\n register", + "offset": 308, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA2": { + "description": "OTG_HS host channel-2 DMA address\n register", + "offset": 340, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA3": { + "description": "OTG_HS host channel-3 DMA address\n register", + "offset": 372, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA4": { + "description": "OTG_HS host channel-4 DMA address\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA5": { + "description": "OTG_HS host channel-5 DMA address\n register", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA6": { + "description": "OTG_HS host channel-6 DMA address\n register", + "offset": 468, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA7": { + "description": "OTG_HS host channel-7 DMA address\n register", + "offset": 500, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA8": { + "description": "OTG_HS host channel-8 DMA address\n register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA9": { + "description": "OTG_HS host channel-9 DMA address\n register", + "offset": 564, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA10": { + "description": "OTG_HS host channel-10 DMA address\n register", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HCDMA11": { + "description": "OTG_HS host channel-11 DMA address\n register", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAADDR": { + "description": "DMA address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "children": { + "registers": { + "POWER": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRCTRL": { + "description": "PWRCTRL", + "offset": 0, + "size": 2 + } + } + } + }, + "CLKCR": { + "description": "SDI clock control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HWFC_EN": { + "description": "HW Flow Control enable", + "offset": 14, + "size": 1 + }, + "NEGEDGE": { + "description": "SDIO_CK dephasing selection\n bit", + "offset": 13, + "size": 1 + }, + "WIDBUS": { + "description": "Wide bus mode enable bit", + "offset": 11, + "size": 2 + }, + "BYPASS": { + "description": "Clock divider bypass enable\n bit", + "offset": 10, + "size": 1 + }, + "PWRSAV": { + "description": "Power saving configuration\n bit", + "offset": 9, + "size": 1 + }, + "CLKEN": { + "description": "Clock enable bit", + "offset": 8, + "size": 1 + }, + "CLKDIV": { + "description": "Clock divide factor", + "offset": 0, + "size": 8 + } + } + } + }, + "ARG": { + "description": "argument register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMDARG": { + "description": "Command argument", + "offset": 0, + "size": 32 + } + } + } + }, + "CMD": { + "description": "command register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CE_ATACMD": { + "description": "CE-ATA command", + "offset": 14, + "size": 1 + }, + "nIEN": { + "description": "not Interrupt Enable", + "offset": 13, + "size": 1 + }, + "ENCMDcompl": { + "description": "Enable CMD completion", + "offset": 12, + "size": 1 + }, + "SDIOSuspend": { + "description": "SD I/O suspend command", + "offset": 11, + "size": 1 + }, + "CPSMEN": { + "description": "Command path state machine (CPSM) Enable\n bit", + "offset": 10, + "size": 1 + }, + "WAITPEND": { + "description": "CPSM Waits for ends of data transfer\n (CmdPend internal signal).", + "offset": 9, + "size": 1 + }, + "WAITINT": { + "description": "CPSM waits for interrupt\n request", + "offset": 8, + "size": 1 + }, + "WAITRESP": { + "description": "Wait for response bits", + "offset": 6, + "size": 2 + }, + "CMDINDEX": { + "description": "Command index", + "offset": 0, + "size": 6 + } + } + } + }, + "RESPCMD": { + "description": "command response register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RESPCMD": { + "description": "Response command index", + "offset": 0, + "size": 6 + } + } + } + }, + "RESP1": { + "description": "response 1..4 register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS1": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP2": { + "description": "response 1..4 register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS2": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP3": { + "description": "response 1..4 register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS3": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "RESP4": { + "description": "response 1..4 register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CARDSTATUS4": { + "description": "see Table 132.", + "offset": 0, + "size": 32 + } + } + } + }, + "DTIMER": { + "description": "data timer register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATATIME": { + "description": "Data timeout period", + "offset": 0, + "size": 32 + } + } + } + }, + "DLEN": { + "description": "data length register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATALENGTH": { + "description": "Data length value", + "offset": 0, + "size": 25 + } + } + } + }, + "DCTRL": { + "description": "data control register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SDIOEN": { + "description": "SD I/O enable functions", + "offset": 11, + "size": 1 + }, + "RWMOD": { + "description": "Read wait mode", + "offset": 10, + "size": 1 + }, + "RWSTOP": { + "description": "Read wait stop", + "offset": 9, + "size": 1 + }, + "RWSTART": { + "description": "Read wait start", + "offset": 8, + "size": 1 + }, + "DBLOCKSIZE": { + "description": "Data block size", + "offset": 4, + "size": 4 + }, + "DMAEN": { + "description": "DMA enable bit", + "offset": 3, + "size": 1 + }, + "DTMODE": { + "description": "Data transfer mode selection 1: Stream\n or SDIO multibyte data transfer.", + "offset": 2, + "size": 1 + }, + "DTDIR": { + "description": "Data transfer direction\n selection", + "offset": 1, + "size": 1 + }, + "DTEN": { + "description": "DTEN", + "offset": 0, + "size": 1 + } + } + } + }, + "DCOUNT": { + "description": "data counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATACOUNT": { + "description": "Data count value", + "offset": 0, + "size": 25 + } + } + } + }, + "STA": { + "description": "status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CEATAEND": { + "description": "CE-ATA command completion signal\n received for CMD61", + "offset": 23, + "size": 1 + }, + "SDIOIT": { + "description": "SDIO interrupt received", + "offset": 22, + "size": 1 + }, + "RXDAVL": { + "description": "Data available in receive\n FIFO", + "offset": 21, + "size": 1 + }, + "TXDAVL": { + "description": "Data available in transmit\n FIFO", + "offset": 20, + "size": 1 + }, + "RXFIFOE": { + "description": "Receive FIFO empty", + "offset": 19, + "size": 1 + }, + "TXFIFOE": { + "description": "Transmit FIFO empty", + "offset": 18, + "size": 1 + }, + "RXFIFOF": { + "description": "Receive FIFO full", + "offset": 17, + "size": 1 + }, + "TXFIFOF": { + "description": "Transmit FIFO full", + "offset": 16, + "size": 1 + }, + "RXFIFOHF": { + "description": "Receive FIFO half full: there are at\n least 8 words in the FIFO", + "offset": 15, + "size": 1 + }, + "TXFIFOHE": { + "description": "Transmit FIFO half empty: at least 8\n words can be written into the FIFO", + "offset": 14, + "size": 1 + }, + "RXACT": { + "description": "Data receive in progress", + "offset": 13, + "size": 1 + }, + "TXACT": { + "description": "Data transmit in progress", + "offset": 12, + "size": 1 + }, + "CMDACT": { + "description": "Command transfer in\n progress", + "offset": 11, + "size": 1 + }, + "DBCKEND": { + "description": "Data block sent/received (CRC check\n passed)", + "offset": 10, + "size": 1 + }, + "STBITERR": { + "description": "Start bit not detected on all data\n signals in wide bus mode", + "offset": 9, + "size": 1 + }, + "DATAEND": { + "description": "Data end (data counter, SDIDCOUNT, is\n zero)", + "offset": 8, + "size": 1 + }, + "CMDSENT": { + "description": "Command sent (no response\n required)", + "offset": 7, + "size": 1 + }, + "CMDREND": { + "description": "Command response received (CRC check\n passed)", + "offset": 6, + "size": 1 + }, + "RXOVERR": { + "description": "Received FIFO overrun\n error", + "offset": 5, + "size": 1 + }, + "TXUNDERR": { + "description": "Transmit FIFO underrun\n error", + "offset": 4, + "size": 1 + }, + "DTIMEOUT": { + "description": "Data timeout", + "offset": 3, + "size": 1 + }, + "CTIMEOUT": { + "description": "Command response timeout", + "offset": 2, + "size": 1 + }, + "DCRCFAIL": { + "description": "Data block sent/received (CRC check\n failed)", + "offset": 1, + "size": 1 + }, + "CCRCFAIL": { + "description": "Command response received (CRC check\n failed)", + "offset": 0, + "size": 1 + } + } + } + }, + "ICR": { + "description": "interrupt clear register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEATAENDC": { + "description": "CEATAEND flag clear bit", + "offset": 23, + "size": 1 + }, + "SDIOITC": { + "description": "SDIOIT flag clear bit", + "offset": 22, + "size": 1 + }, + "DBCKENDC": { + "description": "DBCKEND flag clear bit", + "offset": 10, + "size": 1 + }, + "STBITERRC": { + "description": "STBITERR flag clear bit", + "offset": 9, + "size": 1 + }, + "DATAENDC": { + "description": "DATAEND flag clear bit", + "offset": 8, + "size": 1 + }, + "CMDSENTC": { + "description": "CMDSENT flag clear bit", + "offset": 7, + "size": 1 + }, + "CMDRENDC": { + "description": "CMDREND flag clear bit", + "offset": 6, + "size": 1 + }, + "RXOVERRC": { + "description": "RXOVERR flag clear bit", + "offset": 5, + "size": 1 + }, + "TXUNDERRC": { + "description": "TXUNDERR flag clear bit", + "offset": 4, + "size": 1 + }, + "DTIMEOUTC": { + "description": "DTIMEOUT flag clear bit", + "offset": 3, + "size": 1 + }, + "CTIMEOUTC": { + "description": "CTIMEOUT flag clear bit", + "offset": 2, + "size": 1 + }, + "DCRCFAILC": { + "description": "DCRCFAIL flag clear bit", + "offset": 1, + "size": 1 + }, + "CCRCFAILC": { + "description": "CCRCFAIL flag clear bit", + "offset": 0, + "size": 1 + } + } + } + }, + "MASK": { + "description": "mask register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CEATAENDIE": { + "description": "CE-ATA command completion signal\n received interrupt enable", + "offset": 23, + "size": 1 + }, + "SDIOITIE": { + "description": "SDIO mode interrupt received interrupt\n enable", + "offset": 22, + "size": 1 + }, + "RXDAVLIE": { + "description": "Data available in Rx FIFO interrupt\n enable", + "offset": 21, + "size": 1 + }, + "TXDAVLIE": { + "description": "Data available in Tx FIFO interrupt\n enable", + "offset": 20, + "size": 1 + }, + "RXFIFOEIE": { + "description": "Rx FIFO empty interrupt\n enable", + "offset": 19, + "size": 1 + }, + "TXFIFOEIE": { + "description": "Tx FIFO empty interrupt\n enable", + "offset": 18, + "size": 1 + }, + "RXFIFOFIE": { + "description": "Rx FIFO full interrupt\n enable", + "offset": 17, + "size": 1 + }, + "TXFIFOFIE": { + "description": "Tx FIFO full interrupt\n enable", + "offset": 16, + "size": 1 + }, + "RXFIFOHFIE": { + "description": "Rx FIFO half full interrupt\n enable", + "offset": 15, + "size": 1 + }, + "TXFIFOHEIE": { + "description": "Tx FIFO half empty interrupt\n enable", + "offset": 14, + "size": 1 + }, + "RXACTIE": { + "description": "Data receive acting interrupt\n enable", + "offset": 13, + "size": 1 + }, + "TXACTIE": { + "description": "Data transmit acting interrupt\n enable", + "offset": 12, + "size": 1 + }, + "CMDACTIE": { + "description": "Command acting interrupt\n enable", + "offset": 11, + "size": 1 + }, + "DBCKENDIE": { + "description": "Data block end interrupt\n enable", + "offset": 10, + "size": 1 + }, + "STBITERRIE": { + "description": "Start bit error interrupt\n enable", + "offset": 9, + "size": 1 + }, + "DATAENDIE": { + "description": "Data end interrupt enable", + "offset": 8, + "size": 1 + }, + "CMDSENTIE": { + "description": "Command sent interrupt\n enable", + "offset": 7, + "size": 1 + }, + "CMDRENDIE": { + "description": "Command response received interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXOVERRIE": { + "description": "Rx FIFO overrun error interrupt\n enable", + "offset": 5, + "size": 1 + }, + "TXUNDERRIE": { + "description": "Tx FIFO underrun error interrupt\n enable", + "offset": 4, + "size": 1 + }, + "DTIMEOUTIE": { + "description": "Data timeout interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CTIMEOUTIE": { + "description": "Command timeout interrupt\n enable", + "offset": 2, + "size": 1 + }, + "DCRCFAILIE": { + "description": "Data CRC fail interrupt\n enable", + "offset": 1, + "size": 1 + }, + "CCRCFAILIE": { + "description": "Command CRC fail interrupt\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "FIFOCNT": { + "description": "FIFO counter register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FIFOCOUNT": { + "description": "Remaining number of words to be written\n to or read from the FIFO.", + "offset": 0, + "size": 24 + } + } + } + }, + "FIFO": { + "description": "data FIFO register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FIFOData": { + "description": "Receive and transmit FIFO\n data", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "ADC1": { + "description": "Analog-to-digital converter", + "children": { + "registers": { + "SR": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVR": { + "description": "Overrun", + "offset": 5, + "size": 1 + }, + "STRT": { + "description": "Regular channel start flag", + "offset": 4, + "size": 1 + }, + "JSTRT": { + "description": "Injected channel start\n flag", + "offset": 3, + "size": 1 + }, + "JEOC": { + "description": "Injected channel end of\n conversion", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "Regular channel end of\n conversion", + "offset": 1, + "size": 1 + }, + "AWD": { + "description": "Analog watchdog flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CR1": { + "description": "control register 1", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVRIE": { + "description": "Overrun interrupt enable", + "offset": 26, + "size": 1 + }, + "RES": { + "description": "Resolution", + "offset": 24, + "size": 2 + }, + "AWDEN": { + "description": "Analog watchdog enable on regular\n channels", + "offset": 23, + "size": 1 + }, + "JAWDEN": { + "description": "Analog watchdog enable on injected\n channels", + "offset": 22, + "size": 1 + }, + "DISCNUM": { + "description": "Discontinuous mode channel\n count", + "offset": 13, + "size": 3 + }, + "JDISCEN": { + "description": "Discontinuous mode on injected\n channels", + "offset": 12, + "size": 1 + }, + "DISCEN": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "JAUTO": { + "description": "Automatic injected group\n conversion", + "offset": 10, + "size": 1 + }, + "AWDSGL": { + "description": "Enable the watchdog on a single channel\n in scan mode", + "offset": 9, + "size": 1 + }, + "SCAN": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "JEOCIE": { + "description": "Interrupt enable for injected\n channels", + "offset": 7, + "size": 1 + }, + "AWDIE": { + "description": "Analog watchdog interrupt\n enable", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "AWDCH": { + "description": "Analog watchdog channel select\n bits", + "offset": 0, + "size": 5 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWSTART": { + "description": "Start conversion of regular\n channels", + "offset": 30, + "size": 1 + }, + "EXTEN": { + "description": "External trigger enable for regular\n channels", + "offset": 28, + "size": 2 + }, + "EXTSEL": { + "description": "External event select for regular\n group", + "offset": 24, + "size": 4 + }, + "JSWSTART": { + "description": "Start conversion of injected\n channels", + "offset": 22, + "size": 1 + }, + "JEXTEN": { + "description": "External trigger enable for injected\n channels", + "offset": 20, + "size": 2 + }, + "JEXTSEL": { + "description": "External event select for injected\n group", + "offset": 16, + "size": 4 + }, + "ALIGN": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "EOCS": { + "description": "End of conversion\n selection", + "offset": 10, + "size": 1 + }, + "DDS": { + "description": "DMA disable selection (for single ADC\n mode)", + "offset": 9, + "size": 1 + }, + "DMA": { + "description": "Direct memory access mode (for single\n ADC mode)", + "offset": 8, + "size": 1 + }, + "CONT": { + "description": "Continuous conversion", + "offset": 1, + "size": 1 + }, + "ADON": { + "description": "A/D Converter ON / OFF", + "offset": 0, + "size": 1 + } + } + } + }, + "SMPR1": { + "description": "sample time register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMPx_x": { + "description": "Sample time bits", + "offset": 0, + "size": 32 + } + } + } + }, + "SMPR2": { + "description": "sample time register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMPx_x": { + "description": "Sample time bits", + "offset": 0, + "size": 32 + } + } + } + }, + "JOFR1": { + "description": "injected channel data offset register\n x", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET1": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR2": { + "description": "injected channel data offset register\n x", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET2": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR3": { + "description": "injected channel data offset register\n x", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET3": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "JOFR4": { + "description": "injected channel data offset register\n x", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JOFFSET4": { + "description": "Data offset for injected channel\n x", + "offset": 0, + "size": 12 + } + } + } + }, + "HTR": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "HT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "LTR": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "SQR1": { + "description": "regular sequence register 1", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "L": { + "description": "Regular channel sequence\n length", + "offset": 20, + "size": 4 + }, + "SQ16": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ15": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ14": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ13": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR2": { + "description": "regular sequence register 2", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ12": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ11": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ10": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ9": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ8": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ7": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "SQR3": { + "description": "regular sequence register 3", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SQ6": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "SQ5": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "SQ4": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "SQ3": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "SQ2": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "SQ1": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JSQR": { + "description": "injected sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "JL": { + "description": "Injected sequence length", + "offset": 20, + "size": 2 + }, + "JSQ4": { + "description": "4th conversion in injected\n sequence", + "offset": 15, + "size": 5 + }, + "JSQ3": { + "description": "3rd conversion in injected\n sequence", + "offset": 10, + "size": 5 + }, + "JSQ2": { + "description": "2nd conversion in injected\n sequence", + "offset": 5, + "size": 5 + }, + "JSQ1": { + "description": "1st conversion in injected\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "JDR1": { + "description": "injected data register x", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR2": { + "description": "injected data register x", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR3": { + "description": "injected data register x", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "JDR4": { + "description": "injected data register x", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "JDATA": { + "description": "Injected data", + "offset": 0, + "size": 16 + } + } + } + }, + "DR": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA": { + "description": "Regular data", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "OTG_HS_GLOBAL": { + "description": "USB on the go high speed", + "children": { + "registers": { + "OTG_HS_GOTGCTL": { + "description": "OTG_HS control and status\n register", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRQSCS": { + "description": "Session request success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRQ": { + "description": "Session request", + "offset": 1, + "size": 1 + }, + "HNGSCS": { + "description": "Host negotiation success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPRQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HSHNPEN": { + "description": "Host set HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "CIDSTS": { + "description": "Connector ID status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DBCT": { + "description": "Long/short debounce time", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASVLD": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSVLD": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_GOTGINT": { + "description": "OTG_HS interrupt register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEDET": { + "description": "Session end detected", + "offset": 2, + "size": 1 + }, + "SRSSCHG": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNSSCHG": { + "description": "Host negotiation success status\n change", + "offset": 9, + "size": 1 + }, + "HNGDET": { + "description": "Host negotiation detected", + "offset": 17, + "size": 1 + }, + "ADTOCHG": { + "description": "A-device timeout change", + "offset": 18, + "size": 1 + }, + "DBCDNE": { + "description": "Debounce done", + "offset": 19, + "size": 1 + } + } + } + }, + "OTG_HS_GAHBCFG": { + "description": "OTG_HS AHB configuration\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINT": { + "description": "Global interrupt mask", + "offset": 0, + "size": 1 + }, + "HBSTLEN": { + "description": "Burst length/type", + "offset": 1, + "size": 4 + }, + "DMAEN": { + "description": "DMA enable", + "offset": 5, + "size": 1 + }, + "TXFELVL": { + "description": "TxFIFO empty level", + "offset": 7, + "size": 1 + }, + "PTXFELVL": { + "description": "Periodic TxFIFO empty\n level", + "offset": 8, + "size": 1 + } + } + } + }, + "OTG_HS_GUSBCFG": { + "description": "OTG_HS USB configuration\n register", + "offset": 12, + "size": 32, + "reset_value": 2560, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOCAL": { + "description": "FS timeout calibration", + "offset": 0, + "size": 3 + }, + "PHYSEL": { + "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n full-speed serial transceiver select", + "offset": 6, + "size": 1, + "access": "write-only" + }, + "SRPCAP": { + "description": "SRP-capable", + "offset": 8, + "size": 1 + }, + "HNPCAP": { + "description": "HNP-capable", + "offset": 9, + "size": 1 + }, + "TRDT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "PHYLPCS": { + "description": "PHY Low-power clock select", + "offset": 15, + "size": 1 + }, + "ULPIFSLS": { + "description": "ULPI FS/LS select", + "offset": 17, + "size": 1 + }, + "ULPIAR": { + "description": "ULPI Auto-resume", + "offset": 18, + "size": 1 + }, + "ULPICSM": { + "description": "ULPI Clock SuspendM", + "offset": 19, + "size": 1 + }, + "ULPIEVBUSD": { + "description": "ULPI External VBUS Drive", + "offset": 20, + "size": 1 + }, + "ULPIEVBUSI": { + "description": "ULPI external VBUS\n indicator", + "offset": 21, + "size": 1 + }, + "TSDPS": { + "description": "TermSel DLine pulsing\n selection", + "offset": 22, + "size": 1 + }, + "PCCI": { + "description": "Indicator complement", + "offset": 23, + "size": 1 + }, + "PTCI": { + "description": "Indicator pass through", + "offset": 24, + "size": 1 + }, + "ULPIIPD": { + "description": "ULPI interface protect\n disable", + "offset": 25, + "size": 1 + }, + "FHMOD": { + "description": "Forced host mode", + "offset": 29, + "size": 1 + }, + "FDMOD": { + "description": "Forced peripheral mode", + "offset": 30, + "size": 1 + }, + "CTXPKT": { + "description": "Corrupt Tx packet", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GRSTCTL": { + "description": "OTG_HS reset register", + "offset": 16, + "size": 32, + "reset_value": 536870912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "FCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFFLSH": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFFLSH": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + }, + "DMAREQ": { + "description": "DMA request signal", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "AHBIDL": { + "description": "AHB master idle", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "OTG_HS_GINTSTS": { + "description": "OTG_HS core interrupt register", + "offset": 20, + "size": 32, + "reset_value": 67108896, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMOD": { + "description": "Current mode of operation", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MMIS": { + "description": "Mode mismatch interrupt", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFLVL": { + "description": "RxFIFO nonempty", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFE": { + "description": "Nonperiodic TxFIFO empty", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GINAKEFF": { + "description": "Global IN nonperiodic NAK\n effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "BOUTNAKEFF": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESUSP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "USBSUSP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMDNE": { + "description": "Enumeration done", + "offset": 13, + "size": 1 + }, + "ISOODRP": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPF": { + "description": "End of periodic frame\n interrupt", + "offset": 15, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoint interrupt", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPINT": { + "description": "OUT endpoint interrupt", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "IISOIXFR": { + "description": "Incomplete isochronous IN\n transfer", + "offset": 20, + "size": 1 + }, + "PXFR_INCOMPISOOUT": { + "description": "Incomplete periodic\n transfer", + "offset": 21, + "size": 1 + }, + "DATAFSUSP": { + "description": "Data fetch suspended", + "offset": 22, + "size": 1 + }, + "HPRTINT": { + "description": "Host port interrupt", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCINT": { + "description": "Host channels interrupt", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFE": { + "description": "Periodic TxFIFO empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CIDSCHG": { + "description": "Connector ID status change", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected\n interrupt", + "offset": 29, + "size": 1 + }, + "SRQINT": { + "description": "Session request/new session detected\n interrupt", + "offset": 30, + "size": 1 + }, + "WKUINT": { + "description": "Resume/remote wakeup detected\n interrupt", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GINTMSK": { + "description": "OTG_HS interrupt mask register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMISM": { + "description": "Mode mismatch interrupt\n mask", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt mask", + "offset": 2, + "size": 1 + }, + "SOFM": { + "description": "Start of frame mask", + "offset": 3, + "size": 1 + }, + "RXFLVLM": { + "description": "Receive FIFO nonempty mask", + "offset": 4, + "size": 1 + }, + "NPTXFEM": { + "description": "Nonperiodic TxFIFO empty\n mask", + "offset": 5, + "size": 1 + }, + "GINAKEFFM": { + "description": "Global nonperiodic IN NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "GONAKEFFM": { + "description": "Global OUT NAK effective\n mask", + "offset": 7, + "size": 1 + }, + "ESUSPM": { + "description": "Early suspend mask", + "offset": 10, + "size": 1 + }, + "USBSUSPM": { + "description": "USB suspend mask", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset mask", + "offset": 12, + "size": 1 + }, + "ENUMDNEM": { + "description": "Enumeration done mask", + "offset": 13, + "size": 1 + }, + "ISOODRPM": { + "description": "Isochronous OUT packet dropped interrupt\n mask", + "offset": 14, + "size": 1 + }, + "EOPFM": { + "description": "End of periodic frame interrupt\n mask", + "offset": 15, + "size": 1 + }, + "EPMISM": { + "description": "Endpoint mismatch interrupt\n mask", + "offset": 17, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoints interrupt\n mask", + "offset": 18, + "size": 1 + }, + "OEPINT": { + "description": "OUT endpoints interrupt\n mask", + "offset": 19, + "size": 1 + }, + "IISOIXFRM": { + "description": "Incomplete isochronous IN transfer\n mask", + "offset": 20, + "size": 1 + }, + "PXFRM_IISOOXFRM": { + "description": "Incomplete periodic transfer\n mask", + "offset": 21, + "size": 1 + }, + "FSUSPM": { + "description": "Data fetch suspended mask", + "offset": 22, + "size": 1 + }, + "PRTIM": { + "description": "Host port interrupt mask", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIM": { + "description": "Host channels interrupt\n mask", + "offset": 25, + "size": 1 + }, + "PTXFEM": { + "description": "Periodic TxFIFO empty mask", + "offset": 26, + "size": 1 + }, + "CIDSCHGM": { + "description": "Connector ID status change\n mask", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected interrupt\n mask", + "offset": 29, + "size": 1 + }, + "SRQIM": { + "description": "Session request/new session detected\n interrupt mask", + "offset": 30, + "size": 1 + }, + "WUIM": { + "description": "Resume/remote wakeup detected interrupt\n mask", + "offset": 31, + "size": 1 + } + } + } + }, + "OTG_HS_GRXSTSR_Host": { + "description": "OTG_HS Receive status debug read register\n (host mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CHNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "OTG_HS_GRXSTSP_Host": { + "description": "OTG_HS status read and pop register (host\n mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CHNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "OTG_HS_GRXFSIZ": { + "description": "OTG_HS Receive FIFO size\n register", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "RxFIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "OTG_HS_GNPTXFSIZ_Host": { + "description": "OTG_HS nonperiodic transmit FIFO size\n register (host mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "NPTXFSA": { + "description": "Nonperiodic transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "NPTXFD": { + "description": "Nonperiodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_TX0FSIZ_Peripheral": { + "description": "Endpoint 0 transmit FIFO size (peripheral\n mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX0FSA": { + "description": "Endpoint 0 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "TX0FD": { + "description": "Endpoint 0 TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_GNPTXSTS": { + "description": "OTG_HS nonperiodic transmit FIFO/queue\n status register", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFSAV": { + "description": "Nonperiodic TxFIFO space\n available", + "offset": 0, + "size": 16 + }, + "NPTQXSAV": { + "description": "Nonperiodic transmit request queue space\n available", + "offset": 16, + "size": 8 + }, + "NPTXQTOP": { + "description": "Top of the nonperiodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "OTG_HS_GCCFG": { + "description": "OTG_HS general core configuration\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRDWN": { + "description": "Power down", + "offset": 16, + "size": 1 + }, + "I2CPADEN": { + "description": "Enable I2C bus connection for the\n external I2C PHY interface", + "offset": 17, + "size": 1 + }, + "VBUSASEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 18, + "size": 1 + }, + "VBUSBSEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 19, + "size": 1 + }, + "SOFOUTEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + }, + "NOVBUSSENS": { + "description": "VBUS sensing disable\n option", + "offset": 21, + "size": 1 + } + } + } + }, + "OTG_HS_CID": { + "description": "OTG_HS core ID register", + "offset": 60, + "size": 32, + "reset_value": 4608, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRODUCT_ID": { + "description": "Product ID field", + "offset": 0, + "size": 32 + } + } + } + }, + "OTG_HS_HPTXFSIZ": { + "description": "OTG_HS Host periodic transmit FIFO size\n register", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXSA": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "PTXFD": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF1": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF2": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF3": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 284, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF4": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 288, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF5": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 292, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF6": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 296, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_DIEPTXF7": { + "description": "OTG_HS device IN endpoint transmit FIFO size\n register", + "offset": 300, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFOx transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "OTG_HS_GRXSTSR_Peripheral": { + "description": "OTG_HS Receive status debug read register\n (peripheral mode mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "OTG_HS_GRXSTSP_Peripheral": { + "description": "OTG_HS status read and pop register\n (peripheral mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + } + } + } + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "children": { + "registers": { + "IMR": { + "description": "Interrupt mask register\n (EXTI_IMR)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Interrupt Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Interrupt Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Interrupt Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Interrupt Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Interrupt Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Interrupt Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Interrupt Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Interrupt Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Interrupt Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Interrupt Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Interrupt Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Interrupt Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Interrupt Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Interrupt Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Interrupt Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Interrupt Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Interrupt Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Interrupt Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Interrupt Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Interrupt Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Interrupt Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Interrupt Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Interrupt Mask on line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "EMR": { + "description": "Event mask register (EXTI_EMR)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MR0": { + "description": "Event Mask on line 0", + "offset": 0, + "size": 1 + }, + "MR1": { + "description": "Event Mask on line 1", + "offset": 1, + "size": 1 + }, + "MR2": { + "description": "Event Mask on line 2", + "offset": 2, + "size": 1 + }, + "MR3": { + "description": "Event Mask on line 3", + "offset": 3, + "size": 1 + }, + "MR4": { + "description": "Event Mask on line 4", + "offset": 4, + "size": 1 + }, + "MR5": { + "description": "Event Mask on line 5", + "offset": 5, + "size": 1 + }, + "MR6": { + "description": "Event Mask on line 6", + "offset": 6, + "size": 1 + }, + "MR7": { + "description": "Event Mask on line 7", + "offset": 7, + "size": 1 + }, + "MR8": { + "description": "Event Mask on line 8", + "offset": 8, + "size": 1 + }, + "MR9": { + "description": "Event Mask on line 9", + "offset": 9, + "size": 1 + }, + "MR10": { + "description": "Event Mask on line 10", + "offset": 10, + "size": 1 + }, + "MR11": { + "description": "Event Mask on line 11", + "offset": 11, + "size": 1 + }, + "MR12": { + "description": "Event Mask on line 12", + "offset": 12, + "size": 1 + }, + "MR13": { + "description": "Event Mask on line 13", + "offset": 13, + "size": 1 + }, + "MR14": { + "description": "Event Mask on line 14", + "offset": 14, + "size": 1 + }, + "MR15": { + "description": "Event Mask on line 15", + "offset": 15, + "size": 1 + }, + "MR16": { + "description": "Event Mask on line 16", + "offset": 16, + "size": 1 + }, + "MR17": { + "description": "Event Mask on line 17", + "offset": 17, + "size": 1 + }, + "MR18": { + "description": "Event Mask on line 18", + "offset": 18, + "size": 1 + }, + "MR19": { + "description": "Event Mask on line 19", + "offset": 19, + "size": 1 + }, + "MR20": { + "description": "Event Mask on line 20", + "offset": 20, + "size": 1 + }, + "MR21": { + "description": "Event Mask on line 21", + "offset": 21, + "size": 1 + }, + "MR22": { + "description": "Event Mask on line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "RTSR": { + "description": "Rising Trigger selection register\n (EXTI_RTSR)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Rising trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Rising trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Rising trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Rising trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Rising trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Rising trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Rising trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Rising trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Rising trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Rising trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Rising trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Rising trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Rising trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Rising trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Rising trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Rising trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Rising trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Rising trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Rising trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Rising trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Rising trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Rising trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Rising trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "FTSR": { + "description": "Falling Trigger selection register\n (EXTI_FTSR)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TR0": { + "description": "Falling trigger event configuration of\n line 0", + "offset": 0, + "size": 1 + }, + "TR1": { + "description": "Falling trigger event configuration of\n line 1", + "offset": 1, + "size": 1 + }, + "TR2": { + "description": "Falling trigger event configuration of\n line 2", + "offset": 2, + "size": 1 + }, + "TR3": { + "description": "Falling trigger event configuration of\n line 3", + "offset": 3, + "size": 1 + }, + "TR4": { + "description": "Falling trigger event configuration of\n line 4", + "offset": 4, + "size": 1 + }, + "TR5": { + "description": "Falling trigger event configuration of\n line 5", + "offset": 5, + "size": 1 + }, + "TR6": { + "description": "Falling trigger event configuration of\n line 6", + "offset": 6, + "size": 1 + }, + "TR7": { + "description": "Falling trigger event configuration of\n line 7", + "offset": 7, + "size": 1 + }, + "TR8": { + "description": "Falling trigger event configuration of\n line 8", + "offset": 8, + "size": 1 + }, + "TR9": { + "description": "Falling trigger event configuration of\n line 9", + "offset": 9, + "size": 1 + }, + "TR10": { + "description": "Falling trigger event configuration of\n line 10", + "offset": 10, + "size": 1 + }, + "TR11": { + "description": "Falling trigger event configuration of\n line 11", + "offset": 11, + "size": 1 + }, + "TR12": { + "description": "Falling trigger event configuration of\n line 12", + "offset": 12, + "size": 1 + }, + "TR13": { + "description": "Falling trigger event configuration of\n line 13", + "offset": 13, + "size": 1 + }, + "TR14": { + "description": "Falling trigger event configuration of\n line 14", + "offset": 14, + "size": 1 + }, + "TR15": { + "description": "Falling trigger event configuration of\n line 15", + "offset": 15, + "size": 1 + }, + "TR16": { + "description": "Falling trigger event configuration of\n line 16", + "offset": 16, + "size": 1 + }, + "TR17": { + "description": "Falling trigger event configuration of\n line 17", + "offset": 17, + "size": 1 + }, + "TR18": { + "description": "Falling trigger event configuration of\n line 18", + "offset": 18, + "size": 1 + }, + "TR19": { + "description": "Falling trigger event configuration of\n line 19", + "offset": 19, + "size": 1 + }, + "TR20": { + "description": "Falling trigger event configuration of\n line 20", + "offset": 20, + "size": 1 + }, + "TR21": { + "description": "Falling trigger event configuration of\n line 21", + "offset": 21, + "size": 1 + }, + "TR22": { + "description": "Falling trigger event configuration of\n line 22", + "offset": 22, + "size": 1 + } + } + } + }, + "SWIER": { + "description": "Software interrupt event register\n (EXTI_SWIER)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIER0": { + "description": "Software Interrupt on line\n 0", + "offset": 0, + "size": 1 + }, + "SWIER1": { + "description": "Software Interrupt on line\n 1", + "offset": 1, + "size": 1 + }, + "SWIER2": { + "description": "Software Interrupt on line\n 2", + "offset": 2, + "size": 1 + }, + "SWIER3": { + "description": "Software Interrupt on line\n 3", + "offset": 3, + "size": 1 + }, + "SWIER4": { + "description": "Software Interrupt on line\n 4", + "offset": 4, + "size": 1 + }, + "SWIER5": { + "description": "Software Interrupt on line\n 5", + "offset": 5, + "size": 1 + }, + "SWIER6": { + "description": "Software Interrupt on line\n 6", + "offset": 6, + "size": 1 + }, + "SWIER7": { + "description": "Software Interrupt on line\n 7", + "offset": 7, + "size": 1 + }, + "SWIER8": { + "description": "Software Interrupt on line\n 8", + "offset": 8, + "size": 1 + }, + "SWIER9": { + "description": "Software Interrupt on line\n 9", + "offset": 9, + "size": 1 + }, + "SWIER10": { + "description": "Software Interrupt on line\n 10", + "offset": 10, + "size": 1 + }, + "SWIER11": { + "description": "Software Interrupt on line\n 11", + "offset": 11, + "size": 1 + }, + "SWIER12": { + "description": "Software Interrupt on line\n 12", + "offset": 12, + "size": 1 + }, + "SWIER13": { + "description": "Software Interrupt on line\n 13", + "offset": 13, + "size": 1 + }, + "SWIER14": { + "description": "Software Interrupt on line\n 14", + "offset": 14, + "size": 1 + }, + "SWIER15": { + "description": "Software Interrupt on line\n 15", + "offset": 15, + "size": 1 + }, + "SWIER16": { + "description": "Software Interrupt on line\n 16", + "offset": 16, + "size": 1 + }, + "SWIER17": { + "description": "Software Interrupt on line\n 17", + "offset": 17, + "size": 1 + }, + "SWIER18": { + "description": "Software Interrupt on line\n 18", + "offset": 18, + "size": 1 + }, + "SWIER19": { + "description": "Software Interrupt on line\n 19", + "offset": 19, + "size": 1 + }, + "SWIER20": { + "description": "Software Interrupt on line\n 20", + "offset": 20, + "size": 1 + }, + "SWIER21": { + "description": "Software Interrupt on line\n 21", + "offset": 21, + "size": 1 + }, + "SWIER22": { + "description": "Software Interrupt on line\n 22", + "offset": 22, + "size": 1 + } + } + } + }, + "PR": { + "description": "Pending register (EXTI_PR)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR0": { + "description": "Pending bit 0", + "offset": 0, + "size": 1 + }, + "PR1": { + "description": "Pending bit 1", + "offset": 1, + "size": 1 + }, + "PR2": { + "description": "Pending bit 2", + "offset": 2, + "size": 1 + }, + "PR3": { + "description": "Pending bit 3", + "offset": 3, + "size": 1 + }, + "PR4": { + "description": "Pending bit 4", + "offset": 4, + "size": 1 + }, + "PR5": { + "description": "Pending bit 5", + "offset": 5, + "size": 1 + }, + "PR6": { + "description": "Pending bit 6", + "offset": 6, + "size": 1 + }, + "PR7": { + "description": "Pending bit 7", + "offset": 7, + "size": 1 + }, + "PR8": { + "description": "Pending bit 8", + "offset": 8, + "size": 1 + }, + "PR9": { + "description": "Pending bit 9", + "offset": 9, + "size": 1 + }, + "PR10": { + "description": "Pending bit 10", + "offset": 10, + "size": 1 + }, + "PR11": { + "description": "Pending bit 11", + "offset": 11, + "size": 1 + }, + "PR12": { + "description": "Pending bit 12", + "offset": 12, + "size": 1 + }, + "PR13": { + "description": "Pending bit 13", + "offset": 13, + "size": 1 + }, + "PR14": { + "description": "Pending bit 14", + "offset": 14, + "size": 1 + }, + "PR15": { + "description": "Pending bit 15", + "offset": 15, + "size": 1 + }, + "PR16": { + "description": "Pending bit 16", + "offset": 16, + "size": 1 + }, + "PR17": { + "description": "Pending bit 17", + "offset": 17, + "size": 1 + }, + "PR18": { + "description": "Pending bit 18", + "offset": 18, + "size": 1 + }, + "PR19": { + "description": "Pending bit 19", + "offset": 19, + "size": 1 + }, + "PR20": { + "description": "Pending bit 20", + "offset": 20, + "size": 1 + }, + "PR21": { + "description": "Pending bit 21", + "offset": 21, + "size": 1 + }, + "PR22": { + "description": "Pending bit 22", + "offset": 22, + "size": 1 + } + } + } + } + } + } + }, + "USART6": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "Status register", + "offset": 0, + "size": 32, + "reset_value": 12582912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTS": { + "description": "CTS flag", + "offset": 9, + "size": 1 + }, + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NF": { + "description": "Noise detected flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "CR1": { + "description": "Control register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVER8": { + "description": "Oversampling mode", + "offset": 15, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "CLKEN": { + "description": "Clock enable", + "offset": 11, + "size": 1 + }, + "CPOL": { + "description": "Clock polarity", + "offset": 10, + "size": 1 + }, + "CPHA": { + "description": "Clock phase", + "offset": 9, + "size": 1 + }, + "LBCL": { + "description": "Last bit clock pulse", + "offset": 8, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONEBIT": { + "description": "One sample bit method\n enable", + "offset": 11, + "size": 1 + }, + "CTSIE": { + "description": "CTS interrupt enable", + "offset": 10, + "size": 1 + }, + "CTSE": { + "description": "CTS enable", + "offset": 9, + "size": 1 + }, + "RTSE": { + "description": "RTS enable", + "offset": 8, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "SCEN": { + "description": "Smartcard mode enable", + "offset": 5, + "size": 1 + }, + "NACK": { + "description": "Smartcard NACK enable", + "offset": 4, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GTPR": { + "description": "Guard time and prescaler\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GT": { + "description": "Guard time value", + "offset": 8, + "size": 8 + }, + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "FLASH": { + "description": "FLASH", + "children": { + "registers": { + "ACR": { + "description": "Flash access control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LATENCY": { + "description": "Latency", + "offset": 0, + "size": 3 + }, + "PRFTEN": { + "description": "Prefetch enable", + "offset": 8, + "size": 1 + }, + "ICEN": { + "description": "Instruction cache enable", + "offset": 9, + "size": 1 + }, + "DCEN": { + "description": "Data cache enable", + "offset": 10, + "size": 1 + }, + "ICRST": { + "description": "Instruction cache reset", + "offset": 11, + "size": 1, + "access": "write-only" + }, + "DCRST": { + "description": "Data cache reset", + "offset": 12, + "size": 1 + } + } + } + }, + "KEYR": { + "description": "Flash key register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "FPEC key", + "offset": 0, + "size": 32 + } + } + } + }, + "OPTKEYR": { + "description": "Flash option key register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "OPTKEY": { + "description": "Option byte key", + "offset": 0, + "size": 32 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOP": { + "description": "End of operation", + "offset": 0, + "size": 1 + }, + "OPERR": { + "description": "Operation error", + "offset": 1, + "size": 1 + }, + "WRPERR": { + "description": "Write protection error", + "offset": 4, + "size": 1 + }, + "PGAERR": { + "description": "Programming alignment\n error", + "offset": 5, + "size": 1 + }, + "PGPERR": { + "description": "Programming parallelism\n error", + "offset": 6, + "size": 1 + }, + "PGSERR": { + "description": "Programming sequence error", + "offset": 7, + "size": 1 + }, + "BSY": { + "description": "Busy", + "offset": 16, + "size": 1, + "access": "read-only" + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 16, + "size": 32, + "reset_value": 2147483648, + "reset_mask": 4294967295, + "children": { + "fields": { + "PG": { + "description": "Programming", + "offset": 0, + "size": 1 + }, + "SER": { + "description": "Sector Erase", + "offset": 1, + "size": 1 + }, + "MER": { + "description": "Mass Erase of sectors 0 to\n 11", + "offset": 2, + "size": 1 + }, + "SNB": { + "description": "Sector number", + "offset": 3, + "size": 5 + }, + "PSIZE": { + "description": "Program size", + "offset": 8, + "size": 2 + }, + "MER1": { + "description": "Mass Erase of sectors 12 to\n 23", + "offset": 15, + "size": 1 + }, + "STRT": { + "description": "Start", + "offset": 16, + "size": 1 + }, + "EOPIE": { + "description": "End of operation interrupt\n enable", + "offset": 24, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 25, + "size": 1 + }, + "LOCK": { + "description": "Lock", + "offset": 31, + "size": 1 + } + } + } + }, + "OPTCR": { + "description": "Flash option control register", + "offset": 20, + "size": 32, + "reset_value": 268413677, + "reset_mask": 4294967295, + "children": { + "fields": { + "OPTLOCK": { + "description": "Option lock", + "offset": 0, + "size": 1 + }, + "OPTSTRT": { + "description": "Option start", + "offset": 1, + "size": 1 + }, + "BOR_LEV": { + "description": "BOR reset Level", + "offset": 2, + "size": 2 + }, + "WDG_SW": { + "description": "WDG_SW User option bytes", + "offset": 5, + "size": 1 + }, + "nRST_STOP": { + "description": "nRST_STOP User option\n bytes", + "offset": 6, + "size": 1 + }, + "nRST_STDBY": { + "description": "nRST_STDBY User option\n bytes", + "offset": 7, + "size": 1 + }, + "RDP": { + "description": "Read protect", + "offset": 8, + "size": 8 + }, + "nWRP": { + "description": "Not write protect", + "offset": 16, + "size": 12 + } + } + } + }, + "OPTCR1": { + "description": "Flash option control register\n 1", + "offset": 24, + "size": 32, + "reset_value": 268369920, + "reset_mask": 4294967295, + "children": { + "fields": { + "nWRP": { + "description": "Not write protect", + "offset": 16, + "size": 12 + } + } + } + } + } + } + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "children": { + "registers": { + "ISER0": { + "description": "Interrupt Set-Enable Register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER1": { + "description": "Interrupt Set-Enable Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISER2": { + "description": "Interrupt Set-Enable Register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETENA": { + "description": "SETENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER0": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER1": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ICER2": { + "description": "Interrupt Clear-Enable\n Register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRENA": { + "description": "CLRENA", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR0": { + "description": "Interrupt Set-Pending Register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR1": { + "description": "Interrupt Set-Pending Register", + "offset": 260, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ISPR2": { + "description": "Interrupt Set-Pending Register", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SETPEND": { + "description": "SETPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR0": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR1": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "ICPR2": { + "description": "Interrupt Clear-Pending\n Register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLRPEND": { + "description": "CLRPEND", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR0": { + "description": "Interrupt Active Bit Register", + "offset": 512, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR1": { + "description": "Interrupt Active Bit Register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IABR2": { + "description": "Interrupt Active Bit Register", + "offset": 520, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ACTIVE": { + "description": "ACTIVE", + "offset": 0, + "size": 32 + } + } + } + }, + "IPR0": { + "description": "Interrupt Priority Register", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR1": { + "description": "Interrupt Priority Register", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR2": { + "description": "Interrupt Priority Register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR3": { + "description": "Interrupt Priority Register", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR4": { + "description": "Interrupt Priority Register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR5": { + "description": "Interrupt Priority Register", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR6": { + "description": "Interrupt Priority Register", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR7": { + "description": "Interrupt Priority Register", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR8": { + "description": "Interrupt Priority Register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR9": { + "description": "Interrupt Priority Register", + "offset": 804, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR10": { + "description": "Interrupt Priority Register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR11": { + "description": "Interrupt Priority Register", + "offset": 812, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR12": { + "description": "Interrupt Priority Register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR13": { + "description": "Interrupt Priority Register", + "offset": 820, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR14": { + "description": "Interrupt Priority Register", + "offset": 824, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR15": { + "description": "Interrupt Priority Register", + "offset": 828, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR16": { + "description": "Interrupt Priority Register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR17": { + "description": "Interrupt Priority Register", + "offset": 836, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR18": { + "description": "Interrupt Priority Register", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR19": { + "description": "Interrupt Priority Register", + "offset": 844, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + }, + "IPR20": { + "description": "Interrupt Priority Register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IPR_N0": { + "description": "IPR_N0", + "offset": 0, + "size": 8 + }, + "IPR_N1": { + "description": "IPR_N1", + "offset": 8, + "size": 8 + }, + "IPR_N2": { + "description": "IPR_N2", + "offset": 16, + "size": 8 + }, + "IPR_N3": { + "description": "IPR_N3", + "offset": 24, + "size": 8 + } + } + } + } + } + } + }, + "Ethernet_MAC": { + "description": "Ethernet: media access control\n (MAC)", + "children": { + "registers": { + "MACCR": { + "description": "Ethernet MAC configuration\n register", + "offset": 0, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "RE": { + "description": "RE", + "offset": 2, + "size": 1 + }, + "TE": { + "description": "TE", + "offset": 3, + "size": 1 + }, + "DC": { + "description": "DC", + "offset": 4, + "size": 1 + }, + "BL": { + "description": "BL", + "offset": 5, + "size": 2 + }, + "APCS": { + "description": "APCS", + "offset": 7, + "size": 1 + }, + "RD": { + "description": "RD", + "offset": 9, + "size": 1 + }, + "IPCO": { + "description": "IPCO", + "offset": 10, + "size": 1 + }, + "DM": { + "description": "DM", + "offset": 11, + "size": 1 + }, + "LM": { + "description": "LM", + "offset": 12, + "size": 1 + }, + "ROD": { + "description": "ROD", + "offset": 13, + "size": 1 + }, + "FES": { + "description": "FES", + "offset": 14, + "size": 1 + }, + "CSD": { + "description": "CSD", + "offset": 16, + "size": 1 + }, + "IFG": { + "description": "IFG", + "offset": 17, + "size": 3 + }, + "JD": { + "description": "JD", + "offset": 22, + "size": 1 + }, + "WD": { + "description": "WD", + "offset": 23, + "size": 1 + }, + "CSTF": { + "description": "CSTF", + "offset": 25, + "size": 1 + } + } + } + }, + "MACFFR": { + "description": "Ethernet MAC frame filter\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "PM", + "offset": 0, + "size": 1 + }, + "HU": { + "description": "HU", + "offset": 1, + "size": 1 + }, + "HM": { + "description": "HM", + "offset": 2, + "size": 1 + }, + "DAIF": { + "description": "DAIF", + "offset": 3, + "size": 1 + }, + "RAM": { + "description": "RAM", + "offset": 4, + "size": 1 + }, + "BFD": { + "description": "BFD", + "offset": 5, + "size": 1 + }, + "PCF": { + "description": "PCF", + "offset": 6, + "size": 1 + }, + "SAIF": { + "description": "SAIF", + "offset": 7, + "size": 1 + }, + "SAF": { + "description": "SAF", + "offset": 8, + "size": 1 + }, + "HPF": { + "description": "HPF", + "offset": 9, + "size": 1 + }, + "RA": { + "description": "RA", + "offset": 31, + "size": 1 + } + } + } + }, + "MACHTHR": { + "description": "Ethernet MAC hash table high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTH": { + "description": "HTH", + "offset": 0, + "size": 32 + } + } + } + }, + "MACHTLR": { + "description": "Ethernet MAC hash table low\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HTL": { + "description": "HTL", + "offset": 0, + "size": 32 + } + } + } + }, + "MACMIIAR": { + "description": "Ethernet MAC MII address\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MB": { + "description": "MB", + "offset": 0, + "size": 1 + }, + "MW": { + "description": "MW", + "offset": 1, + "size": 1 + }, + "CR": { + "description": "CR", + "offset": 2, + "size": 3 + }, + "MR": { + "description": "MR", + "offset": 6, + "size": 5 + }, + "PA": { + "description": "PA", + "offset": 11, + "size": 5 + } + } + } + }, + "MACMIIDR": { + "description": "Ethernet MAC MII data register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TD": { + "description": "TD", + "offset": 0, + "size": 16 + } + } + } + }, + "MACFCR": { + "description": "Ethernet MAC flow control\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FCB": { + "description": "FCB", + "offset": 0, + "size": 1 + }, + "TFCE": { + "description": "TFCE", + "offset": 1, + "size": 1 + }, + "RFCE": { + "description": "RFCE", + "offset": 2, + "size": 1 + }, + "UPFD": { + "description": "UPFD", + "offset": 3, + "size": 1 + }, + "PLT": { + "description": "PLT", + "offset": 4, + "size": 2 + }, + "ZQPD": { + "description": "ZQPD", + "offset": 7, + "size": 1 + }, + "PT": { + "description": "PT", + "offset": 16, + "size": 16 + } + } + } + }, + "MACVLANTR": { + "description": "Ethernet MAC VLAN tag register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "VLANTI": { + "description": "VLANTI", + "offset": 0, + "size": 16 + }, + "VLANTC": { + "description": "VLANTC", + "offset": 16, + "size": 1 + } + } + } + }, + "MACPMTCSR": { + "description": "Ethernet MAC PMT control and status\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PD": { + "description": "PD", + "offset": 0, + "size": 1 + }, + "MPE": { + "description": "MPE", + "offset": 1, + "size": 1 + }, + "WFE": { + "description": "WFE", + "offset": 2, + "size": 1 + }, + "MPR": { + "description": "MPR", + "offset": 5, + "size": 1 + }, + "WFR": { + "description": "WFR", + "offset": 6, + "size": 1 + }, + "GU": { + "description": "GU", + "offset": 9, + "size": 1 + }, + "WFFRPR": { + "description": "WFFRPR", + "offset": 31, + "size": 1 + } + } + } + }, + "MACDBGR": { + "description": "Ethernet MAC debug register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CR": { + "description": "CR", + "offset": 0, + "size": 1 + }, + "CSR": { + "description": "CSR", + "offset": 1, + "size": 1 + }, + "ROR": { + "description": "ROR", + "offset": 2, + "size": 1 + }, + "MCF": { + "description": "MCF", + "offset": 3, + "size": 1 + }, + "MCP": { + "description": "MCP", + "offset": 4, + "size": 1 + }, + "MCFHP": { + "description": "MCFHP", + "offset": 5, + "size": 1 + } + } + } + }, + "MACSR": { + "description": "Ethernet MAC interrupt status\n register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTS": { + "description": "PMTS", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "MMCS": { + "description": "MMCS", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "MMCRS": { + "description": "MMCRS", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "MMCTS": { + "description": "MMCTS", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "TSTS": { + "description": "TSTS", + "offset": 9, + "size": 1 + } + } + } + }, + "MACIMR": { + "description": "Ethernet MAC interrupt mask\n register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PMTIM": { + "description": "PMTIM", + "offset": 3, + "size": 1 + }, + "TSTIM": { + "description": "TSTIM", + "offset": 9, + "size": 1 + } + } + } + }, + "MACA0HR": { + "description": "Ethernet MAC address 0 high\n register", + "offset": 64, + "size": 32, + "reset_value": 1114111, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0H": { + "description": "MAC address0 high", + "offset": 0, + "size": 16 + }, + "MO": { + "description": "Always 1", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "MACA0LR": { + "description": "Ethernet MAC address 0 low\n register", + "offset": 68, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA0L": { + "description": "0", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA1HR": { + "description": "Ethernet MAC address 1 high\n register", + "offset": 72, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1H": { + "description": "MACA1H", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA1LR": { + "description": "Ethernet MAC address1 low\n register", + "offset": 76, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA1LR": { + "description": "MACA1LR", + "offset": 0, + "size": 32 + } + } + } + }, + "MACA2HR": { + "description": "Ethernet MAC address 2 high\n register", + "offset": 80, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MAC2AH": { + "description": "MAC2AH", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA2LR": { + "description": "Ethernet MAC address 2 low\n register", + "offset": 84, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA2L": { + "description": "MACA2L", + "offset": 0, + "size": 31 + } + } + } + }, + "MACA3HR": { + "description": "Ethernet MAC address 3 high\n register", + "offset": 88, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "MACA3H": { + "description": "MACA3H", + "offset": 0, + "size": 16 + }, + "MBC": { + "description": "MBC", + "offset": 24, + "size": 6 + }, + "SA": { + "description": "SA", + "offset": 30, + "size": 1 + }, + "AE": { + "description": "AE", + "offset": 31, + "size": 1 + } + } + } + }, + "MACA3LR": { + "description": "Ethernet MAC address 3 low\n register", + "offset": 92, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "MBCA3L": { + "description": "MBCA3L", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "CAN1": { + "description": "Controller area network", + "children": { + "registers": { + "MCR": { + "description": "master control register", + "offset": 0, + "size": 32, + "reset_value": 65538, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBF": { + "description": "DBF", + "offset": 16, + "size": 1 + }, + "RESET": { + "description": "RESET", + "offset": 15, + "size": 1 + }, + "TTCM": { + "description": "TTCM", + "offset": 7, + "size": 1 + }, + "ABOM": { + "description": "ABOM", + "offset": 6, + "size": 1 + }, + "AWUM": { + "description": "AWUM", + "offset": 5, + "size": 1 + }, + "NART": { + "description": "NART", + "offset": 4, + "size": 1 + }, + "RFLM": { + "description": "RFLM", + "offset": 3, + "size": 1 + }, + "TXFP": { + "description": "TXFP", + "offset": 2, + "size": 1 + }, + "SLEEP": { + "description": "SLEEP", + "offset": 1, + "size": 1 + }, + "INRQ": { + "description": "INRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "MSR": { + "description": "master status register", + "offset": 4, + "size": 32, + "reset_value": 3074, + "reset_mask": 4294967295, + "children": { + "fields": { + "RX": { + "description": "RX", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "SAMP": { + "description": "SAMP", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "RXM": { + "description": "RXM", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "TXM": { + "description": "TXM", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "SLAKI": { + "description": "SLAKI", + "offset": 4, + "size": 1 + }, + "WKUI": { + "description": "WKUI", + "offset": 3, + "size": 1 + }, + "ERRI": { + "description": "ERRI", + "offset": 2, + "size": 1 + }, + "SLAK": { + "description": "SLAK", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "INAK": { + "description": "INAK", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "TSR": { + "description": "transmit status register", + "offset": 8, + "size": 32, + "reset_value": 469762048, + "reset_mask": 4294967295, + "children": { + "fields": { + "LOW2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 31, + "size": 1, + "access": "read-only" + }, + "LOW1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LOW0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "TME2": { + "description": "Lowest priority flag for mailbox\n 2", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TME1": { + "description": "Lowest priority flag for mailbox\n 1", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "TME0": { + "description": "Lowest priority flag for mailbox\n 0", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CODE": { + "description": "CODE", + "offset": 24, + "size": 2, + "access": "read-only" + }, + "ABRQ2": { + "description": "ABRQ2", + "offset": 23, + "size": 1 + }, + "TERR2": { + "description": "TERR2", + "offset": 19, + "size": 1 + }, + "ALST2": { + "description": "ALST2", + "offset": 18, + "size": 1 + }, + "TXOK2": { + "description": "TXOK2", + "offset": 17, + "size": 1 + }, + "RQCP2": { + "description": "RQCP2", + "offset": 16, + "size": 1 + }, + "ABRQ1": { + "description": "ABRQ1", + "offset": 15, + "size": 1 + }, + "TERR1": { + "description": "TERR1", + "offset": 11, + "size": 1 + }, + "ALST1": { + "description": "ALST1", + "offset": 10, + "size": 1 + }, + "TXOK1": { + "description": "TXOK1", + "offset": 9, + "size": 1 + }, + "RQCP1": { + "description": "RQCP1", + "offset": 8, + "size": 1 + }, + "ABRQ0": { + "description": "ABRQ0", + "offset": 7, + "size": 1 + }, + "TERR0": { + "description": "TERR0", + "offset": 3, + "size": 1 + }, + "ALST0": { + "description": "ALST0", + "offset": 2, + "size": 1 + }, + "TXOK0": { + "description": "TXOK0", + "offset": 1, + "size": 1 + }, + "RQCP0": { + "description": "RQCP0", + "offset": 0, + "size": 1 + } + } + } + }, + "RF0R": { + "description": "receive FIFO 0 register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM0": { + "description": "RFOM0", + "offset": 5, + "size": 1 + }, + "FOVR0": { + "description": "FOVR0", + "offset": 4, + "size": 1 + }, + "FULL0": { + "description": "FULL0", + "offset": 3, + "size": 1 + }, + "FMP0": { + "description": "FMP0", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "RF1R": { + "description": "receive FIFO 1 register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFOM1": { + "description": "RFOM1", + "offset": 5, + "size": 1 + }, + "FOVR1": { + "description": "FOVR1", + "offset": 4, + "size": 1 + }, + "FULL1": { + "description": "FULL1", + "offset": 3, + "size": 1 + }, + "FMP1": { + "description": "FMP1", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "IER": { + "description": "interrupt enable register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLKIE": { + "description": "SLKIE", + "offset": 17, + "size": 1 + }, + "WKUIE": { + "description": "WKUIE", + "offset": 16, + "size": 1 + }, + "ERRIE": { + "description": "ERRIE", + "offset": 15, + "size": 1 + }, + "LECIE": { + "description": "LECIE", + "offset": 11, + "size": 1 + }, + "BOFIE": { + "description": "BOFIE", + "offset": 10, + "size": 1 + }, + "EPVIE": { + "description": "EPVIE", + "offset": 9, + "size": 1 + }, + "EWGIE": { + "description": "EWGIE", + "offset": 8, + "size": 1 + }, + "FOVIE1": { + "description": "FOVIE1", + "offset": 6, + "size": 1 + }, + "FFIE1": { + "description": "FFIE1", + "offset": 5, + "size": 1 + }, + "FMPIE1": { + "description": "FMPIE1", + "offset": 4, + "size": 1 + }, + "FOVIE0": { + "description": "FOVIE0", + "offset": 3, + "size": 1 + }, + "FFIE0": { + "description": "FFIE0", + "offset": 2, + "size": 1 + }, + "FMPIE0": { + "description": "FMPIE0", + "offset": 1, + "size": 1 + }, + "TMEIE": { + "description": "TMEIE", + "offset": 0, + "size": 1 + } + } + } + }, + "ESR": { + "description": "interrupt enable register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REC": { + "description": "REC", + "offset": 24, + "size": 8, + "access": "read-only" + }, + "TEC": { + "description": "TEC", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "LEC": { + "description": "LEC", + "offset": 4, + "size": 3 + }, + "BOFF": { + "description": "BOFF", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "EPVF": { + "description": "EPVF", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "EWGF": { + "description": "EWGF", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "BTR": { + "description": "bit timing register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SILM": { + "description": "SILM", + "offset": 31, + "size": 1 + }, + "LBKM": { + "description": "LBKM", + "offset": 30, + "size": 1 + }, + "SJW": { + "description": "SJW", + "offset": 24, + "size": 2 + }, + "TS2": { + "description": "TS2", + "offset": 20, + "size": 3 + }, + "TS1": { + "description": "TS1", + "offset": 16, + "size": 4 + }, + "BRP": { + "description": "BRP", + "offset": 0, + "size": 10 + } + } + } + }, + "TI0R": { + "description": "TX mailbox identifier register", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT0R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL0R": { + "description": "mailbox data low register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH0R": { + "description": "mailbox data high register", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "TI1R": { + "description": "mailbox identifier register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT1R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL1R": { + "description": "mailbox data low register", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH1R": { + "description": "mailbox data high register", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "TI2R": { + "description": "mailbox identifier register", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + }, + "TXRQ": { + "description": "TXRQ", + "offset": 0, + "size": 1 + } + } + } + }, + "TDT2R": { + "description": "mailbox data length control and time stamp\n register", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "TGT": { + "description": "TGT", + "offset": 8, + "size": 1 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "TDL2R": { + "description": "mailbox data low register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "TDH2R": { + "description": "mailbox data high register", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "RI0R": { + "description": "receive FIFO mailbox identifier\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + } + } + } + }, + "RDT0R": { + "description": "mailbox data high register", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "FMI": { + "description": "FMI", + "offset": 8, + "size": 8 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "RDL0R": { + "description": "mailbox data high register", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "RDH0R": { + "description": "receive FIFO mailbox data high\n register", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "RI1R": { + "description": "mailbox data high register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STID": { + "description": "STID", + "offset": 21, + "size": 11 + }, + "EXID": { + "description": "EXID", + "offset": 3, + "size": 18 + }, + "IDE": { + "description": "IDE", + "offset": 2, + "size": 1 + }, + "RTR": { + "description": "RTR", + "offset": 1, + "size": 1 + } + } + } + }, + "RDT1R": { + "description": "mailbox data high register", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TIME": { + "description": "TIME", + "offset": 16, + "size": 16 + }, + "FMI": { + "description": "FMI", + "offset": 8, + "size": 8 + }, + "DLC": { + "description": "DLC", + "offset": 0, + "size": 4 + } + } + } + }, + "RDL1R": { + "description": "mailbox data high register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA3": { + "description": "DATA3", + "offset": 24, + "size": 8 + }, + "DATA2": { + "description": "DATA2", + "offset": 16, + "size": 8 + }, + "DATA1": { + "description": "DATA1", + "offset": 8, + "size": 8 + }, + "DATA0": { + "description": "DATA0", + "offset": 0, + "size": 8 + } + } + } + }, + "RDH1R": { + "description": "mailbox data high register", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA7": { + "description": "DATA7", + "offset": 24, + "size": 8 + }, + "DATA6": { + "description": "DATA6", + "offset": 16, + "size": 8 + }, + "DATA5": { + "description": "DATA5", + "offset": 8, + "size": 8 + }, + "DATA4": { + "description": "DATA4", + "offset": 0, + "size": 8 + } + } + } + }, + "FMR": { + "description": "filter master register", + "offset": 512, + "size": 32, + "reset_value": 706481665, + "reset_mask": 4294967295, + "children": { + "fields": { + "CAN2SB": { + "description": "CAN2SB", + "offset": 8, + "size": 6 + }, + "FINIT": { + "description": "FINIT", + "offset": 0, + "size": 1 + } + } + } + }, + "FM1R": { + "description": "filter mode register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FBM0": { + "description": "Filter mode", + "offset": 0, + "size": 1 + }, + "FBM1": { + "description": "Filter mode", + "offset": 1, + "size": 1 + }, + "FBM2": { + "description": "Filter mode", + "offset": 2, + "size": 1 + }, + "FBM3": { + "description": "Filter mode", + "offset": 3, + "size": 1 + }, + "FBM4": { + "description": "Filter mode", + "offset": 4, + "size": 1 + }, + "FBM5": { + "description": "Filter mode", + "offset": 5, + "size": 1 + }, + "FBM6": { + "description": "Filter mode", + "offset": 6, + "size": 1 + }, + "FBM7": { + "description": "Filter mode", + "offset": 7, + "size": 1 + }, + "FBM8": { + "description": "Filter mode", + "offset": 8, + "size": 1 + }, + "FBM9": { + "description": "Filter mode", + "offset": 9, + "size": 1 + }, + "FBM10": { + "description": "Filter mode", + "offset": 10, + "size": 1 + }, + "FBM11": { + "description": "Filter mode", + "offset": 11, + "size": 1 + }, + "FBM12": { + "description": "Filter mode", + "offset": 12, + "size": 1 + }, + "FBM13": { + "description": "Filter mode", + "offset": 13, + "size": 1 + }, + "FBM14": { + "description": "Filter mode", + "offset": 14, + "size": 1 + }, + "FBM15": { + "description": "Filter mode", + "offset": 15, + "size": 1 + }, + "FBM16": { + "description": "Filter mode", + "offset": 16, + "size": 1 + }, + "FBM17": { + "description": "Filter mode", + "offset": 17, + "size": 1 + }, + "FBM18": { + "description": "Filter mode", + "offset": 18, + "size": 1 + }, + "FBM19": { + "description": "Filter mode", + "offset": 19, + "size": 1 + }, + "FBM20": { + "description": "Filter mode", + "offset": 20, + "size": 1 + }, + "FBM21": { + "description": "Filter mode", + "offset": 21, + "size": 1 + }, + "FBM22": { + "description": "Filter mode", + "offset": 22, + "size": 1 + }, + "FBM23": { + "description": "Filter mode", + "offset": 23, + "size": 1 + }, + "FBM24": { + "description": "Filter mode", + "offset": 24, + "size": 1 + }, + "FBM25": { + "description": "Filter mode", + "offset": 25, + "size": 1 + }, + "FBM26": { + "description": "Filter mode", + "offset": 26, + "size": 1 + }, + "FBM27": { + "description": "Filter mode", + "offset": 27, + "size": 1 + } + } + } + }, + "FS1R": { + "description": "filter scale register", + "offset": 524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSC0": { + "description": "Filter scale configuration", + "offset": 0, + "size": 1 + }, + "FSC1": { + "description": "Filter scale configuration", + "offset": 1, + "size": 1 + }, + "FSC2": { + "description": "Filter scale configuration", + "offset": 2, + "size": 1 + }, + "FSC3": { + "description": "Filter scale configuration", + "offset": 3, + "size": 1 + }, + "FSC4": { + "description": "Filter scale configuration", + "offset": 4, + "size": 1 + }, + "FSC5": { + "description": "Filter scale configuration", + "offset": 5, + "size": 1 + }, + "FSC6": { + "description": "Filter scale configuration", + "offset": 6, + "size": 1 + }, + "FSC7": { + "description": "Filter scale configuration", + "offset": 7, + "size": 1 + }, + "FSC8": { + "description": "Filter scale configuration", + "offset": 8, + "size": 1 + }, + "FSC9": { + "description": "Filter scale configuration", + "offset": 9, + "size": 1 + }, + "FSC10": { + "description": "Filter scale configuration", + "offset": 10, + "size": 1 + }, + "FSC11": { + "description": "Filter scale configuration", + "offset": 11, + "size": 1 + }, + "FSC12": { + "description": "Filter scale configuration", + "offset": 12, + "size": 1 + }, + "FSC13": { + "description": "Filter scale configuration", + "offset": 13, + "size": 1 + }, + "FSC14": { + "description": "Filter scale configuration", + "offset": 14, + "size": 1 + }, + "FSC15": { + "description": "Filter scale configuration", + "offset": 15, + "size": 1 + }, + "FSC16": { + "description": "Filter scale configuration", + "offset": 16, + "size": 1 + }, + "FSC17": { + "description": "Filter scale configuration", + "offset": 17, + "size": 1 + }, + "FSC18": { + "description": "Filter scale configuration", + "offset": 18, + "size": 1 + }, + "FSC19": { + "description": "Filter scale configuration", + "offset": 19, + "size": 1 + }, + "FSC20": { + "description": "Filter scale configuration", + "offset": 20, + "size": 1 + }, + "FSC21": { + "description": "Filter scale configuration", + "offset": 21, + "size": 1 + }, + "FSC22": { + "description": "Filter scale configuration", + "offset": 22, + "size": 1 + }, + "FSC23": { + "description": "Filter scale configuration", + "offset": 23, + "size": 1 + }, + "FSC24": { + "description": "Filter scale configuration", + "offset": 24, + "size": 1 + }, + "FSC25": { + "description": "Filter scale configuration", + "offset": 25, + "size": 1 + }, + "FSC26": { + "description": "Filter scale configuration", + "offset": 26, + "size": 1 + }, + "FSC27": { + "description": "Filter scale configuration", + "offset": 27, + "size": 1 + } + } + } + }, + "FFA1R": { + "description": "filter FIFO assignment\n register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FFA0": { + "description": "Filter FIFO assignment for filter\n 0", + "offset": 0, + "size": 1 + }, + "FFA1": { + "description": "Filter FIFO assignment for filter\n 1", + "offset": 1, + "size": 1 + }, + "FFA2": { + "description": "Filter FIFO assignment for filter\n 2", + "offset": 2, + "size": 1 + }, + "FFA3": { + "description": "Filter FIFO assignment for filter\n 3", + "offset": 3, + "size": 1 + }, + "FFA4": { + "description": "Filter FIFO assignment for filter\n 4", + "offset": 4, + "size": 1 + }, + "FFA5": { + "description": "Filter FIFO assignment for filter\n 5", + "offset": 5, + "size": 1 + }, + "FFA6": { + "description": "Filter FIFO assignment for filter\n 6", + "offset": 6, + "size": 1 + }, + "FFA7": { + "description": "Filter FIFO assignment for filter\n 7", + "offset": 7, + "size": 1 + }, + "FFA8": { + "description": "Filter FIFO assignment for filter\n 8", + "offset": 8, + "size": 1 + }, + "FFA9": { + "description": "Filter FIFO assignment for filter\n 9", + "offset": 9, + "size": 1 + }, + "FFA10": { + "description": "Filter FIFO assignment for filter\n 10", + "offset": 10, + "size": 1 + }, + "FFA11": { + "description": "Filter FIFO assignment for filter\n 11", + "offset": 11, + "size": 1 + }, + "FFA12": { + "description": "Filter FIFO assignment for filter\n 12", + "offset": 12, + "size": 1 + }, + "FFA13": { + "description": "Filter FIFO assignment for filter\n 13", + "offset": 13, + "size": 1 + }, + "FFA14": { + "description": "Filter FIFO assignment for filter\n 14", + "offset": 14, + "size": 1 + }, + "FFA15": { + "description": "Filter FIFO assignment for filter\n 15", + "offset": 15, + "size": 1 + }, + "FFA16": { + "description": "Filter FIFO assignment for filter\n 16", + "offset": 16, + "size": 1 + }, + "FFA17": { + "description": "Filter FIFO assignment for filter\n 17", + "offset": 17, + "size": 1 + }, + "FFA18": { + "description": "Filter FIFO assignment for filter\n 18", + "offset": 18, + "size": 1 + }, + "FFA19": { + "description": "Filter FIFO assignment for filter\n 19", + "offset": 19, + "size": 1 + }, + "FFA20": { + "description": "Filter FIFO assignment for filter\n 20", + "offset": 20, + "size": 1 + }, + "FFA21": { + "description": "Filter FIFO assignment for filter\n 21", + "offset": 21, + "size": 1 + }, + "FFA22": { + "description": "Filter FIFO assignment for filter\n 22", + "offset": 22, + "size": 1 + }, + "FFA23": { + "description": "Filter FIFO assignment for filter\n 23", + "offset": 23, + "size": 1 + }, + "FFA24": { + "description": "Filter FIFO assignment for filter\n 24", + "offset": 24, + "size": 1 + }, + "FFA25": { + "description": "Filter FIFO assignment for filter\n 25", + "offset": 25, + "size": 1 + }, + "FFA26": { + "description": "Filter FIFO assignment for filter\n 26", + "offset": 26, + "size": 1 + }, + "FFA27": { + "description": "Filter FIFO assignment for filter\n 27", + "offset": 27, + "size": 1 + } + } + } + }, + "FA1R": { + "description": "filter activation register", + "offset": 540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FACT0": { + "description": "Filter active", + "offset": 0, + "size": 1 + }, + "FACT1": { + "description": "Filter active", + "offset": 1, + "size": 1 + }, + "FACT2": { + "description": "Filter active", + "offset": 2, + "size": 1 + }, + "FACT3": { + "description": "Filter active", + "offset": 3, + "size": 1 + }, + "FACT4": { + "description": "Filter active", + "offset": 4, + "size": 1 + }, + "FACT5": { + "description": "Filter active", + "offset": 5, + "size": 1 + }, + "FACT6": { + "description": "Filter active", + "offset": 6, + "size": 1 + }, + "FACT7": { + "description": "Filter active", + "offset": 7, + "size": 1 + }, + "FACT8": { + "description": "Filter active", + "offset": 8, + "size": 1 + }, + "FACT9": { + "description": "Filter active", + "offset": 9, + "size": 1 + }, + "FACT10": { + "description": "Filter active", + "offset": 10, + "size": 1 + }, + "FACT11": { + "description": "Filter active", + "offset": 11, + "size": 1 + }, + "FACT12": { + "description": "Filter active", + "offset": 12, + "size": 1 + }, + "FACT13": { + "description": "Filter active", + "offset": 13, + "size": 1 + }, + "FACT14": { + "description": "Filter active", + "offset": 14, + "size": 1 + }, + "FACT15": { + "description": "Filter active", + "offset": 15, + "size": 1 + }, + "FACT16": { + "description": "Filter active", + "offset": 16, + "size": 1 + }, + "FACT17": { + "description": "Filter active", + "offset": 17, + "size": 1 + }, + "FACT18": { + "description": "Filter active", + "offset": 18, + "size": 1 + }, + "FACT19": { + "description": "Filter active", + "offset": 19, + "size": 1 + }, + "FACT20": { + "description": "Filter active", + "offset": 20, + "size": 1 + }, + "FACT21": { + "description": "Filter active", + "offset": 21, + "size": 1 + }, + "FACT22": { + "description": "Filter active", + "offset": 22, + "size": 1 + }, + "FACT23": { + "description": "Filter active", + "offset": 23, + "size": 1 + }, + "FACT24": { + "description": "Filter active", + "offset": 24, + "size": 1 + }, + "FACT25": { + "description": "Filter active", + "offset": 25, + "size": 1 + }, + "FACT26": { + "description": "Filter active", + "offset": 26, + "size": 1 + }, + "FACT27": { + "description": "Filter active", + "offset": 27, + "size": 1 + } + } + } + }, + "F0R1": { + "description": "Filter bank 0 register 1", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F0R2": { + "description": "Filter bank 0 register 2", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R1": { + "description": "Filter bank 1 register 1", + "offset": 584, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F1R2": { + "description": "Filter bank 1 register 2", + "offset": 588, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R1": { + "description": "Filter bank 2 register 1", + "offset": 592, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F2R2": { + "description": "Filter bank 2 register 2", + "offset": 596, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R1": { + "description": "Filter bank 3 register 1", + "offset": 600, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F3R2": { + "description": "Filter bank 3 register 2", + "offset": 604, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R1": { + "description": "Filter bank 4 register 1", + "offset": 608, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F4R2": { + "description": "Filter bank 4 register 2", + "offset": 612, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R1": { + "description": "Filter bank 5 register 1", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5R2": { + "description": "Filter bank 5 register 2", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R1": { + "description": "Filter bank 6 register 1", + "offset": 624, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F6R2": { + "description": "Filter bank 6 register 2", + "offset": 628, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R1": { + "description": "Filter bank 7 register 1", + "offset": 632, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F7R2": { + "description": "Filter bank 7 register 2", + "offset": 636, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R1": { + "description": "Filter bank 8 register 1", + "offset": 640, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F8R2": { + "description": "Filter bank 8 register 2", + "offset": 644, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R1": { + "description": "Filter bank 9 register 1", + "offset": 648, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F9R2": { + "description": "Filter bank 9 register 2", + "offset": 652, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R1": { + "description": "Filter bank 10 register 1", + "offset": 656, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F10R2": { + "description": "Filter bank 10 register 2", + "offset": 660, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R1": { + "description": "Filter bank 11 register 1", + "offset": 664, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F11R2": { + "description": "Filter bank 11 register 2", + "offset": 668, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R1": { + "description": "Filter bank 4 register 1", + "offset": 672, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F12R2": { + "description": "Filter bank 12 register 2", + "offset": 676, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R1": { + "description": "Filter bank 13 register 1", + "offset": 680, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13R2": { + "description": "Filter bank 13 register 2", + "offset": 684, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R1": { + "description": "Filter bank 14 register 1", + "offset": 688, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14R2": { + "description": "Filter bank 14 register 2", + "offset": 692, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R1": { + "description": "Filter bank 15 register 1", + "offset": 696, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15R2": { + "description": "Filter bank 15 register 2", + "offset": 700, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R1": { + "description": "Filter bank 16 register 1", + "offset": 704, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F16R2": { + "description": "Filter bank 16 register 2", + "offset": 708, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R1": { + "description": "Filter bank 17 register 1", + "offset": 712, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17R2": { + "description": "Filter bank 17 register 2", + "offset": 716, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R1": { + "description": "Filter bank 18 register 1", + "offset": 720, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18R2": { + "description": "Filter bank 18 register 2", + "offset": 724, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R1": { + "description": "Filter bank 19 register 1", + "offset": 728, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19R2": { + "description": "Filter bank 19 register 2", + "offset": 732, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R1": { + "description": "Filter bank 20 register 1", + "offset": 736, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20R2": { + "description": "Filter bank 20 register 2", + "offset": 740, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R1": { + "description": "Filter bank 21 register 1", + "offset": 744, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F21R2": { + "description": "Filter bank 21 register 2", + "offset": 748, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R1": { + "description": "Filter bank 22 register 1", + "offset": 752, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F22R2": { + "description": "Filter bank 22 register 2", + "offset": 756, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R1": { + "description": "Filter bank 23 register 1", + "offset": 760, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F23R2": { + "description": "Filter bank 23 register 2", + "offset": 764, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R1": { + "description": "Filter bank 24 register 1", + "offset": 768, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24R2": { + "description": "Filter bank 24 register 2", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R1": { + "description": "Filter bank 25 register 1", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25R2": { + "description": "Filter bank 25 register 2", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R1": { + "description": "Filter bank 26 register 1", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26R2": { + "description": "Filter bank 26 register 2", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R1": { + "description": "Filter bank 27 register 1", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27R2": { + "description": "Filter bank 27 register 2", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FB0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FB1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FB2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FB3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FB4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FB5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FB6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FB7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FB8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FB9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FB10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FB11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FB12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FB13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FB14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FB15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FB16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FB17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FB18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FB19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FB20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FB21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FB22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FB23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FB24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FB25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FB26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FB27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FB28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FB29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FB30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FB31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_PCGCCTL": { + "description": "OTG_FS power and clock gating control\n register (OTG_FS_PCGCCTL)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPPCLK": { + "description": "Stop PHY clock", + "offset": 0, + "size": 1 + }, + "GATEHCLK": { + "description": "Gate HCLK", + "offset": 1, + "size": 1 + }, + "PHYSUSP": { + "description": "PHY Suspended", + "offset": 4, + "size": 1 + } + } + } + } + } + } + }, + "DAC": { + "description": "Digital-to-analog converter", + "children": { + "registers": { + "CR": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDRIE2": { + "description": "DAC channel2 DMA underrun interrupt\n enable", + "offset": 29, + "size": 1 + }, + "DMAEN2": { + "description": "DAC channel2 DMA enable", + "offset": 28, + "size": 1 + }, + "MAMP2": { + "description": "DAC channel2 mask/amplitude\n selector", + "offset": 24, + "size": 4 + }, + "WAVE2": { + "description": "DAC channel2 noise/triangle wave\n generation enable", + "offset": 22, + "size": 2 + }, + "TSEL2": { + "description": "DAC channel2 trigger\n selection", + "offset": 19, + "size": 3 + }, + "TEN2": { + "description": "DAC channel2 trigger\n enable", + "offset": 18, + "size": 1 + }, + "BOFF2": { + "description": "DAC channel2 output buffer\n disable", + "offset": 17, + "size": 1 + }, + "EN2": { + "description": "DAC channel2 enable", + "offset": 16, + "size": 1 + }, + "DMAUDRIE1": { + "description": "DAC channel1 DMA Underrun Interrupt\n enable", + "offset": 13, + "size": 1 + }, + "DMAEN1": { + "description": "DAC channel1 DMA enable", + "offset": 12, + "size": 1 + }, + "MAMP1": { + "description": "DAC channel1 mask/amplitude\n selector", + "offset": 8, + "size": 4 + }, + "WAVE1": { + "description": "DAC channel1 noise/triangle wave\n generation enable", + "offset": 6, + "size": 2 + }, + "TSEL1": { + "description": "DAC channel1 trigger\n selection", + "offset": 3, + "size": 3 + }, + "TEN1": { + "description": "DAC channel1 trigger\n enable", + "offset": 2, + "size": 1 + }, + "BOFF1": { + "description": "DAC channel1 output buffer\n disable", + "offset": 1, + "size": 1 + }, + "EN1": { + "description": "DAC channel1 enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SWTRIGR": { + "description": "software trigger register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SWTRIG2": { + "description": "DAC channel2 software\n trigger", + "offset": 1, + "size": 1 + }, + "SWTRIG1": { + "description": "DAC channel1 software\n trigger", + "offset": 0, + "size": 1 + } + } + } + }, + "DHR12R1": { + "description": "channel1 12-bit right-aligned data holding\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L1": { + "description": "channel1 12-bit left aligned data holding\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R1": { + "description": "channel1 8-bit right aligned data holding\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12R2": { + "description": "channel2 12-bit right aligned data holding\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12L2": { + "description": "channel2 12-bit left aligned data holding\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8R2": { + "description": "channel2 8-bit right-aligned data holding\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DHR12RD": { + "description": "Dual DAC 12-bit right-aligned data holding\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit right-aligned\n data", + "offset": 16, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DHR12LD": { + "description": "DUAL DAC 12-bit left aligned data holding\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 12-bit left-aligned\n data", + "offset": 20, + "size": 12 + }, + "DACC1DHR": { + "description": "DAC channel1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DHR8RD": { + "description": "DUAL DAC 8-bit right aligned data holding\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DACC2DHR": { + "description": "DAC channel2 8-bit right-aligned\n data", + "offset": 8, + "size": 8 + }, + "DACC1DHR": { + "description": "DAC channel1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DOR1": { + "description": "channel1 data output register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC1DOR": { + "description": "DAC channel1 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "DOR2": { + "description": "channel2 data output register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DACC2DOR": { + "description": "DAC channel2 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAUDR2": { + "description": "DAC channel2 DMA underrun\n flag", + "offset": 29, + "size": 1 + }, + "DMAUDR1": { + "description": "DAC channel1 DMA underrun\n flag", + "offset": 13, + "size": 1 + } + } + } + } + } + } + }, + "PWR": { + "description": "Power control", + "children": { + "registers": { + "CR": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 49152, + "reset_mask": 4294967295, + "children": { + "fields": { + "LPDS": { + "description": "Low-power deep sleep", + "offset": 0, + "size": 1 + }, + "PDDS": { + "description": "Power down deepsleep", + "offset": 1, + "size": 1 + }, + "CWUF": { + "description": "Clear wakeup flag", + "offset": 2, + "size": 1 + }, + "CSBF": { + "description": "Clear standby flag", + "offset": 3, + "size": 1 + }, + "PVDE": { + "description": "Power voltage detector\n enable", + "offset": 4, + "size": 1 + }, + "PLS": { + "description": "PVD level selection", + "offset": 5, + "size": 3 + }, + "DBP": { + "description": "Disable backup domain write\n protection", + "offset": 8, + "size": 1 + }, + "FPDS": { + "description": "Flash power down in Stop\n mode", + "offset": 9, + "size": 1 + }, + "LPLVDS": { + "description": "Low-Power Regulator Low Voltage in\n deepsleep", + "offset": 10, + "size": 1 + }, + "MRLVDS": { + "description": "Main regulator low voltage in deepsleep\n mode", + "offset": 11, + "size": 1 + }, + "VOS": { + "description": "Regulator voltage scaling output\n selection", + "offset": 14, + "size": 2 + }, + "ODEN": { + "description": "Over-drive enable", + "offset": 16, + "size": 1 + }, + "ODSWEN": { + "description": "Over-drive switching\n enabled", + "offset": 17, + "size": 1 + }, + "UDEN": { + "description": "Under-drive enable in stop\n mode", + "offset": 18, + "size": 2 + } + } + } + }, + "CSR": { + "description": "power control/status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUF": { + "description": "Wakeup flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SBF": { + "description": "Standby flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PVDO": { + "description": "PVD output", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "BRR": { + "description": "Backup regulator ready", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "EWUP": { + "description": "Enable WKUP pin", + "offset": 8, + "size": 1 + }, + "BRE": { + "description": "Backup regulator enable", + "offset": 9, + "size": 1 + }, + "VOSRDY": { + "description": "Regulator voltage scaling output\n selection ready bit", + "offset": 14, + "size": 1 + }, + "ODRDY": { + "description": "Over-drive mode ready", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "ODSWRDY": { + "description": "Over-drive mode switching\n ready", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "UDRDY": { + "description": "Under-drive ready flag", + "offset": 18, + "size": 2 + } + } + } + } + } + } + }, + "IWDG": { + "description": "Independent watchdog", + "children": { + "registers": { + "KR": { + "description": "Key register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Key value (write only, read\n 0000h)", + "offset": 0, + "size": 16 + } + } + } + }, + "PR": { + "description": "Prescaler register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PR": { + "description": "Prescaler divider", + "offset": 0, + "size": 3 + } + } + } + }, + "RLR": { + "description": "Reload register", + "offset": 8, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Watchdog counter reload\n value", + "offset": 0, + "size": 12 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RVU": { + "description": "Watchdog counter reload value\n update", + "offset": 1, + "size": 1 + }, + "PVU": { + "description": "Watchdog prescaler value\n update", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "WWDG": { + "description": "Window watchdog", + "children": { + "registers": { + "CR": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDGA": { + "description": "Activation bit", + "offset": 7, + "size": 1 + }, + "T": { + "description": "7-bit counter (MSB to LSB)", + "offset": 0, + "size": 7 + } + } + } + }, + "CFR": { + "description": "Configuration register", + "offset": 4, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWI": { + "description": "Early wakeup interrupt", + "offset": 9, + "size": 1 + }, + "WDGTB1": { + "description": "Timer base", + "offset": 8, + "size": 1 + }, + "WDGTB0": { + "description": "Timer base", + "offset": 7, + "size": 1 + }, + "W": { + "description": "7-bit window value", + "offset": 0, + "size": 7 + } + } + } + }, + "SR": { + "description": "Status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWIF": { + "description": "Early wakeup interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "RTC": { + "description": "Real-time clock", + "children": { + "registers": { + "TR": { + "description": "time register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "DR": { + "description": "date register", + "offset": 4, + "size": 32, + "reset_value": 8449, + "reset_mask": 4294967295, + "children": { + "fields": { + "YT": { + "description": "Year tens in BCD format", + "offset": 20, + "size": 4 + }, + "YU": { + "description": "Year units in BCD format", + "offset": 16, + "size": 4 + }, + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "CR": { + "description": "control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "COE": { + "description": "Calibration output enable", + "offset": 23, + "size": 1 + }, + "OSEL": { + "description": "Output selection", + "offset": 21, + "size": 2 + }, + "POL": { + "description": "Output polarity", + "offset": 20, + "size": 1 + }, + "BKP": { + "description": "Backup", + "offset": 18, + "size": 1 + }, + "SUB1H": { + "description": "Subtract 1 hour (winter time\n change)", + "offset": 17, + "size": 1 + }, + "ADD1H": { + "description": "Add 1 hour (summer time\n change)", + "offset": 16, + "size": 1 + }, + "TSIE": { + "description": "Time-stamp interrupt\n enable", + "offset": 15, + "size": 1 + }, + "WUTIE": { + "description": "Wakeup timer interrupt\n enable", + "offset": 14, + "size": 1 + }, + "ALRBIE": { + "description": "Alarm B interrupt enable", + "offset": 13, + "size": 1 + }, + "ALRAIE": { + "description": "Alarm A interrupt enable", + "offset": 12, + "size": 1 + }, + "TSE": { + "description": "Time stamp enable", + "offset": 11, + "size": 1 + }, + "WUTE": { + "description": "Wakeup timer enable", + "offset": 10, + "size": 1 + }, + "ALRBE": { + "description": "Alarm B enable", + "offset": 9, + "size": 1 + }, + "ALRAE": { + "description": "Alarm A enable", + "offset": 8, + "size": 1 + }, + "DCE": { + "description": "Coarse digital calibration\n enable", + "offset": 7, + "size": 1 + }, + "FMT": { + "description": "Hour format", + "offset": 6, + "size": 1 + }, + "REFCKON": { + "description": "Reference clock detection enable (50 or\n 60 Hz)", + "offset": 4, + "size": 1 + }, + "TSEDGE": { + "description": "Time-stamp event active\n edge", + "offset": 3, + "size": 1 + }, + "WCKSEL": { + "description": "Wakeup clock selection", + "offset": 0, + "size": 3 + } + } + } + }, + "ISR": { + "description": "initialization and status\n register", + "offset": 12, + "size": 32, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALRAWF": { + "description": "Alarm A write flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "ALRBWF": { + "description": "Alarm B write flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "WUTWF": { + "description": "Wakeup timer write flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SHPF": { + "description": "Shift operation pending", + "offset": 3, + "size": 1 + }, + "INITS": { + "description": "Initialization status flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "RSF": { + "description": "Registers synchronization\n flag", + "offset": 5, + "size": 1 + }, + "INITF": { + "description": "Initialization flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "INIT": { + "description": "Initialization mode", + "offset": 7, + "size": 1 + }, + "ALRAF": { + "description": "Alarm A flag", + "offset": 8, + "size": 1 + }, + "ALRBF": { + "description": "Alarm B flag", + "offset": 9, + "size": 1 + }, + "WUTF": { + "description": "Wakeup timer flag", + "offset": 10, + "size": 1 + }, + "TSF": { + "description": "Time-stamp flag", + "offset": 11, + "size": 1 + }, + "TSOVF": { + "description": "Time-stamp overflow flag", + "offset": 12, + "size": 1 + }, + "TAMP1F": { + "description": "Tamper detection flag", + "offset": 13, + "size": 1 + }, + "TAMP2F": { + "description": "TAMPER2 detection flag", + "offset": 14, + "size": 1 + }, + "RECALPF": { + "description": "Recalibration pending Flag", + "offset": 16, + "size": 1, + "access": "read-only" + } + } + } + }, + "PRER": { + "description": "prescaler register", + "offset": 16, + "size": 32, + "reset_value": 8323327, + "reset_mask": 4294967295, + "children": { + "fields": { + "PREDIV_A": { + "description": "Asynchronous prescaler\n factor", + "offset": 16, + "size": 7 + }, + "PREDIV_S": { + "description": "Synchronous prescaler\n factor", + "offset": 0, + "size": 15 + } + } + } + }, + "WUTR": { + "description": "wakeup timer register", + "offset": 20, + "size": 32, + "reset_value": 65535, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUT": { + "description": "Wakeup auto-reload value\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "CALIBR": { + "description": "calibration register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DCS": { + "description": "Digital calibration sign", + "offset": 7, + "size": 1 + }, + "DC": { + "description": "Digital calibration", + "offset": 0, + "size": 5 + } + } + } + }, + "ALRMAR": { + "description": "alarm A register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm A date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm A hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm A minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm A seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "ALRMBR": { + "description": "alarm B register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSK4": { + "description": "Alarm B date mask", + "offset": 31, + "size": 1 + }, + "WDSEL": { + "description": "Week day selection", + "offset": 30, + "size": 1 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 28, + "size": 2 + }, + "DU": { + "description": "Date units or day in BCD\n format", + "offset": 24, + "size": 4 + }, + "MSK3": { + "description": "Alarm B hours mask", + "offset": 23, + "size": 1 + }, + "PM": { + "description": "AM/PM notation", + "offset": 22, + "size": 1 + }, + "HT": { + "description": "Hour tens in BCD format", + "offset": 20, + "size": 2 + }, + "HU": { + "description": "Hour units in BCD format", + "offset": 16, + "size": 4 + }, + "MSK2": { + "description": "Alarm B minutes mask", + "offset": 15, + "size": 1 + }, + "MNT": { + "description": "Minute tens in BCD format", + "offset": 12, + "size": 3 + }, + "MNU": { + "description": "Minute units in BCD format", + "offset": 8, + "size": 4 + }, + "MSK1": { + "description": "Alarm B seconds mask", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "Second tens in BCD format", + "offset": 4, + "size": 3 + }, + "SU": { + "description": "Second units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "WPR": { + "description": "write protection register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "Write protection key", + "offset": 0, + "size": 8 + } + } + } + }, + "SSR": { + "description": "sub second register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "SHIFTR": { + "description": "shift control register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ADD1S": { + "description": "Add one second", + "offset": 31, + "size": 1 + }, + "SUBFS": { + "description": "Subtract a fraction of a\n second", + "offset": 0, + "size": 15 + } + } + } + }, + "TSTR": { + "description": "time stamp time register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ALARMOUTTYPE": { + "description": "AFO_ALARM output type", + "offset": 18, + "size": 1 + }, + "TSINSEL": { + "description": "TIMESTAMP mapping", + "offset": 17, + "size": 1 + }, + "TAMP1INSEL": { + "description": "TAMPER1 mapping", + "offset": 16, + "size": 1 + }, + "TAMPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TAMP1TRG": { + "description": "Active level for tamper 1", + "offset": 1, + "size": 1 + }, + "TAMP1E": { + "description": "Tamper 1 detection enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TSDR": { + "description": "time stamp date register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WDU": { + "description": "Week day units", + "offset": 13, + "size": 3 + }, + "MT": { + "description": "Month tens in BCD format", + "offset": 12, + "size": 1 + }, + "MU": { + "description": "Month units in BCD format", + "offset": 8, + "size": 4 + }, + "DT": { + "description": "Date tens in BCD format", + "offset": 4, + "size": 2 + }, + "DU": { + "description": "Date units in BCD format", + "offset": 0, + "size": 4 + } + } + } + }, + "TSSSR": { + "description": "timestamp sub second register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SS": { + "description": "Sub second value", + "offset": 0, + "size": 16 + } + } + } + }, + "CALR": { + "description": "calibration register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CALP": { + "description": "Increase frequency of RTC by 488.5\n ppm", + "offset": 15, + "size": 1 + }, + "CALW8": { + "description": "Use an 8-second calibration cycle\n period", + "offset": 14, + "size": 1 + }, + "CALW16": { + "description": "Use a 16-second calibration cycle\n period", + "offset": 13, + "size": 1 + }, + "CALM": { + "description": "Calibration minus", + "offset": 0, + "size": 9 + } + } + } + }, + "TAFCR": { + "description": "tamper and alternate function configuration\n register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ALARMOUTTYPE": { + "description": "AFO_ALARM output type", + "offset": 18, + "size": 1 + }, + "TSINSEL": { + "description": "TIMESTAMP mapping", + "offset": 17, + "size": 1 + }, + "TAMP1INSEL": { + "description": "TAMPER1 mapping", + "offset": 16, + "size": 1 + }, + "TAMPPUDIS": { + "description": "TAMPER pull-up disable", + "offset": 15, + "size": 1 + }, + "TAMPPRCH": { + "description": "Tamper precharge duration", + "offset": 13, + "size": 2 + }, + "TAMPFLT": { + "description": "Tamper filter count", + "offset": 11, + "size": 2 + }, + "TAMPFREQ": { + "description": "Tamper sampling frequency", + "offset": 8, + "size": 3 + }, + "TAMPTS": { + "description": "Activate timestamp on tamper detection\n event", + "offset": 7, + "size": 1 + }, + "TAMP2TRG": { + "description": "Active level for tamper 2", + "offset": 4, + "size": 1 + }, + "TAMP2E": { + "description": "Tamper 2 detection enable", + "offset": 3, + "size": 1 + }, + "TAMPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TAMP1TRG": { + "description": "Active level for tamper 1", + "offset": 1, + "size": 1 + }, + "TAMP1E": { + "description": "Tamper 1 detection enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ALRMASSR": { + "description": "alarm A sub second register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "ALRMBSSR": { + "description": "alarm B sub second register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MASKSS": { + "description": "Mask the most-significant bits starting\n at this bit", + "offset": 24, + "size": 4 + }, + "SS": { + "description": "Sub seconds value", + "offset": 0, + "size": 15 + } + } + } + }, + "BKP0R": { + "description": "backup register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP1R": { + "description": "backup register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP2R": { + "description": "backup register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP3R": { + "description": "backup register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP4R": { + "description": "backup register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP5R": { + "description": "backup register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP6R": { + "description": "backup register", + "offset": 104, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP7R": { + "description": "backup register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP8R": { + "description": "backup register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP9R": { + "description": "backup register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP10R": { + "description": "backup register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP11R": { + "description": "backup register", + "offset": 124, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP12R": { + "description": "backup register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP13R": { + "description": "backup register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP14R": { + "description": "backup register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP15R": { + "description": "backup register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP16R": { + "description": "backup register", + "offset": 144, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP17R": { + "description": "backup register", + "offset": 148, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP18R": { + "description": "backup register", + "offset": 152, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + }, + "BKP19R": { + "description": "backup register", + "offset": 156, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKP": { + "description": "BKP", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "UART4": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "SR": { + "description": "Status register", + "offset": 0, + "size": 32, + "reset_value": 12582912, + "reset_mask": 4294967295, + "children": { + "fields": { + "LBD": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TXE": { + "description": "Transmit data register\n empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RXNE": { + "description": "Read data register not\n empty", + "offset": 5, + "size": 1 + }, + "IDLE": { + "description": "IDLE line detected", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORE": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NF": { + "description": "Noise detected flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FE": { + "description": "Framing error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PE": { + "description": "Parity error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DR": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BRR": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DIV_Mantissa": { + "description": "mantissa of USARTDIV", + "offset": 4, + "size": 12 + }, + "DIV_Fraction": { + "description": "fraction of USARTDIV", + "offset": 0, + "size": 4 + } + } + } + }, + "CR1": { + "description": "Control register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVER8": { + "description": "Oversampling mode", + "offset": 15, + "size": 1 + }, + "UE": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "M": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WAKE": { + "description": "Wakeup method", + "offset": 11, + "size": 1 + }, + "PCE": { + "description": "Parity control enable", + "offset": 10, + "size": 1 + }, + "PS": { + "description": "Parity selection", + "offset": 9, + "size": 1 + }, + "PEIE": { + "description": "PE interrupt enable", + "offset": 8, + "size": 1 + }, + "TXEIE": { + "description": "TXE interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt\n enable", + "offset": 6, + "size": 1 + }, + "RXNEIE": { + "description": "RXNE interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE interrupt enable", + "offset": 4, + "size": 1 + }, + "TE": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "RE": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup", + "offset": 1, + "size": 1 + }, + "SBK": { + "description": "Send break", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "Control register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LINEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STOP": { + "description": "STOP bits", + "offset": 12, + "size": 2 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBDL": { + "description": "lin break detection length", + "offset": 5, + "size": 1 + }, + "ADD": { + "description": "Address of the USART node", + "offset": 0, + "size": 4 + } + } + } + }, + "CR3": { + "description": "Control register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ONEBIT": { + "description": "One sample bit method\n enable", + "offset": 11, + "size": 1 + }, + "DMAT": { + "description": "DMA enable transmitter", + "offset": 7, + "size": 1 + }, + "DMAR": { + "description": "DMA enable receiver", + "offset": 6, + "size": 1 + }, + "HDSEL": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "EIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_DCFG": { + "description": "OTG_FS device configuration register\n (OTG_FS_DCFG)", + "offset": 0, + "size": 32, + "reset_value": 35651584, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSPD": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOHSK": { + "description": "Non-zero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAD": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "PFIVL": { + "description": "Periodic frame interval", + "offset": 11, + "size": 2 + } + } + } + }, + "FS_DCTL": { + "description": "OTG_FS device control register\n (OTG_FS_DCTL)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWUSIG": { + "description": "Remote wakeup signaling", + "offset": 0, + "size": 1 + }, + "SDIS": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINSTS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONSTS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "TCTL": { + "description": "Test control", + "offset": 4, + "size": 3 + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1 + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1 + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1 + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1 + }, + "POPRGDNE": { + "description": "Power-on programming done", + "offset": 11, + "size": 1 + } + } + } + }, + "FS_DSTS": { + "description": "OTG_FS device status register\n (OTG_FS_DSTS)", + "offset": 8, + "size": 32, + "reset_value": 16, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SUSPSTS": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ENUMSPD": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "EERR": { + "description": "Erratic error", + "offset": 3, + "size": 1 + }, + "FNSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "FS_DIEPMSK": { + "description": "OTG_FS device IN endpoint common interrupt\n mask register (OTG_FS_DIEPMSK)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "TOM": { + "description": "Timeout condition mask (Non-isochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "ITTXFEMSK": { + "description": "IN token received when TxFIFO empty\n mask", + "offset": 4, + "size": 1 + }, + "INEPNMM": { + "description": "IN token received with EP mismatch\n mask", + "offset": 5, + "size": 1 + }, + "INEPNEM": { + "description": "IN endpoint NAK effective\n mask", + "offset": 6, + "size": 1 + } + } + } + }, + "FS_DOEPMSK": { + "description": "OTG_FS device OUT endpoint common interrupt\n mask register (OTG_FS_DOEPMSK)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed interrupt\n mask", + "offset": 0, + "size": 1 + }, + "EPDM": { + "description": "Endpoint disabled interrupt\n mask", + "offset": 1, + "size": 1 + }, + "STUPM": { + "description": "SETUP phase done mask", + "offset": 3, + "size": 1 + }, + "OTEPDM": { + "description": "OUT token received when endpoint\n disabled mask", + "offset": 4, + "size": 1 + } + } + } + }, + "FS_DAINT": { + "description": "OTG_FS device all endpoints interrupt\n register (OTG_FS_DAINT)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPINT": { + "description": "IN endpoint interrupt bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DAINTMSK": { + "description": "OTG_FS all endpoints interrupt mask register\n (OTG_FS_DAINTMSK)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPM": { + "description": "IN EP interrupt mask bits", + "offset": 0, + "size": 16 + }, + "OEPINT": { + "description": "OUT endpoint interrupt\n bits", + "offset": 16, + "size": 16 + } + } + } + }, + "DVBUSDIS": { + "description": "OTG_FS device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "VBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "DVBUSPULSE": { + "description": "OTG_FS device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSP": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "DIEPEMPMSK": { + "description": "OTG_FS device IN endpoint FIFO empty\n interrupt mask register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXFEM": { + "description": "IN EP Tx FIFO empty interrupt mask\n bits", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_DIEPCTL0": { + "description": "OTG_FS device control IN endpoint 0 control\n register (OTG_FS_DIEPCTL0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 2 + }, + "USBAEP": { + "description": "USB active endpoint", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "EPENA": { + "description": "Endpoint enable", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "DIEPCTL1": { + "description": "OTG device endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM_SD1PID": { + "description": "SODDFRM/SD1PID", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL2": { + "description": "OTG device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPCTL3": { + "description": "OTG device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "TXFNUM", + "offset": 22, + "size": 4 + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL0": { + "description": "device endpoint-0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1, + "access": "write-only" + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "DOEPCTL1": { + "description": "device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL2": { + "description": "device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEPCTL3": { + "description": "device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPENA": { + "description": "EPENA", + "offset": 31, + "size": 1 + }, + "EPDIS": { + "description": "EPDIS", + "offset": 30, + "size": 1 + }, + "SODDFRM": { + "description": "SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVNFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "SNAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "CNAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "Stall": { + "description": "Stall", + "offset": 21, + "size": 1 + }, + "SNPM": { + "description": "SNPM", + "offset": 20, + "size": 1 + }, + "EPTYP": { + "description": "EPTYP", + "offset": 18, + "size": 2 + }, + "NAKSTS": { + "description": "NAKSTS", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EONUM_DPID": { + "description": "EONUM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "USBAEP": { + "description": "USBAEP", + "offset": 15, + "size": 1 + }, + "MPSIZ": { + "description": "MPSIZ", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEPINT0": { + "description": "device endpoint-x interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "TXFE", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "INEPNE": { + "description": "INEPNE", + "offset": 6, + "size": 1 + }, + "ITTXFE": { + "description": "ITTXFE", + "offset": 4, + "size": 1 + }, + "TOC": { + "description": "TOC", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT0": { + "description": "device endpoint-0 interrupt\n register", + "offset": 776, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT1": { + "description": "device endpoint-1 interrupt\n register", + "offset": 808, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT2": { + "description": "device endpoint-2 interrupt\n register", + "offset": 840, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEPINT3": { + "description": "device endpoint-3 interrupt\n register", + "offset": 872, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "B2BSTUP": { + "description": "B2BSTUP", + "offset": 6, + "size": 1 + }, + "OTEPDIS": { + "description": "OTEPDIS", + "offset": 4, + "size": 1 + }, + "STUP": { + "description": "STUP", + "offset": 3, + "size": 1 + }, + "EPDISD": { + "description": "EPDISD", + "offset": 1, + "size": 1 + }, + "XFRC": { + "description": "XFRC", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEPTSIZ0": { + "description": "device endpoint-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DOEPTSIZ0": { + "description": "device OUT endpoint-0 transfer size\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STUPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 7 + } + } + } + }, + "DIEPTSIZ1": { + "description": "device endpoint-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ2": { + "description": "device endpoint-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEPTSIZ3": { + "description": "device endpoint-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCNT": { + "description": "Multi count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DTXFSTS0": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS1": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS2": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DTXFSTS3": { + "description": "OTG_FS device IN endpoint transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "INEPTFSAV": { + "description": "IN endpoint TxFIFO space\n available", + "offset": 0, + "size": 16 + } + } + } + }, + "DOEPTSIZ1": { + "description": "device OUT endpoint-1 transfer size\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ2": { + "description": "device OUT endpoint-2 transfer size\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEPTSIZ3": { + "description": "device OUT endpoint-3 transfer size\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXDPID_STUPCNT": { + "description": "Received data PID/SETUP packet\n count", + "offset": 29, + "size": 2 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + } + } + } + } + } + } + }, + "C_ADC": { + "description": "Common ADC registers", + "children": { + "registers": { + "CSR": { + "description": "ADC Common status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OVR3": { + "description": "Overrun flag of ADC3", + "offset": 21, + "size": 1 + }, + "STRT3": { + "description": "Regular channel Start flag of ADC\n 3", + "offset": 20, + "size": 1 + }, + "JSTRT3": { + "description": "Injected channel Start flag of ADC\n 3", + "offset": 19, + "size": 1 + }, + "JEOC3": { + "description": "Injected channel end of conversion of\n ADC 3", + "offset": 18, + "size": 1 + }, + "EOC3": { + "description": "End of conversion of ADC 3", + "offset": 17, + "size": 1 + }, + "AWD3": { + "description": "Analog watchdog flag of ADC\n 3", + "offset": 16, + "size": 1 + }, + "OVR2": { + "description": "Overrun flag of ADC 2", + "offset": 13, + "size": 1 + }, + "STRT2": { + "description": "Regular channel Start flag of ADC\n 2", + "offset": 12, + "size": 1 + }, + "JSTRT2": { + "description": "Injected channel Start flag of ADC\n 2", + "offset": 11, + "size": 1 + }, + "JEOC2": { + "description": "Injected channel end of conversion of\n ADC 2", + "offset": 10, + "size": 1 + }, + "EOC2": { + "description": "End of conversion of ADC 2", + "offset": 9, + "size": 1 + }, + "AWD2": { + "description": "Analog watchdog flag of ADC\n 2", + "offset": 8, + "size": 1 + }, + "OVR1": { + "description": "Overrun flag of ADC 1", + "offset": 5, + "size": 1 + }, + "STRT1": { + "description": "Regular channel Start flag of ADC\n 1", + "offset": 4, + "size": 1 + }, + "JSTRT1": { + "description": "Injected channel Start flag of ADC\n 1", + "offset": 3, + "size": 1 + }, + "JEOC1": { + "description": "Injected channel end of conversion of\n ADC 1", + "offset": 2, + "size": 1 + }, + "EOC1": { + "description": "End of conversion of ADC 1", + "offset": 1, + "size": 1 + }, + "AWD1": { + "description": "Analog watchdog flag of ADC\n 1", + "offset": 0, + "size": 1 + } + } + } + }, + "CCR": { + "description": "ADC common control register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSVREFE": { + "description": "Temperature sensor and VREFINT\n enable", + "offset": 23, + "size": 1 + }, + "VBATE": { + "description": "VBAT enable", + "offset": 22, + "size": 1 + }, + "ADCPRE": { + "description": "ADC prescaler", + "offset": 16, + "size": 2 + }, + "DMA": { + "description": "Direct memory access mode for multi ADC\n mode", + "offset": 14, + "size": 2 + }, + "DDS": { + "description": "DMA disable selection for multi-ADC\n mode", + "offset": 13, + "size": 1 + }, + "DELAY": { + "description": "Delay between 2 sampling\n phases", + "offset": 8, + "size": 4 + }, + "MULT": { + "description": "Multi ADC mode selection", + "offset": 0, + "size": 5 + } + } + } + }, + "CDR": { + "description": "ADC common regular data register for dual\n and triple modes", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DATA2": { + "description": "2nd data item of a pair of regular\n conversions", + "offset": 16, + "size": 16 + }, + "DATA1": { + "description": "1st data item of a pair of regular\n conversions", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "TIM1": { + "description": "Advanced-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OIS4": { + "description": "Output Idle state 4", + "offset": 14, + "size": 1 + }, + "OIS3N": { + "description": "Output Idle state 3", + "offset": 13, + "size": 1 + }, + "OIS3": { + "description": "Output Idle state 3", + "offset": 12, + "size": 1 + }, + "OIS2N": { + "description": "Output Idle state 2", + "offset": 11, + "size": 1 + }, + "OIS2": { + "description": "Output Idle state 2", + "offset": 10, + "size": 1 + }, + "OIS1N": { + "description": "Output Idle state 1", + "offset": 9, + "size": 1 + }, + "OIS1": { + "description": "Output Idle state 1", + "offset": 8, + "size": 1 + }, + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + }, + "CCUS": { + "description": "Capture/compare control update\n selection", + "offset": 2, + "size": 1 + }, + "CCPC": { + "description": "Capture/compare preloaded\n control", + "offset": 0, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "COMDE": { + "description": "COM DMA request enable", + "offset": 13, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + }, + "BIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "COMIE": { + "description": "COM interrupt enable", + "offset": 5, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "BIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "COMIF": { + "description": "COM interrupt flag", + "offset": 5, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BG": { + "description": "Break generation", + "offset": 7, + "size": 1 + }, + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "COMG": { + "description": "Capture/Compare control update\n generation", + "offset": 5, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "Output Compare 2 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "Output Compare 1 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC4CE": { + "description": "Output compare 4 clear\n enable", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "Output compare 4 mode", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "Output compare 4 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "Output compare 4 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "Output compare 3 clear\n enable", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "Output compare 3 mode", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "Output compare 3 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "Output compare 3 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "Capture/Compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3NE": { + "description": "Capture/Compare 3 complementary output\n enable", + "offset": 10, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2NE": { + "description": "Capture/Compare 2 complementary output\n enable", + "offset": 6, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1NE": { + "description": "Capture/Compare 1 complementary output\n enable", + "offset": 2, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4": { + "description": "Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "RCR": { + "description": "repetition counter register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "REP": { + "description": "Repetition counter value", + "offset": 0, + "size": 8 + } + } + } + }, + "BDTR": { + "description": "break and dead-time register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MOE": { + "description": "Main output enable", + "offset": 15, + "size": 1 + }, + "AOE": { + "description": "Automatic output enable", + "offset": 14, + "size": 1 + }, + "BKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "BKE": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "OSSR": { + "description": "Off-state selection for Run\n mode", + "offset": 11, + "size": 1 + }, + "OSSI": { + "description": "Off-state selection for Idle\n mode", + "offset": 10, + "size": 1 + }, + "LOCK": { + "description": "Lock configuration", + "offset": 8, + "size": 2 + }, + "DTG": { + "description": "Dead-time generator setup", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_HCFG": { + "description": "OTG_FS host configuration register\n (OTG_FS_HCFG)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FSLSPCS": { + "description": "FS/LS PHY clock select", + "offset": 0, + "size": 2 + }, + "FSLSS": { + "description": "FS- and LS-only support", + "offset": 2, + "size": 1, + "access": "read-only" + } + } + } + }, + "HFIR": { + "description": "OTG_FS Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 60000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRIVL": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HFNUM": { + "description": "OTG_FS host frame number/frame time\n remaining register (OTG_FS_HFNUM)", + "offset": 8, + "size": 32, + "reset_value": 16383, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FTREM": { + "description": "Frame time remaining", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_HPTXSTS": { + "description": "OTG_FS_Host periodic transmit FIFO/queue\n status register (OTG_FS_HPTXSTS)", + "offset": 16, + "size": 32, + "reset_value": 524544, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFSAVL": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16 + }, + "PTXQSAV": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXQTOP": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "HAINT": { + "description": "OTG_FS Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HAINT": { + "description": "Channel interrupts", + "offset": 0, + "size": 16 + } + } + } + }, + "HAINTMSK": { + "description": "OTG_FS host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "HAINTM": { + "description": "Channel interrupt mask", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_HPRT": { + "description": "OTG_FS host port control and status register\n (OTG_FS_HPRT)", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCSTS": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCDET": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PENA": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PENCHNG": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "POCA": { + "description": "Port overcurrent active", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "POCCHNG": { + "description": "Port overcurrent change", + "offset": 5, + "size": 1 + }, + "PRES": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSUSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLSTS": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PPWR": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PTCTL": { + "description": "Port test control", + "offset": 13, + "size": 4 + }, + "PSPD": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "FS_HCCHAR0": { + "description": "OTG_FS host channel-0 characteristics\n register (OTG_FS_HCCHAR0)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR1": { + "description": "OTG_FS host channel-1 characteristics\n register (OTG_FS_HCCHAR1)", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR2": { + "description": "OTG_FS host channel-2 characteristics\n register (OTG_FS_HCCHAR2)", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR3": { + "description": "OTG_FS host channel-3 characteristics\n register (OTG_FS_HCCHAR3)", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR4": { + "description": "OTG_FS host channel-4 characteristics\n register (OTG_FS_HCCHAR4)", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR5": { + "description": "OTG_FS host channel-5 characteristics\n register (OTG_FS_HCCHAR5)", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR6": { + "description": "OTG_FS host channel-6 characteristics\n register (OTG_FS_HCCHAR6)", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCCHAR7": { + "description": "OTG_FS host channel-7 characteristics\n register (OTG_FS_HCCHAR7)", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPSIZ": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSDEV": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYP": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "MCNT": { + "description": "Multicount", + "offset": 20, + "size": 2 + }, + "DAD": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CHDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CHENA": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_HCINT0": { + "description": "OTG_FS host channel-0 interrupt register\n (OTG_FS_HCINT0)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT1": { + "description": "OTG_FS host channel-1 interrupt register\n (OTG_FS_HCINT1)", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT2": { + "description": "OTG_FS host channel-2 interrupt register\n (OTG_FS_HCINT2)", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT3": { + "description": "OTG_FS host channel-3 interrupt register\n (OTG_FS_HCINT3)", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT4": { + "description": "OTG_FS host channel-4 interrupt register\n (OTG_FS_HCINT4)", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT5": { + "description": "OTG_FS host channel-5 interrupt register\n (OTG_FS_HCINT5)", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT6": { + "description": "OTG_FS host channel-6 interrupt register\n (OTG_FS_HCINT6)", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINT7": { + "description": "OTG_FS host channel-7 interrupt register\n (OTG_FS_HCINT7)", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRC": { + "description": "Transfer completed", + "offset": 0, + "size": 1 + }, + "CHH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "TXERR": { + "description": "Transaction error", + "offset": 7, + "size": 1 + }, + "BBERR": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "FRMOR": { + "description": "Frame overrun", + "offset": 9, + "size": 1 + }, + "DTERR": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK0": { + "description": "OTG_FS host channel-0 mask register\n (OTG_FS_HCINTMSK0)", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK1": { + "description": "OTG_FS host channel-1 mask register\n (OTG_FS_HCINTMSK1)", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK2": { + "description": "OTG_FS host channel-2 mask register\n (OTG_FS_HCINTMSK2)", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK3": { + "description": "OTG_FS host channel-3 mask register\n (OTG_FS_HCINTMSK3)", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK4": { + "description": "OTG_FS host channel-4 mask register\n (OTG_FS_HCINTMSK4)", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK5": { + "description": "OTG_FS host channel-5 mask register\n (OTG_FS_HCINTMSK5)", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK6": { + "description": "OTG_FS host channel-6 mask register\n (OTG_FS_HCINTMSK6)", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCINTMSK7": { + "description": "OTG_FS host channel-7 mask register\n (OTG_FS_HCINTMSK7)", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRCM": { + "description": "Transfer completed mask", + "offset": 0, + "size": 1 + }, + "CHHM": { + "description": "Channel halted mask", + "offset": 1, + "size": 1 + }, + "STALLM": { + "description": "STALL response received interrupt\n mask", + "offset": 3, + "size": 1 + }, + "NAKM": { + "description": "NAK response received interrupt\n mask", + "offset": 4, + "size": 1 + }, + "ACKM": { + "description": "ACK response received/transmitted\n interrupt mask", + "offset": 5, + "size": 1 + }, + "NYET": { + "description": "response received interrupt\n mask", + "offset": 6, + "size": 1 + }, + "TXERRM": { + "description": "Transaction error mask", + "offset": 7, + "size": 1 + }, + "BBERRM": { + "description": "Babble error mask", + "offset": 8, + "size": 1 + }, + "FRMORM": { + "description": "Frame overrun mask", + "offset": 9, + "size": 1 + }, + "DTERRM": { + "description": "Data toggle error mask", + "offset": 10, + "size": 1 + } + } + } + }, + "FS_HCTSIZ0": { + "description": "OTG_FS host channel-0 transfer size\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ1": { + "description": "OTG_FS host channel-1 transfer size\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ2": { + "description": "OTG_FS host channel-2 transfer size\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ3": { + "description": "OTG_FS host channel-3 transfer size\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ4": { + "description": "OTG_FS host channel-x transfer size\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ5": { + "description": "OTG_FS host channel-5 transfer size\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ6": { + "description": "OTG_FS host channel-6 transfer size\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "FS_HCTSIZ7": { + "description": "OTG_FS host channel-7 transfer size\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "XFRSIZ": { + "description": "Transfer size", + "offset": 0, + "size": 19 + }, + "PKTCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "TIM2": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "TIM5 option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ITR1_RMP": { + "description": "Timer Input 4 remap", + "offset": 10, + "size": 2 + } + } + } + } + } + } + }, + "TIM3": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "children": { + "registers": { + "FS_GOTGCTL": { + "description": "OTG_FS control and status register\n (OTG_FS_GOTGCTL)", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRQSCS": { + "description": "Session request success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRQ": { + "description": "Session request", + "offset": 1, + "size": 1 + }, + "HNGSCS": { + "description": "Host negotiation success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPRQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HSHNPEN": { + "description": "Host set HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "CIDSTS": { + "description": "Connector ID status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DBCT": { + "description": "Long/short debounce time", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASVLD": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSVLD": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GOTGINT": { + "description": "OTG_FS interrupt register\n (OTG_FS_GOTGINT)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SEDET": { + "description": "Session end detected", + "offset": 2, + "size": 1 + }, + "SRSSCHG": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNSSCHG": { + "description": "Host negotiation success status\n change", + "offset": 9, + "size": 1 + }, + "HNGDET": { + "description": "Host negotiation detected", + "offset": 17, + "size": 1 + }, + "ADTOCHG": { + "description": "A-device timeout change", + "offset": 18, + "size": 1 + }, + "DBCDNE": { + "description": "Debounce done", + "offset": 19, + "size": 1 + } + } + } + }, + "FS_GAHBCFG": { + "description": "OTG_FS AHB configuration register\n (OTG_FS_GAHBCFG)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINT": { + "description": "Global interrupt mask", + "offset": 0, + "size": 1 + }, + "TXFELVL": { + "description": "TxFIFO empty level", + "offset": 7, + "size": 1 + }, + "PTXFELVL": { + "description": "Periodic TxFIFO empty\n level", + "offset": 8, + "size": 1 + } + } + } + }, + "FS_GUSBCFG": { + "description": "OTG_FS USB configuration register\n (OTG_FS_GUSBCFG)", + "offset": 12, + "size": 32, + "reset_value": 2560, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOCAL": { + "description": "FS timeout calibration", + "offset": 0, + "size": 3 + }, + "PHYSEL": { + "description": "Full Speed serial transceiver\n select", + "offset": 6, + "size": 1, + "access": "write-only" + }, + "SRPCAP": { + "description": "SRP-capable", + "offset": 8, + "size": 1 + }, + "HNPCAP": { + "description": "HNP-capable", + "offset": 9, + "size": 1 + }, + "TRDT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "FHMOD": { + "description": "Force host mode", + "offset": 29, + "size": 1 + }, + "FDMOD": { + "description": "Force device mode", + "offset": 30, + "size": 1 + }, + "CTXPKT": { + "description": "Corrupt Tx packet", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRSTCTL": { + "description": "OTG_FS reset register\n (OTG_FS_GRSTCTL)", + "offset": 16, + "size": 32, + "reset_value": 536870912, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "FCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFFLSH": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFFLSH": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + }, + "AHBIDL": { + "description": "AHB master idle", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "FS_GINTSTS": { + "description": "OTG_FS core interrupt register\n (OTG_FS_GINTSTS)", + "offset": 20, + "size": 32, + "reset_value": 67108896, + "reset_mask": 4294967295, + "children": { + "fields": { + "CMOD": { + "description": "Current mode of operation", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MMIS": { + "description": "Mode mismatch interrupt", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFLVL": { + "description": "RxFIFO non-empty", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFE": { + "description": "Non-periodic TxFIFO empty", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GINAKEFF": { + "description": "Global IN non-periodic NAK\n effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "GOUTNAKEFF": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESUSP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "USBSUSP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMDNE": { + "description": "Enumeration done", + "offset": 13, + "size": 1 + }, + "ISOODRP": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPF": { + "description": "End of periodic frame\n interrupt", + "offset": 15, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoint interrupt", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPINT": { + "description": "OUT endpoint interrupt", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "IISOIXFR": { + "description": "Incomplete isochronous IN\n transfer", + "offset": 20, + "size": 1 + }, + "IPXFR_INCOMPISOOUT": { + "description": "Incomplete periodic transfer(Host\n mode)/Incomplete isochronous OUT transfer(Device\n mode)", + "offset": 21, + "size": 1 + }, + "HPRTINT": { + "description": "Host port interrupt", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCINT": { + "description": "Host channels interrupt", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFE": { + "description": "Periodic TxFIFO empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "CIDSCHG": { + "description": "Connector ID status change", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected\n interrupt", + "offset": 29, + "size": 1 + }, + "SRQINT": { + "description": "Session request/new session detected\n interrupt", + "offset": 30, + "size": 1 + }, + "WKUPINT": { + "description": "Resume/remote wakeup detected\n interrupt", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GINTMSK": { + "description": "OTG_FS interrupt mask register\n (OTG_FS_GINTMSK)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMISM": { + "description": "Mode mismatch interrupt\n mask", + "offset": 1, + "size": 1 + }, + "OTGINT": { + "description": "OTG interrupt mask", + "offset": 2, + "size": 1 + }, + "SOFM": { + "description": "Start of frame mask", + "offset": 3, + "size": 1 + }, + "RXFLVLM": { + "description": "Receive FIFO non-empty\n mask", + "offset": 4, + "size": 1 + }, + "NPTXFEM": { + "description": "Non-periodic TxFIFO empty\n mask", + "offset": 5, + "size": 1 + }, + "GINAKEFFM": { + "description": "Global non-periodic IN NAK effective\n mask", + "offset": 6, + "size": 1 + }, + "GONAKEFFM": { + "description": "Global OUT NAK effective\n mask", + "offset": 7, + "size": 1 + }, + "ESUSPM": { + "description": "Early suspend mask", + "offset": 10, + "size": 1 + }, + "USBSUSPM": { + "description": "USB suspend mask", + "offset": 11, + "size": 1 + }, + "USBRST": { + "description": "USB reset mask", + "offset": 12, + "size": 1 + }, + "ENUMDNEM": { + "description": "Enumeration done mask", + "offset": 13, + "size": 1 + }, + "ISOODRPM": { + "description": "Isochronous OUT packet dropped interrupt\n mask", + "offset": 14, + "size": 1 + }, + "EOPFM": { + "description": "End of periodic frame interrupt\n mask", + "offset": 15, + "size": 1 + }, + "EPMISM": { + "description": "Endpoint mismatch interrupt\n mask", + "offset": 17, + "size": 1 + }, + "IEPINT": { + "description": "IN endpoints interrupt\n mask", + "offset": 18, + "size": 1 + }, + "OEPINT": { + "description": "OUT endpoints interrupt\n mask", + "offset": 19, + "size": 1 + }, + "IISOIXFRM": { + "description": "Incomplete isochronous IN transfer\n mask", + "offset": 20, + "size": 1 + }, + "IPXFRM_IISOOXFRM": { + "description": "Incomplete periodic transfer mask(Host\n mode)/Incomplete isochronous OUT transfer mask(Device\n mode)", + "offset": 21, + "size": 1 + }, + "PRTIM": { + "description": "Host port interrupt mask", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIM": { + "description": "Host channels interrupt\n mask", + "offset": 25, + "size": 1 + }, + "PTXFEM": { + "description": "Periodic TxFIFO empty mask", + "offset": 26, + "size": 1 + }, + "CIDSCHGM": { + "description": "Connector ID status change\n mask", + "offset": 28, + "size": 1 + }, + "DISCINT": { + "description": "Disconnect detected interrupt\n mask", + "offset": 29, + "size": 1 + }, + "SRQIM": { + "description": "Session request/new session detected\n interrupt mask", + "offset": 30, + "size": 1 + }, + "WUIM": { + "description": "Resume/remote wakeup detected interrupt\n mask", + "offset": 31, + "size": 1 + } + } + } + }, + "FS_GRXSTSR_Device": { + "description": "OTG_FS Receive status debug read(Device\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXSTSR_Host": { + "description": "OTG_FS Receive status debug\n read(Hostmode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "PKTSTS": { + "description": "Packet status", + "offset": 17, + "size": 4 + }, + "FRMNUM": { + "description": "Frame number", + "offset": 21, + "size": 4 + } + } + } + }, + "FS_GRXFSIZ": { + "description": "OTG_FS Receive FIFO size register\n (OTG_FS_GRXFSIZ)", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "RxFIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Device": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Device mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "TX0FSA": { + "description": "Endpoint 0 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "TX0FD": { + "description": "Endpoint 0 TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXFSIZ_Host": { + "description": "OTG_FS non-periodic transmit FIFO size\n register (Host mode)", + "offset": 40, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "NPTXFSA": { + "description": "Non-periodic transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "NPTXFD": { + "description": "Non-periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_GNPTXSTS": { + "description": "OTG_FS non-periodic transmit FIFO/queue\n status register (OTG_FS_GNPTXSTS)", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFSAV": { + "description": "Non-periodic TxFIFO space\n available", + "offset": 0, + "size": 16 + }, + "NPTQXSAV": { + "description": "Non-periodic transmit request queue\n space available", + "offset": 16, + "size": 8 + }, + "NPTXQTOP": { + "description": "Top of the non-periodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "FS_GCCFG": { + "description": "OTG_FS general core configuration register\n (OTG_FS_GCCFG)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRDWN": { + "description": "Power down", + "offset": 16, + "size": 1 + }, + "VBUSASEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 18, + "size": 1 + }, + "VBUSBSEN": { + "description": "Enable the VBUS sensing\n device", + "offset": 19, + "size": 1 + }, + "SOFOUTEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + } + } + } + }, + "FS_CID": { + "description": "core ID register", + "offset": 60, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "PRODUCT_ID": { + "description": "Product ID field", + "offset": 0, + "size": 32 + } + } + } + }, + "FS_HPTXFSIZ": { + "description": "OTG_FS Host periodic transmit FIFO size\n register (OTG_FS_HPTXFSIZ)", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXSA": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "PTXFSIZ": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF1": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF2)", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO2 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF2": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF3)", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO3 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "FS_DIEPTXF3": { + "description": "OTG_FS device IN endpoint transmit FIFO size\n register (OTG_FS_DIEPTXF4)", + "offset": 268, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "INEPTXSA": { + "description": "IN endpoint FIFO4 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "INEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + } + } + } + }, + "TIM5": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "CMS": { + "description": "Center-aligned mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI1S": { + "description": "TI1 selection", + "offset": 7, + "size": 1 + }, + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + }, + "CCDS": { + "description": "Capture/compare DMA\n selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "ECE": { + "description": "External clock enable", + "offset": 14, + "size": 1 + }, + "ETPS": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETF": { + "description": "External trigger filter", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TDE": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CC4DE": { + "description": "Capture/Compare 4 DMA request\n enable", + "offset": 12, + "size": 1 + }, + "CC3DE": { + "description": "Capture/Compare 3 DMA request\n enable", + "offset": 11, + "size": 1 + }, + "CC2DE": { + "description": "Capture/Compare 2 DMA request\n enable", + "offset": 10, + "size": 1 + }, + "CC1DE": { + "description": "Capture/Compare 1 DMA request\n enable", + "offset": 9, + "size": 1 + }, + "UDE": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC4IE": { + "description": "Capture/Compare 4 interrupt\n enable", + "offset": 4, + "size": 1 + }, + "CC3IE": { + "description": "Capture/Compare 3 interrupt\n enable", + "offset": 3, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4OF": { + "description": "Capture/Compare 4 overcapture\n flag", + "offset": 12, + "size": 1 + }, + "CC3OF": { + "description": "Capture/Compare 3 overcapture\n flag", + "offset": 11, + "size": 1 + }, + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC4IF": { + "description": "Capture/Compare 4 interrupt\n flag", + "offset": 4, + "size": 1 + }, + "CC3IF": { + "description": "Capture/Compare 3 interrupt\n flag", + "offset": 3, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC4G": { + "description": "Capture/compare 4\n generation", + "offset": 4, + "size": 1 + }, + "CC3G": { + "description": "Capture/compare 3\n generation", + "offset": 3, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2CE": { + "description": "OC2CE", + "offset": 15, + "size": 1 + }, + "OC2M": { + "description": "OC2M", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "OC2PE", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "OC2FE", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "CC2S", + "offset": 8, + "size": 2 + }, + "OC1CE": { + "description": "OC1CE", + "offset": 7, + "size": 1 + }, + "OC1M": { + "description": "OC1M", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "OC1PE", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "OC1FE", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "CC1S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 4 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Output": { + "description": "capture/compare mode register 2 (output\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "O24CE": { + "description": "O24CE", + "offset": 15, + "size": 1 + }, + "OC4M": { + "description": "OC4M", + "offset": 12, + "size": 3 + }, + "OC4PE": { + "description": "OC4PE", + "offset": 11, + "size": 1 + }, + "OC4FE": { + "description": "OC4FE", + "offset": 10, + "size": 1 + }, + "CC4S": { + "description": "CC4S", + "offset": 8, + "size": 2 + }, + "OC3CE": { + "description": "OC3CE", + "offset": 7, + "size": 1 + }, + "OC3M": { + "description": "OC3M", + "offset": 4, + "size": 3 + }, + "OC3PE": { + "description": "OC3PE", + "offset": 3, + "size": 1 + }, + "OC3FE": { + "description": "OC3FE", + "offset": 2, + "size": 1 + }, + "CC3S": { + "description": "CC3S", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR2_Input": { + "description": "capture/compare mode register 2 (input\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC4F": { + "description": "Input capture 4 filter", + "offset": 12, + "size": 4 + }, + "IC4PSC": { + "description": "Input capture 4 prescaler", + "offset": 10, + "size": 2 + }, + "CC4S": { + "description": "Capture/Compare 4\n selection", + "offset": 8, + "size": 2 + }, + "IC3F": { + "description": "Input capture 3 filter", + "offset": 4, + "size": 4 + }, + "IC3PSC": { + "description": "Input capture 3 prescaler", + "offset": 2, + "size": 2 + }, + "CC3S": { + "description": "Capture/compare 3\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC4NP": { + "description": "Capture/Compare 4 output\n Polarity", + "offset": 15, + "size": 1 + }, + "CC4P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 13, + "size": 1 + }, + "CC4E": { + "description": "Capture/Compare 4 output\n enable", + "offset": 12, + "size": 1 + }, + "CC3NP": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 11, + "size": 1 + }, + "CC3P": { + "description": "Capture/Compare 3 output\n Polarity", + "offset": 9, + "size": 1 + }, + "CC3E": { + "description": "Capture/Compare 3 output\n enable", + "offset": 8, + "size": 1 + }, + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT_H": { + "description": "High counter value", + "offset": 16, + "size": 16 + }, + "CNT_L": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR_H": { + "description": "High Auto-reload value", + "offset": 16, + "size": 16 + }, + "ARR_L": { + "description": "Low Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1_H": { + "description": "High Capture/Compare 1\n value", + "offset": 16, + "size": 16 + }, + "CCR1_L": { + "description": "Low Capture/Compare 1\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2_H": { + "description": "High Capture/Compare 2\n value", + "offset": 16, + "size": 16 + }, + "CCR2_L": { + "description": "Low Capture/Compare 2\n value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR3": { + "description": "capture/compare register 3", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR3_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR3_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR4": { + "description": "capture/compare register 4", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR4_H": { + "description": "High Capture/Compare value", + "offset": 16, + "size": 16 + }, + "CCR4_L": { + "description": "Low Capture/Compare value", + "offset": 0, + "size": 16 + } + } + } + }, + "DCR": { + "description": "DMA control register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DBL": { + "description": "DMA burst length", + "offset": 8, + "size": 5 + }, + "DBA": { + "description": "DMA base address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMAR": { + "description": "DMA address for full transfer", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMAB": { + "description": "DMA register for burst\n accesses", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "TIM5 option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IT4_RMP": { + "description": "Timer Input 4 remap", + "offset": 6, + "size": 2 + } + } + } + } + } + } + }, + "TIM9": { + "description": "General purpose timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "OPM": { + "description": "One-pulse mode", + "offset": 3, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CR2": { + "description": "control register 2", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMS": { + "description": "Master mode selection", + "offset": 4, + "size": 3 + } + } + } + }, + "SMCR": { + "description": "slave mode control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMS": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CC2IE": { + "description": "Capture/Compare 2 interrupt\n enable", + "offset": 2, + "size": 1 + }, + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2OF": { + "description": "Capture/compare 2 overcapture\n flag", + "offset": 10, + "size": 1 + }, + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "TIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CC2IF": { + "description": "Capture/Compare 2 interrupt\n flag", + "offset": 2, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TG": { + "description": "Trigger generation", + "offset": 6, + "size": 1 + }, + "CC2G": { + "description": "Capture/compare 2\n generation", + "offset": 2, + "size": 1 + }, + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC2M": { + "description": "Output Compare 2 mode", + "offset": 12, + "size": 3 + }, + "OC2PE": { + "description": "Output Compare 2 preload\n enable", + "offset": 11, + "size": 1 + }, + "OC2FE": { + "description": "Output Compare 2 fast\n enable", + "offset": 10, + "size": 1 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC2F": { + "description": "Input capture 2 filter", + "offset": 12, + "size": 3 + }, + "IC2PCS": { + "description": "Input capture 2 prescaler", + "offset": 10, + "size": 2 + }, + "CC2S": { + "description": "Capture/Compare 2\n selection", + "offset": 8, + "size": 2 + }, + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 3 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC2NP": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 7, + "size": 1 + }, + "CC2P": { + "description": "Capture/Compare 2 output\n Polarity", + "offset": 5, + "size": 1 + }, + "CC2E": { + "description": "Capture/Compare 2 output\n enable", + "offset": 4, + "size": 1 + }, + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR2": { + "description": "capture/compare register 2", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR2": { + "description": "Capture/Compare 2 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "CRC": { + "description": "Cryptographic processor", + "children": { + "registers": { + "DR": { + "description": "Data register", + "offset": 0, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "DR": { + "description": "Data Register", + "offset": 0, + "size": 32 + } + } + } + }, + "IDR": { + "description": "Independent Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IDR": { + "description": "Independent Data register", + "offset": 0, + "size": 8 + } + } + } + }, + "CR": { + "description": "Control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CR": { + "description": "Control regidter", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "TIM10": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "Ethernet_DMA": { + "description": "Ethernet: DMA controller operation", + "children": { + "registers": { + "DMABMR": { + "description": "Ethernet DMA bus mode register", + "offset": 0, + "size": 32, + "reset_value": 8449, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "SR", + "offset": 0, + "size": 1 + }, + "DA": { + "description": "DA", + "offset": 1, + "size": 1 + }, + "DSL": { + "description": "DSL", + "offset": 2, + "size": 5 + }, + "EDFE": { + "description": "EDFE", + "offset": 7, + "size": 1 + }, + "PBL": { + "description": "PBL", + "offset": 8, + "size": 6 + }, + "RTPR": { + "description": "RTPR", + "offset": 14, + "size": 2 + }, + "FB": { + "description": "FB", + "offset": 16, + "size": 1 + }, + "RDP": { + "description": "RDP", + "offset": 17, + "size": 6 + }, + "USP": { + "description": "USP", + "offset": 23, + "size": 1 + }, + "FPM": { + "description": "FPM", + "offset": 24, + "size": 1 + }, + "AAB": { + "description": "AAB", + "offset": 25, + "size": 1 + }, + "MB": { + "description": "MB", + "offset": 26, + "size": 1 + } + } + } + }, + "DMATPDR": { + "description": "Ethernet DMA transmit poll demand\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TPD": { + "description": "TPD", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARPDR": { + "description": "EHERNET DMA receive poll demand\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RPD": { + "description": "RPD", + "offset": 0, + "size": 32 + } + } + } + }, + "DMARDLAR": { + "description": "Ethernet DMA receive descriptor list address\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRL": { + "description": "SRL", + "offset": 0, + "size": 32 + } + } + } + }, + "DMATDLAR": { + "description": "Ethernet DMA transmit descriptor list\n address register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STL": { + "description": "STL", + "offset": 0, + "size": 32 + } + } + } + }, + "DMASR": { + "description": "Ethernet DMA status register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "TS", + "offset": 0, + "size": 1 + }, + "TPSS": { + "description": "TPSS", + "offset": 1, + "size": 1 + }, + "TBUS": { + "description": "TBUS", + "offset": 2, + "size": 1 + }, + "TJTS": { + "description": "TJTS", + "offset": 3, + "size": 1 + }, + "ROS": { + "description": "ROS", + "offset": 4, + "size": 1 + }, + "TUS": { + "description": "TUS", + "offset": 5, + "size": 1 + }, + "RS": { + "description": "RS", + "offset": 6, + "size": 1 + }, + "RBUS": { + "description": "RBUS", + "offset": 7, + "size": 1 + }, + "RPSS": { + "description": "RPSS", + "offset": 8, + "size": 1 + }, + "PWTS": { + "description": "PWTS", + "offset": 9, + "size": 1 + }, + "ETS": { + "description": "ETS", + "offset": 10, + "size": 1 + }, + "FBES": { + "description": "FBES", + "offset": 13, + "size": 1 + }, + "ERS": { + "description": "ERS", + "offset": 14, + "size": 1 + }, + "AIS": { + "description": "AIS", + "offset": 15, + "size": 1 + }, + "NIS": { + "description": "NIS", + "offset": 16, + "size": 1 + }, + "RPS": { + "description": "RPS", + "offset": 17, + "size": 3, + "access": "read-only" + }, + "TPS": { + "description": "TPS", + "offset": 20, + "size": 3, + "access": "read-only" + }, + "EBS": { + "description": "EBS", + "offset": 23, + "size": 3, + "access": "read-only" + }, + "MMCS": { + "description": "MMCS", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PMTS": { + "description": "PMTS", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TSTS": { + "description": "TSTS", + "offset": 29, + "size": 1, + "access": "read-only" + } + } + } + }, + "DMAOMR": { + "description": "Ethernet DMA operation mode\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SR": { + "description": "SR", + "offset": 1, + "size": 1 + }, + "OSF": { + "description": "OSF", + "offset": 2, + "size": 1 + }, + "RTC": { + "description": "RTC", + "offset": 3, + "size": 2 + }, + "FUGF": { + "description": "FUGF", + "offset": 6, + "size": 1 + }, + "FEF": { + "description": "FEF", + "offset": 7, + "size": 1 + }, + "ST": { + "description": "ST", + "offset": 13, + "size": 1 + }, + "TTC": { + "description": "TTC", + "offset": 14, + "size": 3 + }, + "FTF": { + "description": "FTF", + "offset": 20, + "size": 1 + }, + "TSF": { + "description": "TSF", + "offset": 21, + "size": 1 + }, + "DFRF": { + "description": "DFRF", + "offset": 24, + "size": 1 + }, + "RSF": { + "description": "RSF", + "offset": 25, + "size": 1 + }, + "DTCEFD": { + "description": "DTCEFD", + "offset": 26, + "size": 1 + } + } + } + }, + "DMAIER": { + "description": "Ethernet DMA interrupt enable\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIE": { + "description": "TIE", + "offset": 0, + "size": 1 + }, + "TPSIE": { + "description": "TPSIE", + "offset": 1, + "size": 1 + }, + "TBUIE": { + "description": "TBUIE", + "offset": 2, + "size": 1 + }, + "TJTIE": { + "description": "TJTIE", + "offset": 3, + "size": 1 + }, + "ROIE": { + "description": "ROIE", + "offset": 4, + "size": 1 + }, + "TUIE": { + "description": "TUIE", + "offset": 5, + "size": 1 + }, + "RIE": { + "description": "RIE", + "offset": 6, + "size": 1 + }, + "RBUIE": { + "description": "RBUIE", + "offset": 7, + "size": 1 + }, + "RPSIE": { + "description": "RPSIE", + "offset": 8, + "size": 1 + }, + "RWTIE": { + "description": "RWTIE", + "offset": 9, + "size": 1 + }, + "ETIE": { + "description": "ETIE", + "offset": 10, + "size": 1 + }, + "FBEIE": { + "description": "FBEIE", + "offset": 13, + "size": 1 + }, + "ERIE": { + "description": "ERIE", + "offset": 14, + "size": 1 + }, + "AISE": { + "description": "AISE", + "offset": 15, + "size": 1 + }, + "NISE": { + "description": "NISE", + "offset": 16, + "size": 1 + } + } + } + }, + "DMAMFBOCR": { + "description": "Ethernet DMA missed frame and buffer\n overflow counter register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MFC": { + "description": "MFC", + "offset": 0, + "size": 16 + }, + "OMFC": { + "description": "OMFC", + "offset": 16, + "size": 1 + }, + "MFA": { + "description": "MFA", + "offset": 17, + "size": 11 + }, + "OFOC": { + "description": "OFOC", + "offset": 28, + "size": 1 + } + } + } + }, + "DMARSWTR": { + "description": "Ethernet DMA receive status watchdog timer\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSWTC": { + "description": "RSWTC", + "offset": 0, + "size": 8 + } + } + } + }, + "DMACHTDR": { + "description": "Ethernet DMA current host transmit\n descriptor register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTDAP": { + "description": "HTDAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRDR": { + "description": "Ethernet DMA current host receive descriptor\n register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRDAP": { + "description": "HRDAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHTBAR": { + "description": "Ethernet DMA current host transmit buffer\n address register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HTBAP": { + "description": "HTBAP", + "offset": 0, + "size": 32 + } + } + } + }, + "DMACHRBAR": { + "description": "Ethernet DMA current host receive buffer\n address register", + "offset": 84, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HRBAP": { + "description": "HRBAP", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "Ethernet_PTP": { + "description": "Ethernet: Precision time protocol", + "children": { + "registers": { + "PTPTSCR": { + "description": "Ethernet PTP time stamp control\n register", + "offset": 0, + "size": 32, + "reset_value": 8192, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSE": { + "description": "TSE", + "offset": 0, + "size": 1 + }, + "TSFCU": { + "description": "TSFCU", + "offset": 1, + "size": 1 + }, + "TSPTPPSV2E": { + "description": "TSPTPPSV2E", + "offset": 10, + "size": 1 + }, + "TSSPTPOEFE": { + "description": "TSSPTPOEFE", + "offset": 11, + "size": 1 + }, + "TSSIPV6FE": { + "description": "TSSIPV6FE", + "offset": 12, + "size": 1 + }, + "TSSIPV4FE": { + "description": "TSSIPV4FE", + "offset": 13, + "size": 1 + }, + "TSSEME": { + "description": "TSSEME", + "offset": 14, + "size": 1 + }, + "TSSMRME": { + "description": "TSSMRME", + "offset": 15, + "size": 1 + }, + "TSCNT": { + "description": "TSCNT", + "offset": 16, + "size": 2 + }, + "TSPFFMAE": { + "description": "TSPFFMAE", + "offset": 18, + "size": 1 + }, + "TSSTI": { + "description": "TSSTI", + "offset": 2, + "size": 1 + }, + "TSSTU": { + "description": "TSSTU", + "offset": 3, + "size": 1 + }, + "TSITE": { + "description": "TSITE", + "offset": 4, + "size": 1 + }, + "TTSARU": { + "description": "TTSARU", + "offset": 5, + "size": 1 + }, + "TSSARFE": { + "description": "TSSARFE", + "offset": 8, + "size": 1 + }, + "TSSSR": { + "description": "TSSSR", + "offset": 9, + "size": 1 + } + } + } + }, + "PTPSSIR": { + "description": "Ethernet PTP subsecond increment\n register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STSSI": { + "description": "STSSI", + "offset": 0, + "size": 8 + } + } + } + }, + "PTPTSHR": { + "description": "Ethernet PTP time stamp high\n register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STS": { + "description": "STS", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLR": { + "description": "Ethernet PTP time stamp low\n register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "STSS": { + "description": "STSS", + "offset": 0, + "size": 31 + }, + "STPNS": { + "description": "STPNS", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSHUR": { + "description": "Ethernet PTP time stamp high update\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUS": { + "description": "TSUS", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSLUR": { + "description": "Ethernet PTP time stamp low update\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSUSS": { + "description": "TSUSS", + "offset": 0, + "size": 31 + }, + "TSUPNS": { + "description": "TSUSS", + "offset": 31, + "size": 1 + } + } + } + }, + "PTPTSAR": { + "description": "Ethernet PTP time stamp addend\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSA": { + "description": "TSA", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTHR": { + "description": "Ethernet PTP target time high\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSH": { + "description": "0", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTTLR": { + "description": "Ethernet PTP target time low\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TTSL": { + "description": "TTSL", + "offset": 0, + "size": 32 + } + } + } + }, + "PTPTSSR": { + "description": "Ethernet PTP time stamp status\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TSSO": { + "description": "TSSO", + "offset": 0, + "size": 1 + }, + "TSTTR": { + "description": "TSTTR", + "offset": 1, + "size": 1 + } + } + } + }, + "PTPPPSCR": { + "description": "Ethernet PTP PPS control\n register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TSSO": { + "description": "TSSO", + "offset": 0, + "size": 1 + }, + "TSTTR": { + "description": "TSTTR", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "TIM11": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CR1": { + "description": "control register 1", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKD": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARPE": { + "description": "Auto-reload preload enable", + "offset": 7, + "size": 1 + }, + "URS": { + "description": "Update request source", + "offset": 2, + "size": 1 + }, + "UDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "DIER": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1IE": { + "description": "Capture/Compare 1 interrupt\n enable", + "offset": 1, + "size": 1 + }, + "UIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SR": { + "description": "status register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1OF": { + "description": "Capture/Compare 1 overcapture\n flag", + "offset": 9, + "size": 1 + }, + "CC1IF": { + "description": "Capture/compare 1 interrupt\n flag", + "offset": 1, + "size": 1 + }, + "UIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "EGR": { + "description": "event generation register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CC1G": { + "description": "Capture/compare 1\n generation", + "offset": 1, + "size": 1 + }, + "UG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CCMR1_Output": { + "description": "capture/compare mode register 1 (output\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OC1M": { + "description": "Output Compare 1 mode", + "offset": 4, + "size": 3 + }, + "OC1PE": { + "description": "Output Compare 1 preload\n enable", + "offset": 3, + "size": 1 + }, + "OC1FE": { + "description": "Output Compare 1 fast\n enable", + "offset": 2, + "size": 1 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCMR1_Input": { + "description": "capture/compare mode register 1 (input\n mode)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IC1F": { + "description": "Input capture 1 filter", + "offset": 4, + "size": 4 + }, + "ICPCS": { + "description": "Input capture 1 prescaler", + "offset": 2, + "size": 2 + }, + "CC1S": { + "description": "Capture/Compare 1\n selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CCER": { + "description": "capture/compare enable\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CC1NP": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 3, + "size": 1 + }, + "CC1P": { + "description": "Capture/Compare 1 output\n Polarity", + "offset": 1, + "size": 1 + }, + "CC1E": { + "description": "Capture/Compare 1 output\n enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 16 + } + } + } + }, + "ARR": { + "description": "auto-reload register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARR": { + "description": "Auto-reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CCR1": { + "description": "capture/compare register 1", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CCR1": { + "description": "Capture/Compare 1 value", + "offset": 0, + "size": 16 + } + } + } + }, + "OR": { + "description": "option register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RMP": { + "description": "Input 1 remapping\n capability", + "offset": 0, + "size": 2 + } + } + } + } + } + } + } + } + }, + "devices": { + "STM32F429": { + "arch": "cortex_m4", + "description": "STM32F429", + "properties": { + "cpu.nvic_prio_bits": "3", + "cpu.mpu": "false", + "cpu.fpu": "false", + "cpu.revision": "r1p0", + "cpu.vendor_systick_config": "false", + "cpu.endian": "little", + "cpu.name": "CM4" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "FPU": { + "index": 81, + "description": "Floating point unit interrupt" + }, + "HASH_RNG": { + "index": 80, + "description": "Hash and Rng global interrupt" + }, + "CRYP": { + "index": 79, + "description": "CRYP crypto global interrupt" + }, + "DCMI": { + "index": 78, + "description": "DCMI global interrupt" + }, + "FMC": { + "index": 48, + "description": "FMC global interrupt" + }, + "DMA2_Stream0": { + "index": 56, + "description": "DMA2 Stream0 global interrupt" + }, + "DMA1_Stream0": { + "index": 11, + "description": "DMA1 Stream0 global interrupt" + }, + "RCC": { + "index": 5, + "description": "RCC global interrupt" + }, + "SPI1": { + "index": 35, + "description": "SPI1 global interrupt" + }, + "SPI2": { + "index": 36, + "description": "SPI2 global interrupt" + }, + "SPI3": { + "index": 51, + "description": "SPI3 global interrupt" + }, + "SPI4": { + "index": 84, + "description": "SPI 4 global interrupt" + }, + "SPI5": { + "index": 85, + "description": "SPI 5 global interrupt" + }, + "SPI6": { + "index": 86, + "description": "SPI 6 global interrupt" + }, + "SDIO": { + "index": 49, + "description": "SDIO global interrupt" + }, + "ADC": { + "index": 18, + "description": "ADC2 global interrupts" + }, + "USART6": { + "index": 71, + "description": "USART6 global interrupt" + }, + "USART1": { + "index": 37, + "description": "USART1 global interrupt" + }, + "USART2": { + "index": 38, + "description": "USART2 global interrupt" + }, + "USART3": { + "index": 39, + "description": "USART3 global interrupt" + }, + "UART7": { + "index": 82, + "description": "UART 7 global interrupt" + }, + "UART8": { + "index": 83, + "description": "UART 8 global interrupt" + }, + "TIM6_DAC": { + "index": 54, + "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n error interrupt" + }, + "PVD": { + "index": 1, + "description": "PVD through EXTI line detection\n interrupt" + }, + "WWDG": { + "index": 0, + "description": "Window Watchdog interrupt" + }, + "RTC_WKUP": { + "index": 3, + "description": "RTC Wakeup interrupt through the EXTI\n line" + }, + "UART4": { + "index": 52, + "description": "UART4 global interrupt" + }, + "UART5": { + "index": 53, + "description": "UART5 global interrupt" + }, + "TIM1_BRK_TIM9": { + "index": 24, + "description": "TIM1 Break interrupt and TIM9 global\n interrupt" + }, + "TIM8_BRK_TIM12": { + "index": 43, + "description": "TIM8 Break interrupt and TIM12 global\n interrupt" + }, + "TIM2": { + "index": 28, + "description": "TIM2 global interrupt" + }, + "TIM3": { + "index": 29, + "description": "TIM3 global interrupt" + }, + "TIM4": { + "index": 30, + "description": "TIM4 global interrupt" + }, + "TIM5": { + "index": 50, + "description": "TIM5 global interrupt" + }, + "TIM8_UP_TIM13": { + "index": 44, + "description": "TIM8 Update interrupt and TIM13 global\n interrupt" + }, + "TIM8_TRG_COM_TIM14": { + "index": 45, + "description": "TIM8 Trigger and Commutation interrupts and\n TIM14 global interrupt" + }, + "TIM7": { + "index": 55, + "description": "TIM7 global interrupt" + }, + "ETH": { + "index": 61, + "description": "Ethernet global interrupt" + }, + "OTG_FS_WKUP": { + "index": 42, + "description": "USB On-The-Go FS Wakeup through EXTI line\n interrupt" + }, + "CAN1_TX": { + "index": 19, + "description": "CAN1 TX interrupts" + }, + "CAN2_TX": { + "index": 63, + "description": "CAN2 TX interrupts" + }, + "FLASH": { + "index": 4, + "description": "Flash global interrupt" + }, + "TAMP_STAMP": { + "index": 2, + "description": "Tamper and TimeStamp interrupts through the\n EXTI line" + }, + "OTG_HS_EP1_OUT": { + "index": 74, + "description": "USB On The Go HS End Point 1 Out global\n interrupt" + }, + "LCD_TFT": { + "index": 88, + "description": "LTDC global interrupt" + }, + "SAI1": { + "index": 87, + "description": "SAI1 global interrupt" + }, + "DMA2D": { + "index": 90, + "description": "DMA2D global interrupt" + }, + "I2C3_EV": { + "index": 72, + "description": "I2C3 event interrupt" + }, + "I2C2_EV": { + "index": 33, + "description": "I2C2 event interrupt" + }, + "I2C1_EV": { + "index": 31, + "description": "I2C1 event interrupt" + } + }, + "peripheral_instances": { + "RNG": { + "description": "Random number generator", + "offset": 1342572544, + "type": "types.peripherals.RNG" + }, + "HASH": { + "description": "Hash processor", + "offset": 1342571520, + "type": "types.peripherals.HASH" + }, + "CRYP": { + "description": "Cryptographic processor", + "offset": 1342570496, + "type": "types.peripherals.CRYP" + }, + "DCMI": { + "description": "Digital camera interface", + "offset": 1342504960, + "type": "types.peripherals.DCMI" + }, + "FMC": { + "description": "Flexible memory controller", + "offset": 2684354560, + "type": "types.peripherals.FMC" + }, + "DBG": { + "description": "Debug support", + "offset": 3758366720, + "type": "types.peripherals.DBG" + }, + "DMA2": { + "description": "DMA controller", + "offset": 1073898496, + "type": "types.peripherals.DMA2" + }, + "DMA1": { + "offset": 1073897472, + "type": "types.peripherals.DMA2" + }, + "RCC": { + "description": "Reset and clock control", + "offset": 1073887232, + "type": "types.peripherals.RCC" + }, + "GPIOK": { + "description": "General-purpose I/Os", + "offset": 1073883136, + "type": "types.peripherals.GPIOK" + }, + "GPIOJ": { + "offset": 1073882112, + "type": "types.peripherals.GPIOK" + }, + "GPIOI": { + "offset": 1073881088, + "type": "types.peripherals.GPIOK" + }, + "GPIOH": { + "offset": 1073880064, + "type": "types.peripherals.GPIOK" + }, + "GPIOG": { + "offset": 1073879040, + "type": "types.peripherals.GPIOK" + }, + "GPIOF": { + "offset": 1073878016, + "type": "types.peripherals.GPIOK" + }, + "GPIOE": { + "offset": 1073876992, + "type": "types.peripherals.GPIOK" + }, + "GPIOD": { + "offset": 1073875968, + "type": "types.peripherals.GPIOK" + }, + "GPIOC": { + "offset": 1073874944, + "type": "types.peripherals.GPIOK" + }, + "GPIOB": { + "description": "General-purpose I/Os", + "offset": 1073873920, + "type": "types.peripherals.GPIOB" + }, + "GPIOA": { + "description": "General-purpose I/Os", + "offset": 1073872896, + "type": "types.peripherals.GPIOA" + }, + "SYSCFG": { + "description": "System configuration controller", + "offset": 1073821696, + "type": "types.peripherals.SYSCFG" + }, + "SPI1": { + "description": "Serial peripheral interface", + "offset": 1073819648, + "type": "types.peripherals.SPI1" + }, + "SPI2": { + "offset": 1073756160, + "type": "types.peripherals.SPI1" + }, + "SPI3": { + "offset": 1073757184, + "type": "types.peripherals.SPI1" + }, + "I2S2ext": { + "offset": 1073755136, + "type": "types.peripherals.SPI1" + }, + "I2S3ext": { + "offset": 1073758208, + "type": "types.peripherals.SPI1" + }, + "SPI4": { + "offset": 1073820672, + "type": "types.peripherals.SPI1" + }, + "SPI5": { + "offset": 1073827840, + "type": "types.peripherals.SPI1" + }, + "SPI6": { + "offset": 1073828864, + "type": "types.peripherals.SPI1" + }, + "SDIO": { + "description": "Secure digital input/output\n interface", + "offset": 1073818624, + "type": "types.peripherals.SDIO" + }, + "ADC1": { + "description": "Analog-to-digital converter", + "offset": 1073815552, + "type": "types.peripherals.ADC1" + }, + "ADC2": { + "offset": 1073815808, + "type": "types.peripherals.ADC1" + }, + "ADC3": { + "offset": 1073816064, + "type": "types.peripherals.ADC1" + }, + "USART6": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073812480, + "type": "types.peripherals.USART6" + }, + "USART1": { + "offset": 1073811456, + "type": "types.peripherals.USART6" + }, + "USART2": { + "offset": 1073759232, + "type": "types.peripherals.USART6" + }, + "USART3": { + "offset": 1073760256, + "type": "types.peripherals.USART6" + }, + "UART7": { + "offset": 1073772544, + "type": "types.peripherals.USART6" + }, + "UART8": { + "offset": 1073773568, + "type": "types.peripherals.USART6" + }, + "DAC": { + "description": "Digital-to-analog converter", + "offset": 1073771520, + "type": "types.peripherals.DAC" + }, + "PWR": { + "description": "Power control", + "offset": 1073770496, + "type": "types.peripherals.PWR" + }, + "IWDG": { + "description": "Independent watchdog", + "offset": 1073754112, + "type": "types.peripherals.IWDG" + }, + "WWDG": { + "description": "Window watchdog", + "offset": 1073753088, + "type": "types.peripherals.WWDG" + }, + "RTC": { + "description": "Real-time clock", + "offset": 1073752064, + "type": "types.peripherals.RTC" + }, + "UART4": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073761280, + "type": "types.peripherals.UART4" + }, + "UART5": { + "offset": 1073762304, + "type": "types.peripherals.UART4" + }, + "C_ADC": { + "description": "Common ADC registers", + "offset": 1073816320, + "type": "types.peripherals.C_ADC" + }, + "TIM1": { + "description": "Advanced-timers", + "offset": 1073807360, + "type": "types.peripherals.TIM1" + }, + "TIM8": { + "offset": 1073808384, + "type": "types.peripherals.TIM1" + }, + "TIM2": { + "description": "General purpose timers", + "offset": 1073741824, + "type": "types.peripherals.TIM2" + }, + "TIM3": { + "description": "General purpose timers", + "offset": 1073742848, + "type": "types.peripherals.TIM3" + }, + "TIM4": { + "offset": 1073743872, + "type": "types.peripherals.TIM3" + }, + "TIM5": { + "description": "General-purpose-timers", + "offset": 1073744896, + "type": "types.peripherals.TIM5" + }, + "TIM9": { + "description": "General purpose timers", + "offset": 1073823744, + "type": "types.peripherals.TIM9" + }, + "TIM12": { + "offset": 1073747968, + "type": "types.peripherals.TIM9" + }, + "TIM10": { + "description": "General-purpose-timers", + "offset": 1073824768, + "type": "types.peripherals.TIM10" + }, + "TIM13": { + "offset": 1073748992, + "type": "types.peripherals.TIM10" + }, + "TIM14": { + "offset": 1073750016, + "type": "types.peripherals.TIM10" + }, + "TIM11": { + "description": "General-purpose-timers", + "offset": 1073825792, + "type": "types.peripherals.TIM11" + }, + "TIM6": { + "description": "Basic timers", + "offset": 1073745920, + "type": "types.peripherals.TIM6" + }, + "TIM7": { + "offset": 1073746944, + "type": "types.peripherals.TIM6" + }, + "Ethernet_MAC": { + "description": "Ethernet: media access control\n (MAC)", + "offset": 1073905664, + "type": "types.peripherals.Ethernet_MAC" + }, + "Ethernet_MMC": { + "description": "Ethernet: MAC management counters", + "offset": 1073905920, + "type": "types.peripherals.Ethernet_MMC" + }, + "Ethernet_PTP": { + "description": "Ethernet: Precision time protocol", + "offset": 1073907456, + "type": "types.peripherals.Ethernet_PTP" + }, + "Ethernet_DMA": { + "description": "Ethernet: DMA controller operation", + "offset": 1073909760, + "type": "types.peripherals.Ethernet_DMA" + }, + "CRC": { + "description": "Cryptographic processor", + "offset": 1073885184, + "type": "types.peripherals.CRC" + }, + "OTG_FS_GLOBAL": { + "description": "USB on the go full speed", + "offset": 1342177280, + "type": "types.peripherals.OTG_FS_GLOBAL" + }, + "OTG_FS_HOST": { + "description": "USB on the go full speed", + "offset": 1342178304, + "type": "types.peripherals.OTG_FS_HOST" + }, + "OTG_FS_DEVICE": { + "description": "USB on the go full speed", + "offset": 1342179328, + "type": "types.peripherals.OTG_FS_DEVICE" + }, + "OTG_FS_PWRCLK": { + "description": "USB on the go full speed", + "offset": 1342180864, + "type": "types.peripherals.OTG_FS_PWRCLK" + }, + "CAN1": { + "description": "Controller area network", + "offset": 1073767424, + "type": "types.peripherals.CAN1" + }, + "CAN2": { + "offset": 1073768448, + "type": "types.peripherals.CAN1" + }, + "NVIC": { + "description": "Nested Vectored Interrupt\n Controller", + "offset": 3758153984, + "type": "types.peripherals.NVIC" + }, + "FLASH": { + "description": "FLASH", + "offset": 1073888256, + "type": "types.peripherals.FLASH" + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "offset": 1073822720, + "type": "types.peripherals.EXTI" + }, + "OTG_HS_GLOBAL": { + "description": "USB on the go high speed", + "offset": 1074003968, + "type": "types.peripherals.OTG_HS_GLOBAL" + }, + "OTG_HS_HOST": { + "description": "USB on the go high speed", + "offset": 1074004992, + "type": "types.peripherals.OTG_HS_HOST" + }, + "OTG_HS_DEVICE": { + "description": "USB on the go high speed", + "offset": 1074006016, + "type": "types.peripherals.OTG_HS_DEVICE" + }, + "OTG_HS_PWRCLK": { + "description": "USB on the go high speed", + "offset": 1074007552, + "type": "types.peripherals.OTG_HS_PWRCLK" + }, + "LTDC": { + "description": "LCD-TFT Controller", + "offset": 1073833984, + "type": "types.peripherals.LTDC" + }, + "SAI": { + "description": "Serial audio interface", + "offset": 1073829888, + "type": "types.peripherals.SAI" + }, + "DMA2D": { + "description": "DMA2D controller", + "offset": 1073917952, + "type": "types.peripherals.DMA2D" + }, + "I2C3": { + "description": "Inter-integrated circuit", + "offset": 1073765376, + "type": "types.peripherals.I2C3" + }, + "I2C2": { + "offset": 1073764352, + "type": "types.peripherals.I2C3" + }, + "I2C1": { + "offset": 1073763328, + "type": "types.peripherals.I2C3" + }, + "FPU": { + "description": "Floting point unit", + "offset": 3758157620, + "type": "types.peripherals.FPU" + }, + "MPU": { + "description": "Memory protection unit", + "offset": 3758157200, + "type": "types.peripherals.MPU" + }, + "STK": { + "description": "SysTick timer", + "offset": 3758153744, + "type": "types.peripherals.STK" + }, + "SCB": { + "description": "System control block", + "offset": 3758157056, + "type": "types.peripherals.SCB" + }, + "NVIC_STIR": { + "description": "Nested vectored interrupt\n controller", + "offset": 3758157568, + "type": "types.peripherals.NVIC_STIR" + }, + "FPU_CPACR": { + "description": "Floating point unit CPACR", + "offset": 3758157192, + "type": "types.peripherals.FPU_CPACR" + }, + "SCB_ACTRL": { + "description": "System control block ACTLR", + "offset": 3758153736, + "type": "types.peripherals.SCB_ACTRL" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/STM32F429.zig b/src/chips/STM32F429.zig new file mode 100644 index 0000000..73b9436 --- /dev/null +++ b/src/chips/STM32F429.zig @@ -0,0 +1,20419 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// STM32F429 + pub const STM32F429 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "3"; + pub const @"cpu.mpu" = "false"; + pub const @"cpu.fpu" = "false"; + pub const @"cpu.revision" = "r1p0"; + pub const @"cpu.vendor_systick_config" = "false"; + pub const @"cpu.endian" = "little"; + pub const @"cpu.name" = "CM4"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + /// Window Watchdog interrupt + WWDG: Handler = unhandled, + /// PVD through EXTI line detection interrupt + PVD: Handler = unhandled, + /// Tamper and TimeStamp interrupts through the EXTI line + TAMP_STAMP: Handler = unhandled, + /// RTC Wakeup interrupt through the EXTI line + RTC_WKUP: Handler = unhandled, + /// Flash global interrupt + FLASH: Handler = unhandled, + /// RCC global interrupt + RCC: Handler = unhandled, + reserved20: [5]u32 = undefined, + /// DMA1 Stream0 global interrupt + DMA1_Stream0: Handler = unhandled, + reserved26: [6]u32 = undefined, + /// ADC2 global interrupts + ADC: Handler = unhandled, + /// CAN1 TX interrupts + CAN1_TX: Handler = unhandled, + reserved34: [4]u32 = undefined, + /// TIM1 Break interrupt and TIM9 global interrupt + TIM1_BRK_TIM9: Handler = unhandled, + reserved39: [3]u32 = undefined, + /// TIM2 global interrupt + TIM2: Handler = unhandled, + /// TIM3 global interrupt + TIM3: Handler = unhandled, + /// TIM4 global interrupt + TIM4: Handler = unhandled, + /// I2C1 event interrupt + I2C1_EV: Handler = unhandled, + reserved46: [1]u32 = undefined, + /// I2C2 event interrupt + I2C2_EV: Handler = unhandled, + reserved48: [1]u32 = undefined, + /// SPI1 global interrupt + SPI1: Handler = unhandled, + /// SPI2 global interrupt + SPI2: Handler = unhandled, + /// USART1 global interrupt + USART1: Handler = unhandled, + /// USART2 global interrupt + USART2: Handler = unhandled, + /// USART3 global interrupt + USART3: Handler = unhandled, + reserved54: [2]u32 = undefined, + /// USB On-The-Go FS Wakeup through EXTI line interrupt + OTG_FS_WKUP: Handler = unhandled, + /// TIM8 Break interrupt and TIM12 global interrupt + TIM8_BRK_TIM12: Handler = unhandled, + /// TIM8 Update interrupt and TIM13 global interrupt + TIM8_UP_TIM13: Handler = unhandled, + /// TIM8 Trigger and Commutation interrupts and TIM14 global interrupt + TIM8_TRG_COM_TIM14: Handler = unhandled, + reserved60: [2]u32 = undefined, + /// FMC global interrupt + FMC: Handler = unhandled, + /// SDIO global interrupt + SDIO: Handler = unhandled, + /// TIM5 global interrupt + TIM5: Handler = unhandled, + /// SPI3 global interrupt + SPI3: Handler = unhandled, + /// UART4 global interrupt + UART4: Handler = unhandled, + /// UART5 global interrupt + UART5: Handler = unhandled, + /// TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt + TIM6_DAC: Handler = unhandled, + /// TIM7 global interrupt + TIM7: Handler = unhandled, + /// DMA2 Stream0 global interrupt + DMA2_Stream0: Handler = unhandled, + reserved71: [4]u32 = undefined, + /// Ethernet global interrupt + ETH: Handler = unhandled, + reserved76: [1]u32 = undefined, + /// CAN2 TX interrupts + CAN2_TX: Handler = unhandled, + reserved78: [7]u32 = undefined, + /// USART6 global interrupt + USART6: Handler = unhandled, + /// I2C3 event interrupt + I2C3_EV: Handler = unhandled, + reserved87: [1]u32 = undefined, + /// USB On The Go HS End Point 1 Out global interrupt + OTG_HS_EP1_OUT: Handler = unhandled, + reserved89: [3]u32 = undefined, + /// DCMI global interrupt + DCMI: Handler = unhandled, + /// CRYP crypto global interrupt + CRYP: Handler = unhandled, + /// Hash and Rng global interrupt + HASH_RNG: Handler = unhandled, + /// FPU interrupt + FPU: Handler = unhandled, + /// UART 7 global interrupt + UART7: Handler = unhandled, + /// UART 8 global interrupt + UART8: Handler = unhandled, + /// SPI 4 global interrupt + SPI4: Handler = unhandled, + /// SPI 5 global interrupt + SPI5: Handler = unhandled, + /// SPI 6 global interrupt + SPI6: Handler = unhandled, + /// SAI1 global interrupt + SAI1: Handler = unhandled, + /// LTDC global interrupt + LCD_TFT: Handler = unhandled, + reserved103: [1]u32 = undefined, + /// DMA2D global interrupt + DMA2D: Handler = unhandled, + }; + + pub const peripherals = struct { + /// General purpose timers + pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000); + /// General purpose timers + pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400); + /// General purpose timers + pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800); + /// General-purpose-timers + pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00); + /// Basic timers + pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000); + /// Basic timers + pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400); + /// General purpose timers + pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800); + /// General-purpose-timers + pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00); + /// General-purpose-timers + pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000); + /// Real-time clock + pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800); + /// Window watchdog + pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00); + /// Independent watchdog + pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000); + /// Serial peripheral interface + pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400); + /// Serial peripheral interface + pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800); + /// Serial peripheral interface + pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00); + /// Serial peripheral interface + pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800); + /// Universal synchronous asynchronous receiver transmitter + pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00); + /// Universal synchronous asynchronous receiver transmitter + pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000); + /// Inter-integrated circuit + pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400); + /// Inter-integrated circuit + pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800); + /// Inter-integrated circuit + pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00); + /// Controller area network + pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400); + /// Controller area network + pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800); + /// Power control + pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000); + /// Digital-to-analog converter + pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400); + /// Universal synchronous asynchronous receiver transmitter + pub const UART7 = @ptrCast(*volatile types.USART6, 0x40007800); + /// Universal synchronous asynchronous receiver transmitter + pub const UART8 = @ptrCast(*volatile types.USART6, 0x40007c00); + /// Advanced-timers + pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000); + /// Advanced-timers + pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400); + /// Analog-to-digital converter + pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000); + /// Analog-to-digital converter + pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100); + /// Analog-to-digital converter + pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200); + /// Common ADC registers + pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300); + /// Secure digital input/output interface + pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00); + /// Serial peripheral interface + pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000); + /// Serial peripheral interface + pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400); + /// System configuration controller + pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800); + /// External interrupt/event controller + pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00); + /// General purpose timers + pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000); + /// General-purpose-timers + pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400); + /// General-purpose-timers + pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800); + /// Serial peripheral interface + pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000); + /// Serial peripheral interface + pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400); + /// Serial audio interface + pub const SAI = @ptrCast(*volatile types.SAI, 0x40015800); + /// LCD-TFT Controller + pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800); + /// General-purpose I/Os + pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000); + /// General-purpose I/Os + pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400); + /// General-purpose I/Os + pub const GPIOC = @ptrCast(*volatile types.GPIOK, 0x40020800); + /// General-purpose I/Os + pub const GPIOD = @ptrCast(*volatile types.GPIOK, 0x40020c00); + /// General-purpose I/Os + pub const GPIOE = @ptrCast(*volatile types.GPIOK, 0x40021000); + /// General-purpose I/Os + pub const GPIOF = @ptrCast(*volatile types.GPIOK, 0x40021400); + /// General-purpose I/Os + pub const GPIOG = @ptrCast(*volatile types.GPIOK, 0x40021800); + /// General-purpose I/Os + pub const GPIOH = @ptrCast(*volatile types.GPIOK, 0x40021c00); + /// General-purpose I/Os + pub const GPIOI = @ptrCast(*volatile types.GPIOK, 0x40022000); + /// General-purpose I/Os + pub const GPIOJ = @ptrCast(*volatile types.GPIOK, 0x40022400); + /// General-purpose I/Os + pub const GPIOK = @ptrCast(*volatile types.GPIOK, 0x40022800); + /// Cryptographic processor + pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000); + /// Reset and clock control + pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800); + /// FLASH + pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00); + /// DMA controller + pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000); + /// DMA controller + pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400); + /// Ethernet: media access control (MAC) + pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000); + /// Ethernet: MAC management counters + pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100); + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700); + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000); + /// DMA2D controller + pub const DMA2D = @ptrCast(*volatile types.DMA2D, 0x4002b000); + /// USB on the go high speed + pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000); + /// USB on the go high speed + pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400); + /// USB on the go high speed + pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800); + /// USB on the go high speed + pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00); + /// USB on the go full speed + pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000); + /// USB on the go full speed + pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400); + /// USB on the go full speed + pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800); + /// USB on the go full speed + pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00); + /// Digital camera interface + pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000); + /// Cryptographic processor + pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000); + /// Hash processor + pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400); + /// Random number generator + pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800); + /// Flexible memory controller + pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000000); + /// System control block ACTLR + pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008); + /// SysTick timer + pub const STK = @ptrCast(*volatile types.STK, 0xe000e010); + /// Nested Vectored Interrupt Controller + pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100); + /// System control block + pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00); + /// Floating point unit CPACR + pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88); + /// Memory protection unit + pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90); + /// Nested vectored interrupt controller + pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00); + /// Floting point unit + pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34); + /// Debug support + pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000); + }; + }; +}; + +pub const types = struct { + /// Random number generator + pub const RNG = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Random number generator enable + RNGEN: u1, + /// Interrupt enable + IE: u1, + padding: u28, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data ready + DRDY: u1, + /// Clock error current status + CECS: u1, + /// Seed error current status + SECS: u1, + reserved5: u2, + /// Clock error interrupt status + CEIS: u1, + /// Seed error interrupt status + SEIS: u1, + padding: u25, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Random data + RNDATA: u32, + }), + }; + + /// Hash processor + pub const HASH = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Initialize message digest calculation + INIT: u1, + /// DMA enable + DMAE: u1, + /// Data type selection + DATATYPE: u2, + /// Mode selection + MODE: u1, + /// Algorithm selection + ALGO0: u1, + /// Number of words already pushed + NBW: u4, + /// DIN not empty + DINNE: u1, + /// Multiple DMA Transfers + MDMAT: u1, + reserved16: u2, + /// Long key selection + LKEY: u1, + reserved18: u1, + /// ALGO + ALGO1: u1, + padding: u13, + }), + /// data input register + DIN: mmio.Mmio(packed struct(u32) { + /// Data input + DATAIN: u32, + }), + /// start register + STR: mmio.Mmio(packed struct(u32) { + /// Number of valid bits in the last word of the message + NBLW: u5, + reserved8: u3, + /// Digest calculation + DCAL: u1, + padding: u23, + }), + /// digest registers + HR0: mmio.Mmio(packed struct(u32) { + /// H0 + H0: u32, + }), + /// digest registers + HR1: mmio.Mmio(packed struct(u32) { + /// H1 + H1: u32, + }), + /// digest registers + HR2: mmio.Mmio(packed struct(u32) { + /// H2 + H2: u32, + }), + /// digest registers + HR3: mmio.Mmio(packed struct(u32) { + /// H3 + H3: u32, + }), + /// digest registers + HR4: mmio.Mmio(packed struct(u32) { + /// H4 + H4: u32, + }), + /// interrupt enable register + IMR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt enable + DINIE: u1, + /// Digest calculation completion interrupt enable + DCIE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Data input interrupt status + DINIS: u1, + /// Digest calculation completion interrupt status + DCIS: u1, + /// DMA Status + DMAS: u1, + /// Busy bit + BUSY: u1, + padding: u28, + }), + reserved248: [208]u8, + /// context swap registers + CSR0: mmio.Mmio(packed struct(u32) { + /// CSR0 + CSR0: u32, + }), + /// context swap registers + CSR1: mmio.Mmio(packed struct(u32) { + /// CSR1 + CSR1: u32, + }), + /// context swap registers + CSR2: mmio.Mmio(packed struct(u32) { + /// CSR2 + CSR2: u32, + }), + /// context swap registers + CSR3: mmio.Mmio(packed struct(u32) { + /// CSR3 + CSR3: u32, + }), + /// context swap registers + CSR4: mmio.Mmio(packed struct(u32) { + /// CSR4 + CSR4: u32, + }), + /// context swap registers + CSR5: mmio.Mmio(packed struct(u32) { + /// CSR5 + CSR5: u32, + }), + /// context swap registers + CSR6: mmio.Mmio(packed struct(u32) { + /// CSR6 + CSR6: u32, + }), + /// context swap registers + CSR7: mmio.Mmio(packed struct(u32) { + /// CSR7 + CSR7: u32, + }), + /// context swap registers + CSR8: mmio.Mmio(packed struct(u32) { + /// CSR8 + CSR8: u32, + }), + /// context swap registers + CSR9: mmio.Mmio(packed struct(u32) { + /// CSR9 + CSR9: u32, + }), + /// context swap registers + CSR10: mmio.Mmio(packed struct(u32) { + /// CSR10 + CSR10: u32, + }), + /// context swap registers + CSR11: mmio.Mmio(packed struct(u32) { + /// CSR11 + CSR11: u32, + }), + /// context swap registers + CSR12: mmio.Mmio(packed struct(u32) { + /// CSR12 + CSR12: u32, + }), + /// context swap registers + CSR13: mmio.Mmio(packed struct(u32) { + /// CSR13 + CSR13: u32, + }), + /// context swap registers + CSR14: mmio.Mmio(packed struct(u32) { + /// CSR14 + CSR14: u32, + }), + /// context swap registers + CSR15: mmio.Mmio(packed struct(u32) { + /// CSR15 + CSR15: u32, + }), + /// context swap registers + CSR16: mmio.Mmio(packed struct(u32) { + /// CSR16 + CSR16: u32, + }), + /// context swap registers + CSR17: mmio.Mmio(packed struct(u32) { + /// CSR17 + CSR17: u32, + }), + /// context swap registers + CSR18: mmio.Mmio(packed struct(u32) { + /// CSR18 + CSR18: u32, + }), + /// context swap registers + CSR19: mmio.Mmio(packed struct(u32) { + /// CSR19 + CSR19: u32, + }), + /// context swap registers + CSR20: mmio.Mmio(packed struct(u32) { + /// CSR20 + CSR20: u32, + }), + /// context swap registers + CSR21: mmio.Mmio(packed struct(u32) { + /// CSR21 + CSR21: u32, + }), + /// context swap registers + CSR22: mmio.Mmio(packed struct(u32) { + /// CSR22 + CSR22: u32, + }), + /// context swap registers + CSR23: mmio.Mmio(packed struct(u32) { + /// CSR23 + CSR23: u32, + }), + /// context swap registers + CSR24: mmio.Mmio(packed struct(u32) { + /// CSR24 + CSR24: u32, + }), + /// context swap registers + CSR25: mmio.Mmio(packed struct(u32) { + /// CSR25 + CSR25: u32, + }), + /// context swap registers + CSR26: mmio.Mmio(packed struct(u32) { + /// CSR26 + CSR26: u32, + }), + /// context swap registers + CSR27: mmio.Mmio(packed struct(u32) { + /// CSR27 + CSR27: u32, + }), + /// context swap registers + CSR28: mmio.Mmio(packed struct(u32) { + /// CSR28 + CSR28: u32, + }), + /// context swap registers + CSR29: mmio.Mmio(packed struct(u32) { + /// CSR29 + CSR29: u32, + }), + /// context swap registers + CSR30: mmio.Mmio(packed struct(u32) { + /// CSR30 + CSR30: u32, + }), + /// context swap registers + CSR31: mmio.Mmio(packed struct(u32) { + /// CSR31 + CSR31: u32, + }), + /// context swap registers + CSR32: mmio.Mmio(packed struct(u32) { + /// CSR32 + CSR32: u32, + }), + /// context swap registers + CSR33: mmio.Mmio(packed struct(u32) { + /// CSR33 + CSR33: u32, + }), + /// context swap registers + CSR34: mmio.Mmio(packed struct(u32) { + /// CSR34 + CSR34: u32, + }), + /// context swap registers + CSR35: mmio.Mmio(packed struct(u32) { + /// CSR35 + CSR35: u32, + }), + /// context swap registers + CSR36: mmio.Mmio(packed struct(u32) { + /// CSR36 + CSR36: u32, + }), + /// context swap registers + CSR37: mmio.Mmio(packed struct(u32) { + /// CSR37 + CSR37: u32, + }), + /// context swap registers + CSR38: mmio.Mmio(packed struct(u32) { + /// CSR38 + CSR38: u32, + }), + /// context swap registers + CSR39: mmio.Mmio(packed struct(u32) { + /// CSR39 + CSR39: u32, + }), + /// context swap registers + CSR40: mmio.Mmio(packed struct(u32) { + /// CSR40 + CSR40: u32, + }), + /// context swap registers + CSR41: mmio.Mmio(packed struct(u32) { + /// CSR41 + CSR41: u32, + }), + /// context swap registers + CSR42: mmio.Mmio(packed struct(u32) { + /// CSR42 + CSR42: u32, + }), + /// context swap registers + CSR43: mmio.Mmio(packed struct(u32) { + /// CSR43 + CSR43: u32, + }), + /// context swap registers + CSR44: mmio.Mmio(packed struct(u32) { + /// CSR44 + CSR44: u32, + }), + /// context swap registers + CSR45: mmio.Mmio(packed struct(u32) { + /// CSR45 + CSR45: u32, + }), + /// context swap registers + CSR46: mmio.Mmio(packed struct(u32) { + /// CSR46 + CSR46: u32, + }), + /// context swap registers + CSR47: mmio.Mmio(packed struct(u32) { + /// CSR47 + CSR47: u32, + }), + /// context swap registers + CSR48: mmio.Mmio(packed struct(u32) { + /// CSR48 + CSR48: u32, + }), + /// context swap registers + CSR49: mmio.Mmio(packed struct(u32) { + /// CSR49 + CSR49: u32, + }), + /// context swap registers + CSR50: mmio.Mmio(packed struct(u32) { + /// CSR50 + CSR50: u32, + }), + /// context swap registers + CSR51: mmio.Mmio(packed struct(u32) { + /// CSR51 + CSR51: u32, + }), + /// context swap registers + CSR52: mmio.Mmio(packed struct(u32) { + /// CSR52 + CSR52: u32, + }), + /// context swap registers + CSR53: mmio.Mmio(packed struct(u32) { + /// CSR53 + CSR53: u32, + }), + reserved784: [320]u8, + /// HASH digest register + HASH_HR0: mmio.Mmio(packed struct(u32) { + /// H0 + H0: u32, + }), + /// read-only + HASH_HR1: mmio.Mmio(packed struct(u32) { + /// H1 + H1: u32, + }), + /// read-only + HASH_HR2: mmio.Mmio(packed struct(u32) { + /// H2 + H2: u32, + }), + /// read-only + HASH_HR3: mmio.Mmio(packed struct(u32) { + /// H3 + H3: u32, + }), + /// read-only + HASH_HR4: mmio.Mmio(packed struct(u32) { + /// H4 + H4: u32, + }), + /// read-only + HASH_HR5: mmio.Mmio(packed struct(u32) { + /// H5 + H5: u32, + }), + /// read-only + HASH_HR6: mmio.Mmio(packed struct(u32) { + /// H6 + H6: u32, + }), + /// read-only + HASH_HR7: mmio.Mmio(packed struct(u32) { + /// H7 + H7: u32, + }), + }; + + /// Cryptographic processor + pub const CRYP = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Algorithm direction + ALGODIR: u1, + /// Algorithm mode + ALGOMODE0: u3, + /// Data type selection + DATATYPE: u2, + /// Key size selection (AES mode only) + KEYSIZE: u2, + reserved14: u4, + /// FIFO flush + FFLUSH: u1, + /// Cryptographic processor enable + CRYPEN: u1, + /// GCM_CCMPH + GCM_CCMPH: u2, + reserved19: u1, + /// ALGOMODE + ALGOMODE3: u1, + padding: u12, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Input FIFO empty + IFEM: u1, + /// Input FIFO not full + IFNF: u1, + /// Output FIFO not empty + OFNE: u1, + /// Output FIFO full + OFFU: u1, + /// Busy bit + BUSY: u1, + padding: u27, + }), + /// data input register + DIN: mmio.Mmio(packed struct(u32) { + /// Data input + DATAIN: u32, + }), + /// data output register + DOUT: mmio.Mmio(packed struct(u32) { + /// Data output + DATAOUT: u32, + }), + /// DMA control register + DMACR: mmio.Mmio(packed struct(u32) { + /// DMA input enable + DIEN: u1, + /// DMA output enable + DOEN: u1, + padding: u30, + }), + /// interrupt mask set/clear register + IMSCR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service interrupt mask + INIM: u1, + /// Output FIFO service interrupt mask + OUTIM: u1, + padding: u30, + }), + /// raw interrupt status register + RISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service raw interrupt status + INRIS: u1, + /// Output FIFO service raw interrupt status + OUTRIS: u1, + padding: u30, + }), + /// masked interrupt status register + MISR: mmio.Mmio(packed struct(u32) { + /// Input FIFO service masked interrupt status + INMIS: u1, + /// Output FIFO service masked interrupt status + OUTMIS: u1, + padding: u30, + }), + /// key registers + K0LR: mmio.Mmio(packed struct(u32) { + /// b224 + b224: u1, + /// b225 + b225: u1, + /// b226 + b226: u1, + /// b227 + b227: u1, + /// b228 + b228: u1, + /// b229 + b229: u1, + /// b230 + b230: u1, + /// b231 + b231: u1, + /// b232 + b232: u1, + /// b233 + b233: u1, + /// b234 + b234: u1, + /// b235 + b235: u1, + /// b236 + b236: u1, + /// b237 + b237: u1, + /// b238 + b238: u1, + /// b239 + b239: u1, + /// b240 + b240: u1, + /// b241 + b241: u1, + /// b242 + b242: u1, + /// b243 + b243: u1, + /// b244 + b244: u1, + /// b245 + b245: u1, + /// b246 + b246: u1, + /// b247 + b247: u1, + /// b248 + b248: u1, + /// b249 + b249: u1, + /// b250 + b250: u1, + /// b251 + b251: u1, + /// b252 + b252: u1, + /// b253 + b253: u1, + /// b254 + b254: u1, + /// b255 + b255: u1, + }), + /// key registers + K0RR: mmio.Mmio(packed struct(u32) { + /// b192 + b192: u1, + /// b193 + b193: u1, + /// b194 + b194: u1, + /// b195 + b195: u1, + /// b196 + b196: u1, + /// b197 + b197: u1, + /// b198 + b198: u1, + /// b199 + b199: u1, + /// b200 + b200: u1, + /// b201 + b201: u1, + /// b202 + b202: u1, + /// b203 + b203: u1, + /// b204 + b204: u1, + /// b205 + b205: u1, + /// b206 + b206: u1, + /// b207 + b207: u1, + /// b208 + b208: u1, + /// b209 + b209: u1, + /// b210 + b210: u1, + /// b211 + b211: u1, + /// b212 + b212: u1, + /// b213 + b213: u1, + /// b214 + b214: u1, + /// b215 + b215: u1, + /// b216 + b216: u1, + /// b217 + b217: u1, + /// b218 + b218: u1, + /// b219 + b219: u1, + /// b220 + b220: u1, + /// b221 + b221: u1, + /// b222 + b222: u1, + /// b223 + b223: u1, + }), + /// key registers + K1LR: mmio.Mmio(packed struct(u32) { + /// b160 + b160: u1, + /// b161 + b161: u1, + /// b162 + b162: u1, + /// b163 + b163: u1, + /// b164 + b164: u1, + /// b165 + b165: u1, + /// b166 + b166: u1, + /// b167 + b167: u1, + /// b168 + b168: u1, + /// b169 + b169: u1, + /// b170 + b170: u1, + /// b171 + b171: u1, + /// b172 + b172: u1, + /// b173 + b173: u1, + /// b174 + b174: u1, + /// b175 + b175: u1, + /// b176 + b176: u1, + /// b177 + b177: u1, + /// b178 + b178: u1, + /// b179 + b179: u1, + /// b180 + b180: u1, + /// b181 + b181: u1, + /// b182 + b182: u1, + /// b183 + b183: u1, + /// b184 + b184: u1, + /// b185 + b185: u1, + /// b186 + b186: u1, + /// b187 + b187: u1, + /// b188 + b188: u1, + /// b189 + b189: u1, + /// b190 + b190: u1, + /// b191 + b191: u1, + }), + /// key registers + K1RR: mmio.Mmio(packed struct(u32) { + /// b128 + b128: u1, + /// b129 + b129: u1, + /// b130 + b130: u1, + /// b131 + b131: u1, + /// b132 + b132: u1, + /// b133 + b133: u1, + /// b134 + b134: u1, + /// b135 + b135: u1, + /// b136 + b136: u1, + /// b137 + b137: u1, + /// b138 + b138: u1, + /// b139 + b139: u1, + /// b140 + b140: u1, + /// b141 + b141: u1, + /// b142 + b142: u1, + /// b143 + b143: u1, + /// b144 + b144: u1, + /// b145 + b145: u1, + /// b146 + b146: u1, + /// b147 + b147: u1, + /// b148 + b148: u1, + /// b149 + b149: u1, + /// b150 + b150: u1, + /// b151 + b151: u1, + /// b152 + b152: u1, + /// b153 + b153: u1, + /// b154 + b154: u1, + /// b155 + b155: u1, + /// b156 + b156: u1, + /// b157 + b157: u1, + /// b158 + b158: u1, + /// b159 + b159: u1, + }), + /// key registers + K2LR: mmio.Mmio(packed struct(u32) { + /// b96 + b96: u1, + /// b97 + b97: u1, + /// b98 + b98: u1, + /// b99 + b99: u1, + /// b100 + b100: u1, + /// b101 + b101: u1, + /// b102 + b102: u1, + /// b103 + b103: u1, + /// b104 + b104: u1, + /// b105 + b105: u1, + /// b106 + b106: u1, + /// b107 + b107: u1, + /// b108 + b108: u1, + /// b109 + b109: u1, + /// b110 + b110: u1, + /// b111 + b111: u1, + /// b112 + b112: u1, + /// b113 + b113: u1, + /// b114 + b114: u1, + /// b115 + b115: u1, + /// b116 + b116: u1, + /// b117 + b117: u1, + /// b118 + b118: u1, + /// b119 + b119: u1, + /// b120 + b120: u1, + /// b121 + b121: u1, + /// b122 + b122: u1, + /// b123 + b123: u1, + /// b124 + b124: u1, + /// b125 + b125: u1, + /// b126 + b126: u1, + /// b127 + b127: u1, + }), + /// key registers + K2RR: mmio.Mmio(packed struct(u32) { + /// b64 + b64: u1, + /// b65 + b65: u1, + /// b66 + b66: u1, + /// b67 + b67: u1, + /// b68 + b68: u1, + /// b69 + b69: u1, + /// b70 + b70: u1, + /// b71 + b71: u1, + /// b72 + b72: u1, + /// b73 + b73: u1, + /// b74 + b74: u1, + /// b75 + b75: u1, + /// b76 + b76: u1, + /// b77 + b77: u1, + /// b78 + b78: u1, + /// b79 + b79: u1, + /// b80 + b80: u1, + /// b81 + b81: u1, + /// b82 + b82: u1, + /// b83 + b83: u1, + /// b84 + b84: u1, + /// b85 + b85: u1, + /// b86 + b86: u1, + /// b87 + b87: u1, + /// b88 + b88: u1, + /// b89 + b89: u1, + /// b90 + b90: u1, + /// b91 + b91: u1, + /// b92 + b92: u1, + /// b93 + b93: u1, + /// b94 + b94: u1, + /// b95 + b95: u1, + }), + /// key registers + K3LR: mmio.Mmio(packed struct(u32) { + /// b32 + b32: u1, + /// b33 + b33: u1, + /// b34 + b34: u1, + /// b35 + b35: u1, + /// b36 + b36: u1, + /// b37 + b37: u1, + /// b38 + b38: u1, + /// b39 + b39: u1, + /// b40 + b40: u1, + /// b41 + b41: u1, + /// b42 + b42: u1, + /// b43 + b43: u1, + /// b44 + b44: u1, + /// b45 + b45: u1, + /// b46 + b46: u1, + /// b47 + b47: u1, + /// b48 + b48: u1, + /// b49 + b49: u1, + /// b50 + b50: u1, + /// b51 + b51: u1, + /// b52 + b52: u1, + /// b53 + b53: u1, + /// b54 + b54: u1, + /// b55 + b55: u1, + /// b56 + b56: u1, + /// b57 + b57: u1, + /// b58 + b58: u1, + /// b59 + b59: u1, + /// b60 + b60: u1, + /// b61 + b61: u1, + /// b62 + b62: u1, + /// b63 + b63: u1, + }), + /// key registers + K3RR: mmio.Mmio(packed struct(u32) { + /// b0 + b0: u1, + /// b1 + b1: u1, + /// b2 + b2: u1, + /// b3 + b3: u1, + /// b4 + b4: u1, + /// b5 + b5: u1, + /// b6 + b6: u1, + /// b7 + b7: u1, + /// b8 + b8: u1, + /// b9 + b9: u1, + /// b10 + b10: u1, + /// b11 + b11: u1, + /// b12 + b12: u1, + /// b13 + b13: u1, + /// b14 + b14: u1, + /// b15 + b15: u1, + /// b16 + b16: u1, + /// b17 + b17: u1, + /// b18 + b18: u1, + /// b19 + b19: u1, + /// b20 + b20: u1, + /// b21 + b21: u1, + /// b22 + b22: u1, + /// b23 + b23: u1, + /// b24 + b24: u1, + /// b25 + b25: u1, + /// b26 + b26: u1, + /// b27 + b27: u1, + /// b28 + b28: u1, + /// b29 + b29: u1, + /// b30 + b30: u1, + /// b31 + b31: u1, + }), + /// initialization vector registers + IV0LR: mmio.Mmio(packed struct(u32) { + /// IV31 + IV31: u1, + /// IV30 + IV30: u1, + /// IV29 + IV29: u1, + /// IV28 + IV28: u1, + /// IV27 + IV27: u1, + /// IV26 + IV26: u1, + /// IV25 + IV25: u1, + /// IV24 + IV24: u1, + /// IV23 + IV23: u1, + /// IV22 + IV22: u1, + /// IV21 + IV21: u1, + /// IV20 + IV20: u1, + /// IV19 + IV19: u1, + /// IV18 + IV18: u1, + /// IV17 + IV17: u1, + /// IV16 + IV16: u1, + /// IV15 + IV15: u1, + /// IV14 + IV14: u1, + /// IV13 + IV13: u1, + /// IV12 + IV12: u1, + /// IV11 + IV11: u1, + /// IV10 + IV10: u1, + /// IV9 + IV9: u1, + /// IV8 + IV8: u1, + /// IV7 + IV7: u1, + /// IV6 + IV6: u1, + /// IV5 + IV5: u1, + /// IV4 + IV4: u1, + /// IV3 + IV3: u1, + /// IV2 + IV2: u1, + /// IV1 + IV1: u1, + /// IV0 + IV0: u1, + }), + /// initialization vector registers + IV0RR: mmio.Mmio(packed struct(u32) { + /// IV63 + IV63: u1, + /// IV62 + IV62: u1, + /// IV61 + IV61: u1, + /// IV60 + IV60: u1, + /// IV59 + IV59: u1, + /// IV58 + IV58: u1, + /// IV57 + IV57: u1, + /// IV56 + IV56: u1, + /// IV55 + IV55: u1, + /// IV54 + IV54: u1, + /// IV53 + IV53: u1, + /// IV52 + IV52: u1, + /// IV51 + IV51: u1, + /// IV50 + IV50: u1, + /// IV49 + IV49: u1, + /// IV48 + IV48: u1, + /// IV47 + IV47: u1, + /// IV46 + IV46: u1, + /// IV45 + IV45: u1, + /// IV44 + IV44: u1, + /// IV43 + IV43: u1, + /// IV42 + IV42: u1, + /// IV41 + IV41: u1, + /// IV40 + IV40: u1, + /// IV39 + IV39: u1, + /// IV38 + IV38: u1, + /// IV37 + IV37: u1, + /// IV36 + IV36: u1, + /// IV35 + IV35: u1, + /// IV34 + IV34: u1, + /// IV33 + IV33: u1, + /// IV32 + IV32: u1, + }), + /// initialization vector registers + IV1LR: mmio.Mmio(packed struct(u32) { + /// IV95 + IV95: u1, + /// IV94 + IV94: u1, + /// IV93 + IV93: u1, + /// IV92 + IV92: u1, + /// IV91 + IV91: u1, + /// IV90 + IV90: u1, + /// IV89 + IV89: u1, + /// IV88 + IV88: u1, + /// IV87 + IV87: u1, + /// IV86 + IV86: u1, + /// IV85 + IV85: u1, + /// IV84 + IV84: u1, + /// IV83 + IV83: u1, + /// IV82 + IV82: u1, + /// IV81 + IV81: u1, + /// IV80 + IV80: u1, + /// IV79 + IV79: u1, + /// IV78 + IV78: u1, + /// IV77 + IV77: u1, + /// IV76 + IV76: u1, + /// IV75 + IV75: u1, + /// IV74 + IV74: u1, + /// IV73 + IV73: u1, + /// IV72 + IV72: u1, + /// IV71 + IV71: u1, + /// IV70 + IV70: u1, + /// IV69 + IV69: u1, + /// IV68 + IV68: u1, + /// IV67 + IV67: u1, + /// IV66 + IV66: u1, + /// IV65 + IV65: u1, + /// IV64 + IV64: u1, + }), + /// initialization vector registers + IV1RR: mmio.Mmio(packed struct(u32) { + /// IV127 + IV127: u1, + /// IV126 + IV126: u1, + /// IV125 + IV125: u1, + /// IV124 + IV124: u1, + /// IV123 + IV123: u1, + /// IV122 + IV122: u1, + /// IV121 + IV121: u1, + /// IV120 + IV120: u1, + /// IV119 + IV119: u1, + /// IV118 + IV118: u1, + /// IV117 + IV117: u1, + /// IV116 + IV116: u1, + /// IV115 + IV115: u1, + /// IV114 + IV114: u1, + /// IV113 + IV113: u1, + /// IV112 + IV112: u1, + /// IV111 + IV111: u1, + /// IV110 + IV110: u1, + /// IV109 + IV109: u1, + /// IV108 + IV108: u1, + /// IV107 + IV107: u1, + /// IV106 + IV106: u1, + /// IV105 + IV105: u1, + /// IV104 + IV104: u1, + /// IV103 + IV103: u1, + /// IV102 + IV102: u1, + /// IV101 + IV101: u1, + /// IV100 + IV100: u1, + /// IV99 + IV99: u1, + /// IV98 + IV98: u1, + /// IV97 + IV97: u1, + /// IV96 + IV96: u1, + }), + /// context swap register + CSGCMCCM0R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM0R + CSGCMCCM0R: u32, + }), + /// context swap register + CSGCMCCM1R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM1R + CSGCMCCM1R: u32, + }), + /// context swap register + CSGCMCCM2R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM2R + CSGCMCCM2R: u32, + }), + /// context swap register + CSGCMCCM3R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM3R + CSGCMCCM3R: u32, + }), + /// context swap register + CSGCMCCM4R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM4R + CSGCMCCM4R: u32, + }), + /// context swap register + CSGCMCCM5R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM5R + CSGCMCCM5R: u32, + }), + /// context swap register + CSGCMCCM6R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM6R + CSGCMCCM6R: u32, + }), + /// context swap register + CSGCMCCM7R: mmio.Mmio(packed struct(u32) { + /// CSGCMCCM7R + CSGCMCCM7R: u32, + }), + /// context swap register + CSGCM0R: mmio.Mmio(packed struct(u32) { + /// CSGCM0R + CSGCM0R: u32, + }), + /// context swap register + CSGCM1R: mmio.Mmio(packed struct(u32) { + /// CSGCM1R + CSGCM1R: u32, + }), + /// context swap register + CSGCM2R: mmio.Mmio(packed struct(u32) { + /// CSGCM2R + CSGCM2R: u32, + }), + /// context swap register + CSGCM3R: mmio.Mmio(packed struct(u32) { + /// CSGCM3R + CSGCM3R: u32, + }), + /// context swap register + CSGCM4R: mmio.Mmio(packed struct(u32) { + /// CSGCM4R + CSGCM4R: u32, + }), + /// context swap register + CSGCM5R: mmio.Mmio(packed struct(u32) { + /// CSGCM5R + CSGCM5R: u32, + }), + /// context swap register + CSGCM6R: mmio.Mmio(packed struct(u32) { + /// CSGCM6R + CSGCM6R: u32, + }), + /// context swap register + CSGCM7R: mmio.Mmio(packed struct(u32) { + /// CSGCM7R + CSGCM7R: u32, + }), + }; + + /// Digital camera interface + pub const DCMI = extern struct { + /// control register 1 + CR: mmio.Mmio(packed struct(u32) { + /// Capture enable + CAPTURE: u1, + /// Capture mode + CM: u1, + /// Crop feature + CROP: u1, + /// JPEG format + JPEG: u1, + /// Embedded synchronization select + ESS: u1, + /// Pixel clock polarity + PCKPOL: u1, + /// Horizontal synchronization polarity + HSPOL: u1, + /// Vertical synchronization polarity + VSPOL: u1, + /// Frame capture rate control + FCRC: u2, + /// Extended data mode + EDM: u2, + reserved14: u2, + /// DCMI enable + ENABLE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// HSYNC + HSYNC: u1, + /// VSYNC + VSYNC: u1, + /// FIFO not empty + FNE: u1, + padding: u29, + }), + /// raw interrupt status register + RIS: mmio.Mmio(packed struct(u32) { + /// Capture complete raw interrupt status + FRAME_RIS: u1, + /// Overrun raw interrupt status + OVR_RIS: u1, + /// Synchronization error raw interrupt status + ERR_RIS: u1, + /// VSYNC raw interrupt status + VSYNC_RIS: u1, + /// Line raw interrupt status + LINE_RIS: u1, + padding: u27, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt enable + FRAME_IE: u1, + /// Overrun interrupt enable + OVR_IE: u1, + /// Synchronization error interrupt enable + ERR_IE: u1, + /// VSYNC interrupt enable + VSYNC_IE: u1, + /// Line interrupt enable + LINE_IE: u1, + padding: u27, + }), + /// masked interrupt status register + MIS: mmio.Mmio(packed struct(u32) { + /// Capture complete masked interrupt status + FRAME_MIS: u1, + /// Overrun masked interrupt status + OVR_MIS: u1, + /// Synchronization error masked interrupt status + ERR_MIS: u1, + /// VSYNC masked interrupt status + VSYNC_MIS: u1, + /// Line masked interrupt status + LINE_MIS: u1, + padding: u27, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// Capture complete interrupt status clear + FRAME_ISC: u1, + /// Overrun interrupt status clear + OVR_ISC: u1, + /// Synchronization error interrupt status clear + ERR_ISC: u1, + /// Vertical synch interrupt status clear + VSYNC_ISC: u1, + /// line interrupt status clear + LINE_ISC: u1, + padding: u27, + }), + /// embedded synchronization code register + ESCR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter code + FSC: u8, + /// Line start delimiter code + LSC: u8, + /// Line end delimiter code + LEC: u8, + /// Frame end delimiter code + FEC: u8, + }), + /// embedded synchronization unmask register + ESUR: mmio.Mmio(packed struct(u32) { + /// Frame start delimiter unmask + FSU: u8, + /// Line start delimiter unmask + LSU: u8, + /// Line end delimiter unmask + LEU: u8, + /// Frame end delimiter unmask + FEU: u8, + }), + /// crop window start + CWSTRT: mmio.Mmio(packed struct(u32) { + /// Horizontal offset count + HOFFCNT: u14, + reserved16: u2, + /// Vertical start line count + VST: u13, + padding: u3, + }), + /// crop window size + CWSIZE: mmio.Mmio(packed struct(u32) { + /// Capture count + CAPCNT: u14, + reserved16: u2, + /// Vertical line count + VLINE: u14, + padding: u2, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + Byte0: u8, + /// Data byte 1 + Byte1: u8, + /// Data byte 2 + Byte2: u8, + /// Data byte 3 + Byte3: u8, + }), + }; + + /// Flexible memory controller + pub const FMC = extern struct { + /// SRAM/NOR-Flash chip-select control register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + reserved11: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + /// CCLKEN + CCLKEN: u1, + padding: u11, + }), + /// SRAM/NOR-Flash chip-select timing register 1 + BTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 2 + BCR2: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 2 + BTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 3 + BCR3: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 3 + BTR3: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + /// SRAM/NOR-Flash chip-select control register 4 + BCR4: mmio.Mmio(packed struct(u32) { + /// MBKEN + MBKEN: u1, + /// MUXEN + MUXEN: u1, + /// MTYP + MTYP: u2, + /// MWID + MWID: u2, + /// FACCEN + FACCEN: u1, + reserved8: u1, + /// BURSTEN + BURSTEN: u1, + /// WAITPOL + WAITPOL: u1, + /// WRAPMOD + WRAPMOD: u1, + /// WAITCFG + WAITCFG: u1, + /// WREN + WREN: u1, + /// WAITEN + WAITEN: u1, + /// EXTMOD + EXTMOD: u1, + /// ASYNCWAIT + ASYNCWAIT: u1, + reserved19: u3, + /// CBURSTRW + CBURSTRW: u1, + padding: u12, + }), + /// SRAM/NOR-Flash chip-select timing register 4 + BTR4: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + /// BUSTURN + BUSTURN: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved96: [64]u8, + /// PC Card/NAND Flash control register 2 + PCR2: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 2 + PMEM2: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 2 + PATT2: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved116: [4]u8, + /// ECC result register 2 + ECCR2: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved128: [8]u8, + /// PC Card/NAND Flash control register 3 + PCR3: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 3 + SR3: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 3 + PMEM3: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 3 + PATT3: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + reserved148: [4]u8, + /// ECC result register 3 + ECCR3: mmio.Mmio(packed struct(u32) { + /// ECCx + ECCx: u32, + }), + reserved160: [8]u8, + /// PC Card/NAND Flash control register 4 + PCR4: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// PWAITEN + PWAITEN: u1, + /// PBKEN + PBKEN: u1, + /// PTYP + PTYP: u1, + /// PWID + PWID: u2, + /// ECCEN + ECCEN: u1, + reserved9: u2, + /// TCLR + TCLR: u4, + /// TAR + TAR: u4, + /// ECCPS + ECCPS: u3, + padding: u12, + }), + /// FIFO status and interrupt register 4 + SR4: mmio.Mmio(packed struct(u32) { + /// IRS + IRS: u1, + /// ILS + ILS: u1, + /// IFS + IFS: u1, + /// IREN + IREN: u1, + /// ILEN + ILEN: u1, + /// IFEN + IFEN: u1, + /// FEMPT + FEMPT: u1, + padding: u25, + }), + /// Common memory space timing register 4 + PMEM4: mmio.Mmio(packed struct(u32) { + /// MEMSETx + MEMSETx: u8, + /// MEMWAITx + MEMWAITx: u8, + /// MEMHOLDx + MEMHOLDx: u8, + /// MEMHIZx + MEMHIZx: u8, + }), + /// Attribute memory space timing register 4 + PATT4: mmio.Mmio(packed struct(u32) { + /// ATTSETx + ATTSETx: u8, + /// ATTWAITx + ATTWAITx: u8, + /// ATTHOLDx + ATTHOLDx: u8, + /// ATTHIZx + ATTHIZx: u8, + }), + /// I/O space timing register 4 + PIO4: mmio.Mmio(packed struct(u32) { + /// IOSETx + IOSETx: u8, + /// IOWAITx + IOWAITx: u8, + /// IOHOLDx + IOHOLDx: u8, + /// IOHIZx + IOHIZx: u8, + }), + reserved260: [80]u8, + /// SRAM/NOR-Flash write timing registers 1 + BWTR1: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved268: [4]u8, + /// SRAM/NOR-Flash write timing registers 2 + BWTR2: mmio.Mmio(packed struct(u32) { + /// ADDSET + ADDSET: u4, + /// ADDHLD + ADDHLD: u4, + /// DATAST + DATAST: u8, + reserved20: u4, + /// CLKDIV + CLKDIV: u4, + /// DATLAT + DATLAT: u4, + /// ACCMOD + ACCMOD: u2, + padding: u2, + }), + reserved320: [48]u8, + /// SDRAM Control Register 1 + SDCR1: mmio.Mmio(packed struct(u32) { + /// Number of column address bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding: u17, + }), + /// SDRAM Control Register 2 + SDCR2: mmio.Mmio(packed struct(u32) { + /// Number of column address bits + NC: u2, + /// Number of row address bits + NR: u2, + /// Memory data bus width + MWID: u2, + /// Number of internal banks + NB: u1, + /// CAS latency + CAS: u2, + /// Write protection + WP: u1, + /// SDRAM clock configuration + SDCLK: u2, + /// Burst read + RBURST: u1, + /// Read pipe + RPIPE: u2, + padding: u17, + }), + /// SDRAM Timing register 1 + SDTR1: mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding: u4, + }), + /// SDRAM Timing register 2 + SDTR2: mmio.Mmio(packed struct(u32) { + /// Load Mode Register to Active + TMRD: u4, + /// Exit self-refresh delay + TXSR: u4, + /// Self refresh time + TRAS: u4, + /// Row cycle delay + TRC: u4, + /// Recovery delay + TWR: u4, + /// Row precharge delay + TRP: u4, + /// Row to column delay + TRCD: u4, + padding: u4, + }), + /// SDRAM Command Mode register + SDCMR: mmio.Mmio(packed struct(u32) { + /// Command mode + MODE: u3, + /// Command target bank 2 + CTB2: u1, + /// Command target bank 1 + CTB1: u1, + /// Number of Auto-refresh + NRFS: u4, + /// Mode Register definition + MRD: u13, + padding: u10, + }), + /// SDRAM Refresh Timer register + SDRTR: mmio.Mmio(packed struct(u32) { + /// Clear Refresh error flag + CRE: u1, + /// Refresh Timer Count + COUNT: u13, + /// RES Interrupt Enable + REIE: u1, + padding: u17, + }), + /// SDRAM Status register + SDSR: mmio.Mmio(packed struct(u32) { + /// Refresh error flag + RE: u1, + /// Status Mode for Bank 1 + MODES1: u2, + /// Status Mode for Bank 2 + MODES2: u2, + /// Busy status + BUSY: u1, + padding: u26, + }), + }; + + /// Debug support + pub const DBG = extern struct { + /// IDCODE + DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) { + /// DEV_ID + DEV_ID: u12, + reserved16: u4, + /// REV_ID + REV_ID: u16, + }), + /// Control Register + DBGMCU_CR: mmio.Mmio(packed struct(u32) { + /// DBG_SLEEP + DBG_SLEEP: u1, + /// DBG_STOP + DBG_STOP: u1, + /// DBG_STANDBY + DBG_STANDBY: u1, + reserved5: u2, + /// TRACE_IOEN + TRACE_IOEN: u1, + /// TRACE_MODE + TRACE_MODE: u2, + padding: u24, + }), + /// Debug MCU APB1 Freeze registe + DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) { + /// DBG_TIM2_STOP + DBG_TIM2_STOP: u1, + /// DBG_TIM3 _STOP + DBG_TIM3_STOP: u1, + /// DBG_TIM4_STOP + DBG_TIM4_STOP: u1, + /// DBG_TIM5_STOP + DBG_TIM5_STOP: u1, + /// DBG_TIM6_STOP + DBG_TIM6_STOP: u1, + /// DBG_TIM7_STOP + DBG_TIM7_STOP: u1, + /// DBG_TIM12_STOP + DBG_TIM12_STOP: u1, + /// DBG_TIM13_STOP + DBG_TIM13_STOP: u1, + /// DBG_TIM14_STOP + DBG_TIM14_STOP: u1, + reserved11: u2, + /// DBG_WWDG_STOP + DBG_WWDG_STOP: u1, + /// DBG_IWDEG_STOP + DBG_IWDEG_STOP: u1, + reserved21: u8, + /// DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT: u1, + /// DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT: u1, + /// DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT: u1, + reserved25: u1, + /// DBG_CAN1_STOP + DBG_CAN1_STOP: u1, + /// DBG_CAN2_STOP + DBG_CAN2_STOP: u1, + padding: u5, + }), + /// Debug MCU APB2 Freeze registe + DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) { + /// TIM1 counter stopped when core is halted + DBG_TIM1_STOP: u1, + /// TIM8 counter stopped when core is halted + DBG_TIM8_STOP: u1, + reserved16: u14, + /// TIM9 counter stopped when core is halted + DBG_TIM9_STOP: u1, + /// TIM10 counter stopped when core is halted + DBG_TIM10_STOP: u1, + /// TIM11 counter stopped when core is halted + DBG_TIM11_STOP: u1, + padding: u13, + }), + }; + + /// DMA controller + pub const DMA2 = extern struct { + /// low interrupt status register + LISR: mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF0: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF0: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF0: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF0: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF0: u1, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF1: u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF1: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF1: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF1: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF1: u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF2: u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF2: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF2: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF2: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF2: u1, + /// Stream x FIFO error interrupt flag (x=3..0) + FEIF3: u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=3..0) + DMEIF3: u1, + /// Stream x transfer error interrupt flag (x=3..0) + TEIF3: u1, + /// Stream x half transfer interrupt flag (x=3..0) + HTIF3: u1, + /// Stream x transfer complete interrupt flag (x = 3..0) + TCIF3: u1, + padding: u4, + }), + /// high interrupt status register + HISR: mmio.Mmio(packed struct(u32) { + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF4: u1, + reserved2: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF4: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF4: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF4: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF4: u1, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF5: u1, + reserved8: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF5: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF5: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF5: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF5: u1, + reserved16: u4, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF6: u1, + reserved18: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF6: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF6: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF6: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF6: u1, + /// Stream x FIFO error interrupt flag (x=7..4) + FEIF7: u1, + reserved24: u1, + /// Stream x direct mode error interrupt flag (x=7..4) + DMEIF7: u1, + /// Stream x transfer error interrupt flag (x=7..4) + TEIF7: u1, + /// Stream x half transfer interrupt flag (x=7..4) + HTIF7: u1, + /// Stream x transfer complete interrupt flag (x=7..4) + TCIF7: u1, + padding: u4, + }), + /// low interrupt flag clear register + LIFCR: mmio.Mmio(packed struct(u32) { + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF0: u1, + reserved2: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF0: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF0: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF0: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF0: u1, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF1: u1, + reserved8: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF1: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF1: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF1: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF1: u1, + reserved16: u4, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF2: u1, + reserved18: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF2: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF2: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF2: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF2: u1, + /// Stream x clear FIFO error interrupt flag (x = 3..0) + CFEIF3: u1, + reserved24: u1, + /// Stream x clear direct mode error interrupt flag (x = 3..0) + CDMEIF3: u1, + /// Stream x clear transfer error interrupt flag (x = 3..0) + CTEIF3: u1, + /// Stream x clear half transfer interrupt flag (x = 3..0) + CHTIF3: u1, + /// Stream x clear transfer complete interrupt flag (x = 3..0) + CTCIF3: u1, + padding: u4, + }), + /// high interrupt flag clear register + HIFCR: mmio.Mmio(packed struct(u32) { + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF4: u1, + reserved2: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF4: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF4: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF4: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF4: u1, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF5: u1, + reserved8: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF5: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF5: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF5: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF5: u1, + reserved16: u4, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF6: u1, + reserved18: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF6: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF6: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF6: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF6: u1, + /// Stream x clear FIFO error interrupt flag (x = 7..4) + CFEIF7: u1, + reserved24: u1, + /// Stream x clear direct mode error interrupt flag (x = 7..4) + CDMEIF7: u1, + /// Stream x clear transfer error interrupt flag (x = 7..4) + CTEIF7: u1, + /// Stream x clear half transfer interrupt flag (x = 7..4) + CHTIF7: u1, + /// Stream x clear transfer complete interrupt flag (x = 7..4) + CTCIF7: u1, + padding: u4, + }), + /// stream x configuration register + S0CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + reserved21: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S0NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S0PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S0M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S0M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S0FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S1CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S1NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S1PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S1M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S1M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S1FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S2CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S2NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S2PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S2M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S2M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S2FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S3CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S3NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S3PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S3M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S3M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S3FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S4CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S4NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S4PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S4M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S4M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S4FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S5CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S5NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S5PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S5M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S5M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S5FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S6CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S6NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S6PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S6M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S6M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S6FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + /// stream x configuration register + S7CR: mmio.Mmio(packed struct(u32) { + /// Stream enable / flag stream ready when read low + EN: u1, + /// Direct mode error interrupt enable + DMEIE: u1, + /// Transfer error interrupt enable + TEIE: u1, + /// Half transfer interrupt enable + HTIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Peripheral flow controller + PFCTRL: u1, + /// Data transfer direction + DIR: u2, + /// Circular mode + CIRC: u1, + /// Peripheral increment mode + PINC: u1, + /// Memory increment mode + MINC: u1, + /// Peripheral data size + PSIZE: u2, + /// Memory data size + MSIZE: u2, + /// Peripheral increment offset size + PINCOS: u1, + /// Priority level + PL: u2, + /// Double buffer mode + DBM: u1, + /// Current target (only in double buffer mode) + CT: u1, + /// ACK + ACK: u1, + /// Peripheral burst transfer configuration + PBURST: u2, + /// Memory burst transfer configuration + MBURST: u2, + /// Channel selection + CHSEL: u3, + padding: u4, + }), + /// stream x number of data register + S7NDTR: mmio.Mmio(packed struct(u32) { + /// Number of data items to transfer + NDT: u16, + padding: u16, + }), + /// stream x peripheral address register + S7PAR: mmio.Mmio(packed struct(u32) { + /// Peripheral address + PA: u32, + }), + /// stream x memory 0 address register + S7M0AR: mmio.Mmio(packed struct(u32) { + /// Memory 0 address + M0A: u32, + }), + /// stream x memory 1 address register + S7M1AR: mmio.Mmio(packed struct(u32) { + /// Memory 1 address (used in case of Double buffer mode) + M1A: u32, + }), + /// stream x FIFO control register + S7FCR: mmio.Mmio(packed struct(u32) { + /// FIFO threshold selection + FTH: u2, + /// Direct mode disable + DMDIS: u1, + /// FIFO status + FS: u3, + reserved7: u1, + /// FIFO error interrupt enable + FEIE: u1, + padding: u24, + }), + }; + + /// System control block ACTLR + pub const SCB_ACTRL = extern struct { + /// Auxiliary control register + ACTRL: mmio.Mmio(packed struct(u32) { + /// DISMCYCINT + DISMCYCINT: u1, + /// DISDEFWBUF + DISDEFWBUF: u1, + /// DISFOLD + DISFOLD: u1, + reserved8: u5, + /// DISFPCA + DISFPCA: u1, + /// DISOOFP + DISOOFP: u1, + padding: u22, + }), + }; + + /// Reset and clock control + pub const RCC = extern struct { + /// clock control register + CR: mmio.Mmio(packed struct(u32) { + /// Internal high-speed clock enable + HSION: u1, + /// Internal high-speed clock ready flag + HSIRDY: u1, + reserved3: u1, + /// Internal high-speed clock trimming + HSITRIM: u5, + /// Internal high-speed clock calibration + HSICAL: u8, + /// HSE clock enable + HSEON: u1, + /// HSE clock ready flag + HSERDY: u1, + /// HSE clock bypass + HSEBYP: u1, + /// Clock security system enable + CSSON: u1, + reserved24: u4, + /// Main PLL (PLL) enable + PLLON: u1, + /// Main PLL (PLL) clock ready flag + PLLRDY: u1, + /// PLLI2S enable + PLLI2SON: u1, + /// PLLI2S clock ready flag + PLLI2SRDY: u1, + padding: u4, + }), + /// PLL configuration register + PLLCFGR: mmio.Mmio(packed struct(u32) { + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM0: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM1: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM2: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM3: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM4: u1, + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + PLLM5: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN0: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN1: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN2: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN3: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN4: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN5: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN6: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN7: u1, + /// Main PLL (PLL) multiplication factor for VCO + PLLN8: u1, + reserved16: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP0: u1, + /// Main PLL (PLL) division factor for main system clock + PLLP1: u1, + reserved22: u4, + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + PLLSRC: u1, + reserved24: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ0: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ1: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ2: u1, + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + PLLQ3: u1, + padding: u4, + }), + /// clock configuration register + CFGR: mmio.Mmio(packed struct(u32) { + /// System clock switch + SW0: u1, + /// System clock switch + SW1: u1, + /// System clock switch status + SWS0: u1, + /// System clock switch status + SWS1: u1, + /// AHB prescaler + HPRE: u4, + reserved10: u2, + /// APB Low speed prescaler (APB1) + PPRE1: u3, + /// APB high-speed prescaler (APB2) + PPRE2: u3, + /// HSE division factor for RTC clock + RTCPRE: u5, + /// Microcontroller clock output 1 + MCO1: u2, + /// I2S clock selection + I2SSRC: u1, + /// MCO1 prescaler + MCO1PRE: u3, + /// MCO2 prescaler + MCO2PRE: u3, + /// Microcontroller clock output 2 + MCO2: u2, + }), + /// clock interrupt register + CIR: mmio.Mmio(packed struct(u32) { + /// LSI ready interrupt flag + LSIRDYF: u1, + /// LSE ready interrupt flag + LSERDYF: u1, + /// HSI ready interrupt flag + HSIRDYF: u1, + /// HSE ready interrupt flag + HSERDYF: u1, + /// Main PLL (PLL) ready interrupt flag + PLLRDYF: u1, + /// PLLI2S ready interrupt flag + PLLI2SRDYF: u1, + reserved7: u1, + /// Clock security system interrupt flag + CSSF: u1, + /// LSI ready interrupt enable + LSIRDYIE: u1, + /// LSE ready interrupt enable + LSERDYIE: u1, + /// HSI ready interrupt enable + HSIRDYIE: u1, + /// HSE ready interrupt enable + HSERDYIE: u1, + /// Main PLL (PLL) ready interrupt enable + PLLRDYIE: u1, + /// PLLI2S ready interrupt enable + PLLI2SRDYIE: u1, + reserved16: u2, + /// LSI ready interrupt clear + LSIRDYC: u1, + /// LSE ready interrupt clear + LSERDYC: u1, + /// HSI ready interrupt clear + HSIRDYC: u1, + /// HSE ready interrupt clear + HSERDYC: u1, + /// Main PLL(PLL) ready interrupt clear + PLLRDYC: u1, + /// PLLI2S ready interrupt clear + PLLI2SRDYC: u1, + reserved23: u1, + /// Clock security system interrupt clear + CSSC: u1, + padding: u8, + }), + /// AHB1 peripheral reset register + AHB1RSTR: mmio.Mmio(packed struct(u32) { + /// IO port A reset + GPIOARST: u1, + /// IO port B reset + GPIOBRST: u1, + /// IO port C reset + GPIOCRST: u1, + /// IO port D reset + GPIODRST: u1, + /// IO port E reset + GPIOERST: u1, + /// IO port F reset + GPIOFRST: u1, + /// IO port G reset + GPIOGRST: u1, + /// IO port H reset + GPIOHRST: u1, + /// IO port I reset + GPIOIRST: u1, + reserved12: u3, + /// CRC reset + CRCRST: u1, + reserved21: u8, + /// DMA2 reset + DMA1RST: u1, + /// DMA2 reset + DMA2RST: u1, + reserved25: u2, + /// Ethernet MAC reset + ETHMACRST: u1, + reserved29: u3, + /// USB OTG HS module reset + OTGHSRST: u1, + padding: u2, + }), + /// AHB2 peripheral reset register + AHB2RSTR: mmio.Mmio(packed struct(u32) { + /// Camera interface reset + DCMIRST: u1, + reserved4: u3, + /// Cryptographic module reset + CRYPRST: u1, + /// Hash module reset + HSAHRST: u1, + /// Random number generator module reset + RNGRST: u1, + /// USB OTG FS module reset + OTGFSRST: u1, + padding: u24, + }), + /// AHB3 peripheral reset register + AHB3RSTR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module reset + FMCRST: u1, + padding: u31, + }), + reserved32: [4]u8, + /// APB1 peripheral reset register + APB1RSTR: mmio.Mmio(packed struct(u32) { + /// TIM2 reset + TIM2RST: u1, + /// TIM3 reset + TIM3RST: u1, + /// TIM4 reset + TIM4RST: u1, + /// TIM5 reset + TIM5RST: u1, + /// TIM6 reset + TIM6RST: u1, + /// TIM7 reset + TIM7RST: u1, + /// TIM12 reset + TIM12RST: u1, + /// TIM13 reset + TIM13RST: u1, + /// TIM14 reset + TIM14RST: u1, + reserved11: u2, + /// Window watchdog reset + WWDGRST: u1, + reserved14: u2, + /// SPI 2 reset + SPI2RST: u1, + /// SPI 3 reset + SPI3RST: u1, + reserved17: u1, + /// USART 2 reset + UART2RST: u1, + /// USART 3 reset + UART3RST: u1, + /// USART 4 reset + UART4RST: u1, + /// USART 5 reset + UART5RST: u1, + /// I2C 1 reset + I2C1RST: u1, + /// I2C 2 reset + I2C2RST: u1, + /// I2C3 reset + I2C3RST: u1, + reserved25: u1, + /// CAN1 reset + CAN1RST: u1, + /// CAN2 reset + CAN2RST: u1, + reserved28: u1, + /// Power interface reset + PWRRST: u1, + /// DAC reset + DACRST: u1, + padding: u2, + }), + /// APB2 peripheral reset register + APB2RSTR: mmio.Mmio(packed struct(u32) { + /// TIM1 reset + TIM1RST: u1, + /// TIM8 reset + TIM8RST: u1, + reserved4: u2, + /// USART1 reset + USART1RST: u1, + /// USART6 reset + USART6RST: u1, + reserved8: u2, + /// ADC interface reset (common to all ADCs) + ADCRST: u1, + reserved11: u2, + /// SDIO reset + SDIORST: u1, + /// SPI 1 reset + SPI1RST: u1, + reserved14: u1, + /// System configuration controller reset + SYSCFGRST: u1, + reserved16: u1, + /// TIM9 reset + TIM9RST: u1, + /// TIM10 reset + TIM10RST: u1, + /// TIM11 reset + TIM11RST: u1, + padding: u13, + }), + reserved48: [8]u8, + /// AHB1 peripheral clock register + AHB1ENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable + GPIOAEN: u1, + /// IO port B clock enable + GPIOBEN: u1, + /// IO port C clock enable + GPIOCEN: u1, + /// IO port D clock enable + GPIODEN: u1, + /// IO port E clock enable + GPIOEEN: u1, + /// IO port F clock enable + GPIOFEN: u1, + /// IO port G clock enable + GPIOGEN: u1, + /// IO port H clock enable + GPIOHEN: u1, + /// IO port I clock enable + GPIOIEN: u1, + reserved12: u3, + /// CRC clock enable + CRCEN: u1, + reserved18: u5, + /// Backup SRAM interface clock enable + BKPSRAMEN: u1, + reserved20: u1, + /// CCM data RAM clock enable + CCMDATARAMEN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// DMA2 clock enable + DMA2EN: u1, + reserved25: u2, + /// Ethernet MAC clock enable + ETHMACEN: u1, + /// Ethernet Transmission clock enable + ETHMACTXEN: u1, + /// Ethernet Reception clock enable + ETHMACRXEN: u1, + /// Ethernet PTP clock enable + ETHMACPTPEN: u1, + /// USB OTG HS clock enable + OTGHSEN: u1, + /// USB OTG HSULPI clock enable + OTGHSULPIEN: u1, + padding: u1, + }), + /// AHB2 peripheral clock enable register + AHB2ENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable + DCMIEN: u1, + reserved4: u3, + /// Cryptographic modules clock enable + CRYPEN: u1, + /// Hash modules clock enable + HASHEN: u1, + /// Random number generator clock enable + RNGEN: u1, + /// USB OTG FS clock enable + OTGFSEN: u1, + padding: u24, + }), + /// AHB3 peripheral clock enable register + AHB3ENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module clock enable + FMCEN: u1, + padding: u31, + }), + reserved64: [4]u8, + /// APB1 peripheral clock enable register + APB1ENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable + TIM2EN: u1, + /// TIM3 clock enable + TIM3EN: u1, + /// TIM4 clock enable + TIM4EN: u1, + /// TIM5 clock enable + TIM5EN: u1, + /// TIM6 clock enable + TIM6EN: u1, + /// TIM7 clock enable + TIM7EN: u1, + /// TIM12 clock enable + TIM12EN: u1, + /// TIM13 clock enable + TIM13EN: u1, + /// TIM14 clock enable + TIM14EN: u1, + reserved11: u2, + /// Window watchdog clock enable + WWDGEN: u1, + reserved14: u2, + /// SPI2 clock enable + SPI2EN: u1, + /// SPI3 clock enable + SPI3EN: u1, + reserved17: u1, + /// USART 2 clock enable + USART2EN: u1, + /// USART3 clock enable + USART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// UART5 clock enable + UART5EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + /// I2C2 clock enable + I2C2EN: u1, + /// I2C3 clock enable + I2C3EN: u1, + reserved25: u1, + /// CAN 1 clock enable + CAN1EN: u1, + /// CAN 2 clock enable + CAN2EN: u1, + reserved28: u1, + /// Power interface clock enable + PWREN: u1, + /// DAC interface clock enable + DACEN: u1, + padding: u2, + }), + /// APB2 peripheral clock enable register + APB2ENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable + TIM1EN: u1, + /// TIM8 clock enable + TIM8EN: u1, + reserved4: u2, + /// USART1 clock enable + USART1EN: u1, + /// USART6 clock enable + USART6EN: u1, + reserved8: u2, + /// ADC1 clock enable + ADC1EN: u1, + /// ADC2 clock enable + ADC2EN: u1, + /// ADC3 clock enable + ADC3EN: u1, + /// SDIO clock enable + SDIOEN: u1, + /// SPI1 clock enable + SPI1EN: u1, + reserved14: u1, + /// System configuration controller clock enable + SYSCFGEN: u1, + reserved16: u1, + /// TIM9 clock enable + TIM9EN: u1, + /// TIM10 clock enable + TIM10EN: u1, + /// TIM11 clock enable + TIM11EN: u1, + padding: u13, + }), + reserved80: [8]u8, + /// AHB1 peripheral clock enable in low power mode register + AHB1LPENR: mmio.Mmio(packed struct(u32) { + /// IO port A clock enable during sleep mode + GPIOALPEN: u1, + /// IO port B clock enable during Sleep mode + GPIOBLPEN: u1, + /// IO port C clock enable during Sleep mode + GPIOCLPEN: u1, + /// IO port D clock enable during Sleep mode + GPIODLPEN: u1, + /// IO port E clock enable during Sleep mode + GPIOELPEN: u1, + /// IO port F clock enable during Sleep mode + GPIOFLPEN: u1, + /// IO port G clock enable during Sleep mode + GPIOGLPEN: u1, + /// IO port H clock enable during Sleep mode + GPIOHLPEN: u1, + /// IO port I clock enable during Sleep mode + GPIOILPEN: u1, + reserved12: u3, + /// CRC clock enable during Sleep mode + CRCLPEN: u1, + reserved15: u2, + /// Flash interface clock enable during Sleep mode + FLITFLPEN: u1, + /// SRAM 1interface clock enable during Sleep mode + SRAM1LPEN: u1, + /// SRAM 2 interface clock enable during Sleep mode + SRAM2LPEN: u1, + /// Backup SRAM interface clock enable during Sleep mode + BKPSRAMLPEN: u1, + reserved21: u2, + /// DMA1 clock enable during Sleep mode + DMA1LPEN: u1, + /// DMA2 clock enable during Sleep mode + DMA2LPEN: u1, + reserved25: u2, + /// Ethernet MAC clock enable during Sleep mode + ETHMACLPEN: u1, + /// Ethernet transmission clock enable during Sleep mode + ETHMACTXLPEN: u1, + /// Ethernet reception clock enable during Sleep mode + ETHMACRXLPEN: u1, + /// Ethernet PTP clock enable during Sleep mode + ETHMACPTPLPEN: u1, + /// USB OTG HS clock enable during Sleep mode + OTGHSLPEN: u1, + /// USB OTG HS ULPI clock enable during Sleep mode + OTGHSULPILPEN: u1, + padding: u1, + }), + /// AHB2 peripheral clock enable in low power mode register + AHB2LPENR: mmio.Mmio(packed struct(u32) { + /// Camera interface enable during Sleep mode + DCMILPEN: u1, + reserved4: u3, + /// Cryptography modules clock enable during Sleep mode + CRYPLPEN: u1, + /// Hash modules clock enable during Sleep mode + HASHLPEN: u1, + /// Random number generator clock enable during Sleep mode + RNGLPEN: u1, + /// USB OTG FS clock enable during Sleep mode + OTGFSLPEN: u1, + padding: u24, + }), + /// AHB3 peripheral clock enable in low power mode register + AHB3LPENR: mmio.Mmio(packed struct(u32) { + /// Flexible memory controller module clock enable during Sleep mode + FMCLPEN: u1, + padding: u31, + }), + reserved96: [4]u8, + /// APB1 peripheral clock enable in low power mode register + APB1LPENR: mmio.Mmio(packed struct(u32) { + /// TIM2 clock enable during Sleep mode + TIM2LPEN: u1, + /// TIM3 clock enable during Sleep mode + TIM3LPEN: u1, + /// TIM4 clock enable during Sleep mode + TIM4LPEN: u1, + /// TIM5 clock enable during Sleep mode + TIM5LPEN: u1, + /// TIM6 clock enable during Sleep mode + TIM6LPEN: u1, + /// TIM7 clock enable during Sleep mode + TIM7LPEN: u1, + /// TIM12 clock enable during Sleep mode + TIM12LPEN: u1, + /// TIM13 clock enable during Sleep mode + TIM13LPEN: u1, + /// TIM14 clock enable during Sleep mode + TIM14LPEN: u1, + reserved11: u2, + /// Window watchdog clock enable during Sleep mode + WWDGLPEN: u1, + reserved14: u2, + /// SPI2 clock enable during Sleep mode + SPI2LPEN: u1, + /// SPI3 clock enable during Sleep mode + SPI3LPEN: u1, + reserved17: u1, + /// USART2 clock enable during Sleep mode + USART2LPEN: u1, + /// USART3 clock enable during Sleep mode + USART3LPEN: u1, + /// UART4 clock enable during Sleep mode + UART4LPEN: u1, + /// UART5 clock enable during Sleep mode + UART5LPEN: u1, + /// I2C1 clock enable during Sleep mode + I2C1LPEN: u1, + /// I2C2 clock enable during Sleep mode + I2C2LPEN: u1, + /// I2C3 clock enable during Sleep mode + I2C3LPEN: u1, + reserved25: u1, + /// CAN 1 clock enable during Sleep mode + CAN1LPEN: u1, + /// CAN 2 clock enable during Sleep mode + CAN2LPEN: u1, + reserved28: u1, + /// Power interface clock enable during Sleep mode + PWRLPEN: u1, + /// DAC interface clock enable during Sleep mode + DACLPEN: u1, + padding: u2, + }), + /// APB2 peripheral clock enabled in low power mode register + APB2LPENR: mmio.Mmio(packed struct(u32) { + /// TIM1 clock enable during Sleep mode + TIM1LPEN: u1, + /// TIM8 clock enable during Sleep mode + TIM8LPEN: u1, + reserved4: u2, + /// USART1 clock enable during Sleep mode + USART1LPEN: u1, + /// USART6 clock enable during Sleep mode + USART6LPEN: u1, + reserved8: u2, + /// ADC1 clock enable during Sleep mode + ADC1LPEN: u1, + /// ADC2 clock enable during Sleep mode + ADC2LPEN: u1, + /// ADC 3 clock enable during Sleep mode + ADC3LPEN: u1, + /// SDIO clock enable during Sleep mode + SDIOLPEN: u1, + /// SPI 1 clock enable during Sleep mode + SPI1LPEN: u1, + reserved14: u1, + /// System configuration controller clock enable during Sleep mode + SYSCFGLPEN: u1, + reserved16: u1, + /// TIM9 clock enable during sleep mode + TIM9LPEN: u1, + /// TIM10 clock enable during Sleep mode + TIM10LPEN: u1, + /// TIM11 clock enable during Sleep mode + TIM11LPEN: u1, + padding: u13, + }), + reserved112: [8]u8, + /// Backup domain control register + BDCR: mmio.Mmio(packed struct(u32) { + /// External low-speed oscillator enable + LSEON: u1, + /// External low-speed oscillator ready + LSERDY: u1, + /// External low-speed oscillator bypass + LSEBYP: u1, + reserved8: u5, + /// RTC clock source selection + RTCSEL0: u1, + /// RTC clock source selection + RTCSEL1: u1, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain software reset + BDRST: u1, + padding: u15, + }), + /// clock control & status register + CSR: mmio.Mmio(packed struct(u32) { + /// Internal low-speed oscillator enable + LSION: u1, + /// Internal low-speed oscillator ready + LSIRDY: u1, + reserved24: u22, + /// Remove reset flag + RMVF: u1, + /// BOR reset flag + BORRSTF: u1, + /// PIN reset flag + PADRSTF: u1, + /// POR/PDR reset flag + PORRSTF: u1, + /// Software reset flag + SFTRSTF: u1, + /// Independent watchdog reset flag + WDGRSTF: u1, + /// Window watchdog reset flag + WWDGRSTF: u1, + /// Low-power reset flag + LPWRRSTF: u1, + }), + reserved128: [8]u8, + /// spread spectrum clock generation register + SSCGR: mmio.Mmio(packed struct(u32) { + /// Modulation period + MODPER: u13, + /// Incrementation step + INCSTEP: u15, + reserved30: u2, + /// Spread Select + SPREADSEL: u1, + /// Spread spectrum modulation enable + SSCGEN: u1, + }), + /// PLLI2S configuration register + PLLI2SCFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLLI2S multiplication factor for VCO + PLLI2SN: u9, + reserved24: u9, + /// PLLI2S division factor for SAI1 clock + PLLI2SQ: u4, + /// PLLI2S division factor for I2S clocks + PLLI2SR: u3, + padding: u1, + }), + /// RCC PLL configuration register + PLLSAICFGR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// PLLSAI division factor for VCO + PLLSAIN: u9, + reserved24: u9, + /// PLLSAI division factor for SAI1 clock + PLLSAIQ: u4, + /// PLLSAI division factor for LCD clock + PLLSAIR: u3, + padding: u1, + }), + /// RCC Dedicated Clock Configuration Register + DCKCFGR: mmio.Mmio(packed struct(u32) { + /// PLLI2S division factor for SAI1 clock + PLLI2SDIVQ: u5, + reserved8: u3, + /// PLLSAI division factor for SAI1 clock + PLLSAIDIVQ: u5, + reserved16: u3, + /// division factor for LCD_CLK + PLLSAIDIVR: u2, + reserved20: u2, + /// SAI1-A clock source selection + SAI1ASRC: u2, + /// SAI1-B clock source selection + SAI1BSRC: u2, + /// Timers clocks prescalers selection + TIMPRE: u1, + padding: u7, + }), + }; + + /// General-purpose I/Os + pub const GPIOK = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// Floating point unit CPACR + pub const FPU_CPACR = extern struct { + /// Coprocessor access control register + CPACR: mmio.Mmio(packed struct(u32) { + reserved20: u20, + /// CP + CP: u4, + padding: u8, + }), + }; + + /// Nested vectored interrupt controller + pub const NVIC_STIR = extern struct { + /// Software trigger interrupt register + STIR: mmio.Mmio(packed struct(u32) { + /// Software generated interrupt ID + INTID: u9, + padding: u23, + }), + }; + + /// System control block + pub const SCB = extern struct { + /// CPUID base register + CPUID: mmio.Mmio(packed struct(u32) { + /// Revision number + Revision: u4, + /// Part number of the processor + PartNo: u12, + /// Reads as 0xF + Constant: u4, + /// Variant number + Variant: u4, + /// Implementer code + Implementer: u8, + }), + /// Interrupt control and state register + ICSR: mmio.Mmio(packed struct(u32) { + /// Active vector + VECTACTIVE: u9, + reserved11: u2, + /// Return to base level + RETTOBASE: u1, + /// Pending vector + VECTPENDING: u7, + reserved22: u3, + /// Interrupt pending flag + ISRPENDING: u1, + reserved25: u2, + /// SysTick exception clear-pending bit + PENDSTCLR: u1, + /// SysTick exception set-pending bit + PENDSTSET: u1, + /// PendSV clear-pending bit + PENDSVCLR: u1, + /// PendSV set-pending bit + PENDSVSET: u1, + reserved31: u2, + /// NMI set-pending bit. + NMIPENDSET: u1, + }), + /// Vector table offset register + VTOR: mmio.Mmio(packed struct(u32) { + reserved9: u9, + /// Vector table base offset field + TBLOFF: u21, + padding: u2, + }), + /// Application interrupt and reset control register + AIRCR: mmio.Mmio(packed struct(u32) { + /// VECTRESET + VECTRESET: u1, + /// VECTCLRACTIVE + VECTCLRACTIVE: u1, + /// SYSRESETREQ + SYSRESETREQ: u1, + reserved8: u5, + /// PRIGROUP + PRIGROUP: u3, + reserved15: u4, + /// ENDIANESS + ENDIANESS: u1, + /// Register key + VECTKEYSTAT: u16, + }), + /// System control register + SCR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SLEEPONEXIT + SLEEPONEXIT: u1, + /// SLEEPDEEP + SLEEPDEEP: u1, + reserved4: u1, + /// Send Event on Pending bit + SEVEONPEND: u1, + padding: u27, + }), + /// Configuration and control register + CCR: mmio.Mmio(packed struct(u32) { + /// Configures how the processor enters Thread mode + NONBASETHRDENA: u1, + /// USERSETMPEND + USERSETMPEND: u1, + reserved3: u1, + /// UNALIGN_ TRP + UNALIGN__TRP: u1, + /// DIV_0_TRP + DIV_0_TRP: u1, + reserved8: u3, + /// BFHFNMIGN + BFHFNMIGN: u1, + /// STKALIGN + STKALIGN: u1, + padding: u22, + }), + /// System handler priority registers + SHPR1: mmio.Mmio(packed struct(u32) { + /// Priority of system handler 4 + PRI_4: u8, + /// Priority of system handler 5 + PRI_5: u8, + /// Priority of system handler 6 + PRI_6: u8, + padding: u8, + }), + /// System handler priority registers + SHPR2: mmio.Mmio(packed struct(u32) { + reserved24: u24, + /// Priority of system handler 11 + PRI_11: u8, + }), + /// System handler priority registers + SHPR3: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Priority of system handler 14 + PRI_14: u8, + /// Priority of system handler 15 + PRI_15: u8, + }), + /// System handler control and state register + SHCRS: mmio.Mmio(packed struct(u32) { + /// Memory management fault exception active bit + MEMFAULTACT: u1, + /// Bus fault exception active bit + BUSFAULTACT: u1, + reserved3: u1, + /// Usage fault exception active bit + USGFAULTACT: u1, + reserved7: u3, + /// SVC call active bit + SVCALLACT: u1, + /// Debug monitor active bit + MONITORACT: u1, + reserved10: u1, + /// PendSV exception active bit + PENDSVACT: u1, + /// SysTick exception active bit + SYSTICKACT: u1, + /// Usage fault exception pending bit + USGFAULTPENDED: u1, + /// Memory management fault exception pending bit + MEMFAULTPENDED: u1, + /// Bus fault exception pending bit + BUSFAULTPENDED: u1, + /// SVC call pending bit + SVCALLPENDED: u1, + /// Memory management fault enable bit + MEMFAULTENA: u1, + /// Bus fault enable bit + BUSFAULTENA: u1, + /// Usage fault enable bit + USGFAULTENA: u1, + padding: u13, + }), + /// Configurable fault status register + CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Instruction access violation flag + IACCVIOL: u1, + reserved3: u1, + /// Memory manager fault on unstacking for a return from exception + MUNSTKERR: u1, + /// Memory manager fault on stacking for exception entry. + MSTKERR: u1, + /// MLSPERR + MLSPERR: u1, + reserved7: u1, + /// Memory Management Fault Address Register (MMAR) valid flag + MMARVALID: u1, + /// Instruction bus error + IBUSERR: u1, + /// Precise data bus error + PRECISERR: u1, + /// Imprecise data bus error + IMPRECISERR: u1, + /// Bus fault on unstacking for a return from exception + UNSTKERR: u1, + /// Bus fault on stacking for exception entry + STKERR: u1, + /// Bus fault on floating-point lazy state preservation + LSPERR: u1, + reserved15: u1, + /// Bus Fault Address Register (BFAR) valid flag + BFARVALID: u1, + /// Undefined instruction usage fault + UNDEFINSTR: u1, + /// Invalid state usage fault + INVSTATE: u1, + /// Invalid PC load usage fault + INVPC: u1, + /// No coprocessor usage fault. + NOCP: u1, + reserved24: u4, + /// Unaligned access usage fault + UNALIGNED: u1, + /// Divide by zero usage fault + DIVBYZERO: u1, + padding: u6, + }), + /// Hard fault status register + HFSR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Vector table hard fault + VECTTBL: u1, + reserved30: u28, + /// Forced hard fault + FORCED: u1, + /// Reserved for Debug use + DEBUG_VT: u1, + }), + reserved52: [4]u8, + /// Memory management fault address register + MMFAR: mmio.Mmio(packed struct(u32) { + /// Memory management fault address + MMFAR: u32, + }), + /// Bus fault address register + BFAR: mmio.Mmio(packed struct(u32) { + /// Bus fault address + BFAR: u32, + }), + /// Auxiliary fault status register + AFSR: mmio.Mmio(packed struct(u32) { + /// Implementation defined + IMPDEF: u32, + }), + }; + + /// SysTick timer + pub const STK = extern struct { + /// SysTick control and status register + CTRL: mmio.Mmio(packed struct(u32) { + /// Counter enable + ENABLE: u1, + /// SysTick exception request enable + TICKINT: u1, + /// Clock source selection + CLKSOURCE: u1, + reserved16: u13, + /// COUNTFLAG + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick reload value register + LOAD: mmio.Mmio(packed struct(u32) { + /// RELOAD value + RELOAD: u24, + padding: u8, + }), + /// SysTick current value register + VAL: mmio.Mmio(packed struct(u32) { + /// Current counter value + CURRENT: u24, + padding: u8, + }), + /// SysTick calibration value register + CALIB: mmio.Mmio(packed struct(u32) { + /// Calibration value + TENMS: u24, + reserved30: u6, + /// SKEW flag: Indicates whether the TENMS value is exact + SKEW: u1, + /// NOREF flag. Reads as zero + NOREF: u1, + }), + }; + + /// Memory protection unit + pub const MPU = extern struct { + /// MPU type register + MPU_TYPER: mmio.Mmio(packed struct(u32) { + /// Separate flag + SEPARATE: u1, + reserved8: u7, + /// Number of MPU data regions + DREGION: u8, + /// Number of MPU instruction regions + IREGION: u8, + padding: u8, + }), + /// MPU control register + MPU_CTRL: mmio.Mmio(packed struct(u32) { + /// Enables the MPU + ENABLE: u1, + /// Enables the operation of MPU during hard fault + HFNMIENA: u1, + /// Enable priviliged software access to default memory map + PRIVDEFENA: u1, + padding: u29, + }), + /// MPU region number register + MPU_RNR: mmio.Mmio(packed struct(u32) { + /// MPU region + REGION: u8, + padding: u24, + }), + /// MPU region base address register + MPU_RBAR: mmio.Mmio(packed struct(u32) { + /// MPU region field + REGION: u4, + /// MPU region number valid + VALID: u1, + /// Region base address field + ADDR: u27, + }), + /// MPU region attribute and size register + MPU_RASR: mmio.Mmio(packed struct(u32) { + /// Region enable bit. + ENABLE: u1, + /// Size of the MPU protection region + SIZE: u5, + reserved8: u2, + /// Subregion disable bits + SRD: u8, + /// memory attribute + B: u1, + /// memory attribute + C: u1, + /// Shareable memory attribute + S: u1, + /// memory attribute + TEX: u3, + reserved24: u2, + /// Access permission + AP: u3, + reserved28: u1, + /// Instruction access disable bit + XN: u1, + padding: u3, + }), + }; + + /// Floting point unit + pub const FPU = extern struct { + /// Floating-point context control register + FPCCR: mmio.Mmio(packed struct(u32) { + /// LSPACT + LSPACT: u1, + /// USER + USER: u1, + reserved3: u1, + /// THREAD + THREAD: u1, + /// HFRDY + HFRDY: u1, + /// MMRDY + MMRDY: u1, + /// BFRDY + BFRDY: u1, + reserved8: u1, + /// MONRDY + MONRDY: u1, + reserved30: u21, + /// LSPEN + LSPEN: u1, + /// ASPEN + ASPEN: u1, + }), + /// Floating-point context address register + FPCAR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Location of unpopulated floating-point + ADDRESS: u29, + }), + /// Floating-point status control register + FPSCR: mmio.Mmio(packed struct(u32) { + /// Invalid operation cumulative exception bit + IOC: u1, + /// Division by zero cumulative exception bit. + DZC: u1, + /// Overflow cumulative exception bit + OFC: u1, + /// Underflow cumulative exception bit + UFC: u1, + /// Inexact cumulative exception bit + IXC: u1, + reserved7: u2, + /// Input denormal cumulative exception bit. + IDC: u1, + reserved22: u14, + /// Rounding Mode control field + RMode: u2, + /// Flush-to-zero mode control bit: + FZ: u1, + /// Default NaN mode control bit + DN: u1, + /// Alternative half-precision control bit + AHP: u1, + reserved28: u1, + /// Overflow condition code flag + V: u1, + /// Carry condition code flag + C: u1, + /// Zero condition code flag + Z: u1, + /// Negative condition code flag + N: u1, + }), + }; + + /// Basic timers + pub const TIM6 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + padding: u24, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + reserved12: [4]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + reserved8: u7, + /// Update DMA request enable + UDE: u1, + padding: u23, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + padding: u31, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + padding: u31, + }), + reserved36: [12]u8, + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR: u16, + padding: u16, + }), + }; + + /// Ethernet: MAC management counters + pub const Ethernet_MMC = extern struct { + /// Ethernet MMC control register + MMCCR: mmio.Mmio(packed struct(u32) { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding: u26, + }), + /// Ethernet MMC receive interrupt register + MMCRIR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// RFCES + RFCES: u1, + /// RFAES + RFAES: u1, + reserved17: u10, + /// RGUFS + RGUFS: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt register + MMCTIR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// TGFSCS + TGFSCS: u1, + /// TGFMSCS + TGFMSCS: u1, + reserved21: u5, + /// TGFS + TGFS: u1, + padding: u10, + }), + /// Ethernet MMC receive interrupt mask register + MMCRIMR: mmio.Mmio(packed struct(u32) { + reserved5: u5, + /// RFCEM + RFCEM: u1, + /// RFAEM + RFAEM: u1, + reserved17: u10, + /// RGUFM + RGUFM: u1, + padding: u14, + }), + /// Ethernet MMC transmit interrupt mask register + MMCTIMR: mmio.Mmio(packed struct(u32) { + reserved14: u14, + /// TGFSCM + TGFSCM: u1, + /// TGFMSCM + TGFMSCM: u1, + /// TGFM + TGFM: u1, + padding: u15, + }), + reserved76: [56]u8, + /// Ethernet MMC transmitted good frames after a single collision counter + MMCTGFSCCR: mmio.Mmio(packed struct(u32) { + /// TGFSCC + TGFSCC: u32, + }), + /// Ethernet MMC transmitted good frames after more than a single collision + MMCTGFMSCCR: mmio.Mmio(packed struct(u32) { + /// TGFMSCC + TGFMSCC: u32, + }), + reserved104: [20]u8, + /// Ethernet MMC transmitted good frames counter register + MMCTGFCR: mmio.Mmio(packed struct(u32) { + /// HTL + TGFC: u32, + }), + reserved148: [40]u8, + /// Ethernet MMC received frames with CRC error counter register + MMCRFCECR: mmio.Mmio(packed struct(u32) { + /// RFCFC + RFCFC: u32, + }), + /// Ethernet MMC received frames with alignment error counter register + MMCRFAECR: mmio.Mmio(packed struct(u32) { + /// RFAEC + RFAEC: u32, + }), + reserved196: [40]u8, + /// MMC received good unicast frames counter register + MMCRGUFCR: mmio.Mmio(packed struct(u32) { + /// RGUFC + RGUFC: u32, + }), + }; + + /// General-purpose I/Os + pub const GPIOB = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// General-purpose I/Os + pub const GPIOA = extern struct { + /// GPIO port mode register + MODER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + MODER0: u2, + /// Port x configuration bits (y = 0..15) + MODER1: u2, + /// Port x configuration bits (y = 0..15) + MODER2: u2, + /// Port x configuration bits (y = 0..15) + MODER3: u2, + /// Port x configuration bits (y = 0..15) + MODER4: u2, + /// Port x configuration bits (y = 0..15) + MODER5: u2, + /// Port x configuration bits (y = 0..15) + MODER6: u2, + /// Port x configuration bits (y = 0..15) + MODER7: u2, + /// Port x configuration bits (y = 0..15) + MODER8: u2, + /// Port x configuration bits (y = 0..15) + MODER9: u2, + /// Port x configuration bits (y = 0..15) + MODER10: u2, + /// Port x configuration bits (y = 0..15) + MODER11: u2, + /// Port x configuration bits (y = 0..15) + MODER12: u2, + /// Port x configuration bits (y = 0..15) + MODER13: u2, + /// Port x configuration bits (y = 0..15) + MODER14: u2, + /// Port x configuration bits (y = 0..15) + MODER15: u2, + }), + /// GPIO port output type register + OTYPER: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OT0: u1, + /// Port x configuration bits (y = 0..15) + OT1: u1, + /// Port x configuration bits (y = 0..15) + OT2: u1, + /// Port x configuration bits (y = 0..15) + OT3: u1, + /// Port x configuration bits (y = 0..15) + OT4: u1, + /// Port x configuration bits (y = 0..15) + OT5: u1, + /// Port x configuration bits (y = 0..15) + OT6: u1, + /// Port x configuration bits (y = 0..15) + OT7: u1, + /// Port x configuration bits (y = 0..15) + OT8: u1, + /// Port x configuration bits (y = 0..15) + OT9: u1, + /// Port x configuration bits (y = 0..15) + OT10: u1, + /// Port x configuration bits (y = 0..15) + OT11: u1, + /// Port x configuration bits (y = 0..15) + OT12: u1, + /// Port x configuration bits (y = 0..15) + OT13: u1, + /// Port x configuration bits (y = 0..15) + OT14: u1, + /// Port x configuration bits (y = 0..15) + OT15: u1, + padding: u16, + }), + /// GPIO port output speed register + OSPEEDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + OSPEEDR0: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR1: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR2: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR3: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR4: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR5: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR6: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR7: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR8: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR9: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR10: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR11: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR12: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR13: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR14: u2, + /// Port x configuration bits (y = 0..15) + OSPEEDR15: u2, + }), + /// GPIO port pull-up/pull-down register + PUPDR: mmio.Mmio(packed struct(u32) { + /// Port x configuration bits (y = 0..15) + PUPDR0: u2, + /// Port x configuration bits (y = 0..15) + PUPDR1: u2, + /// Port x configuration bits (y = 0..15) + PUPDR2: u2, + /// Port x configuration bits (y = 0..15) + PUPDR3: u2, + /// Port x configuration bits (y = 0..15) + PUPDR4: u2, + /// Port x configuration bits (y = 0..15) + PUPDR5: u2, + /// Port x configuration bits (y = 0..15) + PUPDR6: u2, + /// Port x configuration bits (y = 0..15) + PUPDR7: u2, + /// Port x configuration bits (y = 0..15) + PUPDR8: u2, + /// Port x configuration bits (y = 0..15) + PUPDR9: u2, + /// Port x configuration bits (y = 0..15) + PUPDR10: u2, + /// Port x configuration bits (y = 0..15) + PUPDR11: u2, + /// Port x configuration bits (y = 0..15) + PUPDR12: u2, + /// Port x configuration bits (y = 0..15) + PUPDR13: u2, + /// Port x configuration bits (y = 0..15) + PUPDR14: u2, + /// Port x configuration bits (y = 0..15) + PUPDR15: u2, + }), + /// GPIO port input data register + IDR: mmio.Mmio(packed struct(u32) { + /// Port input data (y = 0..15) + IDR0: u1, + /// Port input data (y = 0..15) + IDR1: u1, + /// Port input data (y = 0..15) + IDR2: u1, + /// Port input data (y = 0..15) + IDR3: u1, + /// Port input data (y = 0..15) + IDR4: u1, + /// Port input data (y = 0..15) + IDR5: u1, + /// Port input data (y = 0..15) + IDR6: u1, + /// Port input data (y = 0..15) + IDR7: u1, + /// Port input data (y = 0..15) + IDR8: u1, + /// Port input data (y = 0..15) + IDR9: u1, + /// Port input data (y = 0..15) + IDR10: u1, + /// Port input data (y = 0..15) + IDR11: u1, + /// Port input data (y = 0..15) + IDR12: u1, + /// Port input data (y = 0..15) + IDR13: u1, + /// Port input data (y = 0..15) + IDR14: u1, + /// Port input data (y = 0..15) + IDR15: u1, + padding: u16, + }), + /// GPIO port output data register + ODR: mmio.Mmio(packed struct(u32) { + /// Port output data (y = 0..15) + ODR0: u1, + /// Port output data (y = 0..15) + ODR1: u1, + /// Port output data (y = 0..15) + ODR2: u1, + /// Port output data (y = 0..15) + ODR3: u1, + /// Port output data (y = 0..15) + ODR4: u1, + /// Port output data (y = 0..15) + ODR5: u1, + /// Port output data (y = 0..15) + ODR6: u1, + /// Port output data (y = 0..15) + ODR7: u1, + /// Port output data (y = 0..15) + ODR8: u1, + /// Port output data (y = 0..15) + ODR9: u1, + /// Port output data (y = 0..15) + ODR10: u1, + /// Port output data (y = 0..15) + ODR11: u1, + /// Port output data (y = 0..15) + ODR12: u1, + /// Port output data (y = 0..15) + ODR13: u1, + /// Port output data (y = 0..15) + ODR14: u1, + /// Port output data (y = 0..15) + ODR15: u1, + padding: u16, + }), + /// GPIO port bit set/reset register + BSRR: mmio.Mmio(packed struct(u32) { + /// Port x set bit y (y= 0..15) + BS0: u1, + /// Port x set bit y (y= 0..15) + BS1: u1, + /// Port x set bit y (y= 0..15) + BS2: u1, + /// Port x set bit y (y= 0..15) + BS3: u1, + /// Port x set bit y (y= 0..15) + BS4: u1, + /// Port x set bit y (y= 0..15) + BS5: u1, + /// Port x set bit y (y= 0..15) + BS6: u1, + /// Port x set bit y (y= 0..15) + BS7: u1, + /// Port x set bit y (y= 0..15) + BS8: u1, + /// Port x set bit y (y= 0..15) + BS9: u1, + /// Port x set bit y (y= 0..15) + BS10: u1, + /// Port x set bit y (y= 0..15) + BS11: u1, + /// Port x set bit y (y= 0..15) + BS12: u1, + /// Port x set bit y (y= 0..15) + BS13: u1, + /// Port x set bit y (y= 0..15) + BS14: u1, + /// Port x set bit y (y= 0..15) + BS15: u1, + /// Port x set bit y (y= 0..15) + BR0: u1, + /// Port x reset bit y (y = 0..15) + BR1: u1, + /// Port x reset bit y (y = 0..15) + BR2: u1, + /// Port x reset bit y (y = 0..15) + BR3: u1, + /// Port x reset bit y (y = 0..15) + BR4: u1, + /// Port x reset bit y (y = 0..15) + BR5: u1, + /// Port x reset bit y (y = 0..15) + BR6: u1, + /// Port x reset bit y (y = 0..15) + BR7: u1, + /// Port x reset bit y (y = 0..15) + BR8: u1, + /// Port x reset bit y (y = 0..15) + BR9: u1, + /// Port x reset bit y (y = 0..15) + BR10: u1, + /// Port x reset bit y (y = 0..15) + BR11: u1, + /// Port x reset bit y (y = 0..15) + BR12: u1, + /// Port x reset bit y (y = 0..15) + BR13: u1, + /// Port x reset bit y (y = 0..15) + BR14: u1, + /// Port x reset bit y (y = 0..15) + BR15: u1, + }), + /// GPIO port configuration lock register + LCKR: mmio.Mmio(packed struct(u32) { + /// Port x lock bit y (y= 0..15) + LCK0: u1, + /// Port x lock bit y (y= 0..15) + LCK1: u1, + /// Port x lock bit y (y= 0..15) + LCK2: u1, + /// Port x lock bit y (y= 0..15) + LCK3: u1, + /// Port x lock bit y (y= 0..15) + LCK4: u1, + /// Port x lock bit y (y= 0..15) + LCK5: u1, + /// Port x lock bit y (y= 0..15) + LCK6: u1, + /// Port x lock bit y (y= 0..15) + LCK7: u1, + /// Port x lock bit y (y= 0..15) + LCK8: u1, + /// Port x lock bit y (y= 0..15) + LCK9: u1, + /// Port x lock bit y (y= 0..15) + LCK10: u1, + /// Port x lock bit y (y= 0..15) + LCK11: u1, + /// Port x lock bit y (y= 0..15) + LCK12: u1, + /// Port x lock bit y (y= 0..15) + LCK13: u1, + /// Port x lock bit y (y= 0..15) + LCK14: u1, + /// Port x lock bit y (y= 0..15) + LCK15: u1, + /// Port x lock bit y (y= 0..15) + LCKK: u1, + padding: u15, + }), + /// GPIO alternate function low register + AFRL: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 0..7) + AFRL0: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL1: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL2: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL3: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL4: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL5: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL6: u4, + /// Alternate function selection for port x bit y (y = 0..7) + AFRL7: u4, + }), + /// GPIO alternate function high register + AFRH: mmio.Mmio(packed struct(u32) { + /// Alternate function selection for port x bit y (y = 8..15) + AFRH8: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH9: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH10: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH11: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH12: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH13: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH14: u4, + /// Alternate function selection for port x bit y (y = 8..15) + AFRH15: u4, + }), + }; + + /// System configuration controller + pub const SYSCFG = extern struct { + /// memory remap register + MEMRM: mmio.Mmio(packed struct(u32) { + /// Memory mapping selection + MEM_MODE: u3, + reserved8: u5, + /// Flash bank mode selection + FB_MODE: u1, + reserved10: u1, + /// FMC memory mapping swap + SWP_FMC: u2, + padding: u20, + }), + /// peripheral mode configuration register + PMC: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// ADC1DC2 + ADC1DC2: u1, + /// ADC2DC2 + ADC2DC2: u1, + /// ADC3DC2 + ADC3DC2: u1, + reserved23: u4, + /// Ethernet PHY interface selection + MII_RMII_SEL: u1, + padding: u8, + }), + /// external interrupt configuration register 1 + EXTICR1: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 0 to 3) + EXTI0: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI1: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI2: u4, + /// EXTI x configuration (x = 0 to 3) + EXTI3: u4, + padding: u16, + }), + /// external interrupt configuration register 2 + EXTICR2: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 4 to 7) + EXTI4: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI5: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI6: u4, + /// EXTI x configuration (x = 4 to 7) + EXTI7: u4, + padding: u16, + }), + /// external interrupt configuration register 3 + EXTICR3: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 8 to 11) + EXTI8: u4, + /// EXTI x configuration (x = 8 to 11) + EXTI9: u4, + /// EXTI10 + EXTI10: u4, + /// EXTI x configuration (x = 8 to 11) + EXTI11: u4, + padding: u16, + }), + /// external interrupt configuration register 4 + EXTICR4: mmio.Mmio(packed struct(u32) { + /// EXTI x configuration (x = 12 to 15) + EXTI12: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI13: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI14: u4, + /// EXTI x configuration (x = 12 to 15) + EXTI15: u4, + padding: u16, + }), + reserved32: [8]u8, + /// Compensation cell control register + CMPCR: mmio.Mmio(packed struct(u32) { + /// Compensation cell power-down + CMP_PD: u1, + reserved8: u7, + /// READY + READY: u1, + padding: u23, + }), + }; + + /// Serial peripheral interface + pub const SPI1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Master selection + MSTR: u1, + /// Baud rate control + BR: u3, + /// SPI enable + SPE: u1, + /// Frame format + LSBFIRST: u1, + /// Internal slave select + SSI: u1, + /// Software slave management + SSM: u1, + /// Receive only + RXONLY: u1, + /// Data frame format + DFF: u1, + /// CRC transfer next + CRCNEXT: u1, + /// Hardware CRC calculation enable + CRCEN: u1, + /// Output enable in bidirectional mode + BIDIOE: u1, + /// Bidirectional data mode enable + BIDIMODE: u1, + padding: u16, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Rx buffer DMA enable + RXDMAEN: u1, + /// Tx buffer DMA enable + TXDMAEN: u1, + /// SS output enable + SSOE: u1, + reserved4: u1, + /// Frame format + FRF: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RXNEIE: u1, + /// Tx buffer empty interrupt enable + TXEIE: u1, + padding: u24, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Receive buffer not empty + RXNE: u1, + /// Transmit buffer empty + TXE: u1, + /// Channel side + CHSIDE: u1, + /// Underrun flag + UDR: u1, + /// CRC error flag + CRCERR: u1, + /// Mode fault + MODF: u1, + /// Overrun flag + OVR: u1, + /// Busy flag + BSY: u1, + /// TI frame format error + TIFRFE: u1, + padding: u23, + }), + /// data register + DR: mmio.Mmio(packed struct(u32) { + /// Data register + DR: u16, + padding: u16, + }), + /// CRC polynomial register + CRCPR: mmio.Mmio(packed struct(u32) { + /// CRC polynomial register + CRCPOLY: u16, + padding: u16, + }), + /// RX CRC register + RXCRCR: mmio.Mmio(packed struct(u32) { + /// Rx CRC register + RxCRC: u16, + padding: u16, + }), + /// TX CRC register + TXCRCR: mmio.Mmio(packed struct(u32) { + /// Tx CRC register + TxCRC: u16, + padding: u16, + }), + /// I2S configuration register + I2SCFGR: mmio.Mmio(packed struct(u32) { + /// Channel length (number of bits per audio channel) + CHLEN: u1, + /// Data length to be transferred + DATLEN: u2, + /// Steady state clock polarity + CKPOL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved7: u1, + /// PCM frame synchronization + PCMSYNC: u1, + /// I2S configuration mode + I2SCFG: u2, + /// I2S Enable + I2SE: u1, + /// I2S mode selection + I2SMOD: u1, + padding: u20, + }), + /// I2S prescaler register + I2SPR: mmio.Mmio(packed struct(u32) { + /// I2S Linear prescaler + I2SDIV: u8, + /// Odd factor for the prescaler + ODD: u1, + /// Master clock output enable + MCKOE: u1, + padding: u22, + }), + }; + + /// Inter-integrated circuit + pub const I2C3 = extern struct { + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Peripheral enable + PE: u1, + /// SMBus mode + SMBUS: u1, + reserved3: u1, + /// SMBus type + SMBTYPE: u1, + /// ARP enable + ENARP: u1, + /// PEC enable + ENPEC: u1, + /// General call enable + ENGC: u1, + /// Clock stretching disable (Slave mode) + NOSTRETCH: u1, + /// Start generation + START: u1, + /// Stop generation + STOP: u1, + /// Acknowledge enable + ACK: u1, + /// Acknowledge/PEC Position (for data reception) + POS: u1, + /// Packet error checking + PEC: u1, + /// SMBus alert + ALERT: u1, + reserved15: u1, + /// Software reset + SWRST: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Peripheral clock frequency + FREQ: u6, + reserved8: u2, + /// Error interrupt enable + ITERREN: u1, + /// Event interrupt enable + ITEVTEN: u1, + /// Buffer interrupt enable + ITBUFEN: u1, + /// DMA requests enable + DMAEN: u1, + /// DMA last transfer + LAST: u1, + padding: u19, + }), + /// Own address register 1 + OAR1: mmio.Mmio(packed struct(u32) { + /// Interface address + ADD0: u1, + /// Interface address + ADD7: u7, + /// Interface address + ADD10: u2, + reserved15: u5, + /// Addressing mode (slave mode) + ADDMODE: u1, + padding: u16, + }), + /// Own address register 2 + OAR2: mmio.Mmio(packed struct(u32) { + /// Dual addressing mode enable + ENDUAL: u1, + /// Interface address + ADD2: u7, + padding: u24, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// 8-bit data register + DR: u8, + padding: u24, + }), + /// Status register 1 + SR1: mmio.Mmio(packed struct(u32) { + /// Start bit (Master mode) + SB: u1, + /// Address sent (master mode)/matched (slave mode) + ADDR: u1, + /// Byte transfer finished + BTF: u1, + /// 10-bit header sent (Master mode) + ADD10: u1, + /// Stop detection (slave mode) + STOPF: u1, + reserved6: u1, + /// Data register not empty (receivers) + RxNE: u1, + /// Data register empty (transmitters) + TxE: u1, + /// Bus error + BERR: u1, + /// Arbitration lost (master mode) + ARLO: u1, + /// Acknowledge failure + AF: u1, + /// Overrun/Underrun + OVR: u1, + /// PEC Error in reception + PECERR: u1, + reserved14: u1, + /// Timeout or Tlow error + TIMEOUT: u1, + /// SMBus alert + SMBALERT: u1, + padding: u16, + }), + /// Status register 2 + SR2: mmio.Mmio(packed struct(u32) { + /// Master/slave + MSL: u1, + /// Bus busy + BUSY: u1, + /// Transmitter/receiver + TRA: u1, + reserved4: u1, + /// General call address (Slave mode) + GENCALL: u1, + /// SMBus device default address (Slave mode) + SMBDEFAULT: u1, + /// SMBus host header (Slave mode) + SMBHOST: u1, + /// Dual flag (Slave mode) + DUALF: u1, + /// acket error checking register + PEC: u8, + padding: u16, + }), + /// Clock control register + CCR: mmio.Mmio(packed struct(u32) { + /// Clock control register in Fast/Standard mode (Master mode) + CCR: u12, + reserved14: u2, + /// Fast mode duty cycle + DUTY: u1, + /// I2C master mode selection + F_S: u1, + padding: u16, + }), + /// TRISE register + TRISE: mmio.Mmio(packed struct(u32) { + /// Maximum rise time in Fast/Standard mode (Master mode) + TRISE: u6, + padding: u26, + }), + /// I2C FLTR register + FLTR: mmio.Mmio(packed struct(u32) { + /// Digital noise filter + DNF: u4, + /// Analog noise filter OFF + ANOFF: u1, + padding: u27, + }), + }; + + /// DMA2D controller + pub const DMA2D = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Start + START: u1, + /// Suspend + SUSP: u1, + /// Abort + ABORT: u1, + reserved8: u5, + /// Transfer error interrupt enable + TEIE: u1, + /// Transfer complete interrupt enable + TCIE: u1, + /// Transfer watermark interrupt enable + TWIE: u1, + /// CLUT access error interrupt enable + CAEIE: u1, + /// CLUT transfer complete interrupt enable + CTCIE: u1, + /// Configuration Error Interrupt Enable + CEIE: u1, + reserved16: u2, + /// DMA2D mode + MODE: u2, + padding: u14, + }), + /// Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Transfer error interrupt flag + TEIF: u1, + /// Transfer complete interrupt flag + TCIF: u1, + /// Transfer watermark interrupt flag + TWIF: u1, + /// CLUT access error interrupt flag + CAEIF: u1, + /// CLUT transfer complete interrupt flag + CTCIF: u1, + /// Configuration error interrupt flag + CEIF: u1, + padding: u26, + }), + /// interrupt flag clear register + IFCR: mmio.Mmio(packed struct(u32) { + /// Clear Transfer error interrupt flag + CTEIF: u1, + /// Clear transfer complete interrupt flag + CTCIF: u1, + /// Clear transfer watermark interrupt flag + CTWIF: u1, + /// Clear CLUT access error interrupt flag + CAECIF: u1, + /// Clear CLUT transfer complete interrupt flag + CCTCIF: u1, + /// Clear configuration error interrupt flag + CCEIF: u1, + padding: u26, + }), + /// foreground memory address register + FGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + /// foreground offset register + FGOR: mmio.Mmio(packed struct(u32) { + /// Line offset + LO: u14, + padding: u18, + }), + /// background memory address register + BGMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + /// background offset register + BGOR: mmio.Mmio(packed struct(u32) { + /// Line offset + LO: u14, + padding: u18, + }), + /// foreground PFC control register + FGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: u4, + /// CLUT color mode + CCM: u1, + /// Start + START: u1, + reserved8: u2, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved24: u6, + /// Alpha value + ALPHA: u8, + }), + /// foreground color register + FGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding: u8, + }), + /// background PFC control register + BGPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: u4, + /// CLUT Color mode + CCM: u1, + /// Start + START: u1, + reserved8: u2, + /// CLUT size + CS: u8, + /// Alpha mode + AM: u2, + reserved24: u6, + /// Alpha value + ALPHA: u8, + }), + /// background color register + BGCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + padding: u8, + }), + /// foreground CLUT memory address register + FGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address + MA: u32, + }), + /// background CLUT memory address register + BGCMAR: mmio.Mmio(packed struct(u32) { + /// Memory address + MA: u32, + }), + /// output PFC control register + OPFCCR: mmio.Mmio(packed struct(u32) { + /// Color mode + CM: u3, + padding: u29, + }), + /// output color register + OCOLR: mmio.Mmio(packed struct(u32) { + /// Blue Value + BLUE: u8, + /// Green Value + GREEN: u8, + /// Red Value + RED: u8, + /// Alpha Channel Value + APLHA: u8, + }), + /// output memory address register + OMAR: mmio.Mmio(packed struct(u32) { + /// Memory Address + MA: u32, + }), + /// output offset register + OOR: mmio.Mmio(packed struct(u32) { + /// Line Offset + LO: u14, + padding: u18, + }), + /// number of line register + NLR: mmio.Mmio(packed struct(u32) { + /// Number of lines + NL: u16, + /// Pixel per lines + PL: u14, + padding: u2, + }), + /// line watermark register + LWR: mmio.Mmio(packed struct(u32) { + /// Line watermark + LW: u16, + padding: u16, + }), + /// AHB master timer configuration register + AMTCR: mmio.Mmio(packed struct(u32) { + /// Enable + EN: u1, + reserved8: u7, + /// Dead Time + DT: u8, + padding: u16, + }), + reserved1024: [944]u8, + /// FGCLUT + FGCLUT: mmio.Mmio(packed struct(u32) { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), + reserved2048: [1020]u8, + /// BGCLUT + BGCLUT: mmio.Mmio(packed struct(u32) { + /// BLUE + BLUE: u8, + /// GREEN + GREEN: u8, + /// RED + RED: u8, + /// APLHA + APLHA: u8, + }), + }; + + /// Serial audio interface + pub const SAI = extern struct { + reserved4: [4]u8, + /// AConfiguration register 1 + ACR1: mmio.Mmio(packed struct(u32) { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved5: u1, + /// Data size + DS: u3, + /// Least significant bit first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved16: u2, + /// Audio block A enable + SAIAEN: u1, + /// DMA enable + DMAEN: u1, + reserved19: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding: u8, + }), + /// AConfiguration register 2 + ACR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding: u16, + }), + /// AFRCR + AFRCR: mmio.Mmio(packed struct(u32) { + /// Frame length + FRL: u8, + /// Frame synchronization active level length + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition + FSDEF: u1, + /// Frame synchronization polarity + FSPOL: u1, + /// Frame synchronization offset + FSOFF: u1, + padding: u13, + }), + /// ASlot register + ASLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset + FBOFF: u5, + reserved6: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio frame + NBSLOT: u4, + reserved16: u4, + /// Slot enable + SLOTEN: u16, + }), + /// AInterrupt mask register2 + AIM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable + OVRUDRIE: u1, + /// Mute detection interrupt enable + MUTEDET: u1, + /// Wrong clock configuration interrupt enable + WCKCFG: u1, + /// FIFO request interrupt enable + FREQIE: u1, + /// Codec not ready interrupt enable + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable + LFSDET: u1, + padding: u25, + }), + /// AStatus register + ASR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag. This bit is read only. + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization detection + AFSDET: u1, + /// Late frame synchronization detection + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold + FLVL: u3, + padding: u13, + }), + /// AClear flag register + ACLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration flag + WCKCFG: u1, + reserved4: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization detection flag. + CAFSDET: u1, + /// Clear late frame synchronization detection flag + LFSDET: u1, + padding: u25, + }), + /// AData register + ADR: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, + }), + /// BConfiguration register 1 + BCR1: mmio.Mmio(packed struct(u32) { + /// Audio block mode + MODE: u2, + /// Protocol configuration + PRTCFG: u2, + reserved5: u1, + /// Data size + DS: u3, + /// Least significant bit first + LSBFIRST: u1, + /// Clock strobing edge + CKSTR: u1, + /// Synchronization enable + SYNCEN: u2, + /// Mono mode + MONO: u1, + /// Output drive + OutDri: u1, + reserved16: u2, + /// Audio block B enable + SAIBEN: u1, + /// DMA enable + DMAEN: u1, + reserved19: u1, + /// No divider + NODIV: u1, + /// Master clock divider + MCJDIV: u4, + padding: u8, + }), + /// BConfiguration register 2 + BCR2: mmio.Mmio(packed struct(u32) { + /// FIFO threshold + FTH: u3, + /// FIFO flush + FFLUS: u1, + /// Tristate management on data line + TRIS: u1, + /// Mute + MUTE: u1, + /// Mute value + MUTEVAL: u1, + /// Mute counter + MUTECN: u6, + /// Complement bit + CPL: u1, + /// Companding mode + COMP: u2, + padding: u16, + }), + /// BFRCR + BFRCR: mmio.Mmio(packed struct(u32) { + /// Frame length + FRL: u8, + /// Frame synchronization active level length + FSALL: u7, + reserved16: u1, + /// Frame synchronization definition + FSDEF: u1, + /// Frame synchronization polarity + FSPOL: u1, + /// Frame synchronization offset + FSOFF: u1, + padding: u13, + }), + /// BSlot register + BSLOTR: mmio.Mmio(packed struct(u32) { + /// First bit offset + FBOFF: u5, + reserved6: u1, + /// Slot size + SLOTSZ: u2, + /// Number of slots in an audio frame + NBSLOT: u4, + reserved16: u4, + /// Slot enable + SLOTEN: u16, + }), + /// BInterrupt mask register2 + BIM: mmio.Mmio(packed struct(u32) { + /// Overrun/underrun interrupt enable + OVRUDRIE: u1, + /// Mute detection interrupt enable + MUTEDET: u1, + /// Wrong clock configuration interrupt enable + WCKCFG: u1, + /// FIFO request interrupt enable + FREQIE: u1, + /// Codec not ready interrupt enable + CNRDYIE: u1, + /// Anticipated frame synchronization detection interrupt enable + AFSDETIE: u1, + /// Late frame synchronization detection interrupt enable + LFSDETIE: u1, + padding: u25, + }), + /// BStatus register + BSR: mmio.Mmio(packed struct(u32) { + /// Overrun / underrun + OVRUDR: u1, + /// Mute detection + MUTEDET: u1, + /// Wrong clock configuration flag + WCKCFG: u1, + /// FIFO request + FREQ: u1, + /// Codec not ready + CNRDY: u1, + /// Anticipated frame synchronization detection + AFSDET: u1, + /// Late frame synchronization detection + LFSDET: u1, + reserved16: u9, + /// FIFO level threshold + FLVL: u3, + padding: u13, + }), + /// BClear flag register + BCLRFR: mmio.Mmio(packed struct(u32) { + /// Clear overrun / underrun + OVRUDR: u1, + /// Mute detection flag + MUTEDET: u1, + /// Clear wrong clock configuration flag + WCKCFG: u1, + reserved4: u1, + /// Clear codec not ready flag + CNRDY: u1, + /// Clear anticipated frame synchronization detection flag + CAFSDET: u1, + /// Clear late frame synchronization detection flag + LFSDET: u1, + padding: u25, + }), + /// BData register + BDR: mmio.Mmio(packed struct(u32) { + /// Data + DATA: u32, + }), + }; + + /// LCD-TFT Controller + pub const LTDC = extern struct { + reserved8: [8]u8, + /// Synchronization Size Configuration Register + SSCR: mmio.Mmio(packed struct(u32) { + /// Vertical Synchronization Height (in units of horizontal scan line) + VSH: u11, + reserved16: u5, + /// Horizontal Synchronization Width (in units of pixel clock period) + HSW: u10, + padding: u6, + }), + /// Back Porch Configuration Register + BPCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Vertical back porch (in units of horizontal scan line) + AVBP: u11, + reserved16: u5, + /// Accumulated Horizontal back porch (in units of pixel clock period) + AHBP: u10, + padding: u6, + }), + /// Active Width Configuration Register + AWCR: mmio.Mmio(packed struct(u32) { + /// Accumulated Active Height (in units of horizontal scan line) + AAH: u11, + reserved16: u5, + /// AAV + AAV: u10, + padding: u6, + }), + /// Total Width Configuration Register + TWCR: mmio.Mmio(packed struct(u32) { + /// Total Height (in units of horizontal scan line) + TOTALH: u11, + reserved16: u5, + /// Total Width (in units of pixel clock period) + TOTALW: u10, + padding: u6, + }), + /// Global Control Register + GCR: mmio.Mmio(packed struct(u32) { + /// LCD-TFT controller enable bit + LTDCEN: u1, + reserved4: u3, + /// Dither Blue Width + DBW: u3, + reserved8: u1, + /// Dither Green Width + DGW: u3, + reserved12: u1, + /// Dither Red Width + DRW: u3, + reserved16: u1, + /// Dither Enable + DEN: u1, + reserved28: u11, + /// Pixel Clock Polarity + PCPOL: u1, + /// Data Enable Polarity + DEPOL: u1, + /// Vertical Synchronization Polarity + VSPOL: u1, + /// Horizontal Synchronization Polarity + HSPOL: u1, + }), + reserved36: [8]u8, + /// Shadow Reload Configuration Register + SRCR: mmio.Mmio(packed struct(u32) { + /// Immediate Reload + IMR: u1, + /// Vertical Blanking Reload + VBR: u1, + padding: u30, + }), + reserved44: [4]u8, + /// Background Color Configuration Register + BCCR: mmio.Mmio(packed struct(u32) { + /// Background Color Red value + BC: u24, + padding: u8, + }), + reserved52: [4]u8, + /// Interrupt Enable Register + IER: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Enable + LIE: u1, + /// FIFO Underrun Interrupt Enable + FUIE: u1, + /// Transfer Error Interrupt Enable + TERRIE: u1, + /// Register Reload interrupt enable + RRIE: u1, + padding: u28, + }), + /// Interrupt Status Register + ISR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt flag + LIF: u1, + /// FIFO Underrun Interrupt flag + FUIF: u1, + /// Transfer Error interrupt flag + TERRIF: u1, + /// Register Reload Interrupt Flag + RRIF: u1, + padding: u28, + }), + /// Interrupt Clear Register + ICR: mmio.Mmio(packed struct(u32) { + /// Clears the Line Interrupt Flag + CLIF: u1, + /// Clears the FIFO Underrun Interrupt flag + CFUIF: u1, + /// Clears the Transfer Error Interrupt Flag + CTERRIF: u1, + /// Clears Register Reload Interrupt Flag + CRRIF: u1, + padding: u28, + }), + /// Line Interrupt Position Configuration Register + LIPCR: mmio.Mmio(packed struct(u32) { + /// Line Interrupt Position + LIPOS: u11, + padding: u21, + }), + /// Current Position Status Register + CPSR: mmio.Mmio(packed struct(u32) { + /// Current Y Position + CYPOS: u16, + /// Current X Position + CXPOS: u16, + }), + /// Current Display Status Register + CDSR: mmio.Mmio(packed struct(u32) { + /// Vertical Data Enable display Status + VDES: u1, + /// Horizontal Data Enable display Status + HDES: u1, + /// Vertical Synchronization display Status + VSYNCS: u1, + /// Horizontal Synchronization display Status + HSYNCS: u1, + padding: u28, + }), + reserved132: [56]u8, + /// Layerx Control Register + L1CR: mmio.Mmio(packed struct(u32) { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved4: u2, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding: u27, + }), + /// Layerx Window Horizontal Position Configuration Register + L1WHPCR: mmio.Mmio(packed struct(u32) { + /// Window Horizontal Start Position + WHSTPOS: u12, + reserved16: u4, + /// Window Horizontal Stop Position + WHSPPOS: u12, + padding: u4, + }), + /// Layerx Window Vertical Position Configuration Register + L1WVPCR: mmio.Mmio(packed struct(u32) { + /// Window Vertical Start Position + WVSTPOS: u11, + reserved16: u5, + /// Window Vertical Stop Position + WVSPPOS: u11, + padding: u5, + }), + /// Layerx Color Keying Configuration Register + L1CKCR: mmio.Mmio(packed struct(u32) { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u8, + /// Color Key Red value + CKRED: u8, + padding: u8, + }), + /// Layerx Pixel Format Configuration Register + L1PFCR: mmio.Mmio(packed struct(u32) { + /// Pixel Format + PF: u3, + padding: u29, + }), + /// Layerx Constant Alpha Configuration Register + L1CACR: mmio.Mmio(packed struct(u32) { + /// Constant Alpha + CONSTA: u8, + padding: u24, + }), + /// Layerx Default Color Configuration Register + L1DCCR: mmio.Mmio(packed struct(u32) { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), + /// Layerx Blending Factors Configuration Register + L1BFCR: mmio.Mmio(packed struct(u32) { + /// Blending Factor 2 + BF2: u3, + reserved8: u5, + /// Blending Factor 1 + BF1: u3, + padding: u21, + }), + reserved172: [8]u8, + /// Layerx Color Frame Buffer Address Register + L1CFBAR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Start Address + CFBADD: u32, + }), + /// Layerx Color Frame Buffer Length Register + L1CFBLR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Line Length + CFBLL: u13, + reserved16: u3, + /// Color Frame Buffer Pitch in bytes + CFBP: u13, + padding: u3, + }), + /// Layerx ColorFrame Buffer Line Number Register + L1CFBLNR: mmio.Mmio(packed struct(u32) { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding: u21, + }), + reserved196: [12]u8, + /// Layerx CLUT Write Register + L1CLUTWR: mmio.Mmio(packed struct(u32) { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), + reserved260: [60]u8, + /// Layerx Control Register + L2CR: mmio.Mmio(packed struct(u32) { + /// Layer Enable + LEN: u1, + /// Color Keying Enable + COLKEN: u1, + reserved4: u2, + /// Color Look-Up Table Enable + CLUTEN: u1, + padding: u27, + }), + /// Layerx Window Horizontal Position Configuration Register + L2WHPCR: mmio.Mmio(packed struct(u32) { + /// Window Horizontal Start Position + WHSTPOS: u12, + reserved16: u4, + /// Window Horizontal Stop Position + WHSPPOS: u12, + padding: u4, + }), + /// Layerx Window Vertical Position Configuration Register + L2WVPCR: mmio.Mmio(packed struct(u32) { + /// Window Vertical Start Position + WVSTPOS: u11, + reserved16: u5, + /// Window Vertical Stop Position + WVSPPOS: u11, + padding: u5, + }), + /// Layerx Color Keying Configuration Register + L2CKCR: mmio.Mmio(packed struct(u32) { + /// Color Key Blue value + CKBLUE: u8, + /// Color Key Green value + CKGREEN: u7, + /// Color Key Red value + CKRED: u9, + padding: u8, + }), + /// Layerx Pixel Format Configuration Register + L2PFCR: mmio.Mmio(packed struct(u32) { + /// Pixel Format + PF: u3, + padding: u29, + }), + /// Layerx Constant Alpha Configuration Register + L2CACR: mmio.Mmio(packed struct(u32) { + /// Constant Alpha + CONSTA: u8, + padding: u24, + }), + /// Layerx Default Color Configuration Register + L2DCCR: mmio.Mmio(packed struct(u32) { + /// Default Color Blue + DCBLUE: u8, + /// Default Color Green + DCGREEN: u8, + /// Default Color Red + DCRED: u8, + /// Default Color Alpha + DCALPHA: u8, + }), + /// Layerx Blending Factors Configuration Register + L2BFCR: mmio.Mmio(packed struct(u32) { + /// Blending Factor 2 + BF2: u3, + reserved8: u5, + /// Blending Factor 1 + BF1: u3, + padding: u21, + }), + reserved300: [8]u8, + /// Layerx Color Frame Buffer Address Register + L2CFBAR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Start Address + CFBADD: u32, + }), + /// Layerx Color Frame Buffer Length Register + L2CFBLR: mmio.Mmio(packed struct(u32) { + /// Color Frame Buffer Line Length + CFBLL: u13, + reserved16: u3, + /// Color Frame Buffer Pitch in bytes + CFBP: u13, + padding: u3, + }), + /// Layerx ColorFrame Buffer Line Number Register + L2CFBLNR: mmio.Mmio(packed struct(u32) { + /// Frame Buffer Line Number + CFBLNBR: u11, + padding: u21, + }), + reserved324: [12]u8, + /// Layerx CLUT Write Register + L2CLUTWR: mmio.Mmio(packed struct(u32) { + /// Blue value + BLUE: u8, + /// Green value + GREEN: u8, + /// Red value + RED: u8, + /// CLUT Address + CLUTADD: u8, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_PWRCLK = extern struct { + /// Power and clock gating control register + OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY suspended + PHYSUSP: u1, + padding: u27, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_DEVICE = extern struct { + /// OTG_HS device configuration register + OTG_HS_DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: u2, + /// Nonzero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic (micro)frame interval + PFIVL: u2, + reserved24: u11, + /// Periodic scheduling interval + PERSCHIVL: u2, + padding: u6, + }), + /// OTG_HS device control register + OTG_HS_DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, + }), + /// OTG_HS device status register + OTG_HS_DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// OTG_HS device IN endpoint common interrupt mask register + OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (nonisochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + padding: u22, + }), + /// OTG_HS device OUT endpoint common interrupt mask register + OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + reserved6: u1, + /// Back-to-back SETUP packets received mask + B2BSTUP: u1, + reserved8: u1, + /// OUT packet error mask + OPEM: u1, + /// BNA interrupt mask + BOIM: u1, + padding: u22, + }), + /// OTG_HS device all endpoints interrupt register + OTG_HS_DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + /// OTG_HS all endpoints interrupt mask register + OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT EP interrupt mask bits + OEPM: u16, + }), + reserved40: [8]u8, + /// OTG_HS device VBUS discharge time register + OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, + }), + /// OTG_HS device VBUS pulsing time register + OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + /// OTG_HS Device threshold control register + OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) { + /// Nonisochronous IN endpoints threshold enable + NONISOTHREN: u1, + /// ISO IN endpoint threshold enable + ISOTHREN: u1, + /// Transmit threshold length + TXTHRLEN: u9, + reserved16: u5, + /// Receive threshold enable + RXTHREN: u1, + /// Receive threshold length + RXTHRLEN: u9, + reserved27: u1, + /// Arbiter parking enable + ARPEN: u1, + padding: u4, + }), + /// OTG_HS device IN endpoint FIFO empty interrupt mask register + OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + /// OTG_HS device each endpoint interrupt register + OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// IN endpoint 1interrupt bit + IEP1INT: u1, + reserved17: u15, + /// OUT endpoint 1 interrupt bit + OEP1INT: u1, + padding: u14, + }), + /// OTG_HS device each endpoint interrupt register mask + OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// IN Endpoint 1 interrupt mask bit + IEP1INTM: u1, + reserved17: u15, + /// OUT Endpoint 1 interrupt mask bit + OEP1INTM: u1, + padding: u14, + }), + /// OTG_HS device each in endpoint-1 interrupt register + OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (nonisochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// FIFO underrun mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved13: u3, + /// NAK interrupt mask + NAKM: u1, + padding: u18, + }), + reserved128: [60]u8, + /// OTG_HS device each OUT endpoint-1 interrupt register + OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + reserved8: u1, + /// OUT packet error mask + TXFURM: u1, + /// BNA interrupt mask + BIM: u1, + reserved12: u2, + /// Bubble error interrupt mask + BERRM: u1, + /// NAK interrupt mask + NAKM: u1, + /// NYET interrupt mask + NYETM: u1, + padding: u17, + }), + reserved256: [124]u8, + /// OTG device endpoint-0 control register + OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved264: [4]u8, + /// OTG device endpoint-0 interrupt register + OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved272: [4]u8, + /// OTG_HS device IN endpoint 0 transfer size register + OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u2, + padding: u11, + }), + /// OTG_HS device endpoint-1 DMA address register + OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved288: [4]u8, + /// OTG device endpoint-1 control register + OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved296: [4]u8, + /// OTG device endpoint-1 interrupt register + OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved304: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-2 DMA address register + OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved320: [4]u8, + /// OTG device endpoint-2 control register + OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved328: [4]u8, + /// OTG device endpoint-2 interrupt register + OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved336: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-3 DMA address register + OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved352: [4]u8, + /// OTG device endpoint-3 control register + OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved360: [4]u8, + /// OTG device endpoint-3 interrupt register + OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved368: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-4 DMA address register + OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved384: [4]u8, + /// OTG device endpoint-4 control register + OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved392: [4]u8, + /// OTG device endpoint-4 interrupt register + OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved400: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + /// OTG_HS device endpoint-5 DMA address register + OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved416: [4]u8, + /// OTG device endpoint-5 control register + OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved424: [4]u8, + /// OTG device endpoint-5 interrupt register + OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved432: [4]u8, + /// OTG_HS device endpoint transfer size register + OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved440: [4]u8, + /// OTG_HS device IN endpoint transmit FIFO status register + OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space avail + INEPTFSAV: u16, + padding: u16, + }), + reserved448: [4]u8, + /// OTG device endpoint-6 control register + OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved456: [4]u8, + /// OTG device endpoint-6 interrupt register + OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved480: [20]u8, + /// OTG device endpoint-7 control register + OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even/odd frame + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + Stall: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved488: [4]u8, + /// OTG device endpoint-7 interrupt register + OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// Timeout condition + TOC: u1, + /// IN token received when TxFIFO is empty + ITTXFE: u1, + reserved6: u1, + /// IN endpoint NAK effective + INEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + /// Transmit Fifo Underrun + TXFIFOUDRN: u1, + /// Buffer not available interrupt + BNA: u1, + reserved11: u1, + /// Packet dropped status + PKTDRPSTS: u1, + /// Babble error interrupt + BERR: u1, + /// NAK interrupt + NAK: u1, + padding: u18, + }), + reserved768: [276]u8, + /// OTG_HS device control OUT endpoint 0 control register + OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u2, + reserved15: u13, + /// USB active endpoint + USBAEP: u1, + reserved17: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved776: [4]u8, + /// OTG_HS device endpoint-0 interrupt register + OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved784: [4]u8, + /// OTG_HS device endpoint-1 transfer size register + OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u1, + reserved29: u9, + /// SETUP packet count + STUPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// OTG device endpoint-1 control register + OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved808: [4]u8, + /// OTG_HS device endpoint-1 interrupt register + OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved816: [4]u8, + /// OTG_HS device endpoint-2 transfer size register + OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved832: [12]u8, + /// OTG device endpoint-2 control register + OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved840: [4]u8, + /// OTG_HS device endpoint-2 interrupt register + OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved848: [4]u8, + /// OTG_HS device endpoint-3 transfer size register + OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved864: [12]u8, + /// OTG device endpoint-3 control register + OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + reserved15: u4, + /// USB active endpoint + USBAEP: u1, + /// Even odd frame/Endpoint data PID + EONUM_DPID: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + /// Snoop mode + SNPM: u1, + /// STALL handshake + Stall: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// Set DATA0 PID/Set even frame + SD0PID_SEVNFRM: u1, + /// Set odd frame + SODDFRM: u1, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved872: [4]u8, + /// OTG_HS device endpoint-3 interrupt register + OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved880: [4]u8, + /// OTG_HS device endpoint-4 transfer size register + OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved904: [20]u8, + /// OTG_HS device endpoint-4 interrupt register + OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved912: [4]u8, + /// OTG_HS device endpoint-5 transfer size register + OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved936: [20]u8, + /// OTG_HS device endpoint-5 interrupt register + OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved968: [28]u8, + /// OTG_HS device endpoint-6 interrupt register + OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + reserved1000: [28]u8, + /// OTG_HS device endpoint-7 interrupt register + OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt + XFRC: u1, + /// Endpoint disabled interrupt + EPDISD: u1, + reserved3: u1, + /// SETUP phase done + STUP: u1, + /// OUT token received when endpoint disabled + OTEPDIS: u1, + reserved6: u1, + /// Back-to-back SETUP packets received + B2BSTUP: u1, + reserved14: u7, + /// NYET interrupt + NYET: u1, + padding: u17, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_HOST = extern struct { + /// OTG_HS host configuration register + OTG_HS_HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, + }), + /// OTG_HS Host frame interval register + OTG_HS_HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, + }), + /// OTG_HS host frame number/frame time remaining register + OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), + reserved16: [4]u8, + /// OTG_HS_Host periodic transmit FIFO/queue status register + OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, + }), + /// OTG_HS Host all channels interrupt register + OTG_HS_HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, + }), + /// OTG_HS host all channels interrupt mask register + OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, + }), + reserved64: [36]u8, + /// OTG_HS host port control and status register + OTG_HS_HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, + }), + reserved256: [188]u8, + /// OTG_HS host channel-0 characteristics register + OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-0 split control register + OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-11 interrupt register + OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-11 interrupt mask register + OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-11 transfer size register + OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-0 DMA address register + OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved288: [8]u8, + /// OTG_HS host channel-1 characteristics register + OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-1 split control register + OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-1 interrupt register + OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-1 interrupt mask register + OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-1 transfer size register + OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-1 DMA address register + OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved320: [8]u8, + /// OTG_HS host channel-2 characteristics register + OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-2 split control register + OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-2 interrupt register + OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-2 interrupt mask register + OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-2 transfer size register + OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-2 DMA address register + OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved352: [8]u8, + /// OTG_HS host channel-3 characteristics register + OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-3 split control register + OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-3 interrupt register + OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-3 interrupt mask register + OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-3 transfer size register + OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-3 DMA address register + OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved384: [8]u8, + /// OTG_HS host channel-4 characteristics register + OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-4 split control register + OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-4 interrupt register + OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-4 interrupt mask register + OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-4 transfer size register + OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-4 DMA address register + OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved416: [8]u8, + /// OTG_HS host channel-5 characteristics register + OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-5 split control register + OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-5 interrupt register + OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-5 interrupt mask register + OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-5 transfer size register + OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-5 DMA address register + OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved448: [8]u8, + /// OTG_HS host channel-6 characteristics register + OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-6 split control register + OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-6 interrupt register + OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-6 interrupt mask register + OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-6 transfer size register + OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-6 DMA address register + OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved480: [8]u8, + /// OTG_HS host channel-7 characteristics register + OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-7 split control register + OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-7 interrupt register + OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-7 interrupt mask register + OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-7 transfer size register + OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-7 DMA address register + OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved512: [8]u8, + /// OTG_HS host channel-8 characteristics register + OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-8 split control register + OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-8 interrupt register + OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-8 interrupt mask register + OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-8 transfer size register + OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-8 DMA address register + OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved544: [8]u8, + /// OTG_HS host channel-9 characteristics register + OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-9 split control register + OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-9 interrupt register + OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-9 interrupt mask register + OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-9 transfer size register + OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-9 DMA address register + OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved576: [8]u8, + /// OTG_HS host channel-10 characteristics register + OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-10 split control register + OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-10 interrupt register + OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-10 interrupt mask register + OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-10 transfer size register + OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-10 DMA address register + OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + reserved608: [8]u8, + /// OTG_HS host channel-11 characteristics register + OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multi Count (MC) / Error Count (EC) + MC: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + /// OTG_HS host channel-11 split control register + OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) { + /// Port address + PRTADDR: u7, + /// Hub address + HUBADDR: u7, + /// XACTPOS + XACTPOS: u2, + /// Do complete split + COMPLSPLT: u1, + reserved31: u14, + /// Split enable + SPLITEN: u1, + }), + /// OTG_HS host channel-11 interrupt register + OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + /// Response received interrupt + NYET: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_HS host channel-11 interrupt mask register + OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + /// AHB error + AHBERR: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_HS host channel-11 transfer size register + OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + /// OTG_HS host channel-11 DMA address register + OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) { + /// DMA address + DMAADDR: u32, + }), + }; + + /// Secure digital input/output interface + pub const SDIO = extern struct { + /// power control register + POWER: mmio.Mmio(packed struct(u32) { + /// PWRCTRL + PWRCTRL: u2, + padding: u30, + }), + /// SDI clock control register + CLKCR: mmio.Mmio(packed struct(u32) { + /// Clock divide factor + CLKDIV: u8, + /// Clock enable bit + CLKEN: u1, + /// Power saving configuration bit + PWRSAV: u1, + /// Clock divider bypass enable bit + BYPASS: u1, + /// Wide bus mode enable bit + WIDBUS: u2, + /// SDIO_CK dephasing selection bit + NEGEDGE: u1, + /// HW Flow Control enable + HWFC_EN: u1, + padding: u17, + }), + /// argument register + ARG: mmio.Mmio(packed struct(u32) { + /// Command argument + CMDARG: u32, + }), + /// command register + CMD: mmio.Mmio(packed struct(u32) { + /// Command index + CMDINDEX: u6, + /// Wait for response bits + WAITRESP: u2, + /// CPSM waits for interrupt request + WAITINT: u1, + /// CPSM Waits for ends of data transfer (CmdPend internal signal). + WAITPEND: u1, + /// Command path state machine (CPSM) Enable bit + CPSMEN: u1, + /// SD I/O suspend command + SDIOSuspend: u1, + /// Enable CMD completion + ENCMDcompl: u1, + /// not Interrupt Enable + nIEN: u1, + /// CE-ATA command + CE_ATACMD: u1, + padding: u17, + }), + /// command response register + RESPCMD: mmio.Mmio(packed struct(u32) { + /// Response command index + RESPCMD: u6, + padding: u26, + }), + /// response 1..4 register + RESP1: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS1: u32, + }), + /// response 1..4 register + RESP2: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS2: u32, + }), + /// response 1..4 register + RESP3: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS3: u32, + }), + /// response 1..4 register + RESP4: mmio.Mmio(packed struct(u32) { + /// see Table 132. + CARDSTATUS4: u32, + }), + /// data timer register + DTIMER: mmio.Mmio(packed struct(u32) { + /// Data timeout period + DATATIME: u32, + }), + /// data length register + DLEN: mmio.Mmio(packed struct(u32) { + /// Data length value + DATALENGTH: u25, + padding: u7, + }), + /// data control register + DCTRL: mmio.Mmio(packed struct(u32) { + /// DTEN + DTEN: u1, + /// Data transfer direction selection + DTDIR: u1, + /// Data transfer mode selection 1: Stream or SDIO multibyte data transfer. + DTMODE: u1, + /// DMA enable bit + DMAEN: u1, + /// Data block size + DBLOCKSIZE: u4, + /// Read wait start + RWSTART: u1, + /// Read wait stop + RWSTOP: u1, + /// Read wait mode + RWMOD: u1, + /// SD I/O enable functions + SDIOEN: u1, + padding: u20, + }), + /// data counter register + DCOUNT: mmio.Mmio(packed struct(u32) { + /// Data count value + DATACOUNT: u25, + padding: u7, + }), + /// status register + STA: mmio.Mmio(packed struct(u32) { + /// Command response received (CRC check failed) + CCRCFAIL: u1, + /// Data block sent/received (CRC check failed) + DCRCFAIL: u1, + /// Command response timeout + CTIMEOUT: u1, + /// Data timeout + DTIMEOUT: u1, + /// Transmit FIFO underrun error + TXUNDERR: u1, + /// Received FIFO overrun error + RXOVERR: u1, + /// Command response received (CRC check passed) + CMDREND: u1, + /// Command sent (no response required) + CMDSENT: u1, + /// Data end (data counter, SDIDCOUNT, is zero) + DATAEND: u1, + /// Start bit not detected on all data signals in wide bus mode + STBITERR: u1, + /// Data block sent/received (CRC check passed) + DBCKEND: u1, + /// Command transfer in progress + CMDACT: u1, + /// Data transmit in progress + TXACT: u1, + /// Data receive in progress + RXACT: u1, + /// Transmit FIFO half empty: at least 8 words can be written into the FIFO + TXFIFOHE: u1, + /// Receive FIFO half full: there are at least 8 words in the FIFO + RXFIFOHF: u1, + /// Transmit FIFO full + TXFIFOF: u1, + /// Receive FIFO full + RXFIFOF: u1, + /// Transmit FIFO empty + TXFIFOE: u1, + /// Receive FIFO empty + RXFIFOE: u1, + /// Data available in transmit FIFO + TXDAVL: u1, + /// Data available in receive FIFO + RXDAVL: u1, + /// SDIO interrupt received + SDIOIT: u1, + /// CE-ATA command completion signal received for CMD61 + CEATAEND: u1, + padding: u8, + }), + /// interrupt clear register + ICR: mmio.Mmio(packed struct(u32) { + /// CCRCFAIL flag clear bit + CCRCFAILC: u1, + /// DCRCFAIL flag clear bit + DCRCFAILC: u1, + /// CTIMEOUT flag clear bit + CTIMEOUTC: u1, + /// DTIMEOUT flag clear bit + DTIMEOUTC: u1, + /// TXUNDERR flag clear bit + TXUNDERRC: u1, + /// RXOVERR flag clear bit + RXOVERRC: u1, + /// CMDREND flag clear bit + CMDRENDC: u1, + /// CMDSENT flag clear bit + CMDSENTC: u1, + /// DATAEND flag clear bit + DATAENDC: u1, + /// STBITERR flag clear bit + STBITERRC: u1, + /// DBCKEND flag clear bit + DBCKENDC: u1, + reserved22: u11, + /// SDIOIT flag clear bit + SDIOITC: u1, + /// CEATAEND flag clear bit + CEATAENDC: u1, + padding: u8, + }), + /// mask register + MASK: mmio.Mmio(packed struct(u32) { + /// Command CRC fail interrupt enable + CCRCFAILIE: u1, + /// Data CRC fail interrupt enable + DCRCFAILIE: u1, + /// Command timeout interrupt enable + CTIMEOUTIE: u1, + /// Data timeout interrupt enable + DTIMEOUTIE: u1, + /// Tx FIFO underrun error interrupt enable + TXUNDERRIE: u1, + /// Rx FIFO overrun error interrupt enable + RXOVERRIE: u1, + /// Command response received interrupt enable + CMDRENDIE: u1, + /// Command sent interrupt enable + CMDSENTIE: u1, + /// Data end interrupt enable + DATAENDIE: u1, + /// Start bit error interrupt enable + STBITERRIE: u1, + /// Data block end interrupt enable + DBCKENDIE: u1, + /// Command acting interrupt enable + CMDACTIE: u1, + /// Data transmit acting interrupt enable + TXACTIE: u1, + /// Data receive acting interrupt enable + RXACTIE: u1, + /// Tx FIFO half empty interrupt enable + TXFIFOHEIE: u1, + /// Rx FIFO half full interrupt enable + RXFIFOHFIE: u1, + /// Tx FIFO full interrupt enable + TXFIFOFIE: u1, + /// Rx FIFO full interrupt enable + RXFIFOFIE: u1, + /// Tx FIFO empty interrupt enable + TXFIFOEIE: u1, + /// Rx FIFO empty interrupt enable + RXFIFOEIE: u1, + /// Data available in Tx FIFO interrupt enable + TXDAVLIE: u1, + /// Data available in Rx FIFO interrupt enable + RXDAVLIE: u1, + /// SDIO mode interrupt received interrupt enable + SDIOITIE: u1, + /// CE-ATA command completion signal received interrupt enable + CEATAENDIE: u1, + padding: u8, + }), + reserved72: [8]u8, + /// FIFO counter register + FIFOCNT: mmio.Mmio(packed struct(u32) { + /// Remaining number of words to be written to or read from the FIFO. + FIFOCOUNT: u24, + padding: u8, + }), + reserved128: [52]u8, + /// data FIFO register + FIFO: mmio.Mmio(packed struct(u32) { + /// Receive and transmit FIFO data + FIFOData: u32, + }), + }; + + /// Analog-to-digital converter + pub const ADC1 = extern struct { + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag + AWD: u1, + /// Regular channel end of conversion + EOC: u1, + /// Injected channel end of conversion + JEOC: u1, + /// Injected channel start flag + JSTRT: u1, + /// Regular channel start flag + STRT: u1, + /// Overrun + OVR: u1, + padding: u26, + }), + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select bits + AWDCH: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Analog watchdog interrupt enable + AWDIE: u1, + /// Interrupt enable for injected channels + JEOCIE: u1, + /// Scan mode + SCAN: u1, + /// Enable the watchdog on a single channel in scan mode + AWDSGL: u1, + /// Automatic injected group conversion + JAUTO: u1, + /// Discontinuous mode on regular channels + DISCEN: u1, + /// Discontinuous mode on injected channels + JDISCEN: u1, + /// Discontinuous mode channel count + DISCNUM: u3, + reserved22: u6, + /// Analog watchdog enable on injected channels + JAWDEN: u1, + /// Analog watchdog enable on regular channels + AWDEN: u1, + /// Resolution + RES: u2, + /// Overrun interrupt enable + OVRIE: u1, + padding: u5, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// A/D Converter ON / OFF + ADON: u1, + /// Continuous conversion + CONT: u1, + reserved8: u6, + /// Direct memory access mode (for single ADC mode) + DMA: u1, + /// DMA disable selection (for single ADC mode) + DDS: u1, + /// End of conversion selection + EOCS: u1, + /// Data alignment + ALIGN: u1, + reserved16: u4, + /// External event select for injected group + JEXTSEL: u4, + /// External trigger enable for injected channels + JEXTEN: u2, + /// Start conversion of injected channels + JSWSTART: u1, + reserved24: u1, + /// External event select for regular group + EXTSEL: u4, + /// External trigger enable for regular channels + EXTEN: u2, + /// Start conversion of regular channels + SWSTART: u1, + padding: u1, + }), + /// sample time register 1 + SMPR1: mmio.Mmio(packed struct(u32) { + /// Sample time bits + SMPx_x: u32, + }), + /// sample time register 2 + SMPR2: mmio.Mmio(packed struct(u32) { + /// Sample time bits + SMPx_x: u32, + }), + /// injected channel data offset register x + JOFR1: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET1: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR2: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET2: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR3: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET3: u12, + padding: u20, + }), + /// injected channel data offset register x + JOFR4: mmio.Mmio(packed struct(u32) { + /// Data offset for injected channel x + JOFFSET4: u12, + padding: u20, + }), + /// watchdog higher threshold register + HTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + HT: u12, + padding: u20, + }), + /// watchdog lower threshold register + LTR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + LT: u12, + padding: u20, + }), + /// regular sequence register 1 + SQR1: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + SQ13: u5, + /// 14th conversion in regular sequence + SQ14: u5, + /// 15th conversion in regular sequence + SQ15: u5, + /// 16th conversion in regular sequence + SQ16: u5, + /// Regular channel sequence length + L: u4, + padding: u8, + }), + /// regular sequence register 2 + SQR2: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + SQ7: u5, + /// 8th conversion in regular sequence + SQ8: u5, + /// 9th conversion in regular sequence + SQ9: u5, + /// 10th conversion in regular sequence + SQ10: u5, + /// 11th conversion in regular sequence + SQ11: u5, + /// 12th conversion in regular sequence + SQ12: u5, + padding: u2, + }), + /// regular sequence register 3 + SQR3: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + SQ1: u5, + /// 2nd conversion in regular sequence + SQ2: u5, + /// 3rd conversion in regular sequence + SQ3: u5, + /// 4th conversion in regular sequence + SQ4: u5, + /// 5th conversion in regular sequence + SQ5: u5, + /// 6th conversion in regular sequence + SQ6: u5, + padding: u2, + }), + /// injected sequence register + JSQR: mmio.Mmio(packed struct(u32) { + /// 1st conversion in injected sequence + JSQ1: u5, + /// 2nd conversion in injected sequence + JSQ2: u5, + /// 3rd conversion in injected sequence + JSQ3: u5, + /// 4th conversion in injected sequence + JSQ4: u5, + /// Injected sequence length + JL: u2, + padding: u10, + }), + /// injected data register x + JDR1: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR2: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR3: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// injected data register x + JDR4: mmio.Mmio(packed struct(u32) { + /// Injected data + JDATA: u16, + padding: u16, + }), + /// regular data register + DR: mmio.Mmio(packed struct(u32) { + /// Regular data + DATA: u16, + padding: u16, + }), + }; + + /// USB on the go high speed + pub const OTG_HS_GLOBAL = extern struct { + /// OTG_HS control and status register + OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved8: u6, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, + }), + /// OTG_HS interrupt register + OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding: u12, + }), + /// OTG_HS AHB configuration register + OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + /// Burst length/type + HBSTLEN: u4, + /// DMA enable + DMAEN: u1, + reserved7: u1, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, + }), + /// OTG_HS USB configuration register + OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved15: u1, + /// PHY Low-power clock select + PHYLPCS: u1, + reserved17: u1, + /// ULPI FS/LS select + ULPIFSLS: u1, + /// ULPI Auto-resume + ULPIAR: u1, + /// ULPI Clock SuspendM + ULPICSM: u1, + /// ULPI External VBUS Drive + ULPIEVBUSD: u1, + /// ULPI external VBUS indicator + ULPIEVBUSI: u1, + /// TermSel DLine pulsing selection + TSDPS: u1, + /// Indicator complement + PCCI: u1, + /// Indicator pass through + PTCI: u1, + /// ULPI interface protect disable + ULPIIPD: u1, + reserved29: u3, + /// Forced host mode + FHMOD: u1, + /// Forced peripheral mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), + /// OTG_HS reset register + OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved30: u19, + /// DMA request signal + DMAREQ: u1, + /// AHB master idle + AHBIDL: u1, + }), + /// OTG_HS core interrupt register + OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO nonempty + RXFLVL: u1, + /// Nonperiodic TxFIFO empty + NPTXFE: u1, + /// Global IN nonperiodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + BOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer + PXFR_INCOMPISOOUT: u1, + /// Data fetch suspended + DATAFSUSP: u1, + reserved24: u1, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUINT: u1, + }), + /// OTG_HS interrupt mask register + OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO nonempty mask + RXFLVLM: u1, + /// Nonperiodic TxFIFO empty mask + NPTXFEM: u1, + /// Global nonperiodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask + PXFRM_IISOOXFRM: u1, + /// Data fetch suspended mask + FSUSPM: u1, + reserved24: u1, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved28: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, + }), + /// OTG_HS Receive status debug read register (host mode) + OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding: u11, + }), + /// OTG_HS status read and pop register (host mode) + OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) { + /// Channel number + CHNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + padding: u11, + }), + /// OTG_HS Receive FIFO size register + OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, + }), + /// OTG_HS nonperiodic transmit FIFO size register (host mode) + OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) { + /// Nonperiodic transmit RAM start address + NPTXFSA: u16, + /// Nonperiodic TxFIFO depth + NPTXFD: u16, + }), + /// OTG_HS nonperiodic transmit FIFO/queue status register + OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Nonperiodic TxFIFO space available + NPTXFSAV: u16, + /// Nonperiodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the nonperiodic transmit request queue + NPTXQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// OTG_HS general core configuration register + OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + /// Enable I2C bus connection for the external I2C PHY interface + I2CPADEN: u1, + /// Enable the VBUS sensing device + VBUSASEN: u1, + /// Enable the VBUS sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + /// VBUS sensing disable option + NOVBUSSENS: u1, + padding: u10, + }), + /// OTG_HS core ID register + OTG_HS_CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, + }), + reserved256: [192]u8, + /// OTG_HS Host periodic transmit FIFO size register + OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + reserved284: [16]u8, + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_HS device IN endpoint transmit FIFO size register + OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFOx transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + }; + + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Interrupt mask register (EXTI_IMR) + IMR: mmio.Mmio(packed struct(u32) { + /// Interrupt Mask on line 0 + MR0: u1, + /// Interrupt Mask on line 1 + MR1: u1, + /// Interrupt Mask on line 2 + MR2: u1, + /// Interrupt Mask on line 3 + MR3: u1, + /// Interrupt Mask on line 4 + MR4: u1, + /// Interrupt Mask on line 5 + MR5: u1, + /// Interrupt Mask on line 6 + MR6: u1, + /// Interrupt Mask on line 7 + MR7: u1, + /// Interrupt Mask on line 8 + MR8: u1, + /// Interrupt Mask on line 9 + MR9: u1, + /// Interrupt Mask on line 10 + MR10: u1, + /// Interrupt Mask on line 11 + MR11: u1, + /// Interrupt Mask on line 12 + MR12: u1, + /// Interrupt Mask on line 13 + MR13: u1, + /// Interrupt Mask on line 14 + MR14: u1, + /// Interrupt Mask on line 15 + MR15: u1, + /// Interrupt Mask on line 16 + MR16: u1, + /// Interrupt Mask on line 17 + MR17: u1, + /// Interrupt Mask on line 18 + MR18: u1, + /// Interrupt Mask on line 19 + MR19: u1, + /// Interrupt Mask on line 20 + MR20: u1, + /// Interrupt Mask on line 21 + MR21: u1, + /// Interrupt Mask on line 22 + MR22: u1, + padding: u9, + }), + /// Event mask register (EXTI_EMR) + EMR: mmio.Mmio(packed struct(u32) { + /// Event Mask on line 0 + MR0: u1, + /// Event Mask on line 1 + MR1: u1, + /// Event Mask on line 2 + MR2: u1, + /// Event Mask on line 3 + MR3: u1, + /// Event Mask on line 4 + MR4: u1, + /// Event Mask on line 5 + MR5: u1, + /// Event Mask on line 6 + MR6: u1, + /// Event Mask on line 7 + MR7: u1, + /// Event Mask on line 8 + MR8: u1, + /// Event Mask on line 9 + MR9: u1, + /// Event Mask on line 10 + MR10: u1, + /// Event Mask on line 11 + MR11: u1, + /// Event Mask on line 12 + MR12: u1, + /// Event Mask on line 13 + MR13: u1, + /// Event Mask on line 14 + MR14: u1, + /// Event Mask on line 15 + MR15: u1, + /// Event Mask on line 16 + MR16: u1, + /// Event Mask on line 17 + MR17: u1, + /// Event Mask on line 18 + MR18: u1, + /// Event Mask on line 19 + MR19: u1, + /// Event Mask on line 20 + MR20: u1, + /// Event Mask on line 21 + MR21: u1, + /// Event Mask on line 22 + MR22: u1, + padding: u9, + }), + /// Rising Trigger selection register (EXTI_RTSR) + RTSR: mmio.Mmio(packed struct(u32) { + /// Rising trigger event configuration of line 0 + TR0: u1, + /// Rising trigger event configuration of line 1 + TR1: u1, + /// Rising trigger event configuration of line 2 + TR2: u1, + /// Rising trigger event configuration of line 3 + TR3: u1, + /// Rising trigger event configuration of line 4 + TR4: u1, + /// Rising trigger event configuration of line 5 + TR5: u1, + /// Rising trigger event configuration of line 6 + TR6: u1, + /// Rising trigger event configuration of line 7 + TR7: u1, + /// Rising trigger event configuration of line 8 + TR8: u1, + /// Rising trigger event configuration of line 9 + TR9: u1, + /// Rising trigger event configuration of line 10 + TR10: u1, + /// Rising trigger event configuration of line 11 + TR11: u1, + /// Rising trigger event configuration of line 12 + TR12: u1, + /// Rising trigger event configuration of line 13 + TR13: u1, + /// Rising trigger event configuration of line 14 + TR14: u1, + /// Rising trigger event configuration of line 15 + TR15: u1, + /// Rising trigger event configuration of line 16 + TR16: u1, + /// Rising trigger event configuration of line 17 + TR17: u1, + /// Rising trigger event configuration of line 18 + TR18: u1, + /// Rising trigger event configuration of line 19 + TR19: u1, + /// Rising trigger event configuration of line 20 + TR20: u1, + /// Rising trigger event configuration of line 21 + TR21: u1, + /// Rising trigger event configuration of line 22 + TR22: u1, + padding: u9, + }), + /// Falling Trigger selection register (EXTI_FTSR) + FTSR: mmio.Mmio(packed struct(u32) { + /// Falling trigger event configuration of line 0 + TR0: u1, + /// Falling trigger event configuration of line 1 + TR1: u1, + /// Falling trigger event configuration of line 2 + TR2: u1, + /// Falling trigger event configuration of line 3 + TR3: u1, + /// Falling trigger event configuration of line 4 + TR4: u1, + /// Falling trigger event configuration of line 5 + TR5: u1, + /// Falling trigger event configuration of line 6 + TR6: u1, + /// Falling trigger event configuration of line 7 + TR7: u1, + /// Falling trigger event configuration of line 8 + TR8: u1, + /// Falling trigger event configuration of line 9 + TR9: u1, + /// Falling trigger event configuration of line 10 + TR10: u1, + /// Falling trigger event configuration of line 11 + TR11: u1, + /// Falling trigger event configuration of line 12 + TR12: u1, + /// Falling trigger event configuration of line 13 + TR13: u1, + /// Falling trigger event configuration of line 14 + TR14: u1, + /// Falling trigger event configuration of line 15 + TR15: u1, + /// Falling trigger event configuration of line 16 + TR16: u1, + /// Falling trigger event configuration of line 17 + TR17: u1, + /// Falling trigger event configuration of line 18 + TR18: u1, + /// Falling trigger event configuration of line 19 + TR19: u1, + /// Falling trigger event configuration of line 20 + TR20: u1, + /// Falling trigger event configuration of line 21 + TR21: u1, + /// Falling trigger event configuration of line 22 + TR22: u1, + padding: u9, + }), + /// Software interrupt event register (EXTI_SWIER) + SWIER: mmio.Mmio(packed struct(u32) { + /// Software Interrupt on line 0 + SWIER0: u1, + /// Software Interrupt on line 1 + SWIER1: u1, + /// Software Interrupt on line 2 + SWIER2: u1, + /// Software Interrupt on line 3 + SWIER3: u1, + /// Software Interrupt on line 4 + SWIER4: u1, + /// Software Interrupt on line 5 + SWIER5: u1, + /// Software Interrupt on line 6 + SWIER6: u1, + /// Software Interrupt on line 7 + SWIER7: u1, + /// Software Interrupt on line 8 + SWIER8: u1, + /// Software Interrupt on line 9 + SWIER9: u1, + /// Software Interrupt on line 10 + SWIER10: u1, + /// Software Interrupt on line 11 + SWIER11: u1, + /// Software Interrupt on line 12 + SWIER12: u1, + /// Software Interrupt on line 13 + SWIER13: u1, + /// Software Interrupt on line 14 + SWIER14: u1, + /// Software Interrupt on line 15 + SWIER15: u1, + /// Software Interrupt on line 16 + SWIER16: u1, + /// Software Interrupt on line 17 + SWIER17: u1, + /// Software Interrupt on line 18 + SWIER18: u1, + /// Software Interrupt on line 19 + SWIER19: u1, + /// Software Interrupt on line 20 + SWIER20: u1, + /// Software Interrupt on line 21 + SWIER21: u1, + /// Software Interrupt on line 22 + SWIER22: u1, + padding: u9, + }), + /// Pending register (EXTI_PR) + PR: mmio.Mmio(packed struct(u32) { + /// Pending bit 0 + PR0: u1, + /// Pending bit 1 + PR1: u1, + /// Pending bit 2 + PR2: u1, + /// Pending bit 3 + PR3: u1, + /// Pending bit 4 + PR4: u1, + /// Pending bit 5 + PR5: u1, + /// Pending bit 6 + PR6: u1, + /// Pending bit 7 + PR7: u1, + /// Pending bit 8 + PR8: u1, + /// Pending bit 9 + PR9: u1, + /// Pending bit 10 + PR10: u1, + /// Pending bit 11 + PR11: u1, + /// Pending bit 12 + PR12: u1, + /// Pending bit 13 + PR13: u1, + /// Pending bit 14 + PR14: u1, + /// Pending bit 15 + PR15: u1, + /// Pending bit 16 + PR16: u1, + /// Pending bit 17 + PR17: u1, + /// Pending bit 18 + PR18: u1, + /// Pending bit 19 + PR19: u1, + /// Pending bit 20 + PR20: u1, + /// Pending bit 21 + PR21: u1, + /// Pending bit 22 + PR22: u1, + padding: u9, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART6 = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + /// CTS flag + CTS: u1, + padding: u22, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// Last bit clock pulse + LBCL: u1, + /// Clock phase + CPHA: u1, + /// Clock polarity + CPOL: u1, + /// Clock enable + CLKEN: u1, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + /// Smartcard NACK enable + NACK: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + /// RTS enable + RTSE: u1, + /// CTS enable + CTSE: u1, + /// CTS interrupt enable + CTSIE: u1, + /// One sample bit method enable + ONEBIT: u1, + padding: u20, + }), + /// Guard time and prescaler register + GTPR: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value + GT: u8, + padding: u16, + }), + }; + + /// FLASH + pub const FLASH = extern struct { + /// Flash access control register + ACR: mmio.Mmio(packed struct(u32) { + /// Latency + LATENCY: u3, + reserved8: u5, + /// Prefetch enable + PRFTEN: u1, + /// Instruction cache enable + ICEN: u1, + /// Data cache enable + DCEN: u1, + /// Instruction cache reset + ICRST: u1, + /// Data cache reset + DCRST: u1, + padding: u19, + }), + /// Flash key register + KEYR: mmio.Mmio(packed struct(u32) { + /// FPEC key + KEY: u32, + }), + /// Flash option key register + OPTKEYR: mmio.Mmio(packed struct(u32) { + /// Option byte key + OPTKEY: u32, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// End of operation + EOP: u1, + /// Operation error + OPERR: u1, + reserved4: u2, + /// Write protection error + WRPERR: u1, + /// Programming alignment error + PGAERR: u1, + /// Programming parallelism error + PGPERR: u1, + /// Programming sequence error + PGSERR: u1, + reserved16: u8, + /// Busy + BSY: u1, + padding: u15, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Programming + PG: u1, + /// Sector Erase + SER: u1, + /// Mass Erase of sectors 0 to 11 + MER: u1, + /// Sector number + SNB: u5, + /// Program size + PSIZE: u2, + reserved15: u5, + /// Mass Erase of sectors 12 to 23 + MER1: u1, + /// Start + STRT: u1, + reserved24: u7, + /// End of operation interrupt enable + EOPIE: u1, + /// Error interrupt enable + ERRIE: u1, + reserved31: u5, + /// Lock + LOCK: u1, + }), + /// Flash option control register + OPTCR: mmio.Mmio(packed struct(u32) { + /// Option lock + OPTLOCK: u1, + /// Option start + OPTSTRT: u1, + /// BOR reset Level + BOR_LEV: u2, + reserved5: u1, + /// WDG_SW User option bytes + WDG_SW: u1, + /// nRST_STOP User option bytes + nRST_STOP: u1, + /// nRST_STDBY User option bytes + nRST_STDBY: u1, + /// Read protect + RDP: u8, + /// Not write protect + nWRP: u12, + padding: u4, + }), + /// Flash option control register 1 + OPTCR1: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Not write protect + nWRP: u12, + padding: u4, + }), + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = extern struct { + /// Interrupt Set-Enable Register + ISER0: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER1: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + /// Interrupt Set-Enable Register + ISER2: mmio.Mmio(packed struct(u32) { + /// SETENA + SETENA: u32, + }), + reserved128: [116]u8, + /// Interrupt Clear-Enable Register + ICER0: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER1: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + /// Interrupt Clear-Enable Register + ICER2: mmio.Mmio(packed struct(u32) { + /// CLRENA + CLRENA: u32, + }), + reserved256: [116]u8, + /// Interrupt Set-Pending Register + ISPR0: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR1: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + /// Interrupt Set-Pending Register + ISPR2: mmio.Mmio(packed struct(u32) { + /// SETPEND + SETPEND: u32, + }), + reserved384: [116]u8, + /// Interrupt Clear-Pending Register + ICPR0: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR1: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + /// Interrupt Clear-Pending Register + ICPR2: mmio.Mmio(packed struct(u32) { + /// CLRPEND + CLRPEND: u32, + }), + reserved512: [116]u8, + /// Interrupt Active Bit Register + IABR0: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR1: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + /// Interrupt Active Bit Register + IABR2: mmio.Mmio(packed struct(u32) { + /// ACTIVE + ACTIVE: u32, + }), + reserved768: [244]u8, + /// Interrupt Priority Register + IPR0: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR1: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR2: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR3: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR4: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR5: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR6: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR7: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR8: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR9: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR10: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR11: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR12: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR13: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR14: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR15: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR16: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR17: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR18: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR19: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + /// Interrupt Priority Register + IPR20: mmio.Mmio(packed struct(u32) { + /// IPR_N0 + IPR_N0: u8, + /// IPR_N1 + IPR_N1: u8, + /// IPR_N2 + IPR_N2: u8, + /// IPR_N3 + IPR_N3: u8, + }), + }; + + /// Ethernet: media access control (MAC) + pub const Ethernet_MAC = extern struct { + /// Ethernet MAC configuration register + MACCR: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// RE + RE: u1, + /// TE + TE: u1, + /// DC + DC: u1, + /// BL + BL: u2, + /// APCS + APCS: u1, + reserved9: u1, + /// RD + RD: u1, + /// IPCO + IPCO: u1, + /// DM + DM: u1, + /// LM + LM: u1, + /// ROD + ROD: u1, + /// FES + FES: u1, + reserved16: u1, + /// CSD + CSD: u1, + /// IFG + IFG: u3, + reserved22: u2, + /// JD + JD: u1, + /// WD + WD: u1, + reserved25: u1, + /// CSTF + CSTF: u1, + padding: u6, + }), + /// Ethernet MAC frame filter register + MACFFR: mmio.Mmio(packed struct(u32) { + /// PM + PM: u1, + /// HU + HU: u1, + /// HM + HM: u1, + /// DAIF + DAIF: u1, + /// RAM + RAM: u1, + /// BFD + BFD: u1, + /// PCF + PCF: u1, + /// SAIF + SAIF: u1, + /// SAF + SAF: u1, + /// HPF + HPF: u1, + reserved31: u21, + /// RA + RA: u1, + }), + /// Ethernet MAC hash table high register + MACHTHR: mmio.Mmio(packed struct(u32) { + /// HTH + HTH: u32, + }), + /// Ethernet MAC hash table low register + MACHTLR: mmio.Mmio(packed struct(u32) { + /// HTL + HTL: u32, + }), + /// Ethernet MAC MII address register + MACMIIAR: mmio.Mmio(packed struct(u32) { + /// MB + MB: u1, + /// MW + MW: u1, + /// CR + CR: u3, + reserved6: u1, + /// MR + MR: u5, + /// PA + PA: u5, + padding: u16, + }), + /// Ethernet MAC MII data register + MACMIIDR: mmio.Mmio(packed struct(u32) { + /// TD + TD: u16, + padding: u16, + }), + /// Ethernet MAC flow control register + MACFCR: mmio.Mmio(packed struct(u32) { + /// FCB + FCB: u1, + /// TFCE + TFCE: u1, + /// RFCE + RFCE: u1, + /// UPFD + UPFD: u1, + /// PLT + PLT: u2, + reserved7: u1, + /// ZQPD + ZQPD: u1, + reserved16: u8, + /// PT + PT: u16, + }), + /// Ethernet MAC VLAN tag register + MACVLANTR: mmio.Mmio(packed struct(u32) { + /// VLANTI + VLANTI: u16, + /// VLANTC + VLANTC: u1, + padding: u15, + }), + reserved44: [12]u8, + /// Ethernet MAC PMT control and status register + MACPMTCSR: mmio.Mmio(packed struct(u32) { + /// PD + PD: u1, + /// MPE + MPE: u1, + /// WFE + WFE: u1, + reserved5: u2, + /// MPR + MPR: u1, + /// WFR + WFR: u1, + reserved9: u2, + /// GU + GU: u1, + reserved31: u21, + /// WFFRPR + WFFRPR: u1, + }), + reserved52: [4]u8, + /// Ethernet MAC debug register + MACDBGR: mmio.Mmio(packed struct(u32) { + /// CR + CR: u1, + /// CSR + CSR: u1, + /// ROR + ROR: u1, + /// MCF + MCF: u1, + /// MCP + MCP: u1, + /// MCFHP + MCFHP: u1, + padding: u26, + }), + /// Ethernet MAC interrupt status register + MACSR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMTS + PMTS: u1, + /// MMCS + MMCS: u1, + /// MMCRS + MMCRS: u1, + /// MMCTS + MMCTS: u1, + reserved9: u2, + /// TSTS + TSTS: u1, + padding: u22, + }), + /// Ethernet MAC interrupt mask register + MACIMR: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// PMTIM + PMTIM: u1, + reserved9: u5, + /// TSTIM + TSTIM: u1, + padding: u22, + }), + /// Ethernet MAC address 0 high register + MACA0HR: mmio.Mmio(packed struct(u32) { + /// MAC address0 high + MACA0H: u16, + reserved31: u15, + /// Always 1 + MO: u1, + }), + /// Ethernet MAC address 0 low register + MACA0LR: mmio.Mmio(packed struct(u32) { + /// 0 + MACA0L: u32, + }), + /// Ethernet MAC address 1 high register + MACA1HR: mmio.Mmio(packed struct(u32) { + /// MACA1H + MACA1H: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address1 low register + MACA1LR: mmio.Mmio(packed struct(u32) { + /// MACA1LR + MACA1LR: u32, + }), + /// Ethernet MAC address 2 high register + MACA2HR: mmio.Mmio(packed struct(u32) { + /// MAC2AH + MAC2AH: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address 2 low register + MACA2LR: mmio.Mmio(packed struct(u32) { + /// MACA2L + MACA2L: u31, + padding: u1, + }), + /// Ethernet MAC address 3 high register + MACA3HR: mmio.Mmio(packed struct(u32) { + /// MACA3H + MACA3H: u16, + reserved24: u8, + /// MBC + MBC: u6, + /// SA + SA: u1, + /// AE + AE: u1, + }), + /// Ethernet MAC address 3 low register + MACA3LR: mmio.Mmio(packed struct(u32) { + /// MBCA3L + MBCA3L: u32, + }), + }; + + /// Controller area network + pub const CAN1 = extern struct { + /// master control register + MCR: mmio.Mmio(packed struct(u32) { + /// INRQ + INRQ: u1, + /// SLEEP + SLEEP: u1, + /// TXFP + TXFP: u1, + /// RFLM + RFLM: u1, + /// NART + NART: u1, + /// AWUM + AWUM: u1, + /// ABOM + ABOM: u1, + /// TTCM + TTCM: u1, + reserved15: u7, + /// RESET + RESET: u1, + /// DBF + DBF: u1, + padding: u15, + }), + /// master status register + MSR: mmio.Mmio(packed struct(u32) { + /// INAK + INAK: u1, + /// SLAK + SLAK: u1, + /// ERRI + ERRI: u1, + /// WKUI + WKUI: u1, + /// SLAKI + SLAKI: u1, + reserved8: u3, + /// TXM + TXM: u1, + /// RXM + RXM: u1, + /// SAMP + SAMP: u1, + /// RX + RX: u1, + padding: u20, + }), + /// transmit status register + TSR: mmio.Mmio(packed struct(u32) { + /// RQCP0 + RQCP0: u1, + /// TXOK0 + TXOK0: u1, + /// ALST0 + ALST0: u1, + /// TERR0 + TERR0: u1, + reserved7: u3, + /// ABRQ0 + ABRQ0: u1, + /// RQCP1 + RQCP1: u1, + /// TXOK1 + TXOK1: u1, + /// ALST1 + ALST1: u1, + /// TERR1 + TERR1: u1, + reserved15: u3, + /// ABRQ1 + ABRQ1: u1, + /// RQCP2 + RQCP2: u1, + /// TXOK2 + TXOK2: u1, + /// ALST2 + ALST2: u1, + /// TERR2 + TERR2: u1, + reserved23: u3, + /// ABRQ2 + ABRQ2: u1, + /// CODE + CODE: u2, + /// Lowest priority flag for mailbox 0 + TME0: u1, + /// Lowest priority flag for mailbox 1 + TME1: u1, + /// Lowest priority flag for mailbox 2 + TME2: u1, + /// Lowest priority flag for mailbox 0 + LOW0: u1, + /// Lowest priority flag for mailbox 1 + LOW1: u1, + /// Lowest priority flag for mailbox 2 + LOW2: u1, + }), + /// receive FIFO 0 register + RF0R: mmio.Mmio(packed struct(u32) { + /// FMP0 + FMP0: u2, + reserved3: u1, + /// FULL0 + FULL0: u1, + /// FOVR0 + FOVR0: u1, + /// RFOM0 + RFOM0: u1, + padding: u26, + }), + /// receive FIFO 1 register + RF1R: mmio.Mmio(packed struct(u32) { + /// FMP1 + FMP1: u2, + reserved3: u1, + /// FULL1 + FULL1: u1, + /// FOVR1 + FOVR1: u1, + /// RFOM1 + RFOM1: u1, + padding: u26, + }), + /// interrupt enable register + IER: mmio.Mmio(packed struct(u32) { + /// TMEIE + TMEIE: u1, + /// FMPIE0 + FMPIE0: u1, + /// FFIE0 + FFIE0: u1, + /// FOVIE0 + FOVIE0: u1, + /// FMPIE1 + FMPIE1: u1, + /// FFIE1 + FFIE1: u1, + /// FOVIE1 + FOVIE1: u1, + reserved8: u1, + /// EWGIE + EWGIE: u1, + /// EPVIE + EPVIE: u1, + /// BOFIE + BOFIE: u1, + /// LECIE + LECIE: u1, + reserved15: u3, + /// ERRIE + ERRIE: u1, + /// WKUIE + WKUIE: u1, + /// SLKIE + SLKIE: u1, + padding: u14, + }), + /// interrupt enable register + ESR: mmio.Mmio(packed struct(u32) { + /// EWGF + EWGF: u1, + /// EPVF + EPVF: u1, + /// BOFF + BOFF: u1, + reserved4: u1, + /// LEC + LEC: u3, + reserved16: u9, + /// TEC + TEC: u8, + /// REC + REC: u8, + }), + /// bit timing register + BTR: mmio.Mmio(packed struct(u32) { + /// BRP + BRP: u10, + reserved16: u6, + /// TS1 + TS1: u4, + /// TS2 + TS2: u3, + reserved24: u1, + /// SJW + SJW: u2, + reserved30: u4, + /// LBKM + LBKM: u1, + /// SILM + SILM: u1, + }), + reserved384: [352]u8, + /// TX mailbox identifier register + TI0R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox identifier register + TI1R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox identifier register + TI2R: mmio.Mmio(packed struct(u32) { + /// TXRQ + TXRQ: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data length control and time stamp register + TDT2R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// TGT + TGT: u1, + reserved16: u7, + /// TIME + TIME: u16, + }), + /// mailbox data low register + TDL2R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + TDH2R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// receive FIFO mailbox identifier register + RI0R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data high register + RDT0R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// mailbox data high register + RDL0R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// receive FIFO mailbox data high register + RDH0R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + /// mailbox data high register + RI1R: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// RTR + RTR: u1, + /// IDE + IDE: u1, + /// EXID + EXID: u18, + /// STID + STID: u11, + }), + /// mailbox data high register + RDT1R: mmio.Mmio(packed struct(u32) { + /// DLC + DLC: u4, + reserved8: u4, + /// FMI + FMI: u8, + /// TIME + TIME: u16, + }), + /// mailbox data high register + RDL1R: mmio.Mmio(packed struct(u32) { + /// DATA0 + DATA0: u8, + /// DATA1 + DATA1: u8, + /// DATA2 + DATA2: u8, + /// DATA3 + DATA3: u8, + }), + /// mailbox data high register + RDH1R: mmio.Mmio(packed struct(u32) { + /// DATA4 + DATA4: u8, + /// DATA5 + DATA5: u8, + /// DATA6 + DATA6: u8, + /// DATA7 + DATA7: u8, + }), + reserved512: [48]u8, + /// filter master register + FMR: mmio.Mmio(packed struct(u32) { + /// FINIT + FINIT: u1, + reserved8: u7, + /// CAN2SB + CAN2SB: u6, + padding: u18, + }), + /// filter mode register + FM1R: mmio.Mmio(packed struct(u32) { + /// Filter mode + FBM0: u1, + /// Filter mode + FBM1: u1, + /// Filter mode + FBM2: u1, + /// Filter mode + FBM3: u1, + /// Filter mode + FBM4: u1, + /// Filter mode + FBM5: u1, + /// Filter mode + FBM6: u1, + /// Filter mode + FBM7: u1, + /// Filter mode + FBM8: u1, + /// Filter mode + FBM9: u1, + /// Filter mode + FBM10: u1, + /// Filter mode + FBM11: u1, + /// Filter mode + FBM12: u1, + /// Filter mode + FBM13: u1, + /// Filter mode + FBM14: u1, + /// Filter mode + FBM15: u1, + /// Filter mode + FBM16: u1, + /// Filter mode + FBM17: u1, + /// Filter mode + FBM18: u1, + /// Filter mode + FBM19: u1, + /// Filter mode + FBM20: u1, + /// Filter mode + FBM21: u1, + /// Filter mode + FBM22: u1, + /// Filter mode + FBM23: u1, + /// Filter mode + FBM24: u1, + /// Filter mode + FBM25: u1, + /// Filter mode + FBM26: u1, + /// Filter mode + FBM27: u1, + padding: u4, + }), + reserved524: [4]u8, + /// filter scale register + FS1R: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FSC0: u1, + /// Filter scale configuration + FSC1: u1, + /// Filter scale configuration + FSC2: u1, + /// Filter scale configuration + FSC3: u1, + /// Filter scale configuration + FSC4: u1, + /// Filter scale configuration + FSC5: u1, + /// Filter scale configuration + FSC6: u1, + /// Filter scale configuration + FSC7: u1, + /// Filter scale configuration + FSC8: u1, + /// Filter scale configuration + FSC9: u1, + /// Filter scale configuration + FSC10: u1, + /// Filter scale configuration + FSC11: u1, + /// Filter scale configuration + FSC12: u1, + /// Filter scale configuration + FSC13: u1, + /// Filter scale configuration + FSC14: u1, + /// Filter scale configuration + FSC15: u1, + /// Filter scale configuration + FSC16: u1, + /// Filter scale configuration + FSC17: u1, + /// Filter scale configuration + FSC18: u1, + /// Filter scale configuration + FSC19: u1, + /// Filter scale configuration + FSC20: u1, + /// Filter scale configuration + FSC21: u1, + /// Filter scale configuration + FSC22: u1, + /// Filter scale configuration + FSC23: u1, + /// Filter scale configuration + FSC24: u1, + /// Filter scale configuration + FSC25: u1, + /// Filter scale configuration + FSC26: u1, + /// Filter scale configuration + FSC27: u1, + padding: u4, + }), + reserved532: [4]u8, + /// filter FIFO assignment register + FFA1R: mmio.Mmio(packed struct(u32) { + /// Filter FIFO assignment for filter 0 + FFA0: u1, + /// Filter FIFO assignment for filter 1 + FFA1: u1, + /// Filter FIFO assignment for filter 2 + FFA2: u1, + /// Filter FIFO assignment for filter 3 + FFA3: u1, + /// Filter FIFO assignment for filter 4 + FFA4: u1, + /// Filter FIFO assignment for filter 5 + FFA5: u1, + /// Filter FIFO assignment for filter 6 + FFA6: u1, + /// Filter FIFO assignment for filter 7 + FFA7: u1, + /// Filter FIFO assignment for filter 8 + FFA8: u1, + /// Filter FIFO assignment for filter 9 + FFA9: u1, + /// Filter FIFO assignment for filter 10 + FFA10: u1, + /// Filter FIFO assignment for filter 11 + FFA11: u1, + /// Filter FIFO assignment for filter 12 + FFA12: u1, + /// Filter FIFO assignment for filter 13 + FFA13: u1, + /// Filter FIFO assignment for filter 14 + FFA14: u1, + /// Filter FIFO assignment for filter 15 + FFA15: u1, + /// Filter FIFO assignment for filter 16 + FFA16: u1, + /// Filter FIFO assignment for filter 17 + FFA17: u1, + /// Filter FIFO assignment for filter 18 + FFA18: u1, + /// Filter FIFO assignment for filter 19 + FFA19: u1, + /// Filter FIFO assignment for filter 20 + FFA20: u1, + /// Filter FIFO assignment for filter 21 + FFA21: u1, + /// Filter FIFO assignment for filter 22 + FFA22: u1, + /// Filter FIFO assignment for filter 23 + FFA23: u1, + /// Filter FIFO assignment for filter 24 + FFA24: u1, + /// Filter FIFO assignment for filter 25 + FFA25: u1, + /// Filter FIFO assignment for filter 26 + FFA26: u1, + /// Filter FIFO assignment for filter 27 + FFA27: u1, + padding: u4, + }), + reserved540: [4]u8, + /// filter activation register + FA1R: mmio.Mmio(packed struct(u32) { + /// Filter active + FACT0: u1, + /// Filter active + FACT1: u1, + /// Filter active + FACT2: u1, + /// Filter active + FACT3: u1, + /// Filter active + FACT4: u1, + /// Filter active + FACT5: u1, + /// Filter active + FACT6: u1, + /// Filter active + FACT7: u1, + /// Filter active + FACT8: u1, + /// Filter active + FACT9: u1, + /// Filter active + FACT10: u1, + /// Filter active + FACT11: u1, + /// Filter active + FACT12: u1, + /// Filter active + FACT13: u1, + /// Filter active + FACT14: u1, + /// Filter active + FACT15: u1, + /// Filter active + FACT16: u1, + /// Filter active + FACT17: u1, + /// Filter active + FACT18: u1, + /// Filter active + FACT19: u1, + /// Filter active + FACT20: u1, + /// Filter active + FACT21: u1, + /// Filter active + FACT22: u1, + /// Filter active + FACT23: u1, + /// Filter active + FACT24: u1, + /// Filter active + FACT25: u1, + /// Filter active + FACT26: u1, + /// Filter active + FACT27: u1, + padding: u4, + }), + reserved576: [32]u8, + /// Filter bank 0 register 1 + F0R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 0 register 2 + F0R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 1 + F1R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 1 register 2 + F1R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 1 + F2R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 2 register 2 + F2R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 1 + F3R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 3 register 2 + F3R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F4R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 2 + F4R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 1 + F5R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 5 register 2 + F5R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 1 + F6R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 6 register 2 + F6R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 1 + F7R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 7 register 2 + F7R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 1 + F8R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 8 register 2 + F8R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 1 + F9R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 9 register 2 + F9R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 1 + F10R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 10 register 2 + F10R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 1 + F11R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 11 register 2 + F11R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 4 register 1 + F12R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 12 register 2 + F12R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 1 + F13R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 13 register 2 + F13R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 1 + F14R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 14 register 2 + F14R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 1 + F15R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 15 register 2 + F15R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 1 + F16R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 16 register 2 + F16R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 1 + F17R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 17 register 2 + F17R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 1 + F18R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 18 register 2 + F18R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 1 + F19R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 19 register 2 + F19R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 1 + F20R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 20 register 2 + F20R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 1 + F21R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 21 register 2 + F21R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 1 + F22R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 22 register 2 + F22R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 1 + F23R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 23 register 2 + F23R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 1 + F24R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 24 register 2 + F24R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 1 + F25R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 25 register 2 + F25R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 1 + F26R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 26 register 2 + F26R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 1 + F27R1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + /// Filter bank 27 register 2 + F27R2: mmio.Mmio(packed struct(u32) { + /// Filter bits + FB0: u1, + /// Filter bits + FB1: u1, + /// Filter bits + FB2: u1, + /// Filter bits + FB3: u1, + /// Filter bits + FB4: u1, + /// Filter bits + FB5: u1, + /// Filter bits + FB6: u1, + /// Filter bits + FB7: u1, + /// Filter bits + FB8: u1, + /// Filter bits + FB9: u1, + /// Filter bits + FB10: u1, + /// Filter bits + FB11: u1, + /// Filter bits + FB12: u1, + /// Filter bits + FB13: u1, + /// Filter bits + FB14: u1, + /// Filter bits + FB15: u1, + /// Filter bits + FB16: u1, + /// Filter bits + FB17: u1, + /// Filter bits + FB18: u1, + /// Filter bits + FB19: u1, + /// Filter bits + FB20: u1, + /// Filter bits + FB21: u1, + /// Filter bits + FB22: u1, + /// Filter bits + FB23: u1, + /// Filter bits + FB24: u1, + /// Filter bits + FB25: u1, + /// Filter bits + FB26: u1, + /// Filter bits + FB27: u1, + /// Filter bits + FB28: u1, + /// Filter bits + FB29: u1, + /// Filter bits + FB30: u1, + /// Filter bits + FB31: u1, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_PWRCLK = extern struct { + /// OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) + FS_PCGCCTL: mmio.Mmio(packed struct(u32) { + /// Stop PHY clock + STPPCLK: u1, + /// Gate HCLK + GATEHCLK: u1, + reserved4: u2, + /// PHY Suspended + PHYSUSP: u1, + padding: u27, + }), + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 enable + EN1: u1, + /// DAC channel1 output buffer disable + BOFF1: u1, + /// DAC channel1 trigger enable + TEN1: u1, + /// DAC channel1 trigger selection + TSEL1: u3, + /// DAC channel1 noise/triangle wave generation enable + WAVE1: u2, + /// DAC channel1 mask/amplitude selector + MAMP1: u4, + /// DAC channel1 DMA enable + DMAEN1: u1, + /// DAC channel1 DMA Underrun Interrupt enable + DMAUDRIE1: u1, + reserved16: u2, + /// DAC channel2 enable + EN2: u1, + /// DAC channel2 output buffer disable + BOFF2: u1, + /// DAC channel2 trigger enable + TEN2: u1, + /// DAC channel2 trigger selection + TSEL2: u3, + /// DAC channel2 noise/triangle wave generation enable + WAVE2: u2, + /// DAC channel2 mask/amplitude selector + MAMP2: u4, + /// DAC channel2 DMA enable + DMAEN2: u1, + /// DAC channel2 DMA underrun interrupt enable + DMAUDRIE2: u1, + padding: u2, + }), + /// software trigger register + SWTRIGR: mmio.Mmio(packed struct(u32) { + /// DAC channel1 software trigger + SWTRIG1: u1, + /// DAC channel2 software trigger + SWTRIG2: u1, + padding: u30, + }), + /// channel1 12-bit right-aligned data holding register + DHR12R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + padding: u20, + }), + /// channel1 12-bit left aligned data holding register + DHR12L1: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + padding: u16, + }), + /// channel1 8-bit right aligned data holding register + DHR8R1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + padding: u24, + }), + /// channel2 12-bit right aligned data holding register + DHR12R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u20, + }), + /// channel2 12-bit left aligned data holding register + DHR12L2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + padding: u16, + }), + /// channel2 8-bit right-aligned data holding register + DHR8R2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u24, + }), + /// Dual DAC 12-bit right-aligned data holding register + DHR12RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 12-bit right-aligned data + DACC1DHR: u12, + reserved16: u4, + /// DAC channel2 12-bit right-aligned data + DACC2DHR: u12, + padding: u4, + }), + /// DUAL DAC 12-bit left aligned data holding register + DHR12LD: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC channel1 12-bit left-aligned data + DACC1DHR: u12, + reserved20: u4, + /// DAC channel2 12-bit left-aligned data + DACC2DHR: u12, + }), + /// DUAL DAC 8-bit right aligned data holding register + DHR8RD: mmio.Mmio(packed struct(u32) { + /// DAC channel1 8-bit right-aligned data + DACC1DHR: u8, + /// DAC channel2 8-bit right-aligned data + DACC2DHR: u8, + padding: u16, + }), + /// channel1 data output register + DOR1: mmio.Mmio(packed struct(u32) { + /// DAC channel1 data output + DACC1DOR: u12, + padding: u20, + }), + /// channel2 data output register + DOR2: mmio.Mmio(packed struct(u32) { + /// DAC channel2 data output + DACC2DOR: u12, + padding: u20, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + reserved13: u13, + /// DAC channel1 DMA underrun flag + DMAUDR1: u1, + reserved29: u15, + /// DAC channel2 DMA underrun flag + DMAUDR2: u1, + padding: u2, + }), + }; + + /// Power control + pub const PWR = extern struct { + /// power control register + CR: mmio.Mmio(packed struct(u32) { + /// Low-power deep sleep + LPDS: u1, + /// Power down deepsleep + PDDS: u1, + /// Clear wakeup flag + CWUF: u1, + /// Clear standby flag + CSBF: u1, + /// Power voltage detector enable + PVDE: u1, + /// PVD level selection + PLS: u3, + /// Disable backup domain write protection + DBP: u1, + /// Flash power down in Stop mode + FPDS: u1, + /// Low-Power Regulator Low Voltage in deepsleep + LPLVDS: u1, + /// Main regulator low voltage in deepsleep mode + MRLVDS: u1, + reserved14: u2, + /// Regulator voltage scaling output selection + VOS: u2, + /// Over-drive enable + ODEN: u1, + /// Over-drive switching enabled + ODSWEN: u1, + /// Under-drive enable in stop mode + UDEN: u2, + padding: u12, + }), + /// power control/status register + CSR: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + SBF: u1, + /// PVD output + PVDO: u1, + /// Backup regulator ready + BRR: u1, + reserved8: u4, + /// Enable WKUP pin + EWUP: u1, + /// Backup regulator enable + BRE: u1, + reserved14: u4, + /// Regulator voltage scaling output selection ready bit + VOSRDY: u1, + reserved16: u1, + /// Over-drive mode ready + ODRDY: u1, + /// Over-drive mode switching ready + ODSWRDY: u1, + /// Under-drive ready flag + UDRDY: u2, + padding: u12, + }), + }; + + /// Independent watchdog + pub const IWDG = extern struct { + /// Key register + KR: mmio.Mmio(packed struct(u32) { + /// Key value (write only, read 0000h) + KEY: u16, + padding: u16, + }), + /// Prescaler register + PR: mmio.Mmio(packed struct(u32) { + /// Prescaler divider + PR: u3, + padding: u29, + }), + /// Reload register + RLR: mmio.Mmio(packed struct(u32) { + /// Watchdog counter reload value + RL: u12, + padding: u20, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Watchdog prescaler value update + PVU: u1, + /// Watchdog counter reload value update + RVU: u1, + padding: u30, + }), + }; + + /// Window watchdog + pub const WWDG = extern struct { + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// 7-bit counter (MSB to LSB) + T: u7, + /// Activation bit + WDGA: u1, + padding: u24, + }), + /// Configuration register + CFR: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + W: u7, + /// Timer base + WDGTB0: u1, + /// Timer base + WDGTB1: u1, + /// Early wakeup interrupt + EWI: u1, + padding: u22, + }), + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, + }), + }; + + /// Real-time clock + pub const RTC = extern struct { + /// time register + TR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + reserved8: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + reserved16: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + padding: u9, + }), + /// date register + DR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + /// Year units in BCD format + YU: u4, + /// Year tens in BCD format + YT: u4, + padding: u8, + }), + /// control register + CR: mmio.Mmio(packed struct(u32) { + /// Wakeup clock selection + WCKSEL: u3, + /// Time-stamp event active edge + TSEDGE: u1, + /// Reference clock detection enable (50 or 60 Hz) + REFCKON: u1, + reserved6: u1, + /// Hour format + FMT: u1, + /// Coarse digital calibration enable + DCE: u1, + /// Alarm A enable + ALRAE: u1, + /// Alarm B enable + ALRBE: u1, + /// Wakeup timer enable + WUTE: u1, + /// Time stamp enable + TSE: u1, + /// Alarm A interrupt enable + ALRAIE: u1, + /// Alarm B interrupt enable + ALRBIE: u1, + /// Wakeup timer interrupt enable + WUTIE: u1, + /// Time-stamp interrupt enable + TSIE: u1, + /// Add 1 hour (summer time change) + ADD1H: u1, + /// Subtract 1 hour (winter time change) + SUB1H: u1, + /// Backup + BKP: u1, + reserved20: u1, + /// Output polarity + POL: u1, + /// Output selection + OSEL: u2, + /// Calibration output enable + COE: u1, + padding: u8, + }), + /// initialization and status register + ISR: mmio.Mmio(packed struct(u32) { + /// Alarm A write flag + ALRAWF: u1, + /// Alarm B write flag + ALRBWF: u1, + /// Wakeup timer write flag + WUTWF: u1, + /// Shift operation pending + SHPF: u1, + /// Initialization status flag + INITS: u1, + /// Registers synchronization flag + RSF: u1, + /// Initialization flag + INITF: u1, + /// Initialization mode + INIT: u1, + /// Alarm A flag + ALRAF: u1, + /// Alarm B flag + ALRBF: u1, + /// Wakeup timer flag + WUTF: u1, + /// Time-stamp flag + TSF: u1, + /// Time-stamp overflow flag + TSOVF: u1, + /// Tamper detection flag + TAMP1F: u1, + /// TAMPER2 detection flag + TAMP2F: u1, + reserved16: u1, + /// Recalibration pending Flag + RECALPF: u1, + padding: u15, + }), + /// prescaler register + PRER: mmio.Mmio(packed struct(u32) { + /// Synchronous prescaler factor + PREDIV_S: u15, + reserved16: u1, + /// Asynchronous prescaler factor + PREDIV_A: u7, + padding: u9, + }), + /// wakeup timer register + WUTR: mmio.Mmio(packed struct(u32) { + /// Wakeup auto-reload value bits + WUT: u16, + padding: u16, + }), + /// calibration register + CALIBR: mmio.Mmio(packed struct(u32) { + /// Digital calibration + DC: u5, + reserved7: u2, + /// Digital calibration sign + DCS: u1, + padding: u24, + }), + /// alarm A register + ALRMAR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm A seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm A minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm A hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm A date mask + MSK4: u1, + }), + /// alarm B register + ALRMBR: mmio.Mmio(packed struct(u32) { + /// Second units in BCD format + SU: u4, + /// Second tens in BCD format + ST: u3, + /// Alarm B seconds mask + MSK1: u1, + /// Minute units in BCD format + MNU: u4, + /// Minute tens in BCD format + MNT: u3, + /// Alarm B minutes mask + MSK2: u1, + /// Hour units in BCD format + HU: u4, + /// Hour tens in BCD format + HT: u2, + /// AM/PM notation + PM: u1, + /// Alarm B hours mask + MSK3: u1, + /// Date units or day in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + /// Week day selection + WDSEL: u1, + /// Alarm B date mask + MSK4: u1, + }), + /// write protection register + WPR: mmio.Mmio(packed struct(u32) { + /// Write protection key + KEY: u8, + padding: u24, + }), + /// sub second register + SSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// shift control register + SHIFTR: mmio.Mmio(packed struct(u32) { + /// Subtract a fraction of a second + SUBFS: u15, + reserved31: u16, + /// Add one second + ADD1S: u1, + }), + /// time stamp time register + TSTR: mmio.Mmio(packed struct(u32) { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + reserved16: u13, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// time stamp date register + TSDR: mmio.Mmio(packed struct(u32) { + /// Date units in BCD format + DU: u4, + /// Date tens in BCD format + DT: u2, + reserved8: u2, + /// Month units in BCD format + MU: u4, + /// Month tens in BCD format + MT: u1, + /// Week day units + WDU: u3, + padding: u16, + }), + /// timestamp sub second register + TSSSR: mmio.Mmio(packed struct(u32) { + /// Sub second value + SS: u16, + padding: u16, + }), + /// calibration register + CALR: mmio.Mmio(packed struct(u32) { + /// Calibration minus + CALM: u9, + reserved13: u4, + /// Use a 16-second calibration cycle period + CALW16: u1, + /// Use an 8-second calibration cycle period + CALW8: u1, + /// Increase frequency of RTC by 488.5 ppm + CALP: u1, + padding: u16, + }), + /// tamper and alternate function configuration register + TAFCR: mmio.Mmio(packed struct(u32) { + /// Tamper 1 detection enable + TAMP1E: u1, + /// Active level for tamper 1 + TAMP1TRG: u1, + /// Tamper interrupt enable + TAMPIE: u1, + /// Tamper 2 detection enable + TAMP2E: u1, + /// Active level for tamper 2 + TAMP2TRG: u1, + reserved7: u2, + /// Activate timestamp on tamper detection event + TAMPTS: u1, + /// Tamper sampling frequency + TAMPFREQ: u3, + /// Tamper filter count + TAMPFLT: u2, + /// Tamper precharge duration + TAMPPRCH: u2, + /// TAMPER pull-up disable + TAMPPUDIS: u1, + /// TAMPER1 mapping + TAMP1INSEL: u1, + /// TIMESTAMP mapping + TSINSEL: u1, + /// AFO_ALARM output type + ALARMOUTTYPE: u1, + padding: u13, + }), + /// alarm A sub second register + ALRMASSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + /// alarm B sub second register + ALRMBSSR: mmio.Mmio(packed struct(u32) { + /// Sub seconds value + SS: u15, + reserved24: u9, + /// Mask the most-significant bits starting at this bit + MASKSS: u4, + padding: u4, + }), + reserved80: [4]u8, + /// backup register + BKP0R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP1R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP2R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP3R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP4R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP5R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP6R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP7R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP8R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP9R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP10R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP11R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP12R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP13R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP14R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP15R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP16R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP17R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP18R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + /// backup register + BKP19R: mmio.Mmio(packed struct(u32) { + /// BKP + BKP: u32, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const UART4 = extern struct { + /// Status register + SR: mmio.Mmio(packed struct(u32) { + /// Parity error + PE: u1, + /// Framing error + FE: u1, + /// Noise detected flag + NF: u1, + /// Overrun error + ORE: u1, + /// IDLE line detected + IDLE: u1, + /// Read data register not empty + RXNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data register empty + TXE: u1, + /// LIN break detection flag + LBD: u1, + padding: u23, + }), + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data value + DR: u9, + padding: u23, + }), + /// Baud rate register + BRR: mmio.Mmio(packed struct(u32) { + /// fraction of USARTDIV + DIV_Fraction: u4, + /// mantissa of USARTDIV + DIV_Mantissa: u12, + padding: u16, + }), + /// Control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Send break + SBK: u1, + /// Receiver wakeup + RWU: u1, + /// Receiver enable + RE: u1, + /// Transmitter enable + TE: u1, + /// IDLE interrupt enable + IDLEIE: u1, + /// RXNE interrupt enable + RXNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// TXE interrupt enable + TXEIE: u1, + /// PE interrupt enable + PEIE: u1, + /// Parity selection + PS: u1, + /// Parity control enable + PCE: u1, + /// Wakeup method + WAKE: u1, + /// Word length + M: u1, + /// USART enable + UE: u1, + reserved15: u1, + /// Oversampling mode + OVER8: u1, + padding: u16, + }), + /// Control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Address of the USART node + ADD: u4, + reserved5: u1, + /// lin break detection length + LBDL: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits + STOP: u2, + /// LIN mode enable + LINEN: u1, + padding: u17, + }), + /// Control register 3 + CR3: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + EIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDSEL: u1, + reserved6: u2, + /// DMA enable receiver + DMAR: u1, + /// DMA enable transmitter + DMAT: u1, + reserved11: u3, + /// One sample bit method enable + ONEBIT: u1, + padding: u20, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_DEVICE = extern struct { + /// OTG_FS device configuration register (OTG_FS_DCFG) + FS_DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DSPD: u2, + /// Non-zero-length status OUT handshake + NZLSOHSK: u1, + reserved4: u1, + /// Device address + DAD: u7, + /// Periodic frame interval + PFIVL: u2, + padding: u19, + }), + /// OTG_FS device control register (OTG_FS_DCTL) + FS_DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup signaling + RWUSIG: u1, + /// Soft disconnect + SDIS: u1, + /// Global IN NAK status + GINSTS: u1, + /// Global OUT NAK status + GONSTS: u1, + /// Test control + TCTL: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on programming done + POPRGDNE: u1, + padding: u20, + }), + /// OTG_FS device status register (OTG_FS_DSTS) + FS_DSTS: mmio.Mmio(packed struct(u32) { + /// Suspend status + SUSPSTS: u1, + /// Enumerated speed + ENUMSPD: u2, + /// Erratic error + EERR: u1, + reserved8: u4, + /// Frame number of the received SOF + FNSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) + FS_DIEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// Timeout condition mask (Non-isochronous endpoints) + TOM: u1, + /// IN token received when TxFIFO empty mask + ITTXFEMSK: u1, + /// IN token received with EP mismatch mask + INEPNMM: u1, + /// IN endpoint NAK effective mask + INEPNEM: u1, + padding: u25, + }), + /// OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) + FS_DOEPMSK: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt mask + XFRCM: u1, + /// Endpoint disabled interrupt mask + EPDM: u1, + reserved3: u1, + /// SETUP phase done mask + STUPM: u1, + /// OUT token received when endpoint disabled mask + OTEPDM: u1, + padding: u27, + }), + /// OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) + FS_DAINT: mmio.Mmio(packed struct(u32) { + /// IN endpoint interrupt bits + IEPINT: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + /// OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) + FS_DAINTMSK: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt mask bits + IEPM: u16, + /// OUT endpoint interrupt bits + OEPINT: u16, + }), + reserved40: [8]u8, + /// OTG_FS device VBUS discharge time register + DVBUSDIS: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + VBUSDT: u16, + padding: u16, + }), + /// OTG_FS device VBUS pulsing time register + DVBUSPULSE: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSP: u12, + padding: u20, + }), + reserved52: [4]u8, + /// OTG_FS device IN endpoint FIFO empty interrupt mask register + DIEPEMPMSK: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt mask bits + INEPTXFEM: u16, + padding: u16, + }), + reserved256: [200]u8, + /// OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) + FS_DIEPCTL0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u2, + reserved15: u13, + /// USB active endpoint + USBAEP: u1, + reserved17: u1, + /// NAK status + NAKSTS: u1, + /// Endpoint type + EPTYP: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPDIS: u1, + /// Endpoint enable + EPENA: u1, + }), + reserved264: [4]u8, + /// device endpoint-x interrupt register + DIEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved272: [4]u8, + /// device endpoint-0 transfer size register + DIEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u2, + padding: u11, + }), + reserved280: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS0: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved288: [4]u8, + /// OTG device endpoint-1 control register + DIEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM/SD1PID + SODDFRM_SD1PID: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved296: [4]u8, + /// device endpoint-1 interrupt register + DIEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved304: [4]u8, + /// device endpoint-1 transfer size register + DIEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved312: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS1: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved320: [4]u8, + /// OTG device endpoint-2 control register + DIEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved328: [4]u8, + /// device endpoint-2 interrupt register + DIEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved336: [4]u8, + /// device endpoint-2 transfer size register + DIEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved344: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS2: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved352: [4]u8, + /// OTG device endpoint-3 control register + DIEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + reserved21: u1, + /// Stall + Stall: u1, + /// TXFNUM + TXFNUM: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved360: [4]u8, + /// device endpoint-3 interrupt register + DIEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// TOC + TOC: u1, + /// ITTXFE + ITTXFE: u1, + reserved6: u1, + /// INEPNE + INEPNE: u1, + /// TXFE + TXFE: u1, + padding: u24, + }), + reserved368: [4]u8, + /// device endpoint-3 transfer size register + DIEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Multi count + MCNT: u2, + padding: u1, + }), + reserved376: [4]u8, + /// OTG_FS device IN endpoint transmit FIFO status register + DTXFSTS3: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space available + INEPTFSAV: u16, + padding: u16, + }), + reserved768: [388]u8, + /// device endpoint-0 control register + DOEPCTL0: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u2, + reserved15: u13, + /// USBAEP + USBAEP: u1, + reserved17: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + reserved30: u2, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved776: [4]u8, + /// device endpoint-0 interrupt register + DOEPINT0: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved784: [4]u8, + /// device OUT endpoint-0 transfer size register + DOEPTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u7, + reserved19: u12, + /// Packet count + PKTCNT: u1, + reserved29: u9, + /// SETUP packet count + STUPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// device endpoint-1 control register + DOEPCTL1: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved808: [4]u8, + /// device endpoint-1 interrupt register + DOEPINT1: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved816: [4]u8, + /// device OUT endpoint-1 transfer size register + DOEPTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved832: [12]u8, + /// device endpoint-2 control register + DOEPCTL2: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved840: [4]u8, + /// device endpoint-2 interrupt register + DOEPINT2: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved848: [4]u8, + /// device OUT endpoint-2 transfer size register + DOEPTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + reserved864: [12]u8, + /// device endpoint-3 control register + DOEPCTL3: mmio.Mmio(packed struct(u32) { + /// MPSIZ + MPSIZ: u11, + reserved15: u4, + /// USBAEP + USBAEP: u1, + /// EONUM/DPID + EONUM_DPID: u1, + /// NAKSTS + NAKSTS: u1, + /// EPTYP + EPTYP: u2, + /// SNPM + SNPM: u1, + /// Stall + Stall: u1, + reserved26: u4, + /// CNAK + CNAK: u1, + /// SNAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVNFRM: u1, + /// SODDFRM + SODDFRM: u1, + /// EPDIS + EPDIS: u1, + /// EPENA + EPENA: u1, + }), + reserved872: [4]u8, + /// device endpoint-3 interrupt register + DOEPINT3: mmio.Mmio(packed struct(u32) { + /// XFRC + XFRC: u1, + /// EPDISD + EPDISD: u1, + reserved3: u1, + /// STUP + STUP: u1, + /// OTEPDIS + OTEPDIS: u1, + reserved6: u1, + /// B2BSTUP + B2BSTUP: u1, + padding: u25, + }), + reserved880: [4]u8, + /// device OUT endpoint-3 transfer size register + DOEPTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Received data PID/SETUP packet count + RXDPID_STUPCNT: u2, + padding: u1, + }), + }; + + /// Common ADC registers + pub const C_ADC = extern struct { + /// ADC Common status register + CSR: mmio.Mmio(packed struct(u32) { + /// Analog watchdog flag of ADC 1 + AWD1: u1, + /// End of conversion of ADC 1 + EOC1: u1, + /// Injected channel end of conversion of ADC 1 + JEOC1: u1, + /// Injected channel Start flag of ADC 1 + JSTRT1: u1, + /// Regular channel Start flag of ADC 1 + STRT1: u1, + /// Overrun flag of ADC 1 + OVR1: u1, + reserved8: u2, + /// Analog watchdog flag of ADC 2 + AWD2: u1, + /// End of conversion of ADC 2 + EOC2: u1, + /// Injected channel end of conversion of ADC 2 + JEOC2: u1, + /// Injected channel Start flag of ADC 2 + JSTRT2: u1, + /// Regular channel Start flag of ADC 2 + STRT2: u1, + /// Overrun flag of ADC 2 + OVR2: u1, + reserved16: u2, + /// Analog watchdog flag of ADC 3 + AWD3: u1, + /// End of conversion of ADC 3 + EOC3: u1, + /// Injected channel end of conversion of ADC 3 + JEOC3: u1, + /// Injected channel Start flag of ADC 3 + JSTRT3: u1, + /// Regular channel Start flag of ADC 3 + STRT3: u1, + /// Overrun flag of ADC3 + OVR3: u1, + padding: u10, + }), + /// ADC common control register + CCR: mmio.Mmio(packed struct(u32) { + /// Multi ADC mode selection + MULT: u5, + reserved8: u3, + /// Delay between 2 sampling phases + DELAY: u4, + reserved13: u1, + /// DMA disable selection for multi-ADC mode + DDS: u1, + /// Direct memory access mode for multi ADC mode + DMA: u2, + /// ADC prescaler + ADCPRE: u2, + reserved22: u4, + /// VBAT enable + VBATE: u1, + /// Temperature sensor and VREFINT enable + TSVREFE: u1, + padding: u8, + }), + /// ADC common regular data register for dual and triple modes + CDR: mmio.Mmio(packed struct(u32) { + /// 1st data item of a pair of regular conversions + DATA1: u16, + /// 2nd data item of a pair of regular conversions + DATA2: u16, + }), + }; + + /// Advanced-timers + pub const TIM1 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + /// Capture/compare preloaded control + CCPC: u1, + reserved2: u1, + /// Capture/compare control update selection + CCUS: u1, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + /// Output Idle state 1 + OIS1: u1, + /// Output Idle state 1 + OIS1N: u1, + /// Output Idle state 2 + OIS2: u1, + /// Output Idle state 2 + OIS2N: u1, + /// Output Idle state 3 + OIS3: u1, + /// Output Idle state 3 + OIS3N: u1, + /// Output Idle state 4 + OIS4: u1, + padding: u17, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + /// COM interrupt enable + COMIE: u1, + /// Trigger interrupt enable + TIE: u1, + /// Break interrupt enable + BIE: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + /// COM DMA request enable + COMDE: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + /// COM interrupt flag + COMIF: u1, + /// Trigger interrupt flag + TIF: u1, + /// Break interrupt flag + BIF: u1, + reserved9: u1, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + /// Capture/Compare control update generation + COMG: u1, + /// Trigger generation + TG: u1, + /// Break generation + BG: u1, + padding: u24, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + /// Output Compare 1 clear enable + OC1CE: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + /// Output Compare 2 clear enable + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 3 selection + CC3S: u2, + /// Output compare 3 fast enable + OC3FE: u1, + /// Output compare 3 preload enable + OC3PE: u1, + /// Output compare 3 mode + OC3M: u3, + /// Output compare 3 clear enable + OC3CE: u1, + /// Capture/Compare 4 selection + CC4S: u2, + /// Output compare 4 fast enable + OC4FE: u1, + /// Output compare 4 preload enable + OC4PE: u1, + /// Output compare 4 mode + OC4M: u3, + /// Output compare 4 clear enable + OC4CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + /// Capture/Compare 1 complementary output enable + CC1NE: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + /// Capture/Compare 2 complementary output enable + CC2NE: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + /// Capture/Compare 3 complementary output enable + CC3NE: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + padding: u18, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + /// repetition counter register + RCR: mmio.Mmio(packed struct(u32) { + /// Repetition counter value + REP: u8, + padding: u24, + }), + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR3: u16, + padding: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Capture/Compare value + CCR4: u16, + padding: u16, + }), + /// break and dead-time register + BDTR: mmio.Mmio(packed struct(u32) { + /// Dead-time generator setup + DTG: u8, + /// Lock configuration + LOCK: u2, + /// Off-state selection for Idle mode + OSSI: u1, + /// Off-state selection for Run mode + OSSR: u1, + /// Break enable + BKE: u1, + /// Break polarity + BKP: u1, + /// Automatic output enable + AOE: u1, + /// Main output enable + MOE: u1, + padding: u16, + }), + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_HOST = extern struct { + /// OTG_FS host configuration register (OTG_FS_HCFG) + FS_HCFG: mmio.Mmio(packed struct(u32) { + /// FS/LS PHY clock select + FSLSPCS: u2, + /// FS- and LS-only support + FSLSS: u1, + padding: u29, + }), + /// OTG_FS Host frame interval register + HFIR: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRIVL: u16, + padding: u16, + }), + /// OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) + FS_HFNUM: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame time remaining + FTREM: u16, + }), + reserved16: [4]u8, + /// OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) + FS_HPTXSTS: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFSAVL: u16, + /// Periodic transmit request queue space available + PTXQSAV: u8, + /// Top of the periodic transmit request queue + PTXQTOP: u8, + }), + /// OTG_FS Host all channels interrupt register + HAINT: mmio.Mmio(packed struct(u32) { + /// Channel interrupts + HAINT: u16, + padding: u16, + }), + /// OTG_FS host all channels interrupt mask register + HAINTMSK: mmio.Mmio(packed struct(u32) { + /// Channel interrupt mask + HAINTM: u16, + padding: u16, + }), + reserved64: [36]u8, + /// OTG_FS host port control and status register (OTG_FS_HPRT) + FS_HPRT: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCSTS: u1, + /// Port connect detected + PCDET: u1, + /// Port enable + PENA: u1, + /// Port enable/disable change + PENCHNG: u1, + /// Port overcurrent active + POCA: u1, + /// Port overcurrent change + POCCHNG: u1, + /// Port resume + PRES: u1, + /// Port suspend + PSUSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLSTS: u2, + /// Port power + PPWR: u1, + /// Port test control + PTCTL: u4, + /// Port speed + PSPD: u2, + padding: u13, + }), + reserved256: [188]u8, + /// OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) + FS_HCCHAR0: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved264: [4]u8, + /// OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) + FS_HCINT0: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) + FS_HCINTMSK0: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-0 transfer size register + FS_HCTSIZ0: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved288: [12]u8, + /// OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) + FS_HCCHAR1: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved296: [4]u8, + /// OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) + FS_HCINT1: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) + FS_HCINTMSK1: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-1 transfer size register + FS_HCTSIZ1: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved320: [12]u8, + /// OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) + FS_HCCHAR2: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved328: [4]u8, + /// OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) + FS_HCINT2: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) + FS_HCINTMSK2: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-2 transfer size register + FS_HCTSIZ2: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved352: [12]u8, + /// OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) + FS_HCCHAR3: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved360: [4]u8, + /// OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) + FS_HCINT3: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) + FS_HCINTMSK3: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-3 transfer size register + FS_HCTSIZ3: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved384: [12]u8, + /// OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) + FS_HCCHAR4: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved392: [4]u8, + /// OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) + FS_HCINT4: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) + FS_HCINTMSK4: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-x transfer size register + FS_HCTSIZ4: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved416: [12]u8, + /// OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) + FS_HCCHAR5: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved424: [4]u8, + /// OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) + FS_HCINT5: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) + FS_HCINTMSK5: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-5 transfer size register + FS_HCTSIZ5: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved448: [12]u8, + /// OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) + FS_HCCHAR6: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved456: [4]u8, + /// OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) + FS_HCINT6: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) + FS_HCINTMSK6: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-6 transfer size register + FS_HCTSIZ6: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved480: [12]u8, + /// OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) + FS_HCCHAR7: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPSIZ: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSDEV: u1, + /// Endpoint type + EPTYP: u2, + /// Multicount + MCNT: u2, + /// Device address + DAD: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CHDIS: u1, + /// Channel enable + CHENA: u1, + }), + reserved488: [4]u8, + /// OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) + FS_HCINT7: mmio.Mmio(packed struct(u32) { + /// Transfer completed + XFRC: u1, + /// Channel halted + CHH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// Transaction error + TXERR: u1, + /// Babble error + BBERR: u1, + /// Frame overrun + FRMOR: u1, + /// Data toggle error + DTERR: u1, + padding: u21, + }), + /// OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) + FS_HCINTMSK7: mmio.Mmio(packed struct(u32) { + /// Transfer completed mask + XFRCM: u1, + /// Channel halted mask + CHHM: u1, + reserved3: u1, + /// STALL response received interrupt mask + STALLM: u1, + /// NAK response received interrupt mask + NAKM: u1, + /// ACK response received/transmitted interrupt mask + ACKM: u1, + /// response received interrupt mask + NYET: u1, + /// Transaction error mask + TXERRM: u1, + /// Babble error mask + BBERRM: u1, + /// Frame overrun mask + FRMORM: u1, + /// Data toggle error mask + DTERRM: u1, + padding: u21, + }), + /// OTG_FS host channel-7 transfer size register + FS_HCTSIZ7: mmio.Mmio(packed struct(u32) { + /// Transfer size + XFRSIZ: u19, + /// Packet count + PKTCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + }; + + /// General purpose timers + pub const TIM2 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// TIM5 option register + OR: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// Timer Input 4 remap + ITR1_RMP: u2, + padding: u20, + }), + }; + + /// General purpose timers + pub const TIM3 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + }; + + /// USB on the go full speed + pub const OTG_FS_GLOBAL = extern struct { + /// OTG_FS control and status register (OTG_FS_GOTGCTL) + FS_GOTGCTL: mmio.Mmio(packed struct(u32) { + /// Session request success + SRQSCS: u1, + /// Session request + SRQ: u1, + reserved8: u6, + /// Host negotiation success + HNGSCS: u1, + /// HNP request + HNPRQ: u1, + /// Host set HNP enable + HSHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// Connector ID status + CIDSTS: u1, + /// Long/short debounce time + DBCT: u1, + /// A-session valid + ASVLD: u1, + /// B-session valid + BSVLD: u1, + padding: u12, + }), + /// OTG_FS interrupt register (OTG_FS_GOTGINT) + FS_GOTGINT: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end detected + SEDET: u1, + reserved8: u5, + /// Session request success status change + SRSSCHG: u1, + /// Host negotiation success status change + HNSSCHG: u1, + reserved17: u7, + /// Host negotiation detected + HNGDET: u1, + /// A-device timeout change + ADTOCHG: u1, + /// Debounce done + DBCDNE: u1, + padding: u12, + }), + /// OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + FS_GAHBCFG: mmio.Mmio(packed struct(u32) { + /// Global interrupt mask + GINT: u1, + reserved7: u6, + /// TxFIFO empty level + TXFELVL: u1, + /// Periodic TxFIFO empty level + PTXFELVL: u1, + padding: u23, + }), + /// OTG_FS USB configuration register (OTG_FS_GUSBCFG) + FS_GUSBCFG: mmio.Mmio(packed struct(u32) { + /// FS timeout calibration + TOCAL: u3, + reserved6: u3, + /// Full Speed serial transceiver select + PHYSEL: u1, + reserved8: u1, + /// SRP-capable + SRPCAP: u1, + /// HNP-capable + HNPCAP: u1, + /// USB turnaround time + TRDT: u4, + reserved29: u15, + /// Force host mode + FHMOD: u1, + /// Force device mode + FDMOD: u1, + /// Corrupt Tx packet + CTXPKT: u1, + }), + /// OTG_FS reset register (OTG_FS_GRSTCTL) + FS_GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HSRST: u1, + /// Host frame counter reset + FCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFFLSH: u1, + /// TxFIFO flush + TXFFLSH: u1, + /// TxFIFO number + TXFNUM: u5, + reserved31: u20, + /// AHB master idle + AHBIDL: u1, + }), + /// OTG_FS core interrupt register (OTG_FS_GINTSTS) + FS_GINTSTS: mmio.Mmio(packed struct(u32) { + /// Current mode of operation + CMOD: u1, + /// Mode mismatch interrupt + MMIS: u1, + /// OTG interrupt + OTGINT: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty + RXFLVL: u1, + /// Non-periodic TxFIFO empty + NPTXFE: u1, + /// Global IN non-periodic NAK effective + GINAKEFF: u1, + /// Global OUT NAK effective + GOUTNAKEFF: u1, + reserved10: u2, + /// Early suspend + ESUSP: u1, + /// USB suspend + USBSUSP: u1, + /// USB reset + USBRST: u1, + /// Enumeration done + ENUMDNE: u1, + /// Isochronous OUT packet dropped interrupt + ISOODRP: u1, + /// End of periodic frame interrupt + EOPF: u1, + reserved18: u2, + /// IN endpoint interrupt + IEPINT: u1, + /// OUT endpoint interrupt + OEPINT: u1, + /// Incomplete isochronous IN transfer + IISOIXFR: u1, + /// Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) + IPXFR_INCOMPISOOUT: u1, + reserved24: u2, + /// Host port interrupt + HPRTINT: u1, + /// Host channels interrupt + HCINT: u1, + /// Periodic TxFIFO empty + PTXFE: u1, + reserved28: u1, + /// Connector ID status change + CIDSCHG: u1, + /// Disconnect detected interrupt + DISCINT: u1, + /// Session request/new session detected interrupt + SRQINT: u1, + /// Resume/remote wakeup detected interrupt + WKUPINT: u1, + }), + /// OTG_FS interrupt mask register (OTG_FS_GINTMSK) + FS_GINTMSK: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode mismatch interrupt mask + MMISM: u1, + /// OTG interrupt mask + OTGINT: u1, + /// Start of frame mask + SOFM: u1, + /// Receive FIFO non-empty mask + RXFLVLM: u1, + /// Non-periodic TxFIFO empty mask + NPTXFEM: u1, + /// Global non-periodic IN NAK effective mask + GINAKEFFM: u1, + /// Global OUT NAK effective mask + GONAKEFFM: u1, + reserved10: u2, + /// Early suspend mask + ESUSPM: u1, + /// USB suspend mask + USBSUSPM: u1, + /// USB reset mask + USBRST: u1, + /// Enumeration done mask + ENUMDNEM: u1, + /// Isochronous OUT packet dropped interrupt mask + ISOODRPM: u1, + /// End of periodic frame interrupt mask + EOPFM: u1, + reserved17: u1, + /// Endpoint mismatch interrupt mask + EPMISM: u1, + /// IN endpoints interrupt mask + IEPINT: u1, + /// OUT endpoints interrupt mask + OEPINT: u1, + /// Incomplete isochronous IN transfer mask + IISOIXFRM: u1, + /// Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) + IPXFRM_IISOOXFRM: u1, + reserved24: u2, + /// Host port interrupt mask + PRTIM: u1, + /// Host channels interrupt mask + HCIM: u1, + /// Periodic TxFIFO empty mask + PTXFEM: u1, + reserved28: u1, + /// Connector ID status change mask + CIDSCHGM: u1, + /// Disconnect detected interrupt mask + DISCINT: u1, + /// Session request/new session detected interrupt mask + SRQIM: u1, + /// Resume/remote wakeup detected interrupt mask + WUIM: u1, + }), + /// OTG_FS Receive status debug read(Device mode) + FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCNT: u11, + /// Data PID + DPID: u2, + /// Packet status + PKTSTS: u4, + /// Frame number + FRMNUM: u4, + padding: u7, + }), + reserved36: [4]u8, + /// OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + FS_GRXFSIZ: mmio.Mmio(packed struct(u32) { + /// RxFIFO depth + RXFD: u16, + padding: u16, + }), + /// OTG_FS non-periodic transmit FIFO size register (Device mode) + FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint 0 transmit RAM start address + TX0FSA: u16, + /// Endpoint 0 TxFIFO depth + TX0FD: u16, + }), + /// OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + FS_GNPTXSTS: mmio.Mmio(packed struct(u32) { + /// Non-periodic TxFIFO space available + NPTXFSAV: u16, + /// Non-periodic transmit request queue space available + NPTQXSAV: u8, + /// Top of the non-periodic transmit request queue + NPTXQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// OTG_FS general core configuration register (OTG_FS_GCCFG) + FS_GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power down + PWRDWN: u1, + reserved18: u1, + /// Enable the VBUS sensing device + VBUSASEN: u1, + /// Enable the VBUS sensing device + VBUSBSEN: u1, + /// SOF output enable + SOFOUTEN: u1, + padding: u11, + }), + /// core ID register + FS_CID: mmio.Mmio(packed struct(u32) { + /// Product ID field + PRODUCT_ID: u32, + }), + reserved256: [192]u8, + /// OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + PTXSA: u16, + /// Host periodic TxFIFO depth + PTXFSIZ: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + FS_DIEPTXF1: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO2 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + FS_DIEPTXF2: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO3 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + /// OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + FS_DIEPTXF3: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO4 transmit RAM start address + INEPTXSA: u16, + /// IN endpoint TxFIFO depth + INEPTXFD: u16, + }), + }; + + /// General-purpose-timers + pub const TIM5 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + /// Direction + DIR: u1, + /// Center-aligned mode selection + CMS: u2, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved3: u3, + /// Capture/compare DMA selection + CCDS: u1, + /// Master mode selection + MMS: u3, + /// TI1 selection + TI1S: u1, + padding: u24, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter + ETF: u4, + /// External trigger prescaler + ETPS: u2, + /// External clock enable + ECE: u1, + /// External trigger polarity + ETP: u1, + padding: u16, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + /// Capture/Compare 3 interrupt enable + CC3IE: u1, + /// Capture/Compare 4 interrupt enable + CC4IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TIE: u1, + reserved8: u1, + /// Update DMA request enable + UDE: u1, + /// Capture/Compare 1 DMA request enable + CC1DE: u1, + /// Capture/Compare 2 DMA request enable + CC2DE: u1, + /// Capture/Compare 3 DMA request enable + CC3DE: u1, + /// Capture/Compare 4 DMA request enable + CC4DE: u1, + reserved14: u1, + /// Trigger DMA request enable + TDE: u1, + padding: u17, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + /// Capture/Compare 3 interrupt flag + CC3IF: u1, + /// Capture/Compare 4 interrupt flag + CC4IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + /// Capture/Compare 3 overcapture flag + CC3OF: u1, + /// Capture/Compare 4 overcapture flag + CC4OF: u1, + padding: u19, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + /// Capture/compare 3 generation + CC3G: u1, + /// Capture/compare 4 generation + CC4G: u1, + reserved6: u1, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// CC1S + CC1S: u2, + /// OC1FE + OC1FE: u1, + /// OC1PE + OC1PE: u1, + /// OC1M + OC1M: u3, + /// OC1CE + OC1CE: u1, + /// CC2S + CC2S: u2, + /// OC2FE + OC2FE: u1, + /// OC2PE + OC2PE: u1, + /// OC2M + OC2M: u3, + /// OC2CE + OC2CE: u1, + padding: u16, + }), + /// capture/compare mode register 2 (output mode) + CCMR2_Output: mmio.Mmio(packed struct(u32) { + /// CC3S + CC3S: u2, + /// OC3FE + OC3FE: u1, + /// OC3PE + OC3PE: u1, + /// OC3M + OC3M: u3, + /// OC3CE + OC3CE: u1, + /// CC4S + CC4S: u2, + /// OC4FE + OC4FE: u1, + /// OC4PE + OC4PE: u1, + /// OC4M + OC4M: u3, + /// O24CE + O24CE: u1, + padding: u16, + }), + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + /// Capture/Compare 3 output enable + CC3E: u1, + /// Capture/Compare 3 output Polarity + CC3P: u1, + reserved11: u1, + /// Capture/Compare 3 output Polarity + CC3NP: u1, + /// Capture/Compare 4 output enable + CC4E: u1, + /// Capture/Compare 3 output Polarity + CC4P: u1, + reserved15: u1, + /// Capture/Compare 4 output Polarity + CC4NP: u1, + padding: u16, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// Low counter value + CNT_L: u16, + /// High counter value + CNT_H: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Low Auto-reload value + ARR_L: u16, + /// High Auto-reload value + ARR_H: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 1 value + CCR1_L: u16, + /// High Capture/Compare 1 value + CCR1_H: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare 2 value + CCR2_L: u16, + /// High Capture/Compare 2 value + CCR2_H: u16, + }), + /// capture/compare register 3 + CCR3: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR3_L: u16, + /// High Capture/Compare value + CCR3_H: u16, + }), + /// capture/compare register 4 + CCR4: mmio.Mmio(packed struct(u32) { + /// Low Capture/Compare value + CCR4_L: u16, + /// High Capture/Compare value + CCR4_H: u16, + }), + reserved72: [4]u8, + /// DMA control register + DCR: mmio.Mmio(packed struct(u32) { + /// DMA base address + DBA: u5, + reserved8: u3, + /// DMA burst length + DBL: u5, + padding: u19, + }), + /// DMA address for full transfer + DMAR: mmio.Mmio(packed struct(u32) { + /// DMA register for burst accesses + DMAB: u16, + padding: u16, + }), + /// TIM5 option register + OR: mmio.Mmio(packed struct(u32) { + reserved6: u6, + /// Timer Input 4 remap + IT4_RMP: u2, + padding: u24, + }), + }; + + /// General purpose timers + pub const TIM9 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + /// One-pulse mode + OPM: u1, + reserved7: u3, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + /// control register 2 + CR2: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// Master mode selection + MMS: u3, + padding: u25, + }), + /// slave mode control register + SMCR: mmio.Mmio(packed struct(u32) { + /// Slave mode selection + SMS: u3, + reserved4: u1, + /// Trigger selection + TS: u3, + /// Master/Slave mode + MSM: u1, + padding: u24, + }), + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + /// Capture/Compare 2 interrupt enable + CC2IE: u1, + reserved6: u3, + /// Trigger interrupt enable + TIE: u1, + padding: u25, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + /// Capture/Compare 2 interrupt flag + CC2IF: u1, + reserved6: u3, + /// Trigger interrupt flag + TIF: u1, + reserved9: u2, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + /// Capture/compare 2 overcapture flag + CC2OF: u1, + padding: u21, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + /// Capture/compare 2 generation + CC2G: u1, + reserved6: u3, + /// Trigger generation + TG: u1, + padding: u25, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + reserved8: u1, + /// Capture/Compare 2 selection + CC2S: u2, + /// Output Compare 2 fast enable + OC2FE: u1, + /// Output Compare 2 preload enable + OC2PE: u1, + /// Output Compare 2 mode + OC2M: u3, + padding: u17, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + /// Capture/Compare 2 output enable + CC2E: u1, + /// Capture/Compare 2 output Polarity + CC2P: u1, + reserved7: u1, + /// Capture/Compare 2 output Polarity + CC2NP: u1, + padding: u24, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + /// capture/compare register 2 + CCR2: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 2 value + CCR2: u16, + padding: u16, + }), + }; + + /// Cryptographic processor + pub const CRC = extern struct { + /// Data register + DR: mmio.Mmio(packed struct(u32) { + /// Data Register + DR: u32, + }), + /// Independent Data register + IDR: mmio.Mmio(packed struct(u32) { + /// Independent Data register + IDR: u8, + padding: u24, + }), + /// Control register + CR: mmio.Mmio(packed struct(u32) { + /// Control regidter + CR: u1, + padding: u31, + }), + }; + + /// General-purpose-timers + pub const TIM10 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved7: u4, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved9: u7, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + padding: u30, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding: u25, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + }; + + /// Ethernet: DMA controller operation + pub const Ethernet_DMA = extern struct { + /// Ethernet DMA bus mode register + DMABMR: mmio.Mmio(packed struct(u32) { + /// SR + SR: u1, + /// DA + DA: u1, + /// DSL + DSL: u5, + /// EDFE + EDFE: u1, + /// PBL + PBL: u6, + /// RTPR + RTPR: u2, + /// FB + FB: u1, + /// RDP + RDP: u6, + /// USP + USP: u1, + /// FPM + FPM: u1, + /// AAB + AAB: u1, + /// MB + MB: u1, + padding: u5, + }), + /// Ethernet DMA transmit poll demand register + DMATPDR: mmio.Mmio(packed struct(u32) { + /// TPD + TPD: u32, + }), + /// EHERNET DMA receive poll demand register + DMARPDR: mmio.Mmio(packed struct(u32) { + /// RPD + RPD: u32, + }), + /// Ethernet DMA receive descriptor list address register + DMARDLAR: mmio.Mmio(packed struct(u32) { + /// SRL + SRL: u32, + }), + /// Ethernet DMA transmit descriptor list address register + DMATDLAR: mmio.Mmio(packed struct(u32) { + /// STL + STL: u32, + }), + /// Ethernet DMA status register + DMASR: mmio.Mmio(packed struct(u32) { + /// TS + TS: u1, + /// TPSS + TPSS: u1, + /// TBUS + TBUS: u1, + /// TJTS + TJTS: u1, + /// ROS + ROS: u1, + /// TUS + TUS: u1, + /// RS + RS: u1, + /// RBUS + RBUS: u1, + /// RPSS + RPSS: u1, + /// PWTS + PWTS: u1, + /// ETS + ETS: u1, + reserved13: u2, + /// FBES + FBES: u1, + /// ERS + ERS: u1, + /// AIS + AIS: u1, + /// NIS + NIS: u1, + /// RPS + RPS: u3, + /// TPS + TPS: u3, + /// EBS + EBS: u3, + reserved27: u1, + /// MMCS + MMCS: u1, + /// PMTS + PMTS: u1, + /// TSTS + TSTS: u1, + padding: u2, + }), + /// Ethernet DMA operation mode register + DMAOMR: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// SR + SR: u1, + /// OSF + OSF: u1, + /// RTC + RTC: u2, + reserved6: u1, + /// FUGF + FUGF: u1, + /// FEF + FEF: u1, + reserved13: u5, + /// ST + ST: u1, + /// TTC + TTC: u3, + reserved20: u3, + /// FTF + FTF: u1, + /// TSF + TSF: u1, + reserved24: u2, + /// DFRF + DFRF: u1, + /// RSF + RSF: u1, + /// DTCEFD + DTCEFD: u1, + padding: u5, + }), + /// Ethernet DMA interrupt enable register + DMAIER: mmio.Mmio(packed struct(u32) { + /// TIE + TIE: u1, + /// TPSIE + TPSIE: u1, + /// TBUIE + TBUIE: u1, + /// TJTIE + TJTIE: u1, + /// ROIE + ROIE: u1, + /// TUIE + TUIE: u1, + /// RIE + RIE: u1, + /// RBUIE + RBUIE: u1, + /// RPSIE + RPSIE: u1, + /// RWTIE + RWTIE: u1, + /// ETIE + ETIE: u1, + reserved13: u2, + /// FBEIE + FBEIE: u1, + /// ERIE + ERIE: u1, + /// AISE + AISE: u1, + /// NISE + NISE: u1, + padding: u15, + }), + /// Ethernet DMA missed frame and buffer overflow counter register + DMAMFBOCR: mmio.Mmio(packed struct(u32) { + /// MFC + MFC: u16, + /// OMFC + OMFC: u1, + /// MFA + MFA: u11, + /// OFOC + OFOC: u1, + padding: u3, + }), + /// Ethernet DMA receive status watchdog timer register + DMARSWTR: mmio.Mmio(packed struct(u32) { + /// RSWTC + RSWTC: u8, + padding: u24, + }), + reserved72: [32]u8, + /// Ethernet DMA current host transmit descriptor register + DMACHTDR: mmio.Mmio(packed struct(u32) { + /// HTDAP + HTDAP: u32, + }), + /// Ethernet DMA current host receive descriptor register + DMACHRDR: mmio.Mmio(packed struct(u32) { + /// HRDAP + HRDAP: u32, + }), + /// Ethernet DMA current host transmit buffer address register + DMACHTBAR: mmio.Mmio(packed struct(u32) { + /// HTBAP + HTBAP: u32, + }), + /// Ethernet DMA current host receive buffer address register + DMACHRBAR: mmio.Mmio(packed struct(u32) { + /// HRBAP + HRBAP: u32, + }), + }; + + /// Ethernet: Precision time protocol + pub const Ethernet_PTP = extern struct { + /// Ethernet PTP time stamp control register + PTPTSCR: mmio.Mmio(packed struct(u32) { + /// TSE + TSE: u1, + /// TSFCU + TSFCU: u1, + /// TSSTI + TSSTI: u1, + /// TSSTU + TSSTU: u1, + /// TSITE + TSITE: u1, + /// TTSARU + TTSARU: u1, + reserved8: u2, + /// TSSARFE + TSSARFE: u1, + /// TSSSR + TSSSR: u1, + /// TSPTPPSV2E + TSPTPPSV2E: u1, + /// TSSPTPOEFE + TSSPTPOEFE: u1, + /// TSSIPV6FE + TSSIPV6FE: u1, + /// TSSIPV4FE + TSSIPV4FE: u1, + /// TSSEME + TSSEME: u1, + /// TSSMRME + TSSMRME: u1, + /// TSCNT + TSCNT: u2, + /// TSPFFMAE + TSPFFMAE: u1, + padding: u13, + }), + /// Ethernet PTP subsecond increment register + PTPSSIR: mmio.Mmio(packed struct(u32) { + /// STSSI + STSSI: u8, + padding: u24, + }), + /// Ethernet PTP time stamp high register + PTPTSHR: mmio.Mmio(packed struct(u32) { + /// STS + STS: u32, + }), + /// Ethernet PTP time stamp low register + PTPTSLR: mmio.Mmio(packed struct(u32) { + /// STSS + STSS: u31, + /// STPNS + STPNS: u1, + }), + /// Ethernet PTP time stamp high update register + PTPTSHUR: mmio.Mmio(packed struct(u32) { + /// TSUS + TSUS: u32, + }), + /// Ethernet PTP time stamp low update register + PTPTSLUR: mmio.Mmio(packed struct(u32) { + /// TSUSS + TSUSS: u31, + /// TSUSS + TSUPNS: u1, + }), + /// Ethernet PTP time stamp addend register + PTPTSAR: mmio.Mmio(packed struct(u32) { + /// TSA + TSA: u32, + }), + /// Ethernet PTP target time high register + PTPTTHR: mmio.Mmio(packed struct(u32) { + /// 0 + TTSH: u32, + }), + /// Ethernet PTP target time low register + PTPTTLR: mmio.Mmio(packed struct(u32) { + /// TTSL + TTSL: u32, + }), + reserved40: [4]u8, + /// Ethernet PTP time stamp status register + PTPTSSR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding: u30, + }), + /// Ethernet PTP PPS control register + PTPPPSCR: mmio.Mmio(packed struct(u32) { + /// TSSO + TSSO: u1, + /// TSTTR + TSTTR: u1, + padding: u30, + }), + }; + + /// General-purpose-timers + pub const TIM11 = extern struct { + /// control register 1 + CR1: mmio.Mmio(packed struct(u32) { + /// Counter enable + CEN: u1, + /// Update disable + UDIS: u1, + /// Update request source + URS: u1, + reserved7: u4, + /// Auto-reload preload enable + ARPE: u1, + /// Clock division + CKD: u2, + padding: u22, + }), + reserved12: [8]u8, + /// DMA/Interrupt enable register + DIER: mmio.Mmio(packed struct(u32) { + /// Update interrupt enable + UIE: u1, + /// Capture/Compare 1 interrupt enable + CC1IE: u1, + padding: u30, + }), + /// status register + SR: mmio.Mmio(packed struct(u32) { + /// Update interrupt flag + UIF: u1, + /// Capture/compare 1 interrupt flag + CC1IF: u1, + reserved9: u7, + /// Capture/Compare 1 overcapture flag + CC1OF: u1, + padding: u22, + }), + /// event generation register + EGR: mmio.Mmio(packed struct(u32) { + /// Update generation + UG: u1, + /// Capture/compare 1 generation + CC1G: u1, + padding: u30, + }), + /// capture/compare mode register 1 (output mode) + CCMR1_Output: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 selection + CC1S: u2, + /// Output Compare 1 fast enable + OC1FE: u1, + /// Output Compare 1 preload enable + OC1PE: u1, + /// Output Compare 1 mode + OC1M: u3, + padding: u25, + }), + reserved32: [4]u8, + /// capture/compare enable register + CCER: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 output enable + CC1E: u1, + /// Capture/Compare 1 output Polarity + CC1P: u1, + reserved3: u1, + /// Capture/Compare 1 output Polarity + CC1NP: u1, + padding: u28, + }), + /// counter + CNT: mmio.Mmio(packed struct(u32) { + /// counter value + CNT: u16, + padding: u16, + }), + /// prescaler + PSC: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u16, + padding: u16, + }), + /// auto-reload register + ARR: mmio.Mmio(packed struct(u32) { + /// Auto-reload value + ARR: u16, + padding: u16, + }), + reserved52: [4]u8, + /// capture/compare register 1 + CCR1: mmio.Mmio(packed struct(u32) { + /// Capture/Compare 1 value + CCR1: u16, + padding: u16, + }), + reserved80: [24]u8, + /// option register + OR: mmio.Mmio(packed struct(u32) { + /// Input 1 remapping capability + RMP: u2, + padding: u30, + }), + }; +}; diff --git a/src/hals/stm32f103.zig b/src/hals/stm32f103.zig new file mode 100644 index 0000000..e69de29 diff --git a/src/hals/stm32f303.zig b/src/hals/stm32f303.zig new file mode 100644 index 0000000..272e8b1 --- /dev/null +++ b/src/hals/stm32f303.zig @@ -0,0 +1,602 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code currently assumes the STM32F303xB / STM32F303xC clock configuration. +//! TODO: Do something useful for other STM32f30x chips. +//! +//! Specifically, TIM6 is running on an 8 MHz clock, +//! HSI = 8 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 8 MHz. +//! And with the default APB1 prescaler = /2: +//! +//! ``` +//! RCC.CFGR.modify(.{ .PPRE1 = 4 }); +//! ``` +//! +//! results in PCLK1, +//! and the resulting implicit factor *2 for TIM2/3/4/6/7 +//! makes TIM6 run at 8MHz/2*2 = 8 MHz. +//! +//! The above default configuration makes U(S)ART2..5 +//! (which use PCLK1 without that implicit *2 factor) +//! run at 4 MHz by default. +//! +//! USART1 uses PCLK2, which uses the APB2 prescaler on HCLK, +//! default APB2 prescaler = /1: +//! +//! ``` +//! RCC.CFGR.modify(.{ .PPRE2 = 0 }); +//! ``` +//! +//! and therefore USART1 runs on 8 MHz. + +const std = @import("std"); +const runtime_safety = std.debug.runtime_safety; + +const micro = @import("microzig"); +const SPI1 = micro.peripherals.SPI1; +const RCC = micro.peripherals.RCC; +const USART1 = micro.peripherals.USART1; +const GPIOA = micro.peripherals.GPIOA; +const GPIOB = micro.peripherals.GPIOB; +const GPIOC = micro.peripherals.GPIOC; +const I2C1 = micro.peripherals.I2C1; + +pub const cpu = @import("cpu"); + +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + +// Default clock frequencies after reset, see top comment for calculation +pub const clock_frequencies = .{ + .cpu = 8_000_000, + .ahb = 8_000_000, + .apb1 = 8_000_000, + .apb2 = 8_000_000, +}; + +pub fn parse_pin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'H') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'H' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(micro.peripherals, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn set_output(comptime pin: type) void { + set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn set_input(comptime pin: type) void { + set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1); + set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + switch (state) { + .low => set_reg_field(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1), + .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; + +pub const uart = struct { + pub const DataBits = enum(u4) { + seven = 7, + eight = 8, + }; + + /// uses the values of USART_CR2.STOP + pub const StopBits = enum(u2) { + one = 0b00, + half = 0b01, + two = 0b10, + one_and_half = 0b11, + }; + + /// uses the values of USART_CR1.PS + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (!(index == 1)) @compileError("TODO: only USART1 is currently supported"); + if (pins.tx != null or pins.rx != null) + @compileError("TODO: custom pins are not currently supported"); + + return struct { + parity_read_mask: u8, + + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + // The following must all be written when the USART is disabled (UE=0). + if (USART1.CR1.read().UE == 1) + @panic("Trying to initialize USART1 while it is already enabled"); + // LATER: Alternatively, set UE=0 at this point? Then wait for something? + // Or add a destroy() function which disables the USART? + + // enable the USART1 clock + RCC.APB2ENR.modify(.{ .USART1EN = 1 }); + // enable GPIOC clock + RCC.AHBENR.modify(.{ .IOPCEN = 1 }); + // set PC4+PC5 to alternate function 7, USART1_TX + USART1_RX + GPIOC.MODER.modify(.{ .MODER4 = 0b10, .MODER5 = 0b10 }); + GPIOC.AFRL.modify(.{ .AFRL4 = 7, .AFRL5 = 7 }); + + // clear USART1 configuration to its default + USART1.CR1.raw = 0; + USART1.CR2.raw = 0; + USART1.CR3.raw = 0; + + // set word length + // Per the reference manual, M[1:0] means + // - 00: 8 bits (7 data + 1 parity, or 8 data), probably the chip default + // - 01: 9 bits (8 data + 1 parity) + // - 10: 7 bits (7 data) + // So M1==1 means "7-bit mode" (in which + // "the Smartcard mode, LIN master mode and Auto baud rate [...] are not supported"); + // and M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + const m1: u1 = if (config.data_bits == .seven and config.parity == null) 1 else 0; + const m0: u1 = if (config.data_bits == .eight and config.parity != null) 1 else 0; + // Note that .padding0 = bit 28 = .M1 (.svd file bug?), and .M == .M0. + USART1.CR1.modify(.{ .padding0 = m1, .M = m0 }); + + // set parity + if (config.parity) |parity| { + USART1.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); + } else USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default + + // set number of stop bits + USART1.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); + + // set the baud rate + // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency + // from the chip, which can be affected by how the board configures the chip. + // In our case, these are accidentally the same at chip reset, + // if the board doesn't configure e.g. an HSE external crystal. + // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) + // TODO: Do a rounding div, instead of a truncating div? + const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate)); + USART1.BRR.raw = usartdiv; + // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction, + // those seem to be for another chipset; .svd file bug? + // TODO: We assume the default OVER8=0 configuration above. + + // enable USART1, and its transmitter and receiver + USART1.CR1.modify(.{ .UE = 1 }); + USART1.CR1.modify(.{ .TE = 1 }); + USART1.CR1.modify(.{ .RE = 1 }); + + // For code simplicity, at cost of one or more register reads, + // we read back the actual configuration from the registers, + // instead of using the `config` values. + return read_from_registers(); + } + + pub fn get_or_init(config: micro.uart.Config) !Self { + if (USART1.CR1.read().UE == 1) { + // UART1 already enabled, don't reinitialize and disturb things; + // instead read and use the actual configuration. + return read_from_registers(); + } else return init(config); + } + + fn read_from_registers() Self { + const cr1 = USART1.CR1.read(); + // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, + // then we also mask away the 8th bit. + return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; + } + + pub fn can_write(self: Self) bool { + _ = self; + return switch (USART1.ISR.read().TXE) { + 1 => true, + 0 => false, + }; + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.can_write()) {} // Wait for Previous transmission + USART1.TDR.modify(ch); + } + + pub fn txflush(_: Self) void { + while (USART1.ISR.read().TC == 0) {} + } + + pub fn can_read(self: Self) bool { + _ = self; + return switch (USART1.ISR.read().RXNE) { + 1 => true, + 0 => false, + }; + } + + pub fn rx(self: Self) u8 { + while (!self.can_read()) {} // Wait till the data is received + const data_with_parity_bit: u9 = USART1.RDR.read().RDR; + return @intCast(u8, data_with_parity_bit & self.parity_read_mask); + } + }; +} + +const enable_stm32f303_debug = false; + +fn debug_print(comptime format: []const u8, args: anytype) void { + if (enable_stm32f303_debug) { + micro.debug.writer().print(format, args) catch {}; + } +} + +/// This implementation does not use AUTOEND=1 +pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { + if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported"); + if (pins.scl != null or pins.sda != null) + @compileError("TODO: custom pins are not currently supported"); + + return struct { + const Self = @This(); + + pub fn init(config: micro.i2c.Config) !Self { + // CONFIGURE I2C1 + // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA, + // if GPIO port B is configured for alternate function 4 for these PB pins. + + // 1. Enable the I2C CLOCK and GPIO CLOCK + RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); + RCC.AHBENR.modify(.{ .IOPBEN = 1 }); + debug_print("I2C1 configuration step 1 complete\r\n", .{}); + // 2. Configure the I2C PINs for ALternate Functions + // a) Select Alternate Function in MODER Register + GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 }); + // b) Select Open Drain Output + GPIOB.OTYPER.modify(.{ .OT6 = 1, .OT7 = 1 }); + // c) Select High SPEED for the PINs + GPIOB.OSPEEDR.modify(.{ .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); + // d) Select Pull-up for both the Pins + GPIOB.PUPDR.modify(.{ .PUPDR6 = 0b01, .PUPDR7 = 0b01 }); + // e) Configure the Alternate Function in AFR Register + GPIOB.AFRL.modify(.{ .AFRL6 = 4, .AFRL7 = 4 }); + debug_print("I2C1 configuration step 2 complete\r\n", .{}); + + // 3. Reset the I2C + I2C1.CR1.modify(.{ .PE = 0 }); + while (I2C1.CR1.read().PE == 1) {} + // DO NOT RCC.APB1RSTR.modify(.{ .I2C1RST = 1 }); + debug_print("I2C1 configuration step 3 complete\r\n", .{}); + + // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz + // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/ + // but copying an example from the reference manual, RM0316 section 28.4.9.) + if (config.target_speed != 100_000) @panic("TODO: Support speeds other than 100 kHz"); + I2C1.TIMINGR.modify(.{ + .PRESC = 1, + .SCLL = 0x13, + .SCLH = 0xF, + .SDADEL = 0x2, + .SCLDEL = 0x4, + }); + debug_print("I2C1 configuration steps 4-6 complete\r\n", .{}); + + // 7. Program the I2C_CR1 register to enable the peripheral + I2C1.CR1.modify(.{ .PE = 1 }); + debug_print("I2C1 configuration step 7 complete\r\n", .{}); + + return Self{}; + } + + pub const WriteState = struct { + address: u7, + buffer: [255]u8 = undefined, + buffer_size: u8 = 0, + + pub fn start(address: u7) !WriteState { + return WriteState{ .address = address }; + } + + pub fn write_all(self: *WriteState, bytes: []const u8) !void { + debug_print("I2C1 writeAll() with {d} byte(s); buffer={any}\r\n", .{ bytes.len, self.buffer[0..self.buffer_size] }); + + std.debug.assert(self.buffer_size < 255); + for (bytes) |b| { + self.buffer[self.buffer_size] = b; + self.buffer_size += 1; + if (self.buffer_size == 255) { + try self.send_buffer(1); + } + } + } + + fn send_buffer(self: *WriteState, reload: u1) !void { + debug_print("I2C1 sendBuffer() with {d} byte(s); RELOAD={d}; buffer={any}\r\n", .{ self.buffer_size, reload, self.buffer[0..self.buffer_size] }); + if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); + + std.debug.assert(reload == 0 or self.buffer_size == 255); // see TODOs below + + // As master, initiate write from address, 7 bit address + I2C1.CR2.modify(.{ + .ADD10 = 0, + .SADD1 = self.address, + .RD_WRN = 0, // write + .NBYTES = self.buffer_size, + .RELOAD = reload, + }); + if (reload == 0) { + I2C1.CR2.modify(.{ .START = 1 }); + } else { + // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, + // even though we make sure that we set NBYTES=255 per the docs. + } + for (self.buffer[0..self.buffer_size]) |b| { + // wait for empty transmit buffer + while (I2C1.ISR.read().TXE == 0) { + debug_print("I2C1 waiting for ready to send (TXE=0)\r\n", .{}); + } + debug_print("I2C1 ready to send (TXE=1)\r\n", .{}); + // Write data byte + I2C1.TXDR.modify(.{ .TXDATA = b }); + } + self.buffer_size = 0; + debug_print("I2C1 data written\r\n", .{}); + if (reload == 1) { + // TODO: The RELOAD=1 path is untested but doesn't seem to work yet, + // the following loop never seems to finish. + while (I2C1.ISR.read().TCR == 0) { + debug_print("I2C1 waiting transmit complete (TCR=0)\r\n", .{}); + } + debug_print("I2C1 transmit complete (TCR=1)\r\n", .{}); + } else { + while (I2C1.ISR.read().TC == 0) { + debug_print("I2C1 waiting for transmit complete (TC=0)\r\n", .{}); + } + debug_print("I2C1 transmit complete (TC=1)\r\n", .{}); + } + } + + pub fn stop(self: *WriteState) !void { + try self.send_buffer(0); + // Communication STOP + debug_print("I2C1 STOPping\r\n", .{}); + I2C1.CR2.modify(.{ .STOP = 1 }); + while (I2C1.ISR.read().BUSY == 1) {} + debug_print("I2C1 STOPped\r\n", .{}); + } + + pub fn restart_read(self: *WriteState) !ReadState { + try self.send_buffer(0); + return ReadState{ .address = self.address }; + } + pub fn restart_write(self: *WriteState) !WriteState { + try self.send_buffer(0); + return WriteState{ .address = self.address }; + } + }; + + pub const ReadState = struct { + address: u7, + read_allowed: if (runtime_safety) bool else void = if (runtime_safety) true else {}, + + pub fn start(address: u7) !ReadState { + return ReadState{ .address = address }; + } + + /// Fails with ReadError if incorrect number of bytes is received. + pub fn read_no_eof(self: *ReadState, buffer: []u8) !void { + if (runtime_safety and !self.read_allowed) @panic("second read call not allowed"); + std.debug.assert(buffer.len < 256); // TODO: use RELOAD to read more data + + // As master, initiate read from accelerometer, 7 bit address + I2C1.CR2.modify(.{ + .ADD10 = 0, + .SADD1 = self.address, + .RD_WRN = 1, // read + .NBYTES = @intCast(u8, buffer.len), + }); + debug_print("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address }); + + // Communication START + I2C1.CR2.modify(.{ .START = 1 }); + debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE}); + debug_print("I2C1 STARTed\r\n", .{}); + debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE}); + + if (runtime_safety) self.read_allowed = false; + + for (buffer) |_, i| { + // Wait for data to be received + while (I2C1.ISR.read().RXNE == 0) { + debug_print("I2C1 waiting for data (RXNE=0)\r\n", .{}); + } + debug_print("I2C1 data ready (RXNE=1)\r\n", .{}); + + // Read first data byte + buffer[i] = I2C1.RXDR.read().RXDATA; + } + debug_print("I2C1 data: {any}\r\n", .{buffer}); + } + + pub fn stop(_: *ReadState) !void { + // Communication STOP + I2C1.CR2.modify(.{ .STOP = 1 }); + while (I2C1.ISR.read().BUSY == 1) {} + debug_print("I2C1 STOPped\r\n", .{}); + } + + pub fn restart_read(self: *ReadState) !ReadState { + debug_print("I2C1 no action for restart\r\n", .{}); + return ReadState{ .address = self.address }; + } + pub fn restart_write(self: *ReadState) !WriteState { + debug_print("I2C1 no action for restart\r\n", .{}); + return WriteState{ .address = self.address }; + } + }; + }; +} + +/// An STM32F303 SPI bus +pub fn SpiBus(comptime index: usize) type { + if (!(index == 1)) @compileError("TODO: only SPI1 is currently supported"); + + return struct { + const Self = @This(); + + /// Initialize and enable the bus. + pub fn init(config: micro.spi.BusConfig) !Self { + _ = config; // unused for now + + // CONFIGURE SPI1 + // connected to APB2, MCU pins PA5 + PA7 + PA6 = SPC + SDI + SDO, + // if GPIO port A is configured for alternate function 5 for these PA pins. + + // Enable the GPIO CLOCK + RCC.AHBENR.modify(.{ .IOPAEN = 1 }); + + // Configure the I2C PINs for ALternate Functions + // - Select Alternate Function in MODER Register + GPIOA.MODER.modify(.{ .MODER5 = 0b10, .MODER6 = 0b10, .MODER7 = 0b10 }); + // - Select High SPEED for the PINs + GPIOA.OSPEEDR.modify(.{ .OSPEEDR5 = 0b11, .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 }); + // - Configure the Alternate Function in AFR Register + GPIOA.AFRL.modify(.{ .AFRL5 = 5, .AFRL6 = 5, .AFRL7 = 5 }); + + // Enable the SPI1 CLOCK + RCC.APB2ENR.modify(.{ .SPI1EN = 1 }); + + SPI1.CR1.modify(.{ + .MSTR = 1, + .SSM = 1, + .SSI = 1, + .RXONLY = 0, + .SPE = 1, + }); + // the following configuration is assumed in `transceiveByte()` + SPI1.CR2.raw = 0; + SPI1.CR2.modify(.{ + .DS = 0b0111, // 8-bit data frames, seems default via '0b0000 is interpreted as 0b0111' + .FRXTH = 1, // RXNE event after 1 byte received + }); + + return Self{}; + } + + /// Switch this SPI bus to the given device. + pub fn switch_to_device(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + + SPI1.CR1.modify(.{ + .CPOL = 1, // TODO: make configurable + .CPHA = 1, // TODO: make configurable + .BR = 0b111, // 1/256 the of PCLK TODO: make configurable + .LSBFIRST = 0, // MSB first TODO: make configurable + }); + gpio.set_output(cs_pin); + } + + /// Begin a transfer to the given device. (Assumes `switchToDevice()` was called.) + pub fn begin_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + gpio.write(cs_pin, .low); // select the given device, TODO: support inverse CS devices + debug_print("enabled SPI1\r\n", .{}); + } + + /// The basic operation in the current simplistic implementation: + /// send+receive a single byte. + /// Writing `null` writes an arbitrary byte (`undefined`), and + /// reading into `null` ignores the value received. + pub fn transceive_byte(_: Self, optional_write_byte: ?u8, optional_read_pointer: ?*u8) !void { + + // SPIx_DR's least significant byte is `@bitCast([dr_byte_size]u8, ...)[0]` + const dr_byte_size = @sizeOf(@TypeOf(SPI1.DR.raw)); + + // wait unril ready for write + while (SPI1.SR.read().TXE == 0) { + debug_print("SPI1 TXE == 0\r\n", .{}); + } + debug_print("SPI1 TXE == 1\r\n", .{}); + + // write + const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value + @bitCast([dr_byte_size]u8, SPI1.DR.*)[0] = write_byte; + debug_print("Sent: {X:2}.\r\n", .{write_byte}); + + // wait until read processed + while (SPI1.SR.read().RXNE == 0) { + debug_print("SPI1 RXNE == 0\r\n", .{}); + } + debug_print("SPI1 RXNE == 1\r\n", .{}); + + // read + var data_read = SPI1.DR.raw; + _ = SPI1.SR.read(); // clear overrun flag + const dr_lsb = @bitCast([dr_byte_size]u8, data_read)[0]; + debug_print("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read }); + if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb; + } + + /// Write all given bytes on the bus, not reading anything back. + pub fn write_all(self: Self, bytes: []const u8) !void { + for (bytes) |b| { + try self.transceive_byte(b, null); + } + } + + /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`). + pub fn read_into(self: Self, buffer: []u8) !void { + for (buffer) |_, i| { + try self.transceive_byte(null, &buffer[i]); + } + } + + pub fn end_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void { + _ = config; // for future use + // no delay should be needed here, since we know SPIx_SR's TXE is 1 + debug_print("(disabling SPI1)\r\n", .{}); + gpio.write(cs_pin, .high); // deselect the given device, TODO: support inverse CS devices + // HACK: wait long enough to make any device end an ongoing transfer + var i: u8 = 255; // with the default clock, this seems to delay ~185 microseconds + while (i > 0) : (i -= 1) { + asm volatile ("nop"); + } + } + }; +} diff --git a/src/hals/stm32f407.zig b/src/hals/stm32f407.zig new file mode 100644 index 0000000..6461bd8 --- /dev/null +++ b/src/hals/stm32f407.zig @@ -0,0 +1,623 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code currently assumes the STM32F405xx / STM32F407xx clock configuration. +//! TODO: Do something useful for other STM32F40x chips. +//! +//! Specifically, TIM6 is running on a 16 MHz clock, +//! HSI = 16 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 16 MHz. +//! And with the default APB1 prescaler = /1: +//! +//! ``` +//! RCC.CFGR.modify(.{ .PPRE1 = 0 }); +//! ``` +//! +//! results in PCLK1 = 16 MHz. +//! +//! The above default configuration makes U(S)ART2..5 +//! receive a 16 MHz clock by default. +//! +//! USART1 and USART6 use PCLK2, which uses the APB2 prescaler on HCLK, +//! default APB2 prescaler = /1: +//! +//! ``` +//! RCC.CFGR.modify(.{ .PPRE2 = 0 }); +//! ``` +//! +//! and therefore USART1 and USART6 receive a 16 MHz clock. +//! + +const std = @import("std"); +const micro = @import("microzig"); +const peripherals = micro.peripherals; +const RCC = peripherals.RCC; + +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + +// Default clock frequencies after reset, see top comment for calculation +pub const clock_frequencies = .{ + .cpu = 16_000_000, + .ahb = 16_000_000, + .apb1 = 16_000_000, + .apb2 = 16_000_000, +}; + +pub fn parse_pin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'I') + @compileError(invalid_format_msg); + + return struct { + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + /// 'A'...'I' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub const AlternateFunction = enum(u4) { + af0, + af1, + af2, + af3, + af4, + af5, + af6, + af7, + af8, + af9, + af10, + af11, + af12, + af13, + af14, + af15, + }; + + pub fn set_output(comptime pin: type) void { + set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn set_input(comptime pin: type) void { + set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn set_alternate_function(comptime pin: type, af: AlternateFunction) void { + set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10); + if (pin.pin_number < 8) { + set_reg_field(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @enumToInt(af)); + } else { + set_reg_field(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @enumToInt(af)); + } + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + switch (state) { + .low => set_reg_field(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), + .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; + +pub const uart = struct { + pub const DataBits = enum { + seven, + eight, + nine, + }; + + /// uses the values of USART_CR2.STOP + pub const StopBits = enum(u2) { + one = 0b00, + half = 0b01, + two = 0b10, + one_and_half = 0b11, + }; + + /// uses the values of USART_CR1.PS + pub const Parity = enum(u1) { + even = 0, + odd = 1, + }; + + const PinDirection = std.meta.FieldEnum(micro.uart.Pins); + + /// Checks if a pin is valid for a given uart index and direction + pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime direction: PinDirection) bool { + const pin_name = pin.name; + + return switch (direction) { + .tx => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PA9") or std.mem.eql(u8, pin_name, "PB6"), + 2 => std.mem.eql(u8, pin_name, "PA2") or std.mem.eql(u8, pin_name, "PD5"), + 3 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PC10") or std.mem.eql(u8, pin_name, "PD8"), + 4 => std.mem.eql(u8, pin_name, "PA0") or std.mem.eql(u8, pin_name, "PC10"), + 5 => std.mem.eql(u8, pin_name, "PC12"), + 6 => std.mem.eql(u8, pin_name, "PC6") or std.mem.eql(u8, pin_name, "PG14"), + else => unreachable, + }, + // Valid RX pins for the UARTs + .rx => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PA10") or std.mem.eql(u8, pin_name, "PB7"), + 2 => std.mem.eql(u8, pin_name, "PA3") or std.mem.eql(u8, pin_name, "PD6"), + 3 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PC11") or std.mem.eql(u8, pin_name, "PD9"), + 4 => std.mem.eql(u8, pin_name, "PA1") or std.mem.eql(u8, pin_name, "PC11"), + 5 => std.mem.eql(u8, pin_name, "PD2"), + 6 => std.mem.eql(u8, pin_name, "PC7") or std.mem.eql(u8, pin_name, "PG9"), + else => unreachable, + }, + }; + } +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (index < 1 or index > 6) @compileError("Valid USART index are 1..6"); + + const usart_name = std.fmt.comptimePrint("USART{d}", .{index}); + const tx_pin = + if (pins.tx) |tx| + if (uart.is_valid_pin(tx, index, .tx)) + tx + else + @compileError(std.fmt.comptimePrint("Tx pin {s} is not valid for UART{}", .{ tx.name, index })) + else switch (index) { + // Provide default tx pins if no pin is specified + 1 => micro.Pin("PA9"), + 2 => micro.Pin("PA2"), + 3 => micro.Pin("PB10"), + 4 => micro.Pin("PA0"), + 5 => micro.Pin("PC12"), + 6 => micro.Pin("PC6"), + else => unreachable, + }; + + const rx_pin = + if (pins.rx) |rx| + if (uart.is_valid_pin(rx, index, .rx)) + rx + else + @compileError(std.fmt.comptimePrint("Rx pin {s} is not valid for UART{}", .{ rx.name, index })) + else switch (index) { + // Provide default rx pins if no pin is specified + 1 => micro.Pin("PA10"), + 2 => micro.Pin("PA3"), + 3 => micro.Pin("PB11"), + 4 => micro.Pin("PA1"), + 5 => micro.Pin("PD2"), + 6 => micro.Pin("PC7"), + else => unreachable, + }; + + // USART1..3 are AF7, USART 4..6 are AF8 + const alternate_function = if (index <= 3) .af7 else .af8; + + const tx_gpio = micro.Gpio(tx_pin, .{ + .mode = .alternate_function, + .alternate_function = alternate_function, + }); + const rx_gpio = micro.Gpio(rx_pin, .{ + .mode = .alternate_function, + .alternate_function = alternate_function, + }); + + return struct { + parity_read_mask: u8, + + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + // The following must all be written when the USART is disabled (UE=0). + if (@field(peripherals, usart_name).CR1.read().UE == 1) + @panic("Trying to initialize " ++ usart_name ++ " while it is already enabled"); + // LATER: Alternatively, set UE=0 at this point? Then wait for something? + // Or add a destroy() function which disables the USART? + + // enable the USART clock + const clk_enable_reg = switch (index) { + 1, 6 => RCC.APB2ENR, + 2...5 => RCC.APB1ENR, + else => unreachable, + }; + set_reg_field(clk_enable_reg, usart_name ++ "EN", 1); + + tx_gpio.init(); + rx_gpio.init(); + + // clear USART configuration to its default + @field(peripherals, usart_name).CR1.raw = 0; + @field(peripherals, usart_name).CR2.raw = 0; + @field(peripherals, usart_name).CR3.raw = 0; + + // Return error for unsupported combinations + if (config.data_bits == .nine and config.parity != null) { + // TODO: should we consider this an unsupported word size or unsupported parity? + return error.UnsupportedWordSize; + } else if (config.data_bits == .seven and config.parity == null) { + // TODO: should we consider this an unsupported word size or unsupported parity? + return error.UnsupportedWordSize; + } + + // set word length + // Per the reference manual, M means + // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default + // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits + const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0; + @field(peripherals, usart_name).CR1.modify(.{ .M = m }); + + // set parity + if (config.parity) |parity| { + @field(peripherals, usart_name).CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) }); + } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default + + // set number of stop bits + @field(peripherals, usart_name).CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) }); + + // set the baud rate + // Despite the reference manual talking about fractional calculation and other buzzwords, + // it is actually just a simple divider. Just ignore DIV_Mantissa and DIV_Fraction and + // set the result of the division as the lower 16 bits of BRR. + // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling). + // TODO: Do some checks to see if the baud rate is too high (or perhaps too low) + // TODO: Do a rounding div, instead of a truncating div? + const clocks = micro.clock.get(); + const bus_frequency = switch (index) { + 1, 6 => clocks.apb2, + 2...5 => clocks.apb1, + else => unreachable, + }; + const usartdiv = @intCast(u16, @divTrunc(bus_frequency, config.baud_rate)); + @field(peripherals, usart_name).BRR.raw = usartdiv; + + // enable USART, and its transmitter and receiver + @field(peripherals, usart_name).CR1.modify(.{ .UE = 1 }); + @field(peripherals, usart_name).CR1.modify(.{ .TE = 1 }); + @field(peripherals, usart_name).CR1.modify(.{ .RE = 1 }); + + // For code simplicity, at cost of one or more register reads, + // we read back the actual configuration from the registers, + // instead of using the `config` values. + return read_from_registers(); + } + + pub fn get_or_init(config: micro.uart.Config) !Self { + if (@field(peripherals, usart_name).CR1.read().UE == 1) { + // UART1 already enabled, don't reinitialize and disturb things; + // instead read and use the actual configuration. + return read_from_registers(); + } else return init(config); + } + + fn read_from_registers() Self { + const cr1 = @field(peripherals, usart_name).CR1.read(); + // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'. + // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit, + // then we also mask away the 8th bit. + return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF }; + } + + pub fn can_write(self: Self) bool { + _ = self; + return switch (@field(peripherals, usart_name).SR.read().TXE) { + 1 => true, + 0 => false, + }; + } + + pub fn tx(self: Self, ch: u8) void { + while (!self.can_write()) {} // Wait for Previous transmission + @field(peripherals, usart_name).DR.modify(ch); + } + + pub fn txflush(_: Self) void { + while (@field(peripherals, usart_name).SR.read().TC == 0) {} + } + + pub fn can_read(self: Self) bool { + _ = self; + return switch (@field(peripherals, usart_name).SR.read().RXNE) { + 1 => true, + 0 => false, + }; + } + + pub fn rx(self: Self) u8 { + while (!self.can_read()) {} // Wait till the data is received + const data_with_parity_bit: u9 = @field(peripherals, usart_name).DR.read(); + return @intCast(u8, data_with_parity_bit & self.parity_read_mask); + } + }; +} + +pub const i2c = struct { + const PinLine = std.meta.FieldEnum(micro.i2c.Pins); + + /// Checks if a pin is valid for a given i2c index and line + pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime line: PinLine) bool { + const pin_name = pin.name; + + return switch (line) { + .scl => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PB6") or std.mem.eql(u8, pin_name, "PB8"), + 2 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PF1") or std.mem.eql(u8, pin_name, "PH4"), + 3 => std.mem.eql(u8, pin_name, "PA8") or std.mem.eql(u8, pin_name, "PH7"), + else => unreachable, + }, + // Valid RX pins for the UARTs + .sda => switch (index) { + 1 => std.mem.eql(u8, pin_name, "PB7") or std.mem.eql(u8, pin_name, "PB9"), + 2 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PF0") or std.mem.eql(u8, pin_name, "PH5"), + 3 => std.mem.eql(u8, pin_name, "PC9") or std.mem.eql(u8, pin_name, "PH8"), + else => unreachable, + }, + }; + } +}; + +pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type { + if (index < 1 or index > 3) @compileError("Valid I2C index are 1..3"); + + const i2c_name = std.fmt.comptimePrint("I2C{d}", .{index}); + const scl_pin = + if (pins.scl) |scl| + if (uart.is_valid_pin(scl, index, .scl)) + scl + else + @compileError(std.fmt.comptimePrint("SCL pin {s} is not valid for I2C{}", .{ scl.name, index })) + else switch (index) { + // Provide default scl pins if no pin is specified + 1 => micro.Pin("PB6"), + 2 => micro.Pin("PB10"), + 3 => micro.Pin("PA8"), + else => unreachable, + }; + + const sda_pin = + if (pins.sda) |sda| + if (uart.is_valid_pin(sda, index, .sda)) + sda + else + @compileError(std.fmt.comptimePrint("SDA pin {s} is not valid for UART{}", .{ sda.name, index })) + else switch (index) { + // Provide default sda pins if no pin is specified + 1 => micro.Pin("PB7"), + 2 => micro.Pin("PB11"), + 3 => micro.Pin("PC9"), + else => unreachable, + }; + + const scl_gpio = micro.Gpio(scl_pin, .{ + .mode = .alternate_function, + .alternate_function = .af4, + }); + const sda_gpio = micro.Gpio(sda_pin, .{ + .mode = .alternate_function, + .alternate_function = .af4, + }); + + // Base field of the specific I2C peripheral + const i2c_base = @field(peripherals, i2c_name); + + return struct { + const Self = @This(); + + pub fn init(config: micro.i2c.Config) !Self { + // Configure I2C + + // 1. Enable the I2C CLOCK and GPIO CLOCK + RCC.APB1ENR.modify(.{ .I2C1EN = 1 }); + RCC.AHB1ENR.modify(.{ .GPIOBEN = 1 }); + + // 2. Configure the I2C PINs + // This takes care of setting them alternate function mode with the correct AF + scl_gpio.init(); + sda_gpio.init(); + + // TODO: the stuff below will probably use the microzig gpio API in the future + const scl = scl_pin.source_pin; + const sda = sda_pin.source_pin; + // Select Open Drain Output + set_reg_field(@field(scl.gpio_port, "OTYPER"), "OT" ++ scl.suffix, 1); + set_reg_field(@field(sda.gpio_port, "OTYPER"), "OT" ++ sda.suffix, 1); + // Select High Speed + set_reg_field(@field(scl.gpio_port, "OSPEEDR"), "OSPEEDR" ++ scl.suffix, 0b10); + set_reg_field(@field(sda.gpio_port, "OSPEEDR"), "OSPEEDR" ++ sda.suffix, 0b10); + // Activate Pull-up + set_reg_field(@field(scl.gpio_port, "PUPDR"), "PUPDR" ++ scl.suffix, 0b01); + set_reg_field(@field(sda.gpio_port, "PUPDR"), "PUPDR" ++ sda.suffix, 0b01); + + // 3. Reset the I2C + i2c_base.CR1.modify(.{ .PE = 0 }); + while (i2c_base.CR1.read().PE == 1) {} + + // 4. Configure I2C timing + const bus_frequency_hz = micro.clock.get().apb1; + const bus_frequency_mhz: u6 = @intCast(u6, @divExact(bus_frequency_hz, 1_000_000)); + + if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) { + return error.InvalidBusFrequency; + } + + // .FREQ is set to the bus frequency in Mhz + i2c_base.CR2.modify(.{ .FREQ = bus_frequency_mhz }); + + switch (config.target_speed) { + 10_000...100_000 => { + // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed. + const ccr = @intCast(u12, @divFloor(bus_frequency_hz, config.target_speed * 2)); + i2c_base.CCR.modify(.{ .CCR = ccr }); + // Trise is bus frequency in Mhz + 1 + i2c_base.TRISE.modify(bus_frequency_mhz + 1); + }, + 100_001...400_000 => { + // TODO: handle fast mode + return error.InvalidSpeed; + }, + else => return error.InvalidSpeed, + } + + // 5. Program the I2C_CR1 register to enable the peripheral + i2c_base.CR1.modify(.{ .PE = 1 }); + + return Self{}; + } + + pub const WriteState = struct { + address: u7, + buffer: [255]u8 = undefined, + buffer_size: u8 = 0, + + pub fn start(address: u7) !WriteState { + return WriteState{ .address = address }; + } + + pub fn write_all(self: *WriteState, bytes: []const u8) !void { + std.debug.assert(self.buffer_size < 255); + for (bytes) |b| { + self.buffer[self.buffer_size] = b; + self.buffer_size += 1; + if (self.buffer_size == 255) { + try self.send_buffer(); + } + } + } + + fn send_buffer(self: *WriteState) !void { + if (self.buffer_size == 0) @panic("write of 0 bytes not supported"); + + // Wait for the bus to be free + while (i2c_base.SR2.read().BUSY == 1) {} + + // Send start + i2c_base.CR1.modify(.{ .START = 1 }); + + // Wait for the end of the start condition, master mode selected, and BUSY bit set + while ((i2c_base.SR1.read().SB == 0 or + i2c_base.SR2.read().MSL == 0 or + i2c_base.SR2.read().BUSY == 0)) + {} + + // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation + i2c_base.DR.modify(@intCast(u8, self.address) << 1); + + // Wait for address confirmation + while (i2c_base.SR1.read().ADDR == 0) {} + + // Read SR2 to clear address condition + _ = i2c_base.SR2.read(); + + for (self.buffer[0..self.buffer_size]) |b| { + // Write data byte + i2c_base.DR.modify(b); + // Wait for transfer finished + while (i2c_base.SR1.read().BTF == 0) {} + } + self.buffer_size = 0; + } + + pub fn stop(self: *WriteState) !void { + try self.send_buffer(); + // Communication STOP + i2c_base.CR1.modify(.{ .STOP = 1 }); + while (i2c_base.SR2.read().BUSY == 1) {} + } + + pub fn restart_read(self: *WriteState) !ReadState { + try self.send_buffer(); + return ReadState{ .address = self.address }; + } + pub fn restart_write(self: *WriteState) !WriteState { + try self.send_buffer(); + return WriteState{ .address = self.address }; + } + }; + + pub const ReadState = struct { + address: u7, + + pub fn start(address: u7) !ReadState { + return ReadState{ .address = address }; + } + + /// Fails with ReadError if incorrect number of bytes is received. + pub fn read_no_eof(self: *ReadState, buffer: []u8) !void { + std.debug.assert(buffer.len < 256); + + // Send start and enable ACK + i2c_base.CR1.modify(.{ .START = 1, .ACK = 1 }); + + // Wait for the end of the start condition, master mode selected, and BUSY bit set + while ((i2c_base.SR1.read().SB == 0 or + i2c_base.SR2.read().MSL == 0 or + i2c_base.SR2.read().BUSY == 0)) + {} + + // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation + i2c_base.DR.modify((@intCast(u8, self.address) << 1) | 1); + + // Wait for address confirmation + while (i2c_base.SR1.read().ADDR == 0) {} + + // Read SR2 to clear address condition + _ = i2c_base.SR2.read(); + + for (buffer) |_, i| { + if (i == buffer.len - 1) { + // Disable ACK + i2c_base.CR1.modify(.{ .ACK = 0 }); + } + + // Wait for data to be received + while (i2c_base.SR1.read().RxNE == 0) {} + + // Read data byte + buffer[i] = i2c_base.DR.read(); + } + } + + pub fn stop(_: *ReadState) !void { + // Communication STOP + i2c_base.CR1.modify(.{ .STOP = 1 }); + while (i2c_base.SR2.read().BUSY == 1) {} + } + + pub fn restart_read(self: *ReadState) !ReadState { + return ReadState{ .address = self.address }; + } + pub fn restart_write(self: *ReadState) !WriteState { + return WriteState{ .address = self.address }; + } + }; + }; +} diff --git a/src/hals/stm32f429.zig b/src/hals/stm32f429.zig new file mode 100644 index 0000000..3aed963 --- /dev/null +++ b/src/hals/stm32f429.zig @@ -0,0 +1,92 @@ +//! For now we keep all clock settings on the chip defaults. +//! This code should work with all the STM32F42xx line +//! +//! Specifically, TIM6 is running on a 16 MHz clock, +//! HSI = 16 MHz is the SYSCLK after reset +//! default AHB prescaler = /1 (= values 0..7): +//! +//! ``` +//! RCC.CFGR.modify(.{ .HPRE = 0 }); +//! ``` +//! +//! so also HCLK = 16 MHz. +//! And with the default APB1 prescaler = /1: +//! +//! ``` +//! RCC.CFGR.modify(.{ .PPRE1 = 0 }); +//! ``` +//! +//! results in PCLK1 = 16 MHz. +//! +//! TODO: add more clock calculations when adding Uart + +const std = @import("std"); +const micro = @import("microzig"); +const peripherals = micro.peripherals; +const RCC = peripherals.RCC; + +pub const clock = struct { + pub const Domain = enum { + cpu, + ahb, + apb1, + apb2, + }; +}; + +// Default clock frequencies after reset, see top comment for calculation +pub const clock_frequencies = .{ + .cpu = 16_000_000, + .ahb = 16_000_000, + .apb1 = 16_000_000, + .apb2 = 16_000_000, +}; + +pub fn parsePin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'K') + @compileError(invalid_format_msg); + + const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg); + + return struct { + /// 'A'...'K' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name); + const suffix = std.fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn setOutput(comptime pin: type) void { + setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01); + } + + pub fn setInput(comptime pin: type) void { + setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1); + setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00); + } + + pub fn read(comptime pin: type) micro.gpio.State { + const idr_reg = pin.gpio_port.IDR; + const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()? + return @intToEnum(micro.gpio.State, reg_value); + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + switch (state) { + .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1), + .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1), + } + } +}; diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig new file mode 100644 index 0000000..5258ce3 --- /dev/null +++ b/test/programs/minimal.zig @@ -0,0 +1,5 @@ +const micro = @import("microzig"); + +pub fn main() void { + // This function will contain the application logic. +} diff --git a/tests/stm32f103.robot b/test/stm32f103.robot similarity index 100% rename from tests/stm32f103.robot rename to test/stm32f103.robot