From 4d3d5cce0ddc5d13549df67b59597ceadcb5ffa0 Mon Sep 17 00:00:00 2001
From: Jacob Young <jacobly0@users.noreply.github.com>
Date: Wed, 10 Jul 2024 00:49:43 -0400
Subject: [PATCH] enable atsamd51j19 fpu (#196)

---
 bsp/microchip/atsam/build.zig |  2 +-
 core/build.zig                | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/bsp/microchip/atsam/build.zig b/bsp/microchip/atsam/build.zig
index ec0e8fa..8c73936 100644
--- a/bsp/microchip/atsam/build.zig
+++ b/bsp/microchip/atsam/build.zig
@@ -17,7 +17,7 @@ pub const chips = struct {
         .chip = .{
             .name = "ATSAMD51J19A",
             .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A",
-            .cpu = MicroZig.cpus.cortex_m4,
+            .cpu = MicroZig.cpus.cortex_m4f,
             .register_definition = .{
                 .atdf = .{ .cwd_relative = build_root ++ "/src/chips/ATSAMD51J19A.atdf" },
             },
diff --git a/core/build.zig b/core/build.zig
index 17d0bed..bbe5a65 100644
--- a/core/build.zig
+++ b/core/build.zig
@@ -71,6 +71,18 @@ pub const cpus = struct {
         },
     };
 
+    pub const cortex_m4f = MicroZig.Cpu{
+        .name = "ARM Cortex-M4F",
+        .root_source_file = .{ .path = build_root ++ "/src/cpus/cortex_m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
+            .cpu_features_add = std.Target.arm.featureSet(&.{.vfp4d16sp}),
+            .os_tag = .freestanding,
+            .abi = .eabihf,
+        },
+    };
+
     pub const riscv32_imac = MicroZig.Cpu{
         .name = "RISC-V 32-bit",
         .root_source_file = .{ .cwd_relative = build_root ++ "/src/cpus/riscv32.zig" },