From 29221c27f54ba440e632620ffd3241d74a1ff3b2 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 17:10:04 -0500 Subject: [PATCH 01/20] Initial commit --- .buildkite/pipeline.yml | 4 ++++ .gitignore | 2 ++ .gitmodules | 3 +++ LICENSE | 19 +++++++++++++++++++ README.adoc | 6 ++++++ build.zig | 35 +++++++++++++++++++++++++++++++++++ deps/microzig | 1 + src/boards.zig | 6 ++++++ src/chips.zig | 6 ++++++ test/programs/minimal.zig | 5 +++++ 10 files changed, 87 insertions(+) create mode 100644 .buildkite/pipeline.yml create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 LICENSE create mode 100644 README.adoc create mode 100644 build.zig create mode 160000 deps/microzig create mode 100644 src/boards.zig create mode 100644 src/chips.zig create mode 100644 test/programs/minimal.zig diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml new file mode 100644 index 0000000..7767bbb --- /dev/null +++ b/.buildkite/pipeline.yml @@ -0,0 +1,4 @@ +steps: + - group: Build + steps: + - command: zig build diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4c82b07 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-cache +zig-out diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..32e895c --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "deps/microzig"] + path = deps/microzig + url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..c1cc5ec --- /dev/null +++ b/LICENSE @@ -0,0 +1,19 @@ +Copyright (c) 2022 + +This software is provided 'as-is', without any express or implied warranty. In +no event will the authors be held liable for any damages arising from the use +of this software. + +Permission is granted to anyone to use this software for any purpose, including +commercial applications, and to alter it and redistribute it freely, subject to +the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim +that you wrote the original software. If you use this software in a product, an +acknowledgment in the product documentation would be appreciated but is not +required. + +2. Altered source versions must be plainly marked as such, and must not be +misrepresented as being the original software. + +3. This notice may not be removed or altered from any source distribution. diff --git a/README.adoc b/README.adoc new file mode 100644 index 0000000..46ca057 --- /dev/null +++ b/README.adoc @@ -0,0 +1,6 @@ += Hardware Support Package Template + +1. Update LICENSE file +2. Update `microzig` submodule under `deps/` +3. Add chips/boards/hals +4. Set up buildkite pipeline diff --git a/build.zig b/build.zig new file mode 100644 index 0000000..3b787fe --- /dev/null +++ b/build.zig @@ -0,0 +1,35 @@ +const std = @import("std"); +const microzig = @import("deps/microzig/src/main.zig"); +const boards = @import("src/boards.zig"); +const chips = @import("src/chips.zig"); + +pub fn build(b: *std.build.Builder) void { + const optimize = b.standardOptimizeOption(.{}); + inline for (@typeInfo(boards).Struct.decls) |decl| { + if (!decl.is_pub) + continue; + + const exe = microzig.addEmbeddedExecutable( + b, + @field(boards, decl.name).name ++ ".minimal", + "test/programs/minimal.zig", + .{ .board = @field(boards, decl.name) }, + .{ .optimize = optimize }, + ); + exe.install(); + } + + inline for (@typeInfo(chips).Struct.decls) |decl| { + if (!decl.is_pub) + continue; + + const exe = microzig.addEmbeddedExecutable( + b, + @field(chips, decl.name).name ++ ".minimal", + "test/programs/minimal.zig", + .{ .chip = @field(chips, decl.name) }, + .{ .optimize = optimize }, + ); + exe.install(); + } +} diff --git a/deps/microzig b/deps/microzig new file mode 160000 index 0000000..97ca549 --- /dev/null +++ b/deps/microzig @@ -0,0 +1 @@ +Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 diff --git a/src/boards.zig b/src/boards.zig new file mode 100644 index 0000000..2cb647a --- /dev/null +++ b/src/boards.zig @@ -0,0 +1,6 @@ +const std = @import("std"); +const microzig = @import("../deps/microzig/src/main.zig"); + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse "."; +} diff --git a/src/chips.zig b/src/chips.zig new file mode 100644 index 0000000..2cb647a --- /dev/null +++ b/src/chips.zig @@ -0,0 +1,6 @@ +const std = @import("std"); +const microzig = @import("../deps/microzig/src/main.zig"); + +fn root_dir() []const u8 { + return std.fs.path.dirname(@src().file) orelse "."; +} diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig new file mode 100644 index 0000000..5258ce3 --- /dev/null +++ b/test/programs/minimal.zig @@ -0,0 +1,5 @@ +const micro = @import("microzig"); + +pub fn main() void { + // This function will contain the application logic. +} From 56e3d88bc0a0ebda41588f906a25437592d7f3a9 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 18 Feb 2023 18:06:45 -0500 Subject: [PATCH 02/20] add chips and board (#1) * add chips and board * fix up hal --- LICENSE | 2 +- README.adoc | 7 +- src/boards.zig | 9 +- src/boards/longan_nano.zig | 112 + src/chips.zig | 24 +- src/chips/GD32VF103.json | 32957 +++++++++++++++++++++++++++++++++++ src/chips/GD32VF103.zig | 12849 ++++++++++++++ src/hals/GD32VF103.zig | 112 + 8 files changed, 46062 insertions(+), 10 deletions(-) create mode 100644 src/boards/longan_nano.zig create mode 100644 src/chips/GD32VF103.json create mode 100644 src/chips/GD32VF103.zig create mode 100644 src/hals/GD32VF103.zig diff --git a/LICENSE b/LICENSE index c1cc5ec..bcb425d 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2022 +Copyright (c) 2022 Zig Embedded Group Contributors This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use diff --git a/README.adoc b/README.adoc index 46ca057..f23b1bf 100644 --- a/README.adoc +++ b/README.adoc @@ -1,6 +1 @@ -= Hardware Support Package Template - -1. Update LICENSE file -2. Update `microzig` submodule under `deps/` -3. Add chips/boards/hals -4. Set up buildkite pipeline += GigaDevice GD32 Hardware Support Package diff --git a/src/boards.zig b/src/boards.zig index 2cb647a..d9a73b5 100644 --- a/src/boards.zig +++ b/src/boards.zig @@ -1,6 +1,13 @@ const std = @import("std"); -const microzig = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/src/main.zig"); +const chips = @import("chips.zig"); fn root_dir() []const u8 { return std.fs.path.dirname(@src().file) orelse "."; } + +pub const longan_nano = micro.Board{ + .name = "Longan Nano", + .source = .{ .path = root_dir() ++ "/boards/longan_nano.zig" }, + .chip = chips.gd32vf103xb, +}; diff --git a/src/boards/longan_nano.zig b/src/boards/longan_nano.zig new file mode 100644 index 0000000..e042be1 --- /dev/null +++ b/src/boards/longan_nano.zig @@ -0,0 +1,112 @@ +pub const chip = @import("chip"); +pub const micro = @import("microzig"); + +pub const cpu_frequency = 8_000_000; // 8 MHz + +pub const pin_map = .{ + + // Port A + .PA0 = "PA0", + .PA1 = "PA1", + .PA2 = "PA2", + .PA3 = "PA3", + .PA4 = "PA4", + .PA5 = "PA5", + .PA6 = "PA6", + .PA7 = "PA7", + .PA8 = "PA8", + .PA9 = "PA9", + .PA10 = "PA10", + .PA11 = "PA11", + .PA12 = "PA12", + .PA13 = "PA13", + + // Port B + .PB0 = "PB0", + .PB1 = "PB1", + .PB2 = "PB2", + .PB3 = "PB3", + .PB4 = "PB4", + .PB5 = "PB5", + .PB6 = "PB6", + .PB7 = "PB7", + .PB8 = "PB8", + .PB9 = "PB9", + .PB10 = "PB10", + .PB11 = "PB11", + .PB12 = "PB12", + .PB13 = "PB13", + .PB14 = "PB14", + .PB15 = "PB15", + + // Port C + .PC0 = "PC0", + .PC1 = "PC1", + .PC2 = "PC2", + .PC3 = "PC3", + .PC4 = "PC4", + .PC5 = "PC5", + .PC6 = "PC6", + .PC7 = "PC7", + .PC8 = "PC8", + .PC9 = "PC9", + .PC10 = "PC10", + .PC11 = "PC11", + .PC12 = "PC12", + .PC13 = "PC13", + .PC14 = "PC14", + .PC15 = "PC15", + + // Port D + .PD0 = "PD0", + .PD1 = "PD1", + .PD2 = "PD2", + .PD3 = "PD3", + .PD4 = "PD4", + .PD5 = "PD5", + .PD6 = "PD6", + .PD7 = "PD7", + .PD8 = "PD8", + .PD9 = "PD9", + .PD10 = "PD10", + .PD11 = "PD11", + .PD12 = "PD12", + .PD13 = "PD13", + .PD14 = "PD14", + .PD15 = "PD15", + + // Port E + .PE0 = "PE0", + .PE1 = "PE1", + .PE2 = "PE2", + .PE3 = "PE3", + .PE4 = "PE4", + .PE5 = "PE5", + .PE6 = "PE6", + .PE7 = "PE7", + .PE8 = "PE8", + .PE9 = "PE9", + .PE10 = "PE10", + .PE11 = "PE11", + .PE12 = "PE12", + .PE13 = "PE13", + .PE14 = "PE14", + .PE15 = "PE15", + + // Colors LED + // LCD_COLOR_WHITE 0xFFFF + // LCD_COLOR_BLACK 0x0000 + // LCD_COLOR_GREY 0xF7DE + // LCD_COLOR_BLUE 0x001F + // LCD_COLOR_BLUE2 0x051F + // LCD_COLOR_RED 0xF800 + // LCD_COLOR_MAGENTA 0xF81F + // LCD_COLOR_GREEN 0x07E0 + // LCD_COLOR_CYAN 0x7FFF + // LCD_COLOR_YELLOW 0xFFE0 +}; + +pub fn debugWrite(string: []const u8) void { + _ = string; + // TODO: implement +} diff --git a/src/chips.zig b/src/chips.zig index 2cb647a..ac1beef 100644 --- a/src/chips.zig +++ b/src/chips.zig @@ -1,6 +1,26 @@ const std = @import("std"); -const microzig = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/src/main.zig"); +const Chip = micro.Chip; +const MemoryRegion = micro.MemoryRegion; fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse "."; + return std.fs.path.dirname(@src().file) orelse unreachable; } + +pub const gd32vf103xb = Chip.from_standard_paths(root_dir(), .{ + .name = "GD32VF103", + .cpu = micro.cpus.riscv32_imac, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, + }, +}); + +pub const gd32vf103x8 = Chip.from_standard_paths(root_dir(), .{ + .name = "GD32VF103", + .cpu = micro.cpus.riscv32_imac, + .memory_regions = &.{ + MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + }, +}); diff --git a/src/chips/GD32VF103.json b/src/chips/GD32VF103.json new file mode 100644 index 0000000..7b949cf --- /dev/null +++ b/src/chips/GD32VF103.json @@ -0,0 +1,32957 @@ +{ + "version": "0.1.0", + "types": { + "peripherals": { + "SCS": { + "description": "System Control Space", + "children": { + "register_groups": { + "SysTick": { + "description": "System Tick Timer", + "children": { + "registers": { + "CTRL": { + "description": "SysTick Control and Status Register", + "offset": 0, + "size": 32, + "children": { + "fields": { + "ENABLE": { + "offset": 0, + "size": 1 + }, + "TICKINT": { + "offset": 1, + "size": 1 + }, + "CLKSOURCE": { + "offset": 2, + "size": 1 + }, + "COUNTFLAG": { + "offset": 16, + "size": 1 + } + } + } + }, + "LOAD": { + "description": "SysTick Reload Value Register", + "offset": 4, + "size": 32, + "children": { + "fields": { + "RELOAD": { + "offset": 0, + "size": 24 + } + } + } + }, + "VAL": { + "description": "SysTick Current Value Register", + "offset": 8, + "size": 32, + "children": { + "fields": { + "CURRENT": { + "offset": 0, + "size": 24 + } + } + } + }, + "CALIB": { + "description": "SysTick Calibration Register", + "offset": 12, + "size": 32, + "access": "read-only", + "children": { + "fields": { + "TENMS": { + "offset": 0, + "size": 24 + }, + "SKEW": { + "offset": 30, + "size": 1 + }, + "NOREF": { + "offset": 31, + "size": 1 + } + } + } + } + } + } + } + } + } + }, + "ADC0": { + "description": "Analog to digital converter", + "children": { + "registers": { + "STAT": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STRC": { + "description": "Start flag of regular channel group", + "offset": 4, + "size": 1 + }, + "STIC": { + "description": "Start flag of inserted channel group", + "offset": 3, + "size": 1 + }, + "EOIC": { + "description": "End of inserted group conversion flag", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "End of group conversion flag", + "offset": 1, + "size": 1 + }, + "WDE": { + "description": "Analog watchdog event flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL0": { + "description": "control register 0", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWDEN": { + "description": "Regular channel analog watchdog enable", + "offset": 23, + "size": 1 + }, + "IWDEN": { + "description": "Inserted channel analog watchdog \n\t enable", + "offset": 22, + "size": 1 + }, + "SYNCM": { + "description": "sync mode selection", + "offset": 16, + "size": 4 + }, + "DISNUM": { + "description": "Number of conversions in \n\t discontinuous mode", + "offset": 13, + "size": 3 + }, + "DISIC": { + "description": "Discontinuous mode on \n\t inserted channels", + "offset": 12, + "size": 1 + }, + "DISRC": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "ICA": { + "description": "Inserted channel group convert \n\t automatically", + "offset": 10, + "size": 1 + }, + "WDSC": { + "description": "When in scan mode, analog watchdog\n\t is effective on a single channel", + "offset": 9, + "size": 1 + }, + "SM": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "EOICIE": { + "description": "Interrupt enable for EOIC", + "offset": 7, + "size": 1 + }, + "WDEIE": { + "description": "Interrupt enable for WDE", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "WDCHSEL": { + "description": "Analog watchdog channel select", + "offset": 0, + "size": 5 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TSVREN": { + "description": "Channel 16 and 17 enable of ADC0", + "offset": 23, + "size": 1 + }, + "SWRCST": { + "description": "Start on regular channel", + "offset": 22, + "size": 1 + }, + "SWICST": { + "description": "Start on inserted channel", + "offset": 21, + "size": 1 + }, + "ETERC": { + "description": "External trigger enable for regular channel", + "offset": 20, + "size": 1 + }, + "ETSRC": { + "description": "External trigger select for regular channel", + "offset": 17, + "size": 3 + }, + "ETEIC": { + "description": "External trigger select for inserted channel", + "offset": 15, + "size": 1 + }, + "ETSIC": { + "description": "External trigger select for inserted channel", + "offset": 12, + "size": 3 + }, + "DAL": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "DMA": { + "description": "DMA request enable", + "offset": 8, + "size": 1 + }, + "RSTCLB": { + "description": "Reset calibration", + "offset": 3, + "size": 1 + }, + "CLB": { + "description": "ADC calibration", + "offset": 2, + "size": 1 + }, + "CTN": { + "description": "Continuous mode", + "offset": 1, + "size": 1 + }, + "ADCON": { + "description": "ADC on", + "offset": 0, + "size": 1 + } + } + } + }, + "SAMPT0": { + "description": "Sample time register 0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPT10": { + "description": "Channel 10 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SPT11": { + "description": "Channel 11 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SPT12": { + "description": "Channel 12 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SPT13": { + "description": "Channel 13 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SPT14": { + "description": "Channel 14 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SPT15": { + "description": "Channel 15 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SPT16": { + "description": "Channel 16 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SPT17": { + "description": "Channel 17 sample time\n selection", + "offset": 21, + "size": 3 + } + } + } + }, + "SAMPT1": { + "description": "Sample time register 1", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPT0": { + "description": "Channel 0 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SPT1": { + "description": "Channel 1 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SPT2": { + "description": "Channel 2 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SPT3": { + "description": "Channel 3 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SPT4": { + "description": "Channel 4 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SPT5": { + "description": "Channel 5 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SPT6": { + "description": "Channel 6 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SPT7": { + "description": "Channel 7 sample time\n selection", + "offset": 21, + "size": 3 + }, + "SPT8": { + "description": "Channel 8 sample time\n selection", + "offset": 24, + "size": 3 + }, + "SPT9": { + "description": "Channel 9 sample time\n selection", + "offset": 27, + "size": 3 + } + } + } + }, + "IOFF0": { + "description": "Inserted channel data offset register\n 0", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 0", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF1": { + "description": "Inserted channel data offset register\n 1", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 1", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF2": { + "description": "Inserted channel data offset register\n 2", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 2", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF3": { + "description": "Inserted channel data offset register\n 3", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 3", + "offset": 0, + "size": 12 + } + } + } + }, + "WDHT": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDHT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "WDLT": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDLT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "RSQ0": { + "description": "regular sequence register 0", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Regular channel group\n length", + "offset": 20, + "size": 4 + }, + "RSQ15": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ14": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ13": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ12": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "RSQ1": { + "description": "regular sequence register 1", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSQ11": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "RSQ10": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "RSQ9": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ8": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ7": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ6": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "RSQ2": { + "description": "regular sequence register 2", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSQ5": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "RSQ4": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "RSQ3": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ2": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ1": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ0": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "ISQ": { + "description": "Inserted sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IL": { + "description": "Inserted channel group length", + "offset": 20, + "size": 2 + }, + "ISQ3": { + "description": "4th conversion in inserted\n sequence", + "offset": 15, + "size": 5 + }, + "ISQ2": { + "description": "3rd conversion in inserted\n sequence", + "offset": 10, + "size": 5 + }, + "ISQ1": { + "description": "2nd conversion in inserted\n sequence", + "offset": 5, + "size": 5 + }, + "ISQ0": { + "description": "1st conversion in inserted\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "IDATA0": { + "description": "Inserted data register 0", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA1": { + "description": "Inserted data register 1", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA2": { + "description": "Inserted data register 2", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA3": { + "description": "Inserted data register 3", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "RDATA": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ADC1RDTR": { + "description": "ADC regular channel data", + "offset": 16, + "size": 16 + }, + "RDATA": { + "description": "Regular channel data", + "offset": 0, + "size": 16 + } + } + } + }, + "OVSAMPCTL": { + "description": "Oversample control register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DRES": { + "description": "ADC resolution", + "offset": 12, + "size": 2 + }, + "TOVS": { + "description": "Triggered Oversampling", + "offset": 9, + "size": 1 + }, + "OVSS": { + "description": "Oversampling shift", + "offset": 5, + "size": 4 + }, + "OVSR": { + "description": "Oversampling ratio", + "offset": 2, + "size": 3 + }, + "OVSEN": { + "description": "Oversampler Enable", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "ADC1": { + "description": "Analog to digital converter", + "children": { + "registers": { + "STAT": { + "description": "status register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STRC": { + "description": "Start flag of regular channel group", + "offset": 4, + "size": 1 + }, + "STIC": { + "description": "Start flag of inserted channel group", + "offset": 3, + "size": 1 + }, + "EOIC": { + "description": "End of inserted group conversion flag", + "offset": 2, + "size": 1 + }, + "EOC": { + "description": "End of group conversion flag", + "offset": 1, + "size": 1 + }, + "WDE": { + "description": "Analog watchdog event flag", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL0": { + "description": "control register 0", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWDEN": { + "description": "Regular channel analog watchdog \n\t enable", + "offset": 23, + "size": 1 + }, + "IWDEN": { + "description": "Inserted channel analog watchdog \n\t enable", + "offset": 22, + "size": 1 + }, + "DISNUM": { + "description": "Number of conversions in \n\t discontinuous mode", + "offset": 13, + "size": 3 + }, + "DISIC": { + "description": "Discontinuous mode on \n\t inserted channels", + "offset": 12, + "size": 1 + }, + "DISRC": { + "description": "Discontinuous mode on regular\n channels", + "offset": 11, + "size": 1 + }, + "ICA": { + "description": "Inserted channel group convert \n\t automatically", + "offset": 10, + "size": 1 + }, + "WDSC": { + "description": "When in scan mode, analog watchdog\n\t is effective on a single channel", + "offset": 9, + "size": 1 + }, + "SM": { + "description": "Scan mode", + "offset": 8, + "size": 1 + }, + "EOICIE": { + "description": "Interrupt enable for EOIC", + "offset": 7, + "size": 1 + }, + "WDEIE": { + "description": "Interrupt enable for WDE", + "offset": 6, + "size": 1 + }, + "EOCIE": { + "description": "Interrupt enable for EOC", + "offset": 5, + "size": 1 + }, + "WDCHSEL": { + "description": "Analog watchdog channel select", + "offset": 0, + "size": 5 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWRCST": { + "description": "Start on regular channel", + "offset": 22, + "size": 1 + }, + "SWICST": { + "description": "Start on inserted channel", + "offset": 21, + "size": 1 + }, + "ETERC": { + "description": "External trigger enable for regular channel", + "offset": 20, + "size": 1 + }, + "ETSRC": { + "description": "External trigger select for regular channel", + "offset": 17, + "size": 3 + }, + "ETEIC": { + "description": "External trigger enable for inserted channel", + "offset": 15, + "size": 1 + }, + "ETSIC": { + "description": "External trigger select for inserted channel", + "offset": 12, + "size": 3 + }, + "DAL": { + "description": "Data alignment", + "offset": 11, + "size": 1 + }, + "DMA": { + "description": "DMA request enable", + "offset": 8, + "size": 1 + }, + "RSTCLB": { + "description": "Reset calibration", + "offset": 3, + "size": 1 + }, + "CLB": { + "description": "ADC calibration", + "offset": 2, + "size": 1 + }, + "CTN": { + "description": "Continuous mode", + "offset": 1, + "size": 1 + }, + "ADCON": { + "description": "ADC on", + "offset": 0, + "size": 1 + } + } + } + }, + "SAMPT0": { + "description": "Sample time register 0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPT10": { + "description": "Channel 10 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SPT11": { + "description": "Channel 11 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SPT12": { + "description": "Channel 12 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SPT13": { + "description": "Channel 13 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SPT14": { + "description": "Channel 14 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SPT15": { + "description": "Channel 15 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SPT16": { + "description": "Channel 16 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SPT17": { + "description": "Channel 17 sample time\n selection", + "offset": 21, + "size": 3 + } + } + } + }, + "SAMPT1": { + "description": "Sample time register 1", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPT0": { + "description": "Channel 0 sample time\n selection", + "offset": 0, + "size": 3 + }, + "SPT1": { + "description": "Channel 1 sample time\n selection", + "offset": 3, + "size": 3 + }, + "SPT2": { + "description": "Channel 2 sample time\n selection", + "offset": 6, + "size": 3 + }, + "SPT3": { + "description": "Channel 3 sample time\n selection", + "offset": 9, + "size": 3 + }, + "SPT4": { + "description": "Channel 4 sample time\n selection", + "offset": 12, + "size": 3 + }, + "SPT5": { + "description": "Channel 5 sample time\n selection", + "offset": 15, + "size": 3 + }, + "SPT6": { + "description": "Channel 6 sample time\n selection", + "offset": 18, + "size": 3 + }, + "SPT7": { + "description": "Channel 7 sample time\n selection", + "offset": 21, + "size": 3 + }, + "SPT8": { + "description": "Channel 8 sample time\n selection", + "offset": 24, + "size": 3 + }, + "SPT9": { + "description": "Channel 9 sample time\n selection", + "offset": 27, + "size": 3 + } + } + } + }, + "IOFF0": { + "description": "Inserted channel data offset register\n 0", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 0", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF1": { + "description": "Inserted channel data offset register\n 1", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 1", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF2": { + "description": "Inserted channel data offset register\n 2", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 2", + "offset": 0, + "size": 12 + } + } + } + }, + "IOFF3": { + "description": "Inserted channel data offset register\n 3", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IOFF": { + "description": "Data offset for inserted channel\n 3", + "offset": 0, + "size": 12 + } + } + } + }, + "WDHT": { + "description": "watchdog higher threshold\n register", + "offset": 36, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDHT": { + "description": "Analog watchdog higher\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "WDLT": { + "description": "watchdog lower threshold\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDLT": { + "description": "Analog watchdog lower\n threshold", + "offset": 0, + "size": 12 + } + } + } + }, + "RSQ0": { + "description": "regular sequence register 0", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RL": { + "description": "Regular channel group\n length", + "offset": 20, + "size": 4 + }, + "RSQ15": { + "description": "16th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ14": { + "description": "15th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ13": { + "description": "14th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ12": { + "description": "13th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "RSQ1": { + "description": "regular sequence register 1", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSQ11": { + "description": "12th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "RSQ10": { + "description": "11th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "RSQ9": { + "description": "10th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ8": { + "description": "9th conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ7": { + "description": "8th conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ6": { + "description": "7th conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "RSQ2": { + "description": "regular sequence register 2", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RSQ5": { + "description": "6th conversion in regular\n sequence", + "offset": 25, + "size": 5 + }, + "RSQ4": { + "description": "5th conversion in regular\n sequence", + "offset": 20, + "size": 5 + }, + "RSQ3": { + "description": "4th conversion in regular\n sequence", + "offset": 15, + "size": 5 + }, + "RSQ2": { + "description": "3rd conversion in regular\n sequence", + "offset": 10, + "size": 5 + }, + "RSQ1": { + "description": "2nd conversion in regular\n sequence", + "offset": 5, + "size": 5 + }, + "RSQ0": { + "description": "1st conversion in regular\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "ISQ": { + "description": "Inserted sequence register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IL": { + "description": "Inserted channel group length", + "offset": 20, + "size": 2 + }, + "ISQ3": { + "description": "4th conversion in inserted\n sequence", + "offset": 15, + "size": 5 + }, + "ISQ2": { + "description": "3rd conversion in inserted\n sequence", + "offset": 10, + "size": 5 + }, + "ISQ1": { + "description": "2nd conversion in inserted\n sequence", + "offset": 5, + "size": 5 + }, + "ISQ0": { + "description": "1st conversion in inserted\n sequence", + "offset": 0, + "size": 5 + } + } + } + }, + "IDATA0": { + "description": "Inserted data register 0", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA1": { + "description": "Inserted data register 1", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA2": { + "description": "Inserted data register 2", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "IDATA3": { + "description": "Inserted data register 3", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IDATAn": { + "description": "Inserted number n conversion data", + "offset": 0, + "size": 16 + } + } + } + }, + "RDATA": { + "description": "regular data register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RDATA": { + "description": "Regular channel data", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "AFIO": { + "description": "Alternate-function I/Os", + "children": { + "registers": { + "EC": { + "description": "Event control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EOE": { + "description": "Event output enable", + "offset": 7, + "size": 1 + }, + "PORT": { + "description": "Event output port selection", + "offset": 4, + "size": 3 + }, + "PIN": { + "description": "Event output pin selection", + "offset": 0, + "size": 4 + } + } + } + }, + "PCF0": { + "description": "AFIO port configuration register 0", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMER1ITI1_REMAP": { + "description": "TIMER1 internal trigger 1 remapping", + "offset": 29, + "size": 1 + }, + "SPI2_REMAP": { + "description": " SPI2/I2S2 remapping", + "offset": 28, + "size": 1 + }, + "SWJ_CFG": { + "description": "Serial wire JTAG configuration", + "offset": 24, + "size": 3 + }, + "CAN1_REMAP": { + "description": "CAN1 I/O remapping", + "offset": 22, + "size": 1 + }, + "TIMER4CH3_IREMAP": { + "description": "TIMER4 channel3 internal remapping", + "offset": 16, + "size": 1 + }, + "PD01_REMAP": { + "description": "Port D0/Port D1 mapping on OSC_IN/OSC_OUT", + "offset": 15, + "size": 1 + }, + "CAN0_REMAP": { + "description": "CAN0 alternate interface remapping", + "offset": 13, + "size": 2 + }, + "TIMER3_REMAP": { + "description": "TIMER3 remapping", + "offset": 12, + "size": 1 + }, + "TIMER2_REMAP": { + "description": "TIMER2 remapping", + "offset": 10, + "size": 2 + }, + "TIMER1_REMAP": { + "description": "TIMER1 remapping", + "offset": 8, + "size": 2 + }, + "TIMER0_REMAP": { + "description": "TIMER0 remapping", + "offset": 6, + "size": 2 + }, + "USART2_REMAP": { + "description": "USART2 remapping", + "offset": 4, + "size": 2 + }, + "USART1_REMAP": { + "description": "USART1 remapping", + "offset": 3, + "size": 1 + }, + "USART0_REMAP": { + "description": "USART0 remapping", + "offset": 2, + "size": 1 + }, + "I2C0_REMAP": { + "description": "I2C0 remapping", + "offset": 1, + "size": 1 + }, + "SPI0_REMAP": { + "description": "SPI0 remapping", + "offset": 0, + "size": 1 + } + } + } + }, + "EXTISS0": { + "description": "EXTI sources selection register 0", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI3_SS": { + "description": "EXTI 3 sources selection", + "offset": 12, + "size": 4 + }, + "EXTI2_SS": { + "description": "EXTI 2 sources selection", + "offset": 8, + "size": 4 + }, + "EXTI1_SS": { + "description": "EXTI 1 sources selection", + "offset": 4, + "size": 4 + }, + "EXTI0_SS": { + "description": "EXTI 0 sources selection", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTISS1": { + "description": "EXTI sources selection register 1", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI7_SS": { + "description": "EXTI 7 sources selection", + "offset": 12, + "size": 4 + }, + "EXTI6_SS": { + "description": "EXTI 6 sources selection", + "offset": 8, + "size": 4 + }, + "EXTI5_SS": { + "description": "EXTI 5 sources selection", + "offset": 4, + "size": 4 + }, + "EXTI4_SS": { + "description": "EXTI 4 sources selection", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTISS2": { + "description": "EXTI sources selection register 2", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI11_SS": { + "description": "EXTI 11 sources selection", + "offset": 12, + "size": 4 + }, + "EXTI10_SS": { + "description": "EXTI 10 sources selection", + "offset": 8, + "size": 4 + }, + "EXTI9_SS": { + "description": "EXTI 9 sources selection", + "offset": 4, + "size": 4 + }, + "EXTI8_SS": { + "description": "EXTI 8 sources selection", + "offset": 0, + "size": 4 + } + } + } + }, + "EXTISS3": { + "description": "EXTI sources selection register 3", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXTI15_SS": { + "description": "EXTI 15 sources selection", + "offset": 12, + "size": 4 + }, + "EXTI14_SS": { + "description": "EXTI 14 sources selection", + "offset": 8, + "size": 4 + }, + "EXTI13_SS": { + "description": "EXTI 13 sources selection", + "offset": 4, + "size": 4 + }, + "EXTI12_SS": { + "description": "EXTI 12 sources selection", + "offset": 0, + "size": 4 + } + } + } + }, + "PCF1": { + "description": "AFIO port configuration register 1", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EXMC_NADV": { + "description": "EXMC_NADV connect/disconnect", + "offset": 10, + "size": 1 + } + } + } + } + } + } + }, + "BKP": { + "description": "Backup registers", + "children": { + "registers": { + "DATA0": { + "description": "Backup data register 0", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA1": { + "description": "Backup data register 1", + "offset": 8, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA2": { + "description": "Backup data register 2", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA3": { + "description": "Backup data register 3", + "offset": 16, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA4": { + "description": "Backup data register 4", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA5": { + "description": "Backup data register 5", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA6": { + "description": "Backup data register 6", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA7": { + "description": "Backup data register 7", + "offset": 32, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA8": { + "description": "Backup data register 8", + "offset": 36, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA9": { + "description": "Backup data register 9", + "offset": 40, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA10": { + "description": "Backup data register 10", + "offset": 64, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA11": { + "description": "Backup data register 11", + "offset": 68, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA12": { + "description": "Backup data register 12", + "offset": 72, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA13": { + "description": "Backup data register 13", + "offset": 76, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA14": { + "description": "Backup data register 14", + "offset": 80, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA15": { + "description": "Backup data register 15", + "offset": 84, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA16": { + "description": "Backup data register 16", + "offset": 88, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA17": { + "description": "Backup data register 17", + "offset": 92, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA18": { + "description": "Backup data register 18", + "offset": 96, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA19": { + "description": "Backup data register 19", + "offset": 100, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA20": { + "description": "Backup data register 20", + "offset": 104, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA21": { + "description": "Backup data register 21", + "offset": 108, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA22": { + "description": "Backup data register 22", + "offset": 112, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA23": { + "description": "Backup data register 23", + "offset": 116, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA24": { + "description": "Backup data register 24", + "offset": 120, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA25": { + "description": "Backup data register 25", + "offset": 124, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA26": { + "description": "Backup data register 26", + "offset": 128, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA27": { + "description": "Backup data register 27", + "offset": 132, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA28": { + "description": "Backup data register 28", + "offset": 136, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA29": { + "description": "Backup data register 29", + "offset": 140, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA30": { + "description": "Backup data register 30", + "offset": 144, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA31": { + "description": "Backup data register 31", + "offset": 148, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA32": { + "description": "Backup data register 32", + "offset": 152, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA33": { + "description": "Backup data register 33", + "offset": 156, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA34": { + "description": "Backup data register 34", + "offset": 160, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA35": { + "description": "Backup data register 35", + "offset": 164, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA36": { + "description": "Backup data register 36", + "offset": 168, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA37": { + "description": "Backup data register 37", + "offset": 172, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA38": { + "description": "Backup data register 38", + "offset": 176, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA39": { + "description": "Backup data register 39", + "offset": 180, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA40": { + "description": "Backup data register 40", + "offset": 184, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "DATA41": { + "description": "Backup data register 41", + "offset": 188, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Backup data", + "offset": 0, + "size": 16 + } + } + } + }, + "OCTL": { + "description": "RTC signal output control register", + "offset": 44, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ROSEL": { + "description": "RTC output selection", + "offset": 9, + "size": 1 + }, + "ASOEN": { + "description": "RTC alarm or second signal output enable", + "offset": 8, + "size": 1 + }, + "COEN": { + "description": "RTC clock calibration output enable", + "offset": 7, + "size": 1 + }, + "RCCV": { + "description": "RTC clock calibration value", + "offset": 0, + "size": 7 + } + } + } + }, + "TPCTL": { + "description": "Tamper pin control register", + "offset": 48, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TPAL": { + "description": "TAMPER pin active level", + "offset": 1, + "size": 1 + }, + "TPEN": { + "description": "TAMPER detection enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TPCS": { + "description": "Tamper control and status register", + "offset": 52, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIF": { + "description": "Tamper interrupt flag", + "offset": 9, + "size": 1 + }, + "TEF": { + "description": "Tamper event flag", + "offset": 8, + "size": 1 + }, + "TPIE": { + "description": "Tamper interrupt enable", + "offset": 2, + "size": 1 + }, + "TIR": { + "description": "Tamper interrupt reset", + "offset": 1, + "size": 1 + }, + "TER": { + "description": "Tamper event reset", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "CAN0": { + "description": "Controller area network", + "children": { + "registers": { + "CTL": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 65538, + "reset_mask": 4294967295, + "children": { + "fields": { + "DFZ": { + "description": "Debug freeze", + "offset": 16, + "size": 1 + }, + "SWRST": { + "description": "Software reset", + "offset": 15, + "size": 1 + }, + "TTC": { + "description": "Time-triggered communication", + "offset": 7, + "size": 1 + }, + "ABOR": { + "description": "Automatic bus-off recovery", + "offset": 6, + "size": 1 + }, + "AWU": { + "description": "Automatic wakeup", + "offset": 5, + "size": 1 + }, + "ARD": { + "description": "Automatic retransmission disable", + "offset": 4, + "size": 1 + }, + "RFOD": { + "description": "Receive FIFO overwrite disable", + "offset": 3, + "size": 1 + }, + "TFO": { + "description": "Transmit FIFO order", + "offset": 2, + "size": 1 + }, + "SLPWMOD": { + "description": "Sleep working mode", + "offset": 1, + "size": 1 + }, + "IWMOD": { + "description": "Initial working mode", + "offset": 0, + "size": 1 + } + } + } + }, + "STAT": { + "description": "Status register", + "offset": 4, + "size": 32, + "reset_value": 3074, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXL": { + "description": "RX level", + "offset": 11, + "size": 1, + "access": "read-only" + }, + "LASTRX": { + "description": "Last sample value of RX pin", + "offset": 10, + "size": 1, + "access": "read-only" + }, + "RS": { + "description": "Receiving state", + "offset": 9, + "size": 1, + "access": "read-only" + }, + "TS": { + "description": "Transmitting state", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "SLPIF": { + "description": "Status change interrupt flag of sleep \n\t working mode entering", + "offset": 4, + "size": 1 + }, + "WUIF": { + "description": "Status change interrupt flag of wakeup \n\t from sleep working mode", + "offset": 3, + "size": 1 + }, + "ERRIF": { + "description": "Error interrupt flag", + "offset": 2, + "size": 1 + }, + "SLPWS": { + "description": "Sleep working state", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "IWS": { + "description": "Initial working state", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "TSTAT": { + "description": "Transmit status register", + "offset": 8, + "size": 32, + "reset_value": 469762048, + "reset_mask": 4294967295, + "children": { + "fields": { + "TMLS2": { + "description": "Transmit mailbox 2 last sending \n\t in transmit FIFO", + "offset": 31, + "size": 1, + "access": "read-only" + }, + "TMLS1": { + "description": "Transmit mailbox 1 last sending \n\t in transmit FIFO", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "TMLS0": { + "description": "Transmit mailbox 0 last sending \n\t in transmit FIFO", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "TME2": { + "description": "Transmit mailbox 2 empty", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "TME1": { + "description": "Transmit mailbox 1 empty", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "TME0": { + "description": "Transmit mailbox 0 empty", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "NUM": { + "description": "number of the transmit FIFO mailbox in \n\t which the frame will be transmitted if at least one mailbox is empty", + "offset": 24, + "size": 2, + "access": "read-only" + }, + "MST2": { + "description": "Mailbox 2 stop transmitting", + "offset": 23, + "size": 1 + }, + "MTE2": { + "description": "Mailbox 2 transmit error", + "offset": 19, + "size": 1 + }, + "MAL2": { + "description": "Mailbox 2 arbitration lost", + "offset": 18, + "size": 1 + }, + "MTFNERR2": { + "description": "Mailbox 2 transmit finished and no error", + "offset": 17, + "size": 1 + }, + "MTF2": { + "description": "Mailbox 2 transmit finished", + "offset": 16, + "size": 1 + }, + "MST1": { + "description": "Mailbox 1 stop transmitting", + "offset": 15, + "size": 1 + }, + "MTE1": { + "description": "Mailbox 1 transmit error", + "offset": 11, + "size": 1 + }, + "MAL1": { + "description": "Mailbox 1 arbitration lost", + "offset": 10, + "size": 1 + }, + "MTFNERR1": { + "description": "Mailbox 1 transmit finished and no error", + "offset": 9, + "size": 1 + }, + "MTF1": { + "description": "Mailbox 1 transmit finished", + "offset": 8, + "size": 1 + }, + "MST0": { + "description": "Mailbox 0 stop transmitting", + "offset": 7, + "size": 1 + }, + "MTE0": { + "description": "Mailbox 0 transmit error", + "offset": 3, + "size": 1 + }, + "MAL0": { + "description": "Mailbox 0 arbitration lost", + "offset": 2, + "size": 1 + }, + "MTFNERR0": { + "description": "Mailbox 0 transmit finished and no error", + "offset": 1, + "size": 1 + }, + "MTF0": { + "description": "Mailbox 0 transmit finished", + "offset": 0, + "size": 1 + } + } + } + }, + "RFIFO0": { + "description": "Receive message FIFO0 register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFD0": { + "description": "Receive FIFO0 dequeue", + "offset": 5, + "size": 1 + }, + "RFO0": { + "description": "Receive FIFO0 overfull", + "offset": 4, + "size": 1 + }, + "RFF0": { + "description": "Receive FIFO0 full", + "offset": 3, + "size": 1 + }, + "RFL0": { + "description": "Receive FIFO0 length", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "RFIFO1": { + "description": "Receive message FIFO1 register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RFD1": { + "description": "Receive FIFO1 dequeue", + "offset": 5, + "size": 1 + }, + "RFO1": { + "description": "Receive FIFO1 overfull", + "offset": 4, + "size": 1 + }, + "RFF1": { + "description": "Receive FIFO1 full", + "offset": 3, + "size": 1 + }, + "RFL1": { + "description": "Receive FIFO1 length", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "INTEN": { + "description": "Interrupt enable register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLPWIE": { + "description": "Sleep working interrupt enable", + "offset": 17, + "size": 1 + }, + "WIE": { + "description": "Wakeup interrupt enable", + "offset": 16, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 15, + "size": 1 + }, + "ERRNIE": { + "description": "Error number interrupt enable", + "offset": 11, + "size": 1 + }, + "BOIE": { + "description": "Bus-off interrupt enable", + "offset": 10, + "size": 1 + }, + "PERRIE": { + "description": "Passive error interrupt enable", + "offset": 9, + "size": 1 + }, + "WERRIE": { + "description": "Warning error interrupt enable", + "offset": 8, + "size": 1 + }, + "RFOIE1": { + "description": "Receive FIFO1 overfull interrupt enable", + "offset": 6, + "size": 1 + }, + "RFFIE1": { + "description": "Receive FIFO1 full interrupt enable", + "offset": 5, + "size": 1 + }, + "RFNEIE1": { + "description": "Receive FIFO1 not empty interrupt enable", + "offset": 4, + "size": 1 + }, + "RFOIE0": { + "description": "Receive FIFO0 overfull interrupt enable", + "offset": 3, + "size": 1 + }, + "RFFIE0": { + "description": "Receive FIFO0 full interrupt enable", + "offset": 2, + "size": 1 + }, + "RFNEIE0": { + "description": "Receive FIFO0 not empty interrupt enable", + "offset": 1, + "size": 1 + }, + "TMEIE": { + "description": "Transmit mailbox empty interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "ERR": { + "description": "Error register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RECNT": { + "description": "Receive Error Count defined \n\t by the CAN standard", + "offset": 24, + "size": 8, + "access": "read-only" + }, + "TECNT": { + "description": "Transmit Error Count defined \n\t by the CAN standard", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "ERRN": { + "description": "Error number", + "offset": 4, + "size": 3 + }, + "BOERR": { + "description": "Bus-off error", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "PERR": { + "description": "Passive error", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "WERR": { + "description": "Warning error", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "BT": { + "description": "Bit timing register", + "offset": 28, + "size": 32, + "reset_value": 19070976, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCMOD": { + "description": "Silent communication mode", + "offset": 31, + "size": 1 + }, + "LCMOD": { + "description": "Loopback communication mode", + "offset": 30, + "size": 1 + }, + "SJW": { + "description": "Resynchronization jump width", + "offset": 24, + "size": 2 + }, + "BS2": { + "description": "Bit segment 2", + "offset": 20, + "size": 3 + }, + "BS1": { + "description": "Bit segment 1", + "offset": 16, + "size": 4 + }, + "BAUDPSC": { + "description": "Baud rate prescaler", + "offset": 0, + "size": 10 + } + } + } + }, + "TMI0": { + "description": "Transmit mailbox identifier register 0", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SFID_EFID": { + "description": "The frame identifier", + "offset": 21, + "size": 11 + }, + "EFID": { + "description": "The frame identifier", + "offset": 3, + "size": 18 + }, + "FF": { + "description": "Frame format", + "offset": 2, + "size": 1 + }, + "FT": { + "description": "Frame type", + "offset": 1, + "size": 1 + }, + "TEN": { + "description": "Transmit enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TMP0": { + "description": "Transmit mailbox property register 0", + "offset": 388, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "Time stamp", + "offset": 16, + "size": 16 + }, + "TSEN": { + "description": "Time stamp enable", + "offset": 8, + "size": 1 + }, + "DLENC": { + "description": "Data length code", + "offset": 0, + "size": 4 + } + } + } + }, + "TMDATA00": { + "description": "Transmit mailbox data0 register", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "DB2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "DB1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "DB0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + }, + "TMDATA10": { + "description": "Transmit mailbox data1 register", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + }, + "DB6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "DB5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "DB4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + } + } + } + }, + "TMI1": { + "description": "Transmit mailbox identifier register 1", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SFID_EFID": { + "description": "The frame identifier", + "offset": 21, + "size": 11 + }, + "EFID": { + "description": "The frame identifier", + "offset": 3, + "size": 18 + }, + "FF": { + "description": "Frame format", + "offset": 2, + "size": 1 + }, + "FT": { + "description": "Frame type", + "offset": 1, + "size": 1 + }, + "TEN": { + "description": "Transmit enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TMP1": { + "description": "Transmit mailbox property register 1", + "offset": 404, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "Time stamp", + "offset": 16, + "size": 16 + }, + "TSEN": { + "description": "Time stamp enable", + "offset": 8, + "size": 1 + }, + "DLENC": { + "description": "Data length code", + "offset": 0, + "size": 4 + } + } + } + }, + "TMDATA01": { + "description": "Transmit mailbox data0 register", + "offset": 408, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "DB2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "DB1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "DB0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + }, + "TMDATA11": { + "description": "Transmit mailbox data1 register", + "offset": 412, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + }, + "DB6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "DB5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "DB4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + } + } + } + }, + "TMI2": { + "description": "Transmit mailbox identifier register 2", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SFID_EFID": { + "description": "The frame identifier", + "offset": 21, + "size": 11 + }, + "EFID": { + "description": "The frame identifier", + "offset": 3, + "size": 18 + }, + "FF": { + "description": "Frame format", + "offset": 2, + "size": 1 + }, + "FT": { + "description": "Frame type", + "offset": 1, + "size": 1 + }, + "TEN": { + "description": "Transmit enable", + "offset": 0, + "size": 1 + } + } + } + }, + "TMP2": { + "description": "Transmit mailbox property register 2", + "offset": 420, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TS": { + "description": "Time stamp", + "offset": 16, + "size": 16 + }, + "TSEN": { + "description": "Time stamp enable", + "offset": 8, + "size": 1 + }, + "DLENC": { + "description": "Data length code", + "offset": 0, + "size": 4 + } + } + } + }, + "TMDATA02": { + "description": "Transmit mailbox data0 register", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "DB2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "DB1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "DB0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + }, + "TMDATA12": { + "description": "Transmit mailbox data1 register", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DB7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + }, + "DB6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "DB5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "DB4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + } + } + } + }, + "RFIFOMI0": { + "description": "Receive FIFO mailbox identifier register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SFID_EFID": { + "description": "The frame identifier", + "offset": 21, + "size": 11 + }, + "EFID": { + "description": "The frame identifier", + "offset": 3, + "size": 18 + }, + "FF": { + "description": "Frame format", + "offset": 2, + "size": 1 + }, + "FT": { + "description": "Frame type", + "offset": 1, + "size": 1 + } + } + } + }, + "RFIFOMP0": { + "description": "Receive FIFO0 mailbox property register", + "offset": 436, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TS": { + "description": "Time stamp", + "offset": 16, + "size": 16 + }, + "FI": { + "description": "Filtering index", + "offset": 8, + "size": 8 + }, + "DLENC": { + "description": "Data length code", + "offset": 0, + "size": 4 + } + } + } + }, + "RFIFOMDATA00": { + "description": "Receive FIFO0 mailbox data0 register", + "offset": 440, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DB3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "DB2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "DB1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "DB0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + }, + "RFIFOMDATA10": { + "description": "Receive FIFO0 mailbox data1 register", + "offset": 444, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DB7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + }, + "DB6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "DB5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "DB4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + } + } + } + }, + "RFIFOMI1": { + "description": "Receive FIFO1 mailbox identifier register", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SFID_EFID": { + "description": "The frame identifier", + "offset": 21, + "size": 11 + }, + "EFID": { + "description": "The frame identifier", + "offset": 3, + "size": 18 + }, + "FF": { + "description": "Frame format", + "offset": 2, + "size": 1 + }, + "FT": { + "description": "Frame type", + "offset": 1, + "size": 1 + } + } + } + }, + "RFIFOMP1": { + "description": "Receive FIFO1 mailbox property register", + "offset": 452, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TS": { + "description": "Time stamp", + "offset": 16, + "size": 16 + }, + "FI": { + "description": "Filtering index", + "offset": 8, + "size": 8 + }, + "DLENC": { + "description": "Data length code", + "offset": 0, + "size": 4 + } + } + } + }, + "RFIFOMDATA01": { + "description": "Receive FIFO1 mailbox data0 register", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DB3": { + "description": "Data byte 3", + "offset": 24, + "size": 8 + }, + "DB2": { + "description": "Data byte 2", + "offset": 16, + "size": 8 + }, + "DB1": { + "description": "Data byte 1", + "offset": 8, + "size": 8 + }, + "DB0": { + "description": "Data byte 0", + "offset": 0, + "size": 8 + } + } + } + }, + "RFIFOMDATA11": { + "description": "Receive FIFO1 mailbox data1 register", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DB7": { + "description": "Data byte 7", + "offset": 24, + "size": 8 + }, + "DB6": { + "description": "Data byte 6", + "offset": 16, + "size": 8 + }, + "DB5": { + "description": "Data byte 5", + "offset": 8, + "size": 8 + }, + "DB4": { + "description": "Data byte 4", + "offset": 0, + "size": 8 + } + } + } + }, + "FCTL": { + "description": "Filter control register", + "offset": 512, + "size": 32, + "reset_value": 706481665, + "reset_mask": 4294967295, + "children": { + "fields": { + "HBC1F": { + "description": "Header bank of CAN1 filter", + "offset": 8, + "size": 6 + }, + "FLD": { + "description": "Filter lock disable", + "offset": 0, + "size": 1 + } + } + } + }, + "FMCFG": { + "description": "Filter mode configuration register", + "offset": 516, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FMOD27": { + "description": "Filter mode", + "offset": 27, + "size": 1 + }, + "FMOD26": { + "description": "Filter mode", + "offset": 26, + "size": 1 + }, + "FMOD25": { + "description": "Filter mode", + "offset": 25, + "size": 1 + }, + "FMOD24": { + "description": "Filter mode", + "offset": 24, + "size": 1 + }, + "FMOD23": { + "description": "Filter mode", + "offset": 23, + "size": 1 + }, + "FMOD22": { + "description": "Filter mode", + "offset": 22, + "size": 1 + }, + "FMOD21": { + "description": "Filter mode", + "offset": 21, + "size": 1 + }, + "FMOD20": { + "description": "Filter mode", + "offset": 20, + "size": 1 + }, + "FMOD19": { + "description": "Filter mode", + "offset": 19, + "size": 1 + }, + "FMOD18": { + "description": "Filter mode", + "offset": 18, + "size": 1 + }, + "FMOD17": { + "description": "Filter mode", + "offset": 17, + "size": 1 + }, + "FMOD16": { + "description": "Filter mode", + "offset": 16, + "size": 1 + }, + "FMOD15": { + "description": "Filter mode", + "offset": 15, + "size": 1 + }, + "FMOD14": { + "description": "Filter mode", + "offset": 14, + "size": 1 + }, + "FMOD13": { + "description": "Filter mode", + "offset": 13, + "size": 1 + }, + "FMOD12": { + "description": "Filter mode", + "offset": 12, + "size": 1 + }, + "FMOD11": { + "description": "Filter mode", + "offset": 11, + "size": 1 + }, + "FMOD10": { + "description": "Filter mode", + "offset": 10, + "size": 1 + }, + "FMOD9": { + "description": "Filter mode", + "offset": 9, + "size": 1 + }, + "FMOD8": { + "description": "Filter mode", + "offset": 8, + "size": 1 + }, + "FMOD7": { + "description": "Filter mode", + "offset": 7, + "size": 1 + }, + "FMOD6": { + "description": "Filter mode", + "offset": 6, + "size": 1 + }, + "FMOD5": { + "description": "Filter mode", + "offset": 5, + "size": 1 + }, + "FMOD4": { + "description": "Filter mode", + "offset": 4, + "size": 1 + }, + "FMOD3": { + "description": "Filter mode", + "offset": 3, + "size": 1 + }, + "FMOD2": { + "description": "Filter mode", + "offset": 2, + "size": 1 + }, + "FMOD1": { + "description": "Filter mode", + "offset": 1, + "size": 1 + }, + "FMOD0": { + "description": "Filter mode", + "offset": 0, + "size": 1 + } + } + } + }, + "FSCFG": { + "description": "Filter scale configuration register", + "offset": 524, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FS0": { + "description": "Filter scale configuration", + "offset": 0, + "size": 1 + }, + "FS1": { + "description": "Filter scale configuration", + "offset": 1, + "size": 1 + }, + "FS2": { + "description": "Filter scale configuration", + "offset": 2, + "size": 1 + }, + "FS3": { + "description": "Filter scale configuration", + "offset": 3, + "size": 1 + }, + "FS4": { + "description": "Filter scale configuration", + "offset": 4, + "size": 1 + }, + "FS5": { + "description": "Filter scale configuration", + "offset": 5, + "size": 1 + }, + "FS6": { + "description": "Filter scale configuration", + "offset": 6, + "size": 1 + }, + "FS7": { + "description": "Filter scale configuration", + "offset": 7, + "size": 1 + }, + "FS8": { + "description": "Filter scale configuration", + "offset": 8, + "size": 1 + }, + "FS9": { + "description": "Filter scale configuration", + "offset": 9, + "size": 1 + }, + "FS10": { + "description": "Filter scale configuration", + "offset": 10, + "size": 1 + }, + "FS11": { + "description": "Filter scale configuration", + "offset": 11, + "size": 1 + }, + "FS12": { + "description": "Filter scale configuration", + "offset": 12, + "size": 1 + }, + "FS13": { + "description": "Filter scale configuration", + "offset": 13, + "size": 1 + }, + "FS14": { + "description": "Filter scale configuration", + "offset": 14, + "size": 1 + }, + "FS15": { + "description": "Filter scale configuration", + "offset": 15, + "size": 1 + }, + "FS16": { + "description": "Filter scale configuration", + "offset": 16, + "size": 1 + }, + "FS17": { + "description": "Filter scale configuration", + "offset": 17, + "size": 1 + }, + "FS18": { + "description": "Filter scale configuration", + "offset": 18, + "size": 1 + }, + "FS19": { + "description": "Filter scale configuration", + "offset": 19, + "size": 1 + }, + "FS20": { + "description": "Filter scale configuration", + "offset": 20, + "size": 1 + }, + "FS21": { + "description": "Filter scale configuration", + "offset": 21, + "size": 1 + }, + "FS22": { + "description": "Filter scale configuration", + "offset": 22, + "size": 1 + }, + "FS23": { + "description": "Filter scale configuration", + "offset": 23, + "size": 1 + }, + "FS24": { + "description": "Filter scale configuration", + "offset": 24, + "size": 1 + }, + "FS25": { + "description": "Filter scale configuration", + "offset": 25, + "size": 1 + }, + "FS26": { + "description": "Filter scale configuration", + "offset": 26, + "size": 1 + }, + "FS27": { + "description": "Filter scale configuration", + "offset": 27, + "size": 1 + } + } + } + }, + "FAFIFO": { + "description": "Filter associated FIFO register", + "offset": 532, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FAF0": { + "description": "Filter 0 associated with FIFO", + "offset": 0, + "size": 1 + }, + "FAF1": { + "description": "Filter 1 associated with FIFO", + "offset": 1, + "size": 1 + }, + "FAF2": { + "description": "Filter 2 associated with FIFO", + "offset": 2, + "size": 1 + }, + "FAF3": { + "description": "Filter 3 associated with FIFO", + "offset": 3, + "size": 1 + }, + "FAF4": { + "description": "Filter 4 associated with FIFO", + "offset": 4, + "size": 1 + }, + "FAF5": { + "description": "Filter 5 associated with FIFO", + "offset": 5, + "size": 1 + }, + "FAF6": { + "description": "Filter 6 associated with FIFO", + "offset": 6, + "size": 1 + }, + "FAF7": { + "description": "Filter 7 associated with FIFO", + "offset": 7, + "size": 1 + }, + "FAF8": { + "description": "Filter 8 associated with FIFO", + "offset": 8, + "size": 1 + }, + "FAF9": { + "description": "Filter 9 associated with FIFO", + "offset": 9, + "size": 1 + }, + "FAF10": { + "description": "Filter 10 associated with FIFO", + "offset": 10, + "size": 1 + }, + "FAF11": { + "description": "Filter 11 associated with FIFO", + "offset": 11, + "size": 1 + }, + "FAF12": { + "description": "Filter 12 associated with FIFO", + "offset": 12, + "size": 1 + }, + "FAF13": { + "description": "Filter 13 associated with FIFO", + "offset": 13, + "size": 1 + }, + "FAF14": { + "description": "Filter 14 associated with FIFO", + "offset": 14, + "size": 1 + }, + "FAF15": { + "description": "Filter 15 associated with FIFO", + "offset": 15, + "size": 1 + }, + "FAF16": { + "description": "Filter 16 associated with FIFO", + "offset": 16, + "size": 1 + }, + "FAF17": { + "description": "Filter 17 associated with FIFO", + "offset": 17, + "size": 1 + }, + "FAF18": { + "description": "Filter 18 associated with FIFO", + "offset": 18, + "size": 1 + }, + "FAF19": { + "description": "Filter 19 associated with FIFO", + "offset": 19, + "size": 1 + }, + "FAF20": { + "description": "Filter 20 associated with FIFO", + "offset": 20, + "size": 1 + }, + "FAF21": { + "description": "Filter 21 associated with FIFO", + "offset": 21, + "size": 1 + }, + "FAF22": { + "description": "Filter 22 associated with FIFO", + "offset": 22, + "size": 1 + }, + "FAF23": { + "description": "Filter 23 associated with FIFO", + "offset": 23, + "size": 1 + }, + "FAF24": { + "description": "Filter 24 associated with FIFO", + "offset": 24, + "size": 1 + }, + "FAF25": { + "description": "Filter 25 associated with FIFO", + "offset": 25, + "size": 1 + }, + "FAF26": { + "description": "Filter 26 associated with FIFO", + "offset": 26, + "size": 1 + }, + "FAF27": { + "description": "Filter 27 associated with FIFO", + "offset": 27, + "size": 1 + } + } + } + }, + "FW": { + "description": "Filter working register", + "offset": 540, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FW0": { + "description": "Filter working", + "offset": 0, + "size": 1 + }, + "FW1": { + "description": "Filter working", + "offset": 1, + "size": 1 + }, + "FW2": { + "description": "Filter working", + "offset": 2, + "size": 1 + }, + "FW3": { + "description": "Filter working", + "offset": 3, + "size": 1 + }, + "FW4": { + "description": "Filter working", + "offset": 4, + "size": 1 + }, + "FW5": { + "description": "Filter working", + "offset": 5, + "size": 1 + }, + "FW6": { + "description": "Filter working", + "offset": 6, + "size": 1 + }, + "FW7": { + "description": "Filter working", + "offset": 7, + "size": 1 + }, + "FW8": { + "description": "Filter working", + "offset": 8, + "size": 1 + }, + "FW9": { + "description": "Filter working", + "offset": 9, + "size": 1 + }, + "FW10": { + "description": "Filter working", + "offset": 10, + "size": 1 + }, + "FW11": { + "description": "Filter working", + "offset": 11, + "size": 1 + }, + "FW12": { + "description": "Filter working", + "offset": 12, + "size": 1 + }, + "FW13": { + "description": "Filter working", + "offset": 13, + "size": 1 + }, + "FW14": { + "description": "Filter working", + "offset": 14, + "size": 1 + }, + "FW15": { + "description": "Filter working", + "offset": 15, + "size": 1 + }, + "FW16": { + "description": "Filter working", + "offset": 16, + "size": 1 + }, + "FW17": { + "description": "Filter working", + "offset": 17, + "size": 1 + }, + "FW18": { + "description": "Filter working", + "offset": 18, + "size": 1 + }, + "FW19": { + "description": "Filter working", + "offset": 19, + "size": 1 + }, + "FW20": { + "description": "Filter working", + "offset": 20, + "size": 1 + }, + "FW21": { + "description": "Filter working", + "offset": 21, + "size": 1 + }, + "FW22": { + "description": "Filter working", + "offset": 22, + "size": 1 + }, + "FW23": { + "description": "Filter working", + "offset": 23, + "size": 1 + }, + "FW24": { + "description": "Filter working", + "offset": 24, + "size": 1 + }, + "FW25": { + "description": "Filter working", + "offset": 25, + "size": 1 + }, + "FW26": { + "description": "Filter working", + "offset": 26, + "size": 1 + }, + "FW27": { + "description": "Filter working", + "offset": 27, + "size": 1 + } + } + } + }, + "F0DATA0": { + "description": "Filter 0 data 0 register", + "offset": 576, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F0DATA1": { + "description": "Filter 0 data 1 register", + "offset": 580, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter 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"size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F5DATA0": { + "description": "Filter 5 data 0 register", + "offset": 616, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + 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"offset": 31, + "size": 1 + } + } + } + }, + "F5DATA1": { + "description": "Filter 5 data 1 register", + "offset": 620, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter 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"description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13DATA0": { + "description": "Filter 13 data 0 register", + "offset": 680, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 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"FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F13DATA1": { + "description": "Filter 13 data 1 register", + "offset": 684, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 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1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F14DATA0": { + "description": "Filter 14 data 0 register", + "offset": 688, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", 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"Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F15DATA1": { + "description": "Filter 15 data 1 register", + "offset": 700, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + 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"size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17DATA0": { + "description": "Filter 17 data 0 register", + "offset": 712, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter 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"offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F17DATA1": { + "description": "Filter 17 data 1 register", + "offset": 716, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18DATA0": { + "description": "Filter 18 data 0 register", + "offset": 720, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F18DATA1": { + "description": "Filter 18 data 1 register", + "offset": 724, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + 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"FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19DATA0": { + "description": "Filter 19 data 0 register", + "offset": 728, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F19DATA1": { + "description": "Filter 19 data 1 register", + "offset": 732, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter 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"offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20DATA0": { + "description": "Filter 20 data 0 register", + "offset": 736, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F20DATA1": { + "description": "Filter 20 data 1 register", + "offset": 740, + "size": 32, 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"offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F24DATA1": { + "description": "Filter 24 data 1 register", + "offset": 772, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25DATA0": { + "description": "Filter 25 data 0 register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F25DATA1": { + "description": "Filter 25 data 1 register", + "offset": 780, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26DATA0": { + "description": "Filter 26 data 0 register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F26DATA1": { + "description": "Filter 26 data 1 register", + "offset": 788, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27DATA0": { + "description": "Filter 27 data 0 register", + "offset": 792, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + }, + "F27DATA1": { + "description": "Filter 27 data 1 register", + "offset": 796, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FD0": { + "description": "Filter bits", + "offset": 0, + "size": 1 + }, + "FD1": { + "description": "Filter bits", + "offset": 1, + "size": 1 + }, + "FD2": { + "description": "Filter bits", + "offset": 2, + "size": 1 + }, + "FD3": { + "description": "Filter bits", + "offset": 3, + "size": 1 + }, + "FD4": { + "description": "Filter bits", + "offset": 4, + "size": 1 + }, + "FD5": { + "description": "Filter bits", + "offset": 5, + "size": 1 + }, + "FD6": { + "description": "Filter bits", + "offset": 6, + "size": 1 + }, + "FD7": { + "description": "Filter bits", + "offset": 7, + "size": 1 + }, + "FD8": { + "description": "Filter bits", + "offset": 8, + "size": 1 + }, + "FD9": { + "description": "Filter bits", + "offset": 9, + "size": 1 + }, + "FD10": { + "description": "Filter bits", + "offset": 10, + "size": 1 + }, + "FD11": { + "description": "Filter bits", + "offset": 11, + "size": 1 + }, + "FD12": { + "description": "Filter bits", + "offset": 12, + "size": 1 + }, + "FD13": { + "description": "Filter bits", + "offset": 13, + "size": 1 + }, + "FD14": { + "description": "Filter bits", + "offset": 14, + "size": 1 + }, + "FD15": { + "description": "Filter bits", + "offset": 15, + "size": 1 + }, + "FD16": { + "description": "Filter bits", + "offset": 16, + "size": 1 + }, + "FD17": { + "description": "Filter bits", + "offset": 17, + "size": 1 + }, + "FD18": { + "description": "Filter bits", + "offset": 18, + "size": 1 + }, + "FD19": { + "description": "Filter bits", + "offset": 19, + "size": 1 + }, + "FD20": { + "description": "Filter bits", + "offset": 20, + "size": 1 + }, + "FD21": { + "description": "Filter bits", + "offset": 21, + "size": 1 + }, + "FD22": { + "description": "Filter bits", + "offset": 22, + "size": 1 + }, + "FD23": { + "description": "Filter bits", + "offset": 23, + "size": 1 + }, + "FD24": { + "description": "Filter bits", + "offset": 24, + "size": 1 + }, + "FD25": { + "description": "Filter bits", + "offset": 25, + "size": 1 + }, + "FD26": { + "description": "Filter bits", + "offset": 26, + "size": 1 + }, + "FD27": { + "description": "Filter bits", + "offset": 27, + "size": 1 + }, + "FD28": { + "description": "Filter bits", + "offset": 28, + "size": 1 + }, + "FD29": { + "description": "Filter bits", + "offset": 29, + "size": 1 + }, + "FD30": { + "description": "Filter bits", + "offset": 30, + "size": 1 + }, + "FD31": { + "description": "Filter bits", + "offset": 31, + "size": 1 + } + } + } + } + } + } + }, + "WWDGT": { + "description": "Window watchdog timer", + "children": { + "registers": { + "CTL": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "WDGTEN": { + "description": "Activation bit", + "offset": 7, + "size": 1 + }, + "CNT": { + "description": "7-bit counter", + "offset": 0, + "size": 7 + } + } + } + }, + "CFG": { + "description": "Configuration register", + "offset": 4, + "size": 32, + "reset_value": 127, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWIE": { + "description": "Early wakeup interrupt", + "offset": 9, + "size": 1 + }, + "PSC": { + "description": "Prescaler", + "offset": 7, + "size": 2 + }, + "WIN": { + "description": "7-bit window value", + "offset": 0, + "size": 7 + } + } + } + }, + "STAT": { + "description": "Status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EWIF": { + "description": "Early wakeup interrupt\n flag", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "CRC": { + "description": "cyclic redundancy check calculation unit", + "children": { + "registers": { + "DATA": { + "description": "Data register", + "offset": 0, + "size": 32, + "reset_value": 4294967295, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "CRC calculation result bits", + "offset": 0, + "size": 32 + } + } + } + }, + "FDATA": { + "description": "Free data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FDATA": { + "description": "Free Data Register bits", + "offset": 0, + "size": 8 + } + } + } + }, + "CTL": { + "description": "Control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RST": { + "description": "reset bit", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "DAC": { + "description": "Digital-to-analog converter", + "children": { + "registers": { + "CTL": { + "description": "control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DEN0": { + "description": "DAC0 enable", + "offset": 0, + "size": 1 + }, + "DBOFF0": { + "description": "DAC0 output buffer turn off", + "offset": 1, + "size": 1 + }, + "DTEN0": { + "description": "DAC0 trigger enable", + "offset": 2, + "size": 1 + }, + "DTSEL0": { + "description": "DAC0 trigger selection", + "offset": 3, + "size": 3 + }, + "DWM0": { + "description": "DAC0 noise wave mode", + "offset": 6, + "size": 2 + }, + "DWBW0": { + "description": "DAC0 noise wave bit width", + "offset": 8, + "size": 4 + }, + "DDMAEN0": { + "description": "DAC0 DMA enable", + "offset": 12, + "size": 1 + }, + "DEN1": { + "description": "DAC1 enable", + "offset": 16, + "size": 1 + }, + "DBOFF1": { + "description": "DAC1 output buffer turn off", + "offset": 17, + "size": 1 + }, + "DTEN1": { + "description": "DAC1 trigger enable", + "offset": 18, + "size": 1 + }, + "DTSEL1": { + "description": "DAC1 trigger selection", + "offset": 19, + "size": 3 + }, + "DWM1": { + "description": "DAC1 noise wave mode", + "offset": 22, + "size": 2 + }, + "DWBW1": { + "description": "DAC1 noise wave bit width", + "offset": 24, + "size": 4 + }, + "DDMAEN1": { + "description": "DAC1 DMA enable", + "offset": 28, + "size": 1 + } + } + } + }, + "SWT": { + "description": "software trigger register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "SWTR0": { + "description": "DAC0 software trigger", + "offset": 0, + "size": 1 + }, + "SWTR1": { + "description": "DAC1 software trigger", + "offset": 1, + "size": 1 + } + } + } + }, + "DAC0_R12DH": { + "description": "DAC0 12-bit right-aligned data holding register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DAC0_L12DH": { + "description": "DAC0 12-bit left-aligned data holding register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DAC0_R8DH": { + "description": "DAC0 8-bit right aligned data holding\n register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DAC1_R12DH": { + "description": "DAC1 12-bit right-aligned data holding\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC1_DH": { + "description": "DAC1 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + } + } + } + }, + "DAC1_L12DH": { + "description": "DAC1 12-bit left aligned data holding\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC1_DH": { + "description": "DAC1 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + } + } + } + }, + "DAC1_R8DH": { + "description": "DAC1 8-bit right aligned data holding\n register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC1_DH": { + "description": "DAC1 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + } + } + } + }, + "DACC_R12DH": { + "description": "DAC concurrent mode 12-bit right-aligned data holding\n register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 12-bit right-aligned\n data", + "offset": 0, + "size": 12 + }, + "DAC1_DH": { + "description": "DAC1 12-bit right-aligned\n data", + "offset": 16, + "size": 12 + } + } + } + }, + "DACC_L12DH": { + "description": "DAC concurrent mode 12-bit left aligned data holding\n register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 12-bit left-aligned\n data", + "offset": 4, + "size": 12 + }, + "DAC1_DH": { + "description": "DAC1 12-bit left-aligned\n data", + "offset": 20, + "size": 12 + } + } + } + }, + "DACC_R8DH": { + "description": "DAC concurrent mode 8-bit right aligned data holding\n register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DAC0_DH": { + "description": "DAC0 8-bit right-aligned\n data", + "offset": 0, + "size": 8 + }, + "DAC1_DH": { + "description": "DAC1 8-bit right-aligned\n data", + "offset": 8, + "size": 8 + } + } + } + }, + "DAC0_DO": { + "description": "DAC0 data output register", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DAC0_DO": { + "description": "DAC0 data output", + "offset": 0, + "size": 12 + } + } + } + }, + "DAC1_DO": { + "description": "DAC1 data output register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DAC1_DO": { + "description": "DAC1 data output", + "offset": 0, + "size": 12 + } + } + } + } + } + } + }, + "DBG": { + "description": "Debug support", + "children": { + "registers": { + "ID": { + "description": "ID code register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ID_CODE": { + "description": "DBG ID code register", + "offset": 0, + "size": 32 + } + } + } + }, + "CTL": { + "description": "Control register 0", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SLP_HOLD": { + "description": "Sleep mode hold register", + "offset": 0, + "size": 1 + }, + "DSLP_HOLD": { + "description": "Deep-sleep mode hold register", + "offset": 1, + "size": 1 + }, + "STB_HOLD": { + "description": "Standby mode hold register", + "offset": 2, + "size": 1 + }, + "FWDGT_HOLD": { + "description": "FWDGT hold bit", + "offset": 8, + "size": 1 + }, + "WWDGT_HOLD": { + "description": "WWDGT hold bit", + "offset": 9, + "size": 1 + }, + "TIMER0_HOLD": { + "description": "TIMER 0 hold bit", + "offset": 10, + "size": 1 + }, + "TIMER1_HOLD": { + "description": "TIMER 1 hold bit", + "offset": 11, + "size": 1 + }, + "TIMER2_HOLD": { + "description": "TIMER 2 hold bit", + "offset": 12, + "size": 1 + }, + "TIMER3_HOLD": { + "description": "TIMER 23 hold bit", + "offset": 13, + "size": 1 + }, + "CAN0_HOLD": { + "description": "CAN0 hold bit", + "offset": 14, + "size": 1 + }, + "I2C0_HOLD": { + "description": "I2C0 hold bit", + "offset": 15, + "size": 1 + }, + "I2C1_HOLD": { + "description": "I2C1 hold bit", + "offset": 16, + "size": 1 + }, + "TIMER4_HOLD": { + "description": "TIMER4_HOLD", + "offset": 18, + "size": 1 + }, + "TIMER5_HOLD": { + "description": "TIMER 5 hold bit", + "offset": 19, + "size": 1 + }, + "TIMER6_HOLD": { + "description": "TIMER 6 hold bit", + "offset": 20, + "size": 1 + }, + "CAN1_HOLD": { + "description": "CAN1 hold bit", + "offset": 21, + "size": 1 + } + } + } + } + } + } + }, + "DMA0": { + "description": "DMA controller", + "children": { + "registers": { + "INTF": { + "description": "Interrupt flag register ", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "GIF0": { + "description": "Global interrupt flag of channel 0", + "offset": 0, + "size": 1 + }, + "FTFIF0": { + "description": "Full Transfer finish flag of channe 0", + "offset": 1, + "size": 1 + }, + "HTFIF0": { + "description": "Half transfer finish flag of channel 0", + "offset": 2, + "size": 1 + }, + "ERRIF0": { + "description": "Error flag of channel 0", + "offset": 3, + "size": 1 + }, + "GIF1": { + "description": "Global interrupt flag of channel 1", + "offset": 4, + "size": 1 + }, + "FTFIF1": { + "description": "Full Transfer finish flag of channe 1", + "offset": 5, + "size": 1 + }, + "HTFIF1": { + "description": "Half transfer finish flag of channel 1", + "offset": 6, + "size": 1 + }, + "ERRIF1": { + "description": "Error flag of channel 1", + "offset": 7, + "size": 1 + }, + "GIF2": { + "description": "Global interrupt flag of channel 2", + "offset": 8, + "size": 1 + }, + "FTFIF2": { + "description": "Full Transfer finish flag of channe 2", + "offset": 9, + "size": 1 + }, + "HTFIF2": { + "description": "Half transfer finish flag of channel 2", + "offset": 10, + "size": 1 + }, + "ERRIF2": { + "description": "Error flag of channel 2", + "offset": 11, + "size": 1 + }, + "GIF3": { + "description": "Global interrupt flag of channel 3", + "offset": 12, + "size": 1 + }, + "FTFIF3": { + "description": "Full Transfer finish flag of channe 3", + "offset": 13, + "size": 1 + }, + "HTFIF3": { + "description": "Half transfer finish flag of channel 3", + "offset": 14, + "size": 1 + }, + "ERRIF3": { + "description": "Error flag of channel 3", + "offset": 15, + "size": 1 + }, + "GIF4": { + "description": "Global interrupt flag of channel 4", + "offset": 16, + "size": 1 + }, + "FTFIF4": { + "description": "Full Transfer finish flag of channe 4", + "offset": 17, + "size": 1 + }, + "HTFIF4": { + "description": "Half transfer finish flag of channel 4", + "offset": 18, + "size": 1 + }, + "ERRIF4": { + "description": "Error flag of channel 4", + "offset": 19, + "size": 1 + }, + "GIF5": { + "description": "Global interrupt flag of channel 5", + "offset": 20, + "size": 1 + }, + "FTFIF5": { + "description": "Full Transfer finish flag of channe 5", + "offset": 21, + "size": 1 + }, + "HTFIF5": { + "description": "Half transfer finish flag of channel 5", + "offset": 22, + "size": 1 + }, + "ERRIF5": { + "description": "Error flag of channel 5", + "offset": 23, + "size": 1 + }, + "GIF6": { + "description": "Global interrupt flag of channel 6", + "offset": 24, + "size": 1 + }, + "FTFIF6": { + "description": "Full Transfer finish flag of channe 6", + "offset": 25, + "size": 1 + }, + "HTFIF6": { + "description": "Half transfer finish flag of channel 6", + "offset": 26, + "size": 1 + }, + "ERRIF6": { + "description": "Error flag of channel 6", + "offset": 27, + "size": 1 + } + } + } + }, + "INTC": { + "description": "Interrupt flag clear register ", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "GIFC0": { + "description": "Clear global interrupt flag of channel 0", + "offset": 0, + "size": 1 + }, + "FTFIFC0": { + "description": "Clear bit for full transfer finish flag of channel 0", + "offset": 1, + "size": 1 + }, + "HTFIFC0": { + "description": "Clear bit for half transfer finish flag of channel 0", + "offset": 2, + "size": 1 + }, + "ERRIFC0": { + "description": "Clear bit for error flag of channel 0", + "offset": 3, + "size": 1 + }, + "GIFC1": { + "description": "Clear global interrupt flag of channel 1", + "offset": 4, + "size": 1 + }, + "FTFIFC1": { + "description": "Clear bit for full transfer finish flag of channel 1", + "offset": 5, + "size": 1 + }, + "HTFIFC1": { + "description": "Clear bit for half transfer finish flag of channel 1", + "offset": 6, + "size": 1 + }, + "ERRIFC1": { + "description": "Clear bit for error flag of channel 1", + "offset": 7, + "size": 1 + }, + "GIFC2": { + "description": "Clear global interrupt flag of channel 2", + "offset": 8, + "size": 1 + }, + "FTFIFC2": { + "description": "Clear bit for full transfer finish flag of channel 2", + "offset": 9, + "size": 1 + }, + "HTFIFC2": { + "description": "Clear bit for half transfer finish flag of channel 2", + "offset": 10, + "size": 1 + }, + "ERRIFC2": { + "description": "Clear bit for error flag of channel 2", + "offset": 11, + "size": 1 + }, + "GIFC3": { + "description": "Clear global interrupt flag of channel 3", + "offset": 12, + "size": 1 + }, + "FTFIFC3": { + "description": "Clear bit for full transfer finish flag of channel 3", + "offset": 13, + "size": 1 + }, + "HTFIFC3": { + "description": "Clear bit for half transfer finish flag of channel 3", + "offset": 14, + "size": 1 + }, + "ERRIFC3": { + "description": "Clear bit for error flag of channel 3", + "offset": 15, + "size": 1 + }, + "GIFC4": { + "description": "Clear global interrupt flag of channel 4", + "offset": 16, + "size": 1 + }, + "FTFIFC4": { + "description": "Clear bit for full transfer finish flag of channel 4", + "offset": 17, + "size": 1 + }, + "HTFIFC4": { + "description": "Clear bit for half transfer finish flag of channel 4", + "offset": 18, + "size": 1 + }, + "ERRIFC4": { + "description": "Clear bit for error flag of channel 4", + "offset": 19, + "size": 1 + }, + "GIFC5": { + "description": "Clear global interrupt flag of channel 5", + "offset": 20, + "size": 1 + }, + "FTFIFC5": { + "description": "Clear bit for full transfer finish flag of channel 5", + "offset": 21, + "size": 1 + }, + "HTFIFC5": { + "description": "Clear bit for half transfer finish flag of channel 5", + "offset": 22, + "size": 1 + }, + "ERRIFC5": { + "description": "Clear bit for error flag of channel 5", + "offset": 23, + "size": 1 + }, + "GIFC6": { + "description": "Clear global interrupt flag of channel 6", + "offset": 24, + "size": 1 + }, + "FTFIFC6": { + "description": "Clear bit for full transfer finish flag of channel 6", + "offset": 25, + "size": 1 + }, + "HTFIFC6": { + "description": "Clear bit for half transfer finish flag of channel 6", + "offset": 26, + "size": 1 + }, + "ERRIFC6": { + "description": "Clear bit for error flag of channel 6", + "offset": 27, + "size": 1 + } + } + } + }, + "CH0CTL": { + "description": "Channel 0 control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH0CNT": { + "description": "Channel 0 counter register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH0PADDR": { + "description": "Channel 0 peripheral base address register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH0MADDR": { + "description": "Channel 0 memory base address register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH1CTL": { + "description": "Channel 1 control register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH1CNT": { + "description": "Channel 1 counter register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH1PADDR": { + "description": "Channel 1 peripheral base address register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH1MADDR": { + "description": "Channel 1 memory base address register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH2CTL": { + "description": "Channel 2 control register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH2CNT": { + "description": "Channel 2 counter register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH2PADDR": { + "description": "Channel 2 peripheral base address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH2MADDR": { + "description": "Channel 2 memory base address register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH3CTL": { + "description": "Channel 3 control register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH3CNT": { + "description": "Channel 3 counter register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH3PADDR": { + "description": "Channel 3 peripheral base address register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH3MADDR": { + "description": "Channel 3 memory base address register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH4CTL": { + "description": "Channel 4 control register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH4CNT": { + "description": "Channel 4 counter register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH4PADDR": { + "description": "Channel 4 peripheral base address register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH4MADDR": { + "description": "Channel 4 memory base address register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH5CTL": { + "description": "Channel 5 control register", + "offset": 108, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH5CNT": { + "description": "Channel 5 counter register", + "offset": 112, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH5PADDR": { + "description": "Channel 5 peripheral base address register", + "offset": 116, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH5MADDR": { + "description": "Channel 5 memory base address register", + "offset": 120, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH6CTL": { + "description": "Channel 6 control register", + "offset": 128, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH6CNT": { + "description": "Channel 6 counter register", + "offset": 132, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH6PADDR": { + "description": "Channel 6 peripheral base address register", + "offset": 136, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH6MADDR": { + "description": "Channel 6 memory base address register", + "offset": 140, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "DMA1": { + "description": "Direct memory access controller", + "children": { + "registers": { + "INTF": { + "description": "Interrupt flag register ", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "GIF0": { + "description": "Global interrupt flag of channel 0", + "offset": 0, + "size": 1 + }, + "FTFIF0": { + "description": "Full Transfer finish flag of channe 0", + "offset": 1, + "size": 1 + }, + "HTFIF0": { + "description": "Half transfer finish flag of channel 0", + "offset": 2, + "size": 1 + }, + "ERRIF0": { + "description": "Error flag of channel 0", + "offset": 3, + "size": 1 + }, + "GIF1": { + "description": "Global interrupt flag of channel 1", + "offset": 4, + "size": 1 + }, + "FTFIF1": { + "description": "Full Transfer finish flag of channe 1", + "offset": 5, + "size": 1 + }, + "HTFIF1": { + "description": "Half transfer finish flag of channel 1", + "offset": 6, + "size": 1 + }, + "ERRIF1": { + "description": "Error flag of channel 1", + "offset": 7, + "size": 1 + }, + "GIF2": { + "description": "Global interrupt flag of channel 2", + "offset": 8, + "size": 1 + }, + "FTFIF2": { + "description": "Full Transfer finish flag of channe 2", + "offset": 9, + "size": 1 + }, + "HTFIF2": { + "description": "Half transfer finish flag of channel 2", + "offset": 10, + "size": 1 + }, + "ERRIF2": { + "description": "Error flag of channel 2", + "offset": 11, + "size": 1 + }, + "GIF3": { + "description": "Global interrupt flag of channel 3", + "offset": 12, + "size": 1 + }, + "FTFIF3": { + "description": "Full Transfer finish flag of channe 3", + "offset": 13, + "size": 1 + }, + "HTFIF3": { + "description": "Half transfer finish flag of channel 3", + "offset": 14, + "size": 1 + }, + "ERRIF3": { + "description": "Error flag of channel 3", + "offset": 15, + "size": 1 + }, + "GIF4": { + "description": "Global interrupt flag of channel 4", + "offset": 16, + "size": 1 + }, + "FTFIF4": { + "description": "Full Transfer finish flag of channe 4", + "offset": 17, + "size": 1 + }, + "HTFIF4": { + "description": "Half transfer finish flag of channel 4", + "offset": 18, + "size": 1 + }, + "ERRIF4": { + "description": "Error flag of channel 4", + "offset": 19, + "size": 1 + } + } + } + }, + "INTC": { + "description": "Interrupt flag clear register ", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "GIFC0": { + "description": "Clear global interrupt flag of channel 0", + "offset": 0, + "size": 1 + }, + "FTFIFC0": { + "description": "Clear bit for full transfer finish flag of channel 0", + "offset": 1, + "size": 1 + }, + "HTFIFC0": { + "description": "Clear bit for half transfer finish flag of channel 0", + "offset": 2, + "size": 1 + }, + "ERRIFC0": { + "description": "Clear bit for error flag of channel 0", + "offset": 3, + "size": 1 + }, + "GIFC1": { + "description": "Clear global interrupt flag of channel 1", + "offset": 4, + "size": 1 + }, + "FTFIFC1": { + "description": "Clear bit for full transfer finish flag of channel 1", + "offset": 5, + "size": 1 + }, + "HTFIFC1": { + "description": "Clear bit for half transfer finish flag of channel 1", + "offset": 6, + "size": 1 + }, + "ERRIFC1": { + "description": "Clear bit for error flag of channel 1", + "offset": 7, + "size": 1 + }, + "GIFC2": { + "description": "Clear global interrupt flag of channel 2", + "offset": 8, + "size": 1 + }, + "FTFIFC2": { + "description": "Clear bit for full transfer finish flag of channel 2", + "offset": 9, + "size": 1 + }, + "HTFIFC2": { + "description": "Clear bit for half transfer finish flag of channel 2", + "offset": 10, + "size": 1 + }, + "ERRIFC2": { + "description": "Clear bit for error flag of channel 2", + "offset": 11, + "size": 1 + }, + "GIFC3": { + "description": "Clear global interrupt flag of channel 3", + "offset": 12, + "size": 1 + }, + "FTFIFC3": { + "description": "Clear bit for full transfer finish flag of channel 3", + "offset": 13, + "size": 1 + }, + "HTFIFC3": { + "description": "Clear bit for half transfer finish flag of channel 3", + "offset": 14, + "size": 1 + }, + "ERRIFC3": { + "description": "Clear bit for error flag of channel 3", + "offset": 15, + "size": 1 + }, + "GIFC4": { + "description": "Clear global interrupt flag of channel 4", + "offset": 16, + "size": 1 + }, + "FTFIFC4": { + "description": "Clear bit for full transfer finish flag of channel 4", + "offset": 17, + "size": 1 + }, + "HTFIFC4": { + "description": "Clear bit for half transfer finish flag of channel 4", + "offset": 18, + "size": 1 + }, + "ERRIFC4": { + "description": "Clear bit for error flag of channel 4", + "offset": 19, + "size": 1 + } + } + } + }, + "CH0CTL": { + "description": "Channel 0 control register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH0CNT": { + "description": "Channel 0 counter register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH0PADDR": { + "description": "Channel 0 peripheral base address register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH0MADDR": { + "description": "Channel 0 memory base address register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH1CTL": { + "description": "Channel 1 control register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH1CNT": { + "description": "Channel 1 counter register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH1PADDR": { + "description": "Channel 1 peripheral base address register", + "offset": 36, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH1MADDR": { + "description": "Channel 1 memory base address register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH2CTL": { + "description": "Channel 2 control register", + "offset": 48, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH2CNT": { + "description": "Channel 2 counter register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH2PADDR": { + "description": "Channel 2 peripheral base address register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH2MADDR": { + "description": "Channel 2 memory base address register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH3CTL": { + "description": "Channel 3 control register", + "offset": 68, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH3CNT": { + "description": "Channel 3 counter register", + "offset": 72, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH3PADDR": { + "description": "Channel 3 peripheral base address register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH3MADDR": { + "description": "Channel 3 memory base address register", + "offset": 80, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH4CTL": { + "description": "Channel 4 control register", + "offset": 88, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CHEN": { + "description": "Channel enable", + "offset": 0, + "size": 1 + }, + "FTFIE": { + "description": "Enable bit for channel full transfer finish interrupt", + "offset": 1, + "size": 1 + }, + "HTFIE": { + "description": "Enable bit for channel half transfer finish interrupt", + "offset": 2, + "size": 1 + }, + "ERRIE": { + "description": "Enable bit for channel error interrupt", + "offset": 3, + "size": 1 + }, + "DIR": { + "description": "Transfer direction", + "offset": 4, + "size": 1 + }, + "CMEN": { + "description": "Circular mode enable", + "offset": 5, + "size": 1 + }, + "PNAGA": { + "description": "Next address generation algorithm of peripheral", + "offset": 6, + "size": 1 + }, + "MNAGA": { + "description": "Next address generation algorithm of memory", + "offset": 7, + "size": 1 + }, + "PWIDTH": { + "description": "Transfer data size of peripheral", + "offset": 8, + "size": 2 + }, + "MWIDTH": { + "description": "Transfer data size of memory", + "offset": 10, + "size": 2 + }, + "PRIO": { + "description": "Priority level", + "offset": 12, + "size": 2 + }, + "M2M": { + "description": "Memory to Memory Mode", + "offset": 14, + "size": 1 + } + } + } + }, + "CH4CNT": { + "description": "Channel 4 counter register", + "offset": 92, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Transfer counter", + "offset": 0, + "size": 16 + } + } + } + }, + "CH4PADDR": { + "description": "Channel 4 peripheral base address register", + "offset": 96, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PADDR": { + "description": "Peripheral base address", + "offset": 0, + "size": 32 + } + } + } + }, + "CH4MADDR": { + "description": "Channel 4 memory base address register", + "offset": 100, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MADDR": { + "description": "Memory base address", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "EXMC": { + "description": "External memory controller", + "children": { + "registers": { + "SNCTL0": { + "description": "SRAM/NOR flash control register 0", + "offset": 0, + "size": 32, + "reset_value": 12506, + "reset_mask": 4294967295, + "children": { + "fields": { + "ASYNCWAIT": { + "description": "Asynchronous wait", + "offset": 15, + "size": 1 + }, + "NRWTEN": { + "description": "NWAIT signal enable", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "Write enable", + "offset": 12, + "size": 1 + }, + "NRWTPOL": { + "description": "NWAIT signal polarity", + "offset": 9, + "size": 1 + }, + "NREN": { + "description": "NOR Flash access enable", + "offset": 6, + "size": 1 + }, + "NRW": { + "description": "NOR bank memory data bus width", + "offset": 4, + "size": 2 + }, + "NRTP": { + "description": "NOR bank memory type", + "offset": 2, + "size": 2 + }, + "NRMUX": { + "description": "NOR bank memory address/data multiplexing", + "offset": 1, + "size": 1 + }, + "NRBKEN": { + "description": "NOR bank enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SNTCFG0": { + "description": "SRAM/NOR flash timing configuration register 0", + "offset": 4, + "size": 32, + "reset_value": 268435455, + "reset_mask": 4294967295, + "children": { + "fields": { + "BUSLAT": { + "description": "Bus latency", + "offset": 16, + "size": 4 + }, + "DSET": { + "description": "Data setup time", + "offset": 8, + "size": 8 + }, + "AHLD": { + "description": "Address hold time", + "offset": 4, + "size": 4 + }, + "ASET": { + "description": "Address setup time", + "offset": 0, + "size": 4 + } + } + } + }, + "SNCTL1": { + "description": "SRAM/NOR flash control register 1", + "offset": 8, + "size": 32, + "reset_value": 12506, + "reset_mask": 4294967295, + "children": { + "fields": { + "ASYNCWAIT": { + "description": "Asynchronous wait", + "offset": 15, + "size": 1 + }, + "NRWTEN": { + "description": "NWAIT signal enable", + "offset": 13, + "size": 1 + }, + "WREN": { + "description": "Write enable", + "offset": 12, + "size": 1 + }, + "NRWTPOL": { + "description": "NWAIT signal polarity", + "offset": 9, + "size": 1 + }, + "NREN": { + "description": "NOR Flash access enable", + "offset": 6, + "size": 1 + }, + "NRW": { + "description": "NOR bank memory data bus width", + "offset": 4, + "size": 2 + }, + "NRTP": { + "description": "NOR bank memory type", + "offset": 2, + "size": 2 + }, + "NRMUX": { + "description": "NOR bank memory address/data multiplexing", + "offset": 1, + "size": 1 + }, + "NRBKEN": { + "description": "NOR bank enable", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "children": { + "registers": { + "INTEN": { + "description": "Interrupt enable register\n (EXTI_INTEN)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTEN0": { + "description": "Enable Interrupt on line 0", + "offset": 0, + "size": 1 + }, + "INTEN1": { + "description": "Enable Interrupt on line 1", + "offset": 1, + "size": 1 + }, + "INTEN2": { + "description": "Enable Interrupt on line 2", + "offset": 2, + "size": 1 + }, + "INTEN3": { + "description": "Enable Interrupt on line 3", + "offset": 3, + "size": 1 + }, + "INTEN4": { + "description": "Enable Interrupt on line 4", + "offset": 4, + "size": 1 + }, + "INTEN5": { + "description": "Enable Interrupt on line 5", + "offset": 5, + "size": 1 + }, + "INTEN6": { + "description": "Enable Interrupt on line 6", + "offset": 6, + "size": 1 + }, + "INTEN7": { + "description": "Enable Interrupt on line 7", + "offset": 7, + "size": 1 + }, + "INTEN8": { + "description": "Enable Interrupt on line 8", + "offset": 8, + "size": 1 + }, + "INTEN9": { + "description": "Enable Interrupt on line 9", + "offset": 9, + "size": 1 + }, + "INTEN10": { + "description": "Enable Interrupt on line 10", + "offset": 10, + "size": 1 + }, + "INTEN11": { + "description": "Enable Interrupt on line 11", + "offset": 11, + "size": 1 + }, + "INTEN12": { + "description": "Enable Interrupt on line 12", + "offset": 12, + "size": 1 + }, + "INTEN13": { + "description": "Enable Interrupt on line 13", + "offset": 13, + "size": 1 + }, + "INTEN14": { + "description": "Enable Interrupt on line 14", + "offset": 14, + "size": 1 + }, + "INTEN15": { + "description": "Enable Interrupt on line 15", + "offset": 15, + "size": 1 + }, + "INTEN16": { + "description": "Enable Interrupt on line 16", + "offset": 16, + "size": 1 + }, + "INTEN17": { + "description": "Enable Interrupt on line 17", + "offset": 17, + "size": 1 + }, + "INTEN18": { + "description": "Enable Interrupt on line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "EVEN": { + "description": "Event enable register (EXTI_EVEN)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EVEN0": { + "description": "Enable Event on line 0", + "offset": 0, + "size": 1 + }, + "EVEN1": { + "description": "Enable Event on line 1", + "offset": 1, + "size": 1 + }, + "EVEN2": { + "description": "Enable Event on line 2", + "offset": 2, + "size": 1 + }, + "EVEN3": { + "description": "Enable Event on line 3", + "offset": 3, + "size": 1 + }, + "EVEN4": { + "description": "Enable Event on line 4", + "offset": 4, + "size": 1 + }, + "EVEN5": { + "description": "Enable Event on line 5", + "offset": 5, + "size": 1 + }, + "EVEN6": { + "description": "Enable Event on line 6", + "offset": 6, + "size": 1 + }, + "EVEN7": { + "description": "Enable Event on line 7", + "offset": 7, + "size": 1 + }, + "EVEN8": { + "description": "Enable Event on line 8", + "offset": 8, + "size": 1 + }, + "EVEN9": { + "description": "Enable Event on line 9", + "offset": 9, + "size": 1 + }, + "EVEN10": { + "description": "Enable Event on line 10", + "offset": 10, + "size": 1 + }, + "EVEN11": { + "description": "Enable Event on line 11", + "offset": 11, + "size": 1 + }, + "EVEN12": { + "description": "Enable Event on line 12", + "offset": 12, + "size": 1 + }, + "EVEN13": { + "description": "Enable Event on line 13", + "offset": 13, + "size": 1 + }, + "EVEN14": { + "description": "Enable Event on line 14", + "offset": 14, + "size": 1 + }, + "EVEN15": { + "description": "Enable Event on line 15", + "offset": 15, + "size": 1 + }, + "EVEN16": { + "description": "Enable Event on line 16", + "offset": 16, + "size": 1 + }, + "EVEN17": { + "description": "Enable Event on line 17", + "offset": 17, + "size": 1 + }, + "EVEN18": { + "description": "Enable Event on line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "RTEN": { + "description": "Rising Edge Trigger Enable register\n (EXTI_RTEN)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RTEN0": { + "description": "Rising edge trigger enable of\n line 0", + "offset": 0, + "size": 1 + }, + "RTEN1": { + "description": "Rising edge trigger enable of\n line 1", + "offset": 1, + "size": 1 + }, + "RTEN2": { + "description": "Rising edge trigger enable of\n line 2", + "offset": 2, + "size": 1 + }, + "RTEN3": { + "description": "Rising edge trigger enable of\n line 3", + "offset": 3, + "size": 1 + }, + "RTEN4": { + "description": "Rising edge trigger enable of\n line 4", + "offset": 4, + "size": 1 + }, + "RTEN5": { + "description": "Rising edge trigger enable of\n line 5", + "offset": 5, + "size": 1 + }, + "RTEN6": { + "description": "Rising edge trigger enable of\n line 6", + "offset": 6, + "size": 1 + }, + "RTEN7": { + "description": "Rising edge trigger enable of\n line 7", + "offset": 7, + "size": 1 + }, + "RTEN8": { + "description": "Rising edge trigger enable of\n line 8", + "offset": 8, + "size": 1 + }, + "RTEN9": { + "description": "Rising edge trigger enable of\n line 9", + "offset": 9, + "size": 1 + }, + "RTEN10": { + "description": "Rising edge trigger enable of\n line 10", + "offset": 10, + "size": 1 + }, + "RTEN11": { + "description": "Rising edge trigger enable of\n line 11", + "offset": 11, + "size": 1 + }, + "RTEN12": { + "description": "Rising edge trigger enable of\n line 12", + "offset": 12, + "size": 1 + }, + "RTEN13": { + "description": "Rising edge trigger enable of\n line 13", + "offset": 13, + "size": 1 + }, + "RTEN14": { + "description": "Rising edge trigger enable of\n line 14", + "offset": 14, + "size": 1 + }, + "RTEN15": { + "description": "Rising edge trigger enable of\n line 15", + "offset": 15, + "size": 1 + }, + "RTEN16": { + "description": "Rising edge trigger enable of\n line 16", + "offset": 16, + "size": 1 + }, + "RTEN17": { + "description": "Rising edge trigger enable of\n line 17", + "offset": 17, + "size": 1 + }, + "RTEN18": { + "description": "Rising edge trigger enable of\n line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "FTEN": { + "description": "Falling Egde Trigger Enable register\n (EXTI_FTEN)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FTEN0": { + "description": "Falling edge trigger enable of\n line 0", + "offset": 0, + "size": 1 + }, + "FTEN1": { + "description": "Falling edge trigger enable of\n line 1", + "offset": 1, + "size": 1 + }, + "FTEN2": { + "description": "Falling edge trigger enable of\n line 2", + "offset": 2, + "size": 1 + }, + "FTEN3": { + "description": "Falling edge trigger enable of\n line 3", + "offset": 3, + "size": 1 + }, + "FTEN4": { + "description": "Falling edge trigger enable of\n line 4", + "offset": 4, + "size": 1 + }, + "FTEN5": { + "description": "Falling edge trigger enable of\n line 5", + "offset": 5, + "size": 1 + }, + "FTEN6": { + "description": "Falling edge trigger enable of\n line 6", + "offset": 6, + "size": 1 + }, + "FTEN7": { + "description": "Falling edge trigger enable of\n line 7", + "offset": 7, + "size": 1 + }, + "FTEN8": { + "description": "Falling edge trigger enable of\n line 8", + "offset": 8, + "size": 1 + }, + "FTEN9": { + "description": "Falling edge trigger enable of\n line 9", + "offset": 9, + "size": 1 + }, + "FTEN10": { + "description": "Falling edge trigger enable of\n line 10", + "offset": 10, + "size": 1 + }, + "FTEN11": { + "description": "Falling edge trigger enable of\n line 11", + "offset": 11, + "size": 1 + }, + "FTEN12": { + "description": "Falling edge trigger enable of\n line 12", + "offset": 12, + "size": 1 + }, + "FTEN13": { + "description": "Falling edge trigger enable of\n line 13", + "offset": 13, + "size": 1 + }, + "FTEN14": { + "description": "Falling edge trigger enable of\n line 14", + "offset": 14, + "size": 1 + }, + "FTEN15": { + "description": "Falling edge trigger enable of\n line 15", + "offset": 15, + "size": 1 + }, + "FTEN16": { + "description": "Falling edge trigger enable of\n line 16", + "offset": 16, + "size": 1 + }, + "FTEN17": { + "description": "Falling edge trigger enable of\n line 17", + "offset": 17, + "size": 1 + }, + "FTEN18": { + "description": "Falling edge trigger enable of\n line 18", + "offset": 18, + "size": 1 + } + } + } + }, + "SWIEV": { + "description": "Software interrupt event register\n (EXTI_SWIEV)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SWIEV0": { + "description": "Interrupt/Event software trigger on line\n 0", + "offset": 0, + "size": 1 + }, + "SWIEV1": { + "description": "Interrupt/Event software trigger on line\n 1", + "offset": 1, + "size": 1 + }, + "SWIEV2": { + "description": "Interrupt/Event software trigger on line\n 2", + "offset": 2, + "size": 1 + }, + "SWIEV3": { + "description": "Interrupt/Event software trigger on line\n 3", + "offset": 3, + "size": 1 + }, + "SWIEV4": { + "description": "Interrupt/Event software trigger on line\n 4", + "offset": 4, + "size": 1 + }, + "SWIEV5": { + "description": "Interrupt/Event software trigger on line\n 5", + "offset": 5, + "size": 1 + }, + "SWIEV6": { + "description": "Interrupt/Event software trigger on line\n 6", + "offset": 6, + "size": 1 + }, + "SWIEV7": { + "description": "Interrupt/Event software trigger on line\n 7", + "offset": 7, + "size": 1 + }, + "SWIEV8": { + "description": "Interrupt/Event software trigger on line\n 8", + "offset": 8, + "size": 1 + }, + "SWIEV9": { + "description": "Interrupt/Event software trigger on line\n 9", + "offset": 9, + "size": 1 + }, + "SWIEV10": { + "description": "Interrupt/Event software trigger on line\n 10", + "offset": 10, + "size": 1 + }, + "SWIEV11": { + "description": "Interrupt/Event software trigger on line\n 11", + "offset": 11, + "size": 1 + }, + "SWIEV12": { + "description": "Interrupt/Event software trigger on line\n 12", + "offset": 12, + "size": 1 + }, + "SWIEV13": { + "description": "Interrupt/Event software trigger on line\n 13", + "offset": 13, + "size": 1 + }, + "SWIEV14": { + "description": "Interrupt/Event software trigger on line\n 14", + "offset": 14, + "size": 1 + }, + "SWIEV15": { + "description": "Interrupt/Event software trigger on line\n 15", + "offset": 15, + "size": 1 + }, + "SWIEV16": { + "description": "Interrupt/Event software trigger on line\n 16", + "offset": 16, + "size": 1 + }, + "SWIEV17": { + "description": "Interrupt/Event software trigger on line\n 17", + "offset": 17, + "size": 1 + }, + "SWIEV18": { + "description": "Interrupt/Event software trigger on line\n 18", + "offset": 18, + "size": 1 + } + } + } + }, + "PD": { + "description": "Pending register (EXTI_PD)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PD0": { + "description": "Interrupt pending status of line 0", + "offset": 0, + "size": 1 + }, + "PD1": { + "description": "Interrupt pending status of line 1", + "offset": 1, + "size": 1 + }, + "PD2": { + "description": "Interrupt pending status of line 2", + "offset": 2, + "size": 1 + }, + "PD3": { + "description": "Interrupt pending status of line 3", + "offset": 3, + "size": 1 + }, + "PD4": { + "description": "Interrupt pending status of line 4", + "offset": 4, + "size": 1 + }, + "PD5": { + "description": "Interrupt pending status of line 5", + "offset": 5, + "size": 1 + }, + "PD6": { + "description": "Interrupt pending status of line 6", + "offset": 6, + "size": 1 + }, + "PD7": { + "description": "Interrupt pending status of line 7", + "offset": 7, + "size": 1 + }, + "PD8": { + "description": "Interrupt pending status of line 8", + "offset": 8, + "size": 1 + }, + "PD9": { + "description": "Interrupt pending status of line 9", + "offset": 9, + "size": 1 + }, + "PD10": { + "description": "Interrupt pending status of line 10", + "offset": 10, + "size": 1 + }, + "PD11": { + "description": "Interrupt pending status of line 11", + "offset": 11, + "size": 1 + }, + "PD12": { + "description": "Interrupt pending status of line 12", + "offset": 12, + "size": 1 + }, + "PD13": { + "description": "Interrupt pending status of line 13", + "offset": 13, + "size": 1 + }, + "PD14": { + "description": "Interrupt pending status of line 14", + "offset": 14, + "size": 1 + }, + "PD15": { + "description": "Interrupt pending status of line 15", + "offset": 15, + "size": 1 + }, + "PD16": { + "description": "Interrupt pending status of line 16", + "offset": 16, + "size": 1 + }, + "PD17": { + "description": "Interrupt pending status of line 17", + "offset": 17, + "size": 1 + }, + "PD18": { + "description": "Interrupt pending status of line 18", + "offset": 18, + "size": 1 + } + } + } + } + } + } + }, + "FMC": { + "description": "FMC", + "children": { + "registers": { + "WS": { + "description": "wait state counter register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WSCNT": { + "description": "wait state counter register", + "offset": 0, + "size": 3 + } + } + } + }, + "KEY0": { + "description": "Unlock key register 0", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "KEY": { + "description": "FMC_CTL0 unlock key", + "offset": 0, + "size": 32 + } + } + } + }, + "OBKEY": { + "description": "Option byte unlock key register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "OBKEY": { + "description": "FMC_ CTL0 option byte operation unlock register", + "offset": 0, + "size": 32 + } + } + } + }, + "STAT0": { + "description": "Status register 0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDF": { + "description": "End of operation flag bit", + "offset": 5, + "size": 1 + }, + "WPERR": { + "description": "Erase/Program protection error flag bit", + "offset": 4, + "size": 1 + }, + "PGERR": { + "description": "Program error flag bit", + "offset": 2, + "size": 1 + }, + "BUSY": { + "description": "The flash is busy bit", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "CTL0": { + "description": "Control register 0", + "offset": 16, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "ENDIE": { + "description": "End of operation interrupt enable bit", + "offset": 12, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable bit", + "offset": 10, + "size": 1 + }, + "OBWEN": { + "description": "Option byte erase/program enable bit", + "offset": 9, + "size": 1 + }, + "LK": { + "description": "FMC_CTL0 lock bit", + "offset": 7, + "size": 1 + }, + "START": { + "description": "Send erase command to FMC bit", + "offset": 6, + "size": 1 + }, + "OBER": { + "description": "Option bytes erase command bit", + "offset": 5, + "size": 1 + }, + "OBPG": { + "description": "Option bytes program command bit", + "offset": 4, + "size": 1 + }, + "MER": { + "description": "Main flash mass erase for bank0 command bit", + "offset": 2, + "size": 1 + }, + "PER": { + "description": "Main flash page erase for bank0 command bit", + "offset": 1, + "size": 1 + }, + "PG": { + "description": "Main flash program for bank0 command bit", + "offset": 0, + "size": 1 + } + } + } + }, + "ADDR0": { + "description": "Address register 0", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "ADDR": { + "description": "Flash erase/program command address bits", + "offset": 0, + "size": 32 + } + } + } + }, + "OBSTAT": { + "description": "Option byte status register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "OBERR": { + "description": "Option bytes read error bit", + "offset": 0, + "size": 1 + }, + "SPC": { + "description": "Option bytes security protection code", + "offset": 1, + "size": 1 + }, + "USER": { + "description": "Store USER of option bytes block after system reset", + "offset": 2, + "size": 8 + }, + "DATA": { + "description": "Store DATA[15:0] of option bytes block after system reset", + "offset": 10, + "size": 16 + } + } + } + }, + "WP": { + "description": "Erase/Program Protection register", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "WP": { + "description": "Store WP[31:0] of option bytes block after system reset", + "offset": 0, + "size": 32 + } + } + } + }, + "PID": { + "description": "Product ID register", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PID": { + "description": "Product reserved ID code register", + "offset": 0, + "size": 32 + } + } + } + } + } + } + }, + "FWDGT": { + "description": "free watchdog timer", + "children": { + "registers": { + "CTL": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CMD": { + "description": "Key value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "Prescaler register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Free watchdog timer prescaler selection", + "offset": 0, + "size": 3 + } + } + } + }, + "RLD": { + "description": "Reload register", + "offset": 8, + "size": 32, + "reset_value": 4095, + "reset_mask": 4294967295, + "children": { + "fields": { + "RLD": { + "description": "Free watchdog timer counter reload value", + "offset": 0, + "size": 12 + } + } + } + }, + "STAT": { + "description": "Status register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PUD": { + "description": "Free watchdog timer prescaler value update", + "offset": 0, + "size": 1 + }, + "RUD": { + "description": "Free watchdog timer counter reload value update", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "GPIOA": { + "description": "General-purpose I/Os", + "children": { + "registers": { + "CTL0": { + "description": "port control register 0", + "offset": 0, + "size": 32, + "reset_value": 1145324612, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTL7": { + "description": "Port x configuration bits (x =\n 7)", + "offset": 30, + "size": 2 + }, + "MD7": { + "description": "Port x mode bits (x =\n 7)", + "offset": 28, + "size": 2 + }, + "CTL6": { + "description": "Port x configuration bits (x =\n 6)", + "offset": 26, + "size": 2 + }, + "MD6": { + "description": "Port x mode bits (x =\n 6)", + "offset": 24, + "size": 2 + }, + "CTL5": { + "description": "Port x configuration bits (x =\n 5)", + "offset": 22, + "size": 2 + }, + "MD5": { + "description": "Port x mode bits (x =\n 5)", + "offset": 20, + "size": 2 + }, + "CTL4": { + "description": "Port x configuration bits (x =\n 4)", + "offset": 18, + "size": 2 + }, + "MD4": { + "description": "Port x mode bits (x =\n 4)", + "offset": 16, + "size": 2 + }, + "CTL3": { + "description": "Port x configuration bits (x =\n 3)", + "offset": 14, + "size": 2 + }, + "MD3": { + "description": "Port x mode bits (x =\n 3 )", + "offset": 12, + "size": 2 + }, + "CTL2": { + "description": "Port x configuration bits (x =\n 2)", + "offset": 10, + "size": 2 + }, + "MD2": { + "description": "Port x mode bits (x =\n 2 )", + "offset": 8, + "size": 2 + }, + "CTL1": { + "description": "Port x configuration bits (x =\n 1)", + "offset": 6, + "size": 2 + }, + "MD1": { + "description": "Port x mode bits (x =\n 1)", + "offset": 4, + "size": 2 + }, + "CTL0": { + "description": "Port x configuration bits (x =\n 0)", + "offset": 2, + "size": 2 + }, + "MD0": { + "description": "Port x mode bits (x =\n 0)", + "offset": 0, + "size": 2 + } + } + } + }, + "CTL1": { + "description": "port control register 1", + "offset": 4, + "size": 32, + "reset_value": 1145324612, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTL15": { + "description": "Port x configuration bits (x =\n 15)", + "offset": 30, + "size": 2 + }, + "MD15": { + "description": "Port x mode bits (x =\n 15)", + "offset": 28, + "size": 2 + }, + "CTL14": { + "description": "Port x configuration bits (x =\n 14)", + "offset": 26, + "size": 2 + }, + "MD14": { + "description": "Port x mode bits (x =\n 14)", + "offset": 24, + "size": 2 + }, + "CTL13": { + "description": "Port x configuration bits (x =\n 13)", + "offset": 22, + "size": 2 + }, + "MD13": { + "description": "Port x mode bits (x =\n 13)", + "offset": 20, + "size": 2 + }, + "CTL12": { + "description": "Port x configuration bits (x =\n 12)", + "offset": 18, + "size": 2 + }, + "MD12": { + "description": "Port x mode bits (x =\n 12)", + "offset": 16, + "size": 2 + }, + "CTL11": { + "description": "Port x configuration bits (x =\n 11)", + "offset": 14, + "size": 2 + }, + "MD11": { + "description": "Port x mode bits (x =\n 11 )", + "offset": 12, + "size": 2 + }, + "CTL10": { + "description": "Port x configuration bits (x =\n 10)", + "offset": 10, + "size": 2 + }, + "MD10": { + "description": "Port x mode bits (x =\n 10 )", + "offset": 8, + "size": 2 + }, + "CTL9": { + "description": "Port x configuration bits (x =\n 9)", + "offset": 6, + "size": 2 + }, + "MD9": { + "description": "Port x mode bits (x =\n 9)", + "offset": 4, + "size": 2 + }, + "CTL8": { + "description": "Port x configuration bits (x =\n 8)", + "offset": 2, + "size": 2 + }, + "MD8": { + "description": "Port x mode bits (x =\n 8)", + "offset": 0, + "size": 2 + } + } + } + }, + "ISTAT": { + "description": "Port input status register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "ISTAT15": { + "description": "Port input status", + "offset": 15, + "size": 1 + }, + "ISTAT14": { + "description": "Port input status", + "offset": 14, + "size": 1 + }, + "ISTAT13": { + "description": "Port input status", + "offset": 13, + "size": 1 + }, + "ISTAT12": { + "description": "Port input status", + "offset": 12, + "size": 1 + }, + "ISTAT11": { + "description": "Port input status", + "offset": 11, + "size": 1 + }, + "ISTAT10": { + "description": "Port input status", + "offset": 10, + "size": 1 + }, + "ISTAT9": { + "description": "Port input status", + "offset": 9, + "size": 1 + }, + "ISTAT8": { + "description": "Port input status", + "offset": 8, + "size": 1 + }, + "ISTAT7": { + "description": "Port input status", + "offset": 7, + "size": 1 + }, + "ISTAT6": { + "description": "Port input status", + "offset": 6, + "size": 1 + }, + "ISTAT5": { + "description": "Port input status", + "offset": 5, + "size": 1 + }, + "ISTAT4": { + "description": "Port input status", + "offset": 4, + "size": 1 + }, + "ISTAT3": { + "description": "Port input status", + "offset": 3, + "size": 1 + }, + "ISTAT2": { + "description": "Port input status", + "offset": 2, + "size": 1 + }, + "ISTAT1": { + "description": "Port input status", + "offset": 1, + "size": 1 + }, + "ISTAT0": { + "description": "Port input status", + "offset": 0, + "size": 1 + } + } + } + }, + "OCTL": { + "description": "Port output control register", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OCTL15": { + "description": "Port output control", + "offset": 15, + "size": 1 + }, + "OCTL14": { + "description": "Port output control", + "offset": 14, + "size": 1 + }, + "OCTL13": { + "description": "Port output control", + "offset": 13, + "size": 1 + }, + "OCTL12": { + "description": "Port output control", + "offset": 12, + "size": 1 + }, + "OCTL11": { + "description": "Port output control", + "offset": 11, + "size": 1 + }, + "OCTL10": { + "description": "Port output control", + "offset": 10, + "size": 1 + }, + "OCTL9": { + "description": "Port output control", + "offset": 9, + "size": 1 + }, + "OCTL8": { + "description": "Port output control", + "offset": 8, + "size": 1 + }, + "OCTL7": { + "description": "Port output control", + "offset": 7, + "size": 1 + }, + "OCTL6": { + "description": "Port output control", + "offset": 6, + "size": 1 + }, + "OCTL5": { + "description": "Port output control", + "offset": 5, + "size": 1 + }, + "OCTL4": { + "description": "Port output control", + "offset": 4, + "size": 1 + }, + "OCTL3": { + "description": "Port output control", + "offset": 3, + "size": 1 + }, + "OCTL2": { + "description": "Port output control", + "offset": 2, + "size": 1 + }, + "OCTL1": { + "description": "Port output control", + "offset": 1, + "size": 1 + }, + "OCTL0": { + "description": "Port output control", + "offset": 0, + "size": 1 + } + } + } + }, + "BOP": { + "description": "Port bit operate register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CR15": { + "description": "Port 15 Clear bit", + "offset": 31, + "size": 1 + }, + "CR14": { + "description": "Port 14 Clear bit", + "offset": 30, + "size": 1 + }, + "CR13": { + "description": "Port 13 Clear bit", + "offset": 29, + "size": 1 + }, + "CR12": { + "description": "Port 12 Clear bit", + "offset": 28, + "size": 1 + }, + "CR11": { + "description": "Port 11 Clear bit", + "offset": 27, + "size": 1 + }, + "CR10": { + "description": "Port 10 Clear bit", + "offset": 26, + "size": 1 + }, + "CR9": { + "description": "Port 9 Clear bit", + "offset": 25, + "size": 1 + }, + "CR8": { + "description": "Port 8 Clear bit", + "offset": 24, + "size": 1 + }, + "CR7": { + "description": "Port 7 Clear bit", + "offset": 23, + "size": 1 + }, + "CR6": { + "description": "Port 6 Clear bit", + "offset": 22, + "size": 1 + }, + "CR5": { + "description": "Port 5 Clear bit", + "offset": 21, + "size": 1 + }, + "CR4": { + "description": "Port 4 Clear bit", + "offset": 20, + "size": 1 + }, + "CR3": { + "description": "Port 3 Clear bit", + "offset": 19, + "size": 1 + }, + "CR2": { + "description": "Port 2 Clear bit", + "offset": 18, + "size": 1 + }, + "CR1": { + "description": "Port 1 Clear bit", + "offset": 17, + "size": 1 + }, + "CR0": { + "description": "Port 0 Clear bit", + "offset": 16, + "size": 1 + }, + "BOP15": { + "description": "Port 15 Set bit", + "offset": 15, + "size": 1 + }, + "BOP14": { + "description": "Port 14 Set bit", + "offset": 14, + "size": 1 + }, + "BOP13": { + "description": "Port 13 Set bit", + "offset": 13, + "size": 1 + }, + "BOP12": { + "description": "Port 12 Set bit", + "offset": 12, + "size": 1 + }, + "BOP11": { + "description": "Port 11 Set bit", + "offset": 11, + "size": 1 + }, + "BOP10": { + "description": "Port 10 Set bit", + "offset": 10, + "size": 1 + }, + "BOP9": { + "description": "Port 9 Set bit", + "offset": 9, + "size": 1 + }, + "BOP8": { + "description": "Port 8 Set bit", + "offset": 8, + "size": 1 + }, + "BOP7": { + "description": "Port 7 Set bit", + "offset": 7, + "size": 1 + }, + "BOP6": { + "description": "Port 6 Set bit", + "offset": 6, + "size": 1 + }, + "BOP5": { + "description": "Port 5 Set bit", + "offset": 5, + "size": 1 + }, + "BOP4": { + "description": "Port 4 Set bit", + "offset": 4, + "size": 1 + }, + "BOP3": { + "description": "Port 3 Set bit", + "offset": 3, + "size": 1 + }, + "BOP2": { + "description": "Port 2 Set bit", + "offset": 2, + "size": 1 + }, + "BOP1": { + "description": "Port 1 Set bit", + "offset": 1, + "size": 1 + }, + "BOP0": { + "description": "Port 0 Set bit", + "offset": 0, + "size": 1 + } + } + } + }, + "BC": { + "description": "Port bit clear register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "CR15": { + "description": "Port 15 Clear bit", + "offset": 15, + "size": 1 + }, + "CR14": { + "description": "Port 14 Clear bit", + "offset": 14, + "size": 1 + }, + "CR13": { + "description": "Port 13 Clear bit", + "offset": 13, + "size": 1 + }, + "CR12": { + "description": "Port 12 Clear bit", + "offset": 12, + "size": 1 + }, + "CR11": { + "description": "Port 11 Clear bit", + "offset": 11, + "size": 1 + }, + "CR10": { + "description": "Port 10 Clear bit", + "offset": 10, + "size": 1 + }, + "CR9": { + "description": "Port 9 Clear bit", + "offset": 9, + "size": 1 + }, + "CR8": { + "description": "Port 8 Clear bit", + "offset": 8, + "size": 1 + }, + "CR7": { + "description": "Port 7 Clear bit", + "offset": 7, + "size": 1 + }, + "CR6": { + "description": "Port 6 Clear bit", + "offset": 6, + "size": 1 + }, + "CR5": { + "description": "Port 5 Clear bit", + "offset": 5, + "size": 1 + }, + "CR4": { + "description": "Port 4 Clear bit", + "offset": 4, + "size": 1 + }, + "CR3": { + "description": "Port 3 Clear bit", + "offset": 3, + "size": 1 + }, + "CR2": { + "description": "Port 2 Clear bit", + "offset": 2, + "size": 1 + }, + "CR1": { + "description": "Port 1 Clear bit", + "offset": 1, + "size": 1 + }, + "CR0": { + "description": "Port 0 Clear bit", + "offset": 0, + "size": 1 + } + } + } + }, + "LOCK": { + "description": "GPIO port configuration lock\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LKK": { + "description": "Lock sequence key\n ", + "offset": 16, + "size": 1 + }, + "LK15": { + "description": "Port Lock bit 15", + "offset": 15, + "size": 1 + }, + "LK14": { + "description": "Port Lock bit 14", + "offset": 14, + "size": 1 + }, + "LK13": { + "description": "Port Lock bit 13", + "offset": 13, + "size": 1 + }, + "LK12": { + "description": "Port Lock bit 12", + "offset": 12, + "size": 1 + }, + "LK11": { + "description": "Port Lock bit 11", + "offset": 11, + "size": 1 + }, + "LK10": { + "description": "Port Lock bit 10", + "offset": 10, + "size": 1 + }, + "LK9": { + "description": "Port Lock bit 9", + "offset": 9, + "size": 1 + }, + "LK8": { + "description": "Port Lock bit 8", + "offset": 8, + "size": 1 + }, + "LK7": { + "description": "Port Lock bit 7", + "offset": 7, + "size": 1 + }, + "LK6": { + "description": "Port Lock bit 6", + "offset": 6, + "size": 1 + }, + "LK5": { + "description": "Port Lock bit 5", + "offset": 5, + "size": 1 + }, + "LK4": { + "description": "Port Lock bit 4", + "offset": 4, + "size": 1 + }, + "LK3": { + "description": "Port Lock bit 3", + "offset": 3, + "size": 1 + }, + "LK2": { + "description": "Port Lock bit 2", + "offset": 2, + "size": 1 + }, + "LK1": { + "description": "Port Lock bit 1", + "offset": 1, + "size": 1 + }, + "LK0": { + "description": "Port Lock bit 0", + "offset": 0, + "size": 1 + } + } + } + } + } + } + }, + "USBFS_PWRCLK": { + "description": "USB on the go full speed", + "children": { + "registers": { + "PWRCLKCTL": { + "description": "power and clock gating control\n register (PWRCLKCTL)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SUCLK": { + "description": "Stop the USB clock", + "offset": 0, + "size": 1 + }, + "SHCLK": { + "description": "Stop HCLK", + "offset": 1, + "size": 1 + } + } + } + } + } + } + }, + "USBFS_DEVICE": { + "description": "USB on the go full speed device", + "children": { + "registers": { + "DCFG": { + "description": "device configuration register\n (DCFG)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DS": { + "description": "Device speed", + "offset": 0, + "size": 2 + }, + "NZLSOH": { + "description": "Non-zero-length status OUT\n handshake", + "offset": 2, + "size": 1 + }, + "DAR": { + "description": "Device address", + "offset": 4, + "size": 7 + }, + "EOPFT": { + "description": "end of periodic frame time", + "offset": 11, + "size": 2 + } + } + } + }, + "DCTL": { + "description": "device control register\n (DCTL)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "RWKUP": { + "description": "Remote wakeup", + "offset": 0, + "size": 1 + }, + "SD": { + "description": "Soft disconnect", + "offset": 1, + "size": 1 + }, + "GINS": { + "description": "Global IN NAK status", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "GONS": { + "description": "Global OUT NAK status", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "SGINAK": { + "description": "Set global IN NAK", + "offset": 7, + "size": 1, + "access": "write-only" + }, + "CGINAK": { + "description": "Clear global IN NAK", + "offset": 8, + "size": 1, + "access": "write-only" + }, + "SGONAK": { + "description": "Set global OUT NAK", + "offset": 9, + "size": 1, + "access": "write-only" + }, + "CGONAK": { + "description": "Clear global OUT NAK", + "offset": 10, + "size": 1, + "access": "write-only" + }, + "POIF": { + "description": "Power-on initialization flag", + "offset": 11, + "size": 1 + } + } + } + }, + "DSTAT": { + "description": "device status register\n (DSTAT)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "SPST": { + "description": "Suspend status", + "offset": 0, + "size": 1 + }, + "ES": { + "description": "Enumerated speed", + "offset": 1, + "size": 2 + }, + "FNRSOF": { + "description": "Frame number of the received\n SOF", + "offset": 8, + "size": 14 + } + } + } + }, + "DIEPINTEN": { + "description": "device IN endpoint common interrupt\n mask register (DIEPINTEN)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFEN": { + "description": "Transfer finished interrupt\n enable", + "offset": 0, + "size": 1 + }, + "EPDISEN": { + "description": "Endpoint disabled interrupt\n enable", + "offset": 1, + "size": 1 + }, + "CITOEN": { + "description": "Control IN timeout condition interrupt enable (Non-isochronous\n endpoints)", + "offset": 3, + "size": 1 + }, + "EPTXFUDEN": { + "description": "Endpoint Tx FIFO underrun interrupt enable bit", + "offset": 4, + "size": 1 + }, + "IEPNEEN": { + "description": "IN endpoint NAK effective\n interrupt enable", + "offset": 6, + "size": 1 + } + } + } + }, + "DOEPINTEN": { + "description": "device OUT endpoint common interrupt\n enable register (DOEPINTEN)", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFEN": { + "description": "Transfer finished interrupt\n enable", + "offset": 0, + "size": 1 + }, + "EPDISEN": { + "description": "Endpoint disabled interrupt\n enable", + "offset": 1, + "size": 1 + }, + "STPFEN": { + "description": "SETUP phase finished interrupt enable", + "offset": 3, + "size": 1 + }, + "EPRXFOVREN": { + "description": " Endpoint Rx FIFO overrun interrupt enable", + "offset": 4, + "size": 1 + }, + "BTBSTPEN": { + "description": " Back-to-back SETUP packets\n interrupt enable", + "offset": 6, + "size": 1 + } + } + } + }, + "DAEPINT": { + "description": "device all endpoints interrupt\n register (DAEPINT)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPITB": { + "description": "Device all IN endpoint interrupt bits", + "offset": 0, + "size": 4 + }, + "OEPITB": { + "description": "Device all OUT endpoint interrupt bits", + "offset": 16, + "size": 4 + } + } + } + }, + "DAEPINTEN": { + "description": "Device all endpoints interrupt enable register\n (DAEPINTEN)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPIE": { + "description": "IN EP interrupt interrupt enable bits", + "offset": 0, + "size": 4 + }, + "OEPIE": { + "description": "OUT endpoint interrupt enable bits", + "offset": 16, + "size": 4 + } + } + } + }, + "DVBUSDT": { + "description": "device VBUS discharge time\n register", + "offset": 40, + "size": 32, + "reset_value": 6103, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSDT": { + "description": "Device VBUS discharge time", + "offset": 0, + "size": 16 + } + } + } + }, + "DVBUSPT": { + "description": "device VBUS pulsing time\n register", + "offset": 44, + "size": 32, + "reset_value": 1464, + "reset_mask": 4294967295, + "children": { + "fields": { + "DVBUSPT": { + "description": "Device VBUS pulsing time", + "offset": 0, + "size": 12 + } + } + } + }, + "DIEPFEINTEN": { + "description": "device IN endpoint FIFO empty\n interrupt enable register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPTXFEIE": { + "description": "IN EP Tx FIFO empty interrupt enable\n bits", + "offset": 0, + "size": 4 + } + } + } + }, + "DIEP0CTL": { + "description": "device IN endpoint 0 control\n register (DIEP0CTL)", + "offset": 256, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet length", + "offset": 0, + "size": 2 + }, + "EPACT": { + "description": "endpoint active", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 22, + "size": 4 + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + } + } + } + }, + "DIEP1CTL": { + "description": "device in endpoint-1 control\n register", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "Set DATA1 PID/Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "Tx FIFO number", + "offset": 22, + "size": 4 + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEP2CTL": { + "description": "device endpoint-2 control\n register", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "Set DATA1 PID/Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "Tx FIFO number", + "offset": 22, + "size": 4 + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEP3CTL": { + "description": "device endpoint-3 control\n register", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "Set DATA1 PID/Set odd frame", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVNFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "TXFNUM": { + "description": "Tx FIFO number", + "offset": 22, + "size": 4 + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEP0CTL": { + "description": "device endpoint-0 control\n register", + "offset": 768, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "SNOOP": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2, + "access": "read-only" + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1, + "access": "read-only" + }, + "MPL": { + "description": "Maximum packet length", + "offset": 0, + "size": 2, + "access": "read-only" + } + } + } + }, + "DOEP1CTL": { + "description": "device endpoint-1 control\n register", + "offset": 800, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "SD1PID/SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVENFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "SNOOP": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEP2CTL": { + "description": "device endpoint-2 control\n register", + "offset": 832, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "SD1PID/SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVENFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "SNOOP": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DOEP3CTL": { + "description": "device endpoint-3 control\n register", + "offset": 864, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "EPEN": { + "description": "Endpoint enable", + "offset": 31, + "size": 1 + }, + "EPD": { + "description": "Endpoint disable", + "offset": 30, + "size": 1 + }, + "SD1PID_SODDFRM": { + "description": "SD1PID/SODDFRM", + "offset": 29, + "size": 1, + "access": "write-only" + }, + "SD0PID_SEVENFRM": { + "description": "SD0PID/SEVENFRM", + "offset": 28, + "size": 1, + "access": "write-only" + }, + "SNAK": { + "description": "Set NAK", + "offset": 27, + "size": 1, + "access": "write-only" + }, + "CNAK": { + "description": "Clear NAK", + "offset": 26, + "size": 1, + "access": "write-only" + }, + "STALL": { + "description": "STALL handshake", + "offset": 21, + "size": 1 + }, + "SNOOP": { + "description": "Snoop mode", + "offset": 20, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "NAKS": { + "description": "NAK status", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "EOFRM_DPID": { + "description": "EOFRM/DPID", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "EPACT": { + "description": "Endpoint active", + "offset": 15, + "size": 1 + }, + "MPL": { + "description": "maximum packet length", + "offset": 0, + "size": 11 + } + } + } + }, + "DIEP0INTF": { + "description": "device endpoint-0 interrupt\n register", + "offset": 264, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "IEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "EPTXFUD": { + "description": "Endpoint Tx FIFO underrun", + "offset": 4, + "size": 1 + }, + "CITO": { + "description": "Control in timeout interrupt", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint finished", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEP1INTF": { + "description": "device endpoint-1 interrupt\n register", + "offset": 296, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "IEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "EPTXFUD": { + "description": "Endpoint Tx FIFO underrun", + "offset": 4, + "size": 1 + }, + "CITO": { + "description": "Control in timeout interrupt", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint finished", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEP2INTF": { + "description": "device endpoint-2 interrupt\n register", + "offset": 328, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "IEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "EPTXFUD": { + "description": "Endpoint Tx FIFO underrun", + "offset": 4, + "size": 1 + }, + "CITO": { + "description": "Control in timeout interrupt", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint finished", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEP3INTF": { + "description": "device endpoint-3 interrupt\n register", + "offset": 360, + "size": 32, + "reset_value": 128, + "reset_mask": 4294967295, + "children": { + "fields": { + "TXFE": { + "description": "Transmit FIFO empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "IEPNE": { + "description": "IN endpoint NAK effective", + "offset": 6, + "size": 1 + }, + "EPTXFUD": { + "description": "Endpoint Tx FIFO underrun", + "offset": 4, + "size": 1 + }, + "CITO": { + "description": "Control in timeout interrupt", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint finished", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEP0INTF": { + "description": "device out endpoint-0 interrupt flag \n register", + "offset": 776, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTBSTP": { + "description": "Back-to-back SETUP packets", + "offset": 6, + "size": 1 + }, + "EPRXFOVR": { + "description": "Endpoint Rx FIFO overrun", + "offset": 4, + "size": 1 + }, + "STPF": { + "description": "Setup phase finished", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint disabled", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEP1INTF": { + "description": "device out endpoint-1 interrupt flag \n register", + "offset": 808, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTBSTP": { + "description": "Back-to-back SETUP packets", + "offset": 6, + "size": 1 + }, + "EPRXFOVR": { + "description": "Endpoint Rx FIFO overrun", + "offset": 4, + "size": 1 + }, + "STPF": { + "description": "Setup phase finished", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint disabled", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEP2INTF": { + "description": "device out endpoint-2 interrupt flag \n register", + "offset": 840, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTBSTP": { + "description": "Back-to-back SETUP packets", + "offset": 6, + "size": 1 + }, + "EPRXFOVR": { + "description": "Endpoint Rx FIFO overrun", + "offset": 4, + "size": 1 + }, + "STPF": { + "description": "Setup phase finished", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint disabled", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DOEP3INTF": { + "description": "device out endpoint-3 interrupt flag \n register", + "offset": 872, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BTBSTP": { + "description": "Back-to-back SETUP packets", + "offset": 6, + "size": 1 + }, + "EPRXFOVR": { + "description": "Endpoint Rx FIFO overrun", + "offset": 4, + "size": 1 + }, + "STPF": { + "description": "Setup phase finished", + "offset": 3, + "size": 1 + }, + "EPDIS": { + "description": "Endpoint disabled", + "offset": 1, + "size": 1 + }, + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + } + } + } + }, + "DIEP0LEN": { + "description": "device IN endpoint-0 transfer length\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 2 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 7 + } + } + } + }, + "DOEP0LEN": { + "description": "device OUT endpoint-0 transfer length\n register", + "offset": 784, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPCNT": { + "description": "SETUP packet count", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 1 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 7 + } + } + } + }, + "DIEP1LEN": { + "description": "device IN endpoint-1 transfer length\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCPF": { + "description": "Multi packet count per frame", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEP2LEN": { + "description": "device IN endpoint-2 transfer length\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCPF": { + "description": "Multi packet count per frame", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEP3LEN": { + "description": "device IN endpoint-3 transfer length\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCPF": { + "description": "Multi packet count per frame", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEP1LEN": { + "description": "device OUT endpoint-1 transfer length\n register", + "offset": 816, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPCNT_RXDPID": { + "description": "SETUP packet count/Received data PID", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEP2LEN": { + "description": "device OUT endpoint-2 transfer length\n register", + "offset": 848, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPCNT_RXDPID": { + "description": "SETUP packet count/Received data PID", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DOEP3LEN": { + "description": "device OUT endpoint-3 transfer length\n register", + "offset": 880, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "STPCNT_RXDPID": { + "description": "SETUP packet count/Received data PID", + "offset": 29, + "size": 2 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + } + } + } + }, + "DIEP0TFSTAT": { + "description": "device IN endpoint 0 transmit FIFO\n status register", + "offset": 280, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPTFS": { + "description": "IN endpoint TxFIFO space\n remaining", + "offset": 0, + "size": 16 + } + } + } + }, + "DIEP1TFSTAT": { + "description": "device IN endpoint 1 transmit FIFO\n status register", + "offset": 312, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPTFS": { + "description": "IN endpoint TxFIFO space\n remaining", + "offset": 0, + "size": 16 + } + } + } + }, + "DIEP2TFSTAT": { + "description": "device IN endpoint 2 transmit FIFO\n status register", + "offset": 344, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPTFS": { + "description": "IN endpoint TxFIFO space\n remaining", + "offset": 0, + "size": 16 + } + } + } + }, + "DIEP3TFSTAT": { + "description": "device IN endpoint 3 transmit FIFO\n status register", + "offset": 376, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "IEPTFS": { + "description": "IN endpoint TxFIFO space\n remaining", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "USBFS_HOST": { + "description": "USB on the go full speed host", + "children": { + "registers": { + "HCTL": { + "description": "host configuration register\n (HCTL)", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CLKSEL": { + "description": "clock select for USB clock", + "offset": 0, + "size": 2 + } + } + } + }, + "HFT": { + "description": "Host frame interval\n register", + "offset": 4, + "size": 32, + "reset_value": 48000, + "reset_mask": 4294967295, + "children": { + "fields": { + "FRI": { + "description": "Frame interval", + "offset": 0, + "size": 16 + } + } + } + }, + "HFINFR": { + "description": "FS host frame number/frame time\n remaining register (HFINFR)", + "offset": 8, + "size": 32, + "reset_value": 3145728000, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "FRNUM": { + "description": "Frame number", + "offset": 0, + "size": 16 + }, + "FRT": { + "description": "Frame remaining time", + "offset": 16, + "size": 16 + } + } + } + }, + "HPTFQSTAT": { + "description": "Host periodic transmit FIFO/queue\n status register (HPTFQSTAT)", + "offset": 16, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "children": { + "fields": { + "PTXFS": { + "description": "Periodic transmit data FIFO space\n available", + "offset": 0, + "size": 16, + "access": "read-only" + }, + "PTXREQS": { + "description": "Periodic transmit request queue space\n available", + "offset": 16, + "size": 8, + "access": "read-only" + }, + "PTXREQT": { + "description": "Top of the periodic transmit request\n queue", + "offset": 24, + "size": 8, + "access": "read-only" + } + } + } + }, + "HACHINT": { + "description": " Host all channels interrupt\n register", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "HACHINT": { + "description": "Host all channel interrupts", + "offset": 0, + "size": 8 + } + } + } + }, + "HACHINTEN": { + "description": "host all channels interrupt mask\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CINTEN": { + "description": "Channel interrupt enable", + "offset": 0, + "size": 8 + } + } + } + }, + "HPCS": { + "description": "Host port control and status register (USBFS_HPCS)", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PCST": { + "description": "Port connect status", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "PCD": { + "description": "Port connect detected", + "offset": 1, + "size": 1 + }, + "PE": { + "description": "Port enable", + "offset": 2, + "size": 1 + }, + "PEDC": { + "description": "Port enable/disable change", + "offset": 3, + "size": 1 + }, + "PREM": { + "description": "Port resume", + "offset": 6, + "size": 1 + }, + "PSP": { + "description": "Port suspend", + "offset": 7, + "size": 1 + }, + "PRST": { + "description": "Port reset", + "offset": 8, + "size": 1 + }, + "PLST": { + "description": "Port line status", + "offset": 10, + "size": 2, + "access": "read-only" + }, + "PP": { + "description": "Port power", + "offset": 12, + "size": 1 + }, + "PS": { + "description": "Port speed", + "offset": 17, + "size": 2, + "access": "read-only" + } + } + } + }, + "HCH0CTL": { + "description": "host channel-0 characteristics\n register (HCH0CTL)", + "offset": 256, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH1CTL": { + "description": " host channel-1 characteristics\n register (HCH1CTL)", + "offset": 288, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH2CTL": { + "description": "host channel-2 characteristics\n register (HCH2CTL)", + "offset": 320, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH3CTL": { + "description": "host channel-3 characteristics\n register (HCH3CTL)", + "offset": 352, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH4CTL": { + "description": " host channel-4 characteristics\n register (HCH4CTL)", + "offset": 384, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH5CTL": { + "description": "host channel-5 characteristics\n register (HCH5CTL)", + "offset": 416, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH6CTL": { + "description": "host channel-6 characteristics\n register (HCH6CTL)", + "offset": 448, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH7CTL": { + "description": "host channel-7 characteristics\n register (HCH7CTL)", + "offset": 480, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MPL": { + "description": "Maximum packet size", + "offset": 0, + "size": 11 + }, + "EPNUM": { + "description": "Endpoint number", + "offset": 11, + "size": 4 + }, + "EPDIR": { + "description": "Endpoint direction", + "offset": 15, + "size": 1 + }, + "LSD": { + "description": "Low-speed device", + "offset": 17, + "size": 1 + }, + "EPTYPE": { + "description": "Endpoint type", + "offset": 18, + "size": 2 + }, + "DAR": { + "description": "Device address", + "offset": 22, + "size": 7 + }, + "ODDFRM": { + "description": "Odd frame", + "offset": 29, + "size": 1 + }, + "CDIS": { + "description": "Channel disable", + "offset": 30, + "size": 1 + }, + "CEN": { + "description": "Channel enable", + "offset": 31, + "size": 1 + } + } + } + }, + "HCH0INTF": { + "description": "host channel-0 interrupt register\n (USBFS_HCHxINTF)", + "offset": 264, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH1INTF": { + "description": "host channel-1 interrupt register\n (HCH1INTF)", + "offset": 296, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH2INTF": { + "description": "host channel-2 interrupt register\n (HCH2INTF)", + "offset": 328, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH3INTF": { + "description": "host channel-3 interrupt register\n (HCH3INTF)", + "offset": 360, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH4INTF": { + "description": "host channel-4 interrupt register\n (HCH4INTF)", + "offset": 392, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH5INTF": { + "description": "host channel-5 interrupt register\n (HCH5INTF)", + "offset": 424, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH6INTF": { + "description": "host channel-6 interrupt register\n (HCH6INTF)", + "offset": 456, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH7INTF": { + "description": "host channel-7 interrupt register\n (HCH7INTF)", + "offset": 488, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TF": { + "description": "Transfer finished", + "offset": 0, + "size": 1 + }, + "CH": { + "description": "Channel halted", + "offset": 1, + "size": 1 + }, + "STALL": { + "description": "STALL response received\n interrupt", + "offset": 3, + "size": 1 + }, + "NAK": { + "description": "NAK response received\n interrupt", + "offset": 4, + "size": 1 + }, + "ACK": { + "description": "ACK response received/transmitted\n interrupt", + "offset": 5, + "size": 1 + }, + "USBER": { + "description": "USB bus error", + "offset": 7, + "size": 1 + }, + "BBER": { + "description": "Babble error", + "offset": 8, + "size": 1 + }, + "REQOVR": { + "description": "Request queue overrun", + "offset": 9, + "size": 1 + }, + "DTER": { + "description": "Data toggle error", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH0INTEN": { + "description": "host channel-0 interrupt enable register\n (HCH0INTEN)", + "offset": 268, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH1INTEN": { + "description": "host channel-1 interrupt enable register\n (HCH1INTEN)", + "offset": 300, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH2INTEN": { + "description": "host channel-2 interrupt enable register\n (HCH2INTEN)", + "offset": 332, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH3INTEN": { + "description": "host channel-3 interrupt enable register\n (HCH3INTEN)", + "offset": 364, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH4INTEN": { + "description": "host channel-4 interrupt enable register\n (HCH4INTEN)", + "offset": 396, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH5INTEN": { + "description": "host channel-5 interrupt enable register\n (HCH5INTEN)", + "offset": 428, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH6INTEN": { + "description": "host channel-6 interrupt enable register\n (HCH6INTEN)", + "offset": 460, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH7INTEN": { + "description": "host channel-7 interrupt enable register\n (HCH7INTEN)", + "offset": 492, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TFIE": { + "description": "Transfer completed interrupt enable", + "offset": 0, + "size": 1 + }, + "CHIE": { + "description": "Channel halted interrupt enable", + "offset": 1, + "size": 1 + }, + "STALLIE": { + "description": "STALL interrupt enable", + "offset": 3, + "size": 1 + }, + "NAKIE": { + "description": "NAK interrupt enable", + "offset": 4, + "size": 1 + }, + "ACKIE": { + "description": "ACK interrupt enable", + "offset": 5, + "size": 1 + }, + "USBERIE": { + "description": "USB bus error interrupt enable", + "offset": 7, + "size": 1 + }, + "BBERIE": { + "description": "Babble error interrupt enable", + "offset": 8, + "size": 1 + }, + "REQOVRIE": { + "description": "request queue overrun interrupt enable", + "offset": 9, + "size": 1 + }, + "DTERIE": { + "description": "Data toggle error interrupt enable", + "offset": 10, + "size": 1 + } + } + } + }, + "HCH0LEN": { + "description": "host channel-0 transfer length\n register", + "offset": 272, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH1LEN": { + "description": "host channel-1 transfer length\n register", + "offset": 304, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH2LEN": { + "description": " host channel-2 transfer length\n register", + "offset": 336, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH3LEN": { + "description": " host channel-3 transfer length\n register", + "offset": 368, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH4LEN": { + "description": "host channel-4 transfer length\n register", + "offset": 400, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH5LEN": { + "description": "host channel-5 transfer length\n register", + "offset": 432, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH6LEN": { + "description": "host channel-6 transfer length\n register", + "offset": 464, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + }, + "HCH7LEN": { + "description": "host channel-7 transfer length\n register", + "offset": 496, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TLEN": { + "description": "Transfer length", + "offset": 0, + "size": 19 + }, + "PCNT": { + "description": "Packet count", + "offset": 19, + "size": 10 + }, + "DPID": { + "description": "Data PID", + "offset": 29, + "size": 2 + } + } + } + } + } + } + }, + "USBFS_GLOBAL": { + "description": "USB full speed global registers", + "children": { + "registers": { + "GOTGCS": { + "description": "Global OTG control and status register \n (USBFS_GOTGCS)", + "offset": 0, + "size": 32, + "reset_value": 2048, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRPS": { + "description": "SRP success", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "SRPREQ": { + "description": "SRP request", + "offset": 1, + "size": 1 + }, + "HNPS": { + "description": "Host success", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "HNPREQ": { + "description": "HNP request", + "offset": 9, + "size": 1 + }, + "HHNPEN": { + "description": "Host HNP enable", + "offset": 10, + "size": 1 + }, + "DHNPEN": { + "description": "Device HNP enabled", + "offset": 11, + "size": 1 + }, + "IDPS": { + "description": "ID pin status", + "offset": 16, + "size": 1, + "access": "read-only" + }, + "DI": { + "description": "Debounce interval", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "ASV": { + "description": "A-session valid", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "BSV": { + "description": "B-session valid", + "offset": 19, + "size": 1, + "access": "read-only" + } + } + } + }, + "GOTGINTF": { + "description": "Global OTG interrupt flag register\n (USBFS_GOTGINTF)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SESEND": { + "description": "Session end ", + "offset": 2, + "size": 1 + }, + "SRPEND": { + "description": "Session request success status\n change", + "offset": 8, + "size": 1 + }, + "HNPEND": { + "description": "HNP end", + "offset": 9, + "size": 1 + }, + "HNPDET": { + "description": "Host negotiation request detected", + "offset": 17, + "size": 1 + }, + "ADTO": { + "description": "A-device timeout", + "offset": 18, + "size": 1 + }, + "DF": { + "description": "Debounce finish", + "offset": 19, + "size": 1 + } + } + } + }, + "GAHBCS": { + "description": "Global AHB control and status register\n (USBFS_GAHBCS)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GINTEN": { + "description": "Global interrupt enable", + "offset": 0, + "size": 1 + }, + "TXFTH": { + "description": "Tx FIFO threshold", + "offset": 7, + "size": 1 + }, + "PTXFTH": { + "description": "Periodic Tx FIFO threshold", + "offset": 8, + "size": 1 + } + } + } + }, + "GUSBCS": { + "description": "Global USB control and status register\n (USBFS_GUSBCSR)", + "offset": 12, + "size": 32, + "reset_value": 2688, + "reset_mask": 4294967295, + "children": { + "fields": { + "TOC": { + "description": "Timeout calibration", + "offset": 0, + "size": 3 + }, + "SRPCEN": { + "description": "SRP capability enable", + "offset": 8, + "size": 1 + }, + "HNPCEN": { + "description": "HNP capability enable", + "offset": 9, + "size": 1 + }, + "UTT": { + "description": "USB turnaround time", + "offset": 10, + "size": 4 + }, + "FHM": { + "description": "Force host mode", + "offset": 29, + "size": 1 + }, + "FDM": { + "description": "Force device mode", + "offset": 30, + "size": 1 + } + } + } + }, + "GRSTCTL": { + "description": "Global reset control register (USBFS_GRSTCTL)", + "offset": 16, + "size": 32, + "reset_value": 2147483648, + "reset_mask": 4294967295, + "children": { + "fields": { + "CSRST": { + "description": "Core soft reset", + "offset": 0, + "size": 1 + }, + "HCSRST": { + "description": "HCLK soft reset", + "offset": 1, + "size": 1 + }, + "HFCRST": { + "description": "Host frame counter reset", + "offset": 2, + "size": 1 + }, + "RXFF": { + "description": "RxFIFO flush", + "offset": 4, + "size": 1 + }, + "TXFF": { + "description": "TxFIFO flush", + "offset": 5, + "size": 1 + }, + "TXFNUM": { + "description": "TxFIFO number", + "offset": 6, + "size": 5 + } + } + } + }, + "GINTF": { + "description": "Global interrupt flag register (USBFS_GINTF)", + "offset": 20, + "size": 32, + "reset_value": 67108897, + "reset_mask": 4294967295, + "children": { + "fields": { + "COPM": { + "description": "Current operation mode", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "MFIF": { + "description": "Mode fault interrupt flag", + "offset": 1, + "size": 1 + }, + "OTGIF": { + "description": "OTG interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "SOF": { + "description": "Start of frame", + "offset": 3, + "size": 1 + }, + "RXFNEIF": { + "description": "RxFIFO non-empty interrupt flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "NPTXFEIF": { + "description": "Non-periodic TxFIFO empty interrupt flag", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "GNPINAK": { + "description": "Global Non-Periodic IN NAK effective", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "GONAK": { + "description": "Global OUT NAK effective", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "ESP": { + "description": "Early suspend", + "offset": 10, + "size": 1 + }, + "SP": { + "description": "USB suspend", + "offset": 11, + "size": 1 + }, + "RST": { + "description": "USB reset", + "offset": 12, + "size": 1 + }, + "ENUMF": { + "description": "Enumeration finished", + "offset": 13, + "size": 1 + }, + "ISOOPDIF": { + "description": "Isochronous OUT packet dropped\n interrupt", + "offset": 14, + "size": 1 + }, + "EOPFIF": { + "description": "End of periodic frame\n interrupt flag", + "offset": 15, + "size": 1 + }, + "IEPIF": { + "description": "IN endpoint interrupt flag", + "offset": 18, + "size": 1, + "access": "read-only" + }, + "OEPIF": { + "description": "OUT endpoint interrupt flag", + "offset": 19, + "size": 1, + "access": "read-only" + }, + "ISOINCIF": { + "description": "Isochronous IN transfer Not Complete Interrupt Flag", + "offset": 20, + "size": 1 + }, + "PXNCIF_ISOONCIF": { + "description": "periodic transfer not complete interrupt flag(Host\n mode)/isochronous OUT transfer not complete interrupt flag(Device\n mode)", + "offset": 21, + "size": 1 + }, + "HPIF": { + "description": "Host port interrupt flag", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIF": { + "description": "Host channels interrupt flag", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PTXFEIF": { + "description": "Periodic TxFIFO empty interrupt flag", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "IDPSC": { + "description": "ID pin status change", + "offset": 28, + "size": 1 + }, + "DISCIF": { + "description": "Disconnect interrupt flag", + "offset": 29, + "size": 1 + }, + "SESIF": { + "description": "Session interrupt flag", + "offset": 30, + "size": 1 + }, + "WKUPIF": { + "description": "Wakeup interrupt flag", + "offset": 31, + "size": 1 + } + } + } + }, + "GINTEN": { + "description": "Global interrupt enable register\n (USBFS_GINTEN)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MFIE": { + "description": "Mode fault interrupt\n enable", + "offset": 1, + "size": 1 + }, + "OTGIE": { + "description": "OTG interrupt enable ", + "offset": 2, + "size": 1 + }, + "SOFIE": { + "description": "Start of frame interrupt enable", + "offset": 3, + "size": 1 + }, + "RXFNEIE": { + "description": "Receive FIFO non-empty\n interrupt enable", + "offset": 4, + "size": 1 + }, + "NPTXFEIE": { + "description": "Non-periodic TxFIFO empty\n interrupt enable", + "offset": 5, + "size": 1 + }, + "GNPINAKIE": { + "description": "Global non-periodic IN NAK effective interrupt enable", + "offset": 6, + "size": 1 + }, + "GONAKIE": { + "description": "Global OUT NAK effective\n interrupt enable", + "offset": 7, + "size": 1 + }, + "ESPIE": { + "description": "Early suspend interrupt enable", + "offset": 10, + "size": 1 + }, + "SPIE": { + "description": "USB suspend interrupt enable", + "offset": 11, + "size": 1 + }, + "RSTIE": { + "description": "USB reset interrupt enable", + "offset": 12, + "size": 1 + }, + "ENUMFIE": { + "description": "Enumeration finish interrupt enable", + "offset": 13, + "size": 1 + }, + "ISOOPDIE": { + "description": "Isochronous OUT packet dropped interrupt enable", + "offset": 14, + "size": 1 + }, + "EOPFIE": { + "description": "End of periodic frame interrupt enable", + "offset": 15, + "size": 1 + }, + "IEPIE": { + "description": "IN endpoints interrupt enable", + "offset": 18, + "size": 1 + }, + "OEPIE": { + "description": "OUT endpoints interrupt enable", + "offset": 19, + "size": 1 + }, + "ISOINCIE": { + "description": "isochronous IN transfer not complete\n interrupt enable", + "offset": 20, + "size": 1 + }, + "PXNCIE_ISOONCIE": { + "description": "periodic transfer not compelete Interrupt enable(Host\n mode)/isochronous OUT transfer not complete interrupt enable(Device\n mode)", + "offset": 21, + "size": 1 + }, + "HPIE": { + "description": "Host port interrupt enable", + "offset": 24, + "size": 1, + "access": "read-only" + }, + "HCIE": { + "description": "Host channels interrupt enable", + "offset": 25, + "size": 1 + }, + "PTXFEIE": { + "description": "Periodic TxFIFO empty interrupt enable", + "offset": 26, + "size": 1 + }, + "IDPSCIE": { + "description": "ID pin status change interrupt enable", + "offset": 28, + "size": 1 + }, + "DISCIE": { + "description": "Disconnect interrupt enable", + "offset": 29, + "size": 1 + }, + "SESIE": { + "description": "Session interrupt enable", + "offset": 30, + "size": 1 + }, + "WKUPIE": { + "description": "Wakeup interrupt enable", + "offset": 31, + "size": 1 + } + } + } + }, + "GRSTATR_Device": { + "description": "Global Receive status read(Device\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCOUNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "RPCKST": { + "description": "Recieve packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "GRSTATR_Host": { + "description": "Global Receive status read(Host\n mode)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCOUNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "RPCKST": { + "description": "Reivece packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "GRSTATP_Device": { + "description": "Global Receive status pop(Device\n mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "EPNUM": { + "description": "Endpoint number", + "offset": 0, + "size": 4 + }, + "BCOUNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "RPCKST": { + "description": "Recieve packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "GRSTATP_Host": { + "description": "Global Receive status pop(Host\n mode)", + "offset": 32, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "CNUM": { + "description": "Channel number", + "offset": 0, + "size": 4 + }, + "BCOUNT": { + "description": "Byte count", + "offset": 4, + "size": 11 + }, + "DPID": { + "description": "Data PID", + "offset": 15, + "size": 2 + }, + "RPCKST": { + "description": "Reivece packet status", + "offset": 17, + "size": 4 + } + } + } + }, + "GRFLEN": { + "description": "Global Receive FIFO size register\n (USBFS_GRFLEN)", + "offset": 36, + "size": 32, + "reset_value": 512, + "reset_mask": 4294967295, + "children": { + "fields": { + "RXFD": { + "description": "Rx FIFO depth", + "offset": 0, + "size": 16 + } + } + } + }, + "HNPTFLEN": { + "description": "Host non-periodic transmit FIFO length register\n (Host mode)", + "offset": 40, + "size": 32, + "reset_value": 33554944, + "reset_mask": 4294967295, + "children": { + "fields": { + "HNPTXRSAR": { + "description": "host non-periodic transmit Tx RAM start\n address", + "offset": 0, + "size": 16 + }, + "HNPTXFD": { + "description": "host non-periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "DIEP0TFLEN": { + "description": "Device IN endpoint 0 transmit FIFO length\n (Device mode)", + "offset": 40, + "size": 32, + "reset_value": 33554944, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEP0TXFD": { + "description": "in endpoint 0 Tx FIFO depth", + "offset": 16, + "size": 16 + }, + "IEP0TXRSAR": { + "description": "in endpoint 0 Tx RAM start address", + "offset": 0, + "size": 16 + } + } + } + }, + "HNPTFQSTAT": { + "description": "Host non-periodic transmit FIFO/queue\n status register (HNPTFQSTAT)", + "offset": 44, + "size": 32, + "reset_value": 524800, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NPTXFS": { + "description": "Non-periodic TxFIFO space", + "offset": 0, + "size": 16 + }, + "NPTXRQS": { + "description": "Non-periodic transmit request queue\n space ", + "offset": 16, + "size": 8 + }, + "NPTXRQTOP": { + "description": "Top of the non-periodic transmit request\n queue", + "offset": 24, + "size": 7 + } + } + } + }, + "GCCFG": { + "description": "Global core configuration register (USBFS_GCCFG)", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PWRON": { + "description": "Power on", + "offset": 16, + "size": 1 + }, + "VBUSACEN": { + "description": "The VBUS A-device Comparer enable", + "offset": 18, + "size": 1 + }, + "VBUSBCEN": { + "description": "The VBUS B-device Comparer enable", + "offset": 19, + "size": 1 + }, + "SOFOEN": { + "description": "SOF output enable", + "offset": 20, + "size": 1 + }, + "VBUSIG": { + "description": "VBUS ignored", + "offset": 21, + "size": 1 + } + } + } + }, + "CID": { + "description": "core ID register", + "offset": 60, + "size": 32, + "reset_value": 4096, + "reset_mask": 4294967295, + "children": { + "fields": { + "CID": { + "description": "Core ID", + "offset": 0, + "size": 32 + } + } + } + }, + "HPTFLEN": { + "description": "Host periodic transmit FIFO length register (HPTFLEN)", + "offset": 256, + "size": 32, + "reset_value": 33555968, + "reset_mask": 4294967295, + "children": { + "fields": { + "HPTXFSAR": { + "description": "Host periodic TxFIFO start\n address", + "offset": 0, + "size": 16 + }, + "HPTXFD": { + "description": "Host periodic TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "DIEP1TFLEN": { + "description": "device IN endpoint transmit FIFO size\n register (DIEP1TFLEN)", + "offset": 260, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPTXRSAR": { + "description": "IN endpoint FIFO transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "IEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "DIEP2TFLEN": { + "description": "device IN endpoint transmit FIFO size\n register (DIEP2TFLEN)", + "offset": 264, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPTXRSAR": { + "description": "IN endpoint FIFO transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "IEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + }, + "DIEP3TFLEN": { + "description": "device IN endpoint transmit FIFO size\n register (FS_DIEP3TXFLEN)", + "offset": 268, + "size": 32, + "reset_value": 33555456, + "reset_mask": 4294967295, + "children": { + "fields": { + "IEPTXRSAR": { + "description": "IN endpoint FIFO4 transmit RAM start\n address", + "offset": 0, + "size": 16 + }, + "IEPTXFD": { + "description": "IN endpoint TxFIFO depth", + "offset": 16, + "size": 16 + } + } + } + } + } + } + }, + "I2C0": { + "description": "Inter integrated circuit", + "children": { + "registers": { + "CTL0": { + "description": "Control register 0", + "offset": 0, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SRESET": { + "description": "Software reset", + "offset": 15, + "size": 1 + }, + "SALT": { + "description": "SMBus alert", + "offset": 13, + "size": 1 + }, + "PECTRANS": { + "description": "PEC Transfer", + "offset": 12, + "size": 1 + }, + "POAP": { + "description": "Position of ACK and PEC when receiving", + "offset": 11, + "size": 1 + }, + "ACKEN": { + "description": "Whether or not to send an ACK", + "offset": 10, + "size": 1 + }, + "STOP": { + "description": "Generate a STOP condition on I2C bus", + "offset": 9, + "size": 1 + }, + "START": { + "description": "Generate a START condition on I2C bus", + "offset": 8, + "size": 1 + }, + "SS": { + "description": "Whether to stretch SCL low when data is not ready in slave mode", + "offset": 7, + "size": 1 + }, + "GCEN": { + "description": "Whether or not to response to a General Call (0x00)", + "offset": 6, + "size": 1 + }, + "PECEN": { + "description": "PEC Calculation Switch", + "offset": 5, + "size": 1 + }, + "ARPEN": { + "description": "ARP protocol in SMBus switch", + "offset": 4, + "size": 1 + }, + "SMBSEL": { + "description": "SMBusType Selection", + "offset": 3, + "size": 1 + }, + "SMBEN": { + "description": "SMBus/I2C mode switch", + "offset": 1, + "size": 1 + }, + "I2CEN": { + "description": "I2C peripheral enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "Control register 1", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMALST": { + "description": "Flag indicating DMA last transfer", + "offset": 12, + "size": 1 + }, + "DMAON": { + "description": "DMA mode switch", + "offset": 11, + "size": 1 + }, + "BUFIE": { + "description": "Buffer interrupt enable", + "offset": 10, + "size": 1 + }, + "EVIE": { + "description": "Event interrupt enable", + "offset": 9, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 8, + "size": 1 + }, + "I2CCLK": { + "description": "I2C Peripheral clock frequency", + "offset": 0, + "size": 6 + } + } + } + }, + "SADDR0": { + "description": "Slave address register 0", + "offset": 8, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDFORMAT": { + "description": "Address mode for the I2C slave", + "offset": 15, + "size": 1 + }, + "ADDRESS9_8": { + "description": "Highest two bits of a 10-bit address", + "offset": 8, + "size": 2 + }, + "ADDRESS7_1": { + "description": "7-bit address or bits 7:1 of a 10-bit address", + "offset": 1, + "size": 7 + }, + "ADDRESS0": { + "description": "Bit 0 of a 10-bit address", + "offset": 0, + "size": 1 + } + } + } + }, + "SADDR1": { + "description": "Slave address register 1", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ADDRESS2": { + "description": "Second I2C address for the slave in Dual-Address mode", + "offset": 1, + "size": 7 + }, + "DUADEN": { + "description": "Dual-Address mode switch", + "offset": 0, + "size": 1 + } + } + } + }, + "DATA": { + "description": "Transfer buffer register", + "offset": 16, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRB": { + "description": "Transmission or reception data buffer register", + "offset": 0, + "size": 8 + } + } + } + }, + "STAT0": { + "description": "Transfer status register 0", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SMBALT": { + "description": "SMBus Alert status", + "offset": 15, + "size": 1 + }, + "SMBTO": { + "description": "Timeout signal in SMBus mode", + "offset": 14, + "size": 1 + }, + "PECERR": { + "description": "PEC error when receiving data", + "offset": 12, + "size": 1 + }, + "OUERR": { + "description": "Over-run or under-run situation occurs in slave mode", + "offset": 11, + "size": 1 + }, + "AERR": { + "description": "Acknowledge error", + "offset": 10, + "size": 1 + }, + "LOSTARB": { + "description": "Arbitration Lost in master mode", + "offset": 9, + "size": 1 + }, + "BERR": { + "description": "A bus error occurs indication a unexpected START or STOP condition on I2C bus", + "offset": 8, + "size": 1 + }, + "TBE": { + "description": "I2C_DATA is Empty during transmitting", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "RBNE": { + "description": "I2C_DATA is not Empty during receiving", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "STPDET": { + "description": "STOP condition detected in slave mode", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ADD10SEND": { + "description": "Header of 10-bit address is sent in master mode", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "BTC": { + "description": "Byte transmission completed", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "ADDSEND": { + "description": "Address is sent in master mode or received and matches in slave mode", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "SBSEND": { + "description": "START condition sent out in master mode", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "STAT1": { + "description": "Transfer status register 1", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "PECV": { + "description": "Packet Error Checking Value that calculated by hardware when PEC is enabled", + "offset": 8, + "size": 8 + }, + "DUMODF": { + "description": "Dual Flag in slave mode", + "offset": 7, + "size": 1 + }, + "HSTSMB": { + "description": "SMBus Host Header detected in slave mode", + "offset": 6, + "size": 1 + }, + "DEFSMB": { + "description": "Default address of SMBusDevice", + "offset": 5, + "size": 1 + }, + "RXGC": { + "description": "General call address (00h) received", + "offset": 4, + "size": 1 + }, + "TR": { + "description": "Whether the I2C is a transmitter or a receiver", + "offset": 2, + "size": 1 + }, + "I2CBSY": { + "description": "Busy flag", + "offset": 1, + "size": 1 + }, + "MASTER": { + "description": "A flag indicating whether I2C block is in master or slave mode", + "offset": 0, + "size": 1 + } + } + } + }, + "CKCFG": { + "description": "Clock configure register", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "FAST": { + "description": "I2C speed selection in master mode", + "offset": 15, + "size": 1 + }, + "DTCY": { + "description": "Duty cycle in fast mode", + "offset": 14, + "size": 1 + }, + "CLKC": { + "description": "I2C Clock control in master mode", + "offset": 0, + "size": 12 + } + } + } + }, + "RT": { + "description": "Rise time register", + "offset": 32, + "size": 16, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "RISETIME": { + "description": "Maximum rise time in master mode", + "offset": 0, + "size": 6 + } + } + } + } + } + } + }, + "TIMER5": { + "description": "Basic-timers", + "children": { + "registers": { + "CTL0": { + "description": "control register 0", + "offset": 0, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ARSE": { + "description": "Auto-reload shadow enable", + "offset": 7, + "size": 1 + }, + "SPM": { + "description": "Single pulse mode", + "offset": 3, + "size": 1 + }, + "UPS": { + "description": "Update source", + "offset": 2, + "size": 1 + }, + "UPDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MMC": { + "description": "Master mode control", + "offset": 4, + "size": 3 + } + } + } + }, + "DMAINTEN": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UPDEN": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "UPIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "INTF": { + "description": "Interrupt flag register", + "offset": 16, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UPIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SWEVG": { + "description": "event generation register", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "UPG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "Counter register", + "offset": 36, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "Low counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "Prescaler register", + "offset": 40, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value of the counter clock", + "offset": 0, + "size": 16 + } + } + } + }, + "CAR": { + "description": "Counter auto reload register", + "offset": 44, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CARL": { + "description": "Counter auto reload value", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "ECLIC": { + "description": "Enhanced Core Local Interrupt Controller", + "children": { + "registers": { + "CLICCFG": { + "description": "cliccfg Register", + "offset": 0, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "NLBITS": { + "description": "NLBITS", + "offset": 1, + "size": 4 + } + } + } + }, + "CLICINFO": { + "description": "clicinfo Register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "NUM_INTERRUPT": { + "description": "NUM_INTERRUPT", + "offset": 0, + "size": 13 + }, + "VERSION": { + "description": "VERSION", + "offset": 13, + "size": 8 + }, + "CLICINTCTLBITS": { + "description": "CLICINTCTLBITS", + "offset": 21, + "size": 4 + } + } + } + }, + "MTH": { + "description": "MTH Register", + "offset": 11, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "MTH": { + "description": "MTH", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTIP_0": { + "description": "clicintip Register", + "offset": 4096, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_1": { + "description": "clicintip Register", + "offset": 4100, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_2": { + "description": "clicintip Register", + "offset": 4104, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_3": { + "description": "clicintip Register", + "offset": 4108, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_4": { + "description": "clicintip Register", + "offset": 4112, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_5": { + "description": "clicintip Register", + "offset": 4116, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_6": { + "description": "clicintip Register", + "offset": 4120, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_7": { + "description": "clicintip Register", + "offset": 4124, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_8": { + "description": "clicintip Register", + "offset": 4128, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_9": { + "description": "clicintip Register", + "offset": 4132, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_10": { + "description": "clicintip Register", + "offset": 4136, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_11": { + "description": "clicintip Register", + "offset": 4140, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_12": { + "description": "clicintip Register", + "offset": 4144, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_13": { + "description": "clicintip Register", + "offset": 4148, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_14": { + "description": "clicintip Register", + "offset": 4152, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_15": { + "description": "clicintip Register", + "offset": 4156, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_16": { + "description": "clicintip Register", + "offset": 4160, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_17": { + "description": "clicintip Register", + "offset": 4164, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_18": { + "description": "clicintip Register", + "offset": 4168, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_19": { + "description": "clicintip Register", + "offset": 4172, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_20": { + "description": "clicintip Register", + "offset": 4176, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_21": { + "description": "clicintip Register", + "offset": 4180, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_22": { + "description": "clicintip Register", + "offset": 4184, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_23": { + "description": "clicintip Register", + "offset": 4188, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_24": { + "description": "clicintip Register", + "offset": 4192, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_25": { + "description": "clicintip Register", + "offset": 4196, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_26": { + "description": "clicintip Register", + "offset": 4200, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_27": { + "description": "clicintip Register", + "offset": 4204, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_28": { + "description": "clicintip Register", + "offset": 4208, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_29": { + "description": "clicintip Register", + "offset": 4212, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_30": { + "description": "clicintip Register", + "offset": 4216, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_31": { + "description": "clicintip Register", + "offset": 4220, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_32": { + "description": "clicintip Register", + "offset": 4224, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_33": { + "description": "clicintip Register", + "offset": 4228, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_34": { + "description": "clicintip Register", + "offset": 4232, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_35": { + "description": "clicintip Register", + "offset": 4236, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_36": { + "description": "clicintip Register", + "offset": 4240, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_37": { + "description": "clicintip Register", + "offset": 4244, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_38": { + "description": "clicintip Register", + "offset": 4248, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_39": { + "description": "clicintip Register", + "offset": 4252, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_40": { + "description": "clicintip Register", + "offset": 4256, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_41": { + "description": "clicintip Register", + "offset": 4260, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_42": { + "description": "clicintip Register", + "offset": 4264, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_43": { + "description": "clicintip Register", + "offset": 4268, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_44": { + "description": "clicintip Register", + "offset": 4272, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_45": { + "description": "clicintip Register", + "offset": 4276, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_46": { + "description": "clicintip Register", + "offset": 4280, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_47": { + "description": "clicintip Register", + "offset": 4284, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_48": { + "description": "clicintip Register", + "offset": 4288, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_49": { + "description": "clicintip Register", + "offset": 4292, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_50": { + "description": "clicintip Register", + "offset": 4296, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_51": { + "description": "clicintip Register", + "offset": 4300, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_52": { + "description": "clicintip Register", + "offset": 4304, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_53": { + "description": "clicintip Register", + "offset": 4308, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_54": { + "description": "clicintip Register", + "offset": 4312, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_55": { + "description": "clicintip Register", + "offset": 4316, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_56": { + "description": "clicintip Register", + "offset": 4320, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_57": { + "description": "clicintip Register", + "offset": 4324, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_58": { + "description": "clicintip Register", + "offset": 4328, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_59": { + "description": "clicintip Register", + "offset": 4332, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_60": { + "description": "clicintip Register", + "offset": 4336, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_61": { + "description": "clicintip Register", + "offset": 4340, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_62": { + "description": "clicintip Register", + "offset": 4344, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_63": { + "description": "clicintip Register", + "offset": 4348, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_64": { + "description": "clicintip Register", + "offset": 4352, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_65": { + "description": "clicintip Register", + "offset": 4356, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_66": { + "description": "clicintip Register", + "offset": 4360, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_67": { + "description": "clicintip Register", + "offset": 4364, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_68": { + "description": "clicintip Register", + "offset": 4368, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_69": { + "description": "clicintip Register", + "offset": 4372, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_70": { + "description": "clicintip Register", + "offset": 4376, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_71": { + "description": "clicintip Register", + "offset": 4380, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_72": { + "description": "clicintip Register", + "offset": 4384, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_73": { + "description": "clicintip Register", + "offset": 4388, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_74": { + "description": "clicintip Register", + "offset": 4392, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_75": { + "description": "clicintip Register", + "offset": 4396, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_76": { + "description": "clicintip Register", + "offset": 4400, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_77": { + "description": "clicintip Register", + "offset": 4404, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_78": { + "description": "clicintip Register", + "offset": 4408, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_79": { + "description": "clicintip Register", + "offset": 4412, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_80": { + "description": "clicintip Register", + "offset": 4416, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_81": { + "description": "clicintip Register", + "offset": 4420, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_82": { + "description": "clicintip Register", + "offset": 4424, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_83": { + "description": "clicintip Register", + "offset": 4428, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_84": { + "description": "clicintip Register", + "offset": 4432, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_85": { + "description": "clicintip Register", + "offset": 4440, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIP_86": { + "description": "clicintip Register", + "offset": 4444, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IP": { + "description": "IP", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_0": { + "description": "clicintie Register", + "offset": 4097, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_1": { + "description": "clicintie Register", + "offset": 4101, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_2": { + "description": "clicintie Register", + "offset": 4105, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_3": { + "description": "clicintie Register", + "offset": 4109, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_4": { + "description": "clicintie Register", + "offset": 4113, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_5": { + "description": "clicintie Register", + "offset": 4117, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_6": { + "description": "clicintie Register", + "offset": 4121, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_7": { + "description": "clicintie Register", + "offset": 4125, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_8": { + "description": "clicintie Register", + "offset": 4129, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_9": { + "description": "clicintie Register", + "offset": 4133, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_10": { + "description": "clicintie Register", + "offset": 4137, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_11": { + "description": "clicintie Register", + "offset": 4141, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IE": { + "description": "IE", + "offset": 0, + "size": 1 + } + } + } + }, + "CLICINTIE_12": { + "description": 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4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_18": { + "description": "clicintattr Register", + "offset": 4170, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_19": { + "description": "clicintattr Register", + "offset": 4174, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_20": { + "description": "clicintattr Register", + "offset": 4178, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": 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"offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_24": { + "description": "clicintattr Register", + "offset": 4194, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_25": { + "description": "clicintattr Register", + "offset": 4198, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_26": { + "description": "clicintattr Register", + "offset": 4202, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_27": { + "description": "clicintattr Register", + "offset": 4206, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_28": { + "description": "clicintattr Register", + "offset": 4210, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_29": { + "description": "clicintattr Register", + "offset": 4214, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_30": { + "description": "clicintattr Register", + "offset": 4218, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_31": { + "description": "clicintattr Register", + "offset": 4222, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_32": { + "description": "clicintattr Register", + "offset": 4226, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + 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{ + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_46": { + "description": "clicintattr Register", + "offset": 4282, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_47": { + "description": "clicintattr Register", + "offset": 4286, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_48": { + "description": "clicintattr Register", + "offset": 4290, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_49": { + "description": "clicintattr Register", + "offset": 4294, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_50": { + "description": "clicintattr Register", + "offset": 4298, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_51": { + "description": "clicintattr Register", + "offset": 4302, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_52": { + "description": "clicintattr Register", + "offset": 4306, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_53": { + "description": "clicintattr Register", + "offset": 4310, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_54": { + "description": "clicintattr Register", + "offset": 4314, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_55": { + "description": "clicintattr Register", + "offset": 4318, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_56": { + "description": "clicintattr Register", + "offset": 4322, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_57": { + "description": "clicintattr Register", + "offset": 4326, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_58": { + "description": "clicintattr Register", + "offset": 4330, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_59": { + "description": "clicintattr Register", + "offset": 4334, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_60": { + "description": "clicintattr Register", + "offset": 4338, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_61": { + "description": "clicintattr Register", + "offset": 4342, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_62": { + "description": "clicintattr Register", + "offset": 4346, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_63": { + "description": "clicintattr Register", + "offset": 4350, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_64": { + "description": "clicintattr Register", + "offset": 4354, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_65": { + "description": "clicintattr Register", + "offset": 4358, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_66": { + "description": "clicintattr Register", + "offset": 4362, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_67": { + "description": "clicintattr Register", + "offset": 4366, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_68": { + "description": "clicintattr Register", + "offset": 4370, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_69": { + "description": "clicintattr Register", + "offset": 4374, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_70": { + "description": "clicintattr Register", + "offset": 4378, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_71": { + "description": "clicintattr Register", + "offset": 4382, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_72": { + "description": "clicintattr Register", + "offset": 4386, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_73": { + "description": "clicintattr Register", + "offset": 4390, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_74": { + "description": "clicintattr Register", + "offset": 4394, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_75": { + "description": "clicintattr Register", + "offset": 4398, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_76": { + "description": "clicintattr Register", + "offset": 4402, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_77": { + "description": "clicintattr Register", + "offset": 4406, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_78": { + "description": "clicintattr Register", + "offset": 4410, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_79": { + "description": "clicintattr Register", + "offset": 4414, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_80": { + "description": "clicintattr Register", + "offset": 4418, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_81": { + "description": "clicintattr Register", + "offset": 4422, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_82": { + "description": "clicintattr Register", + "offset": 4426, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_83": { + "description": "clicintattr Register", + "offset": 4430, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_84": { + "description": "clicintattr Register", + "offset": 4434, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_85": { + "description": "clicintattr Register", + "offset": 4438, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTATTR_86": { + "description": "clicintattr Register", + "offset": 4442, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SHV": { + "description": "SHV", + "offset": 0, + "size": 1 + }, + "TRIG": { + "description": "TRIG", + "offset": 1, + "size": 2 + } + } + } + }, + "CLICINTCTL_0": { + "description": "clicintctl Register", + "offset": 4099, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_1": { + "description": "clicintctl Register", + "offset": 4103, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_2": { + "description": "clicintctl Register", + "offset": 4107, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_3": { + "description": "clicintctl Register", + "offset": 4111, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_4": { + "description": "clicintctl Register", + "offset": 4115, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_5": { + "description": "clicintctl Register", + "offset": 4119, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_6": { + "description": "clicintctl Register", + "offset": 4123, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_7": { + "description": "clicintctl Register", + "offset": 4127, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_8": { + "description": "clicintctl Register", + "offset": 4131, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_9": { + "description": "clicintctl Register", + "offset": 4135, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_10": { + "description": "clicintctl Register", + "offset": 4139, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_11": { + "description": "clicintctl Register", + "offset": 4143, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_12": { + "description": "clicintctl Register", + "offset": 4147, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_13": { + "description": "clicintctl Register", + "offset": 4151, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_14": { + "description": "clicintctl Register", + "offset": 4155, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_15": { + "description": "clicintctl Register", + "offset": 4159, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_16": { + "description": "clicintctl Register", + "offset": 4163, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_17": { + "description": "clicintctl Register", + "offset": 4167, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_18": { + "description": "clicintctl Register", + "offset": 4171, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_19": { + "description": "clicintctl Register", + "offset": 4175, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_20": { + "description": "clicintctl Register", + "offset": 4179, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_21": { + "description": "clicintctl Register", + "offset": 4183, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_22": { + "description": "clicintctl Register", + "offset": 4187, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_23": { + "description": "clicintctl Register", + "offset": 4191, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_24": { + "description": "clicintctl Register", + "offset": 4195, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_25": { + "description": "clicintctl Register", + "offset": 4199, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_26": { + "description": "clicintctl Register", + "offset": 4203, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_27": { + "description": "clicintctl Register", + "offset": 4207, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_28": { + "description": "clicintctl Register", + "offset": 4211, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_29": { + "description": "clicintctl Register", + "offset": 4215, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_30": { + "description": "clicintctl Register", + "offset": 4219, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_31": { + "description": "clicintctl Register", + "offset": 4223, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_32": { + "description": "clicintctl Register", + "offset": 4227, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_33": { + "description": "clicintctl Register", + "offset": 4231, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_34": { + "description": "clicintctl Register", + "offset": 4235, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_35": { + "description": "clicintctl Register", + "offset": 4239, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_36": { + "description": "clicintctl Register", + "offset": 4243, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_37": { + "description": "clicintctl Register", + "offset": 4247, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_38": { + "description": "clicintctl Register", + "offset": 4251, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_39": { + "description": "clicintctl Register", + "offset": 4255, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_40": { + "description": "clicintctl Register", + "offset": 4259, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_41": { + "description": "clicintctl Register", + "offset": 4263, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_42": { + "description": "clicintctl Register", + "offset": 4267, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_43": { + "description": "clicintctl Register", + "offset": 4271, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_44": { + "description": "clicintctl Register", + "offset": 4275, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_45": { + "description": "clicintctl Register", + "offset": 4279, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_46": { + "description": "clicintctl Register", + "offset": 4283, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_47": { + "description": "clicintctl Register", + "offset": 4287, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_48": { + "description": "clicintctl Register", + "offset": 4291, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_49": { + "description": "clicintctl Register", + "offset": 4295, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_50": { + "description": "clicintctl Register", + "offset": 4299, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_51": { + "description": "clicintctl Register", + "offset": 4303, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_52": { + "description": "clicintctl Register", + "offset": 4307, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_53": { + "description": "clicintctl Register", + "offset": 4311, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_54": { + "description": "clicintctl Register", + "offset": 4315, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_55": { + "description": "clicintctl Register", + "offset": 4319, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_56": { + "description": "clicintctl Register", + "offset": 4323, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_57": { + "description": "clicintctl Register", + "offset": 4327, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_58": { + "description": "clicintctl Register", + "offset": 4331, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_59": { + "description": "clicintctl Register", + "offset": 4335, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_60": { + "description": "clicintctl Register", + "offset": 4339, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_61": { + "description": "clicintctl Register", + "offset": 4343, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_62": { + "description": "clicintctl Register", + "offset": 4347, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_63": { + "description": "clicintctl Register", + "offset": 4351, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_64": { + "description": "clicintctl Register", + "offset": 4355, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_65": { + "description": "clicintctl Register", + "offset": 4359, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_66": { + "description": "clicintctl Register", + "offset": 4363, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_67": { + "description": "clicintctl Register", + "offset": 4367, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_68": { + "description": "clicintctl Register", + "offset": 4371, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_69": { + "description": "clicintctl Register", + "offset": 4375, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_70": { + "description": "clicintctl Register", + "offset": 4379, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_71": { + "description": "clicintctl Register", + "offset": 4383, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_72": { + "description": "clicintctl Register", + "offset": 4387, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_73": { + "description": "clicintctl Register", + "offset": 4391, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_74": { + "description": "clicintctl Register", + "offset": 4395, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_75": { + "description": "clicintctl Register", + "offset": 4399, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_76": { + "description": "clicintctl Register", + "offset": 4403, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_77": { + "description": "clicintctl Register", + "offset": 4407, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_78": { + "description": "clicintctl Register", + "offset": 4411, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_79": { + "description": "clicintctl Register", + "offset": 4415, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_80": { + "description": "clicintctl Register", + "offset": 4419, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_81": { + "description": "clicintctl Register", + "offset": 4423, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_82": { + "description": "clicintctl Register", + "offset": 4427, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_83": { + "description": "clicintctl Register", + "offset": 4431, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_84": { + "description": "clicintctl Register", + "offset": 4435, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_85": { + "description": "clicintctl Register", + "offset": 4439, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + }, + "CLICINTCTL_86": { + "description": "clicintctl Register", + "offset": 4443, + "size": 8, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LEVEL_PRIORITY": { + "description": "LEVEL_PRIORITY", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "PMU": { + "description": "Power management unit", + "children": { + "registers": { + "CTL": { + "description": "power control register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BKPWEN": { + "description": "Backup Domain Write Enable", + "offset": 8, + "size": 1 + }, + "LVDT": { + "description": "Low Voltage Detector Threshold", + "offset": 5, + "size": 3 + }, + "LVDEN": { + "description": "Low Voltage Detector Enable", + "offset": 4, + "size": 1 + }, + "STBRST": { + "description": "Standby Flag Reset", + "offset": 3, + "size": 1 + }, + "WURST": { + "description": "Wakeup Flag Reset", + "offset": 2, + "size": 1 + }, + "STBMOD": { + "description": "Standby Mode", + "offset": 1, + "size": 1 + }, + "LDOLP": { + "description": "LDO Low Power Mode", + "offset": 0, + "size": 1 + } + } + } + }, + "CS": { + "description": "power control/status register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "WUPEN": { + "description": "Enable WKUP pin", + "offset": 8, + "size": 1 + }, + "LVDF": { + "description": "Low Voltage Detector Status Flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "STBF": { + "description": "Standby flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "WUF": { + "description": "Wakeup flag", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + } + } + } + }, + "RCU": { + "description": "Reset and clock unit", + "children": { + "registers": { + "CTL": { + "description": "Control register", + "offset": 0, + "size": 32, + "reset_value": 131, + "reset_mask": 4294967295, + "children": { + "fields": { + "IRC8MEN": { + "description": "Internal 8MHz RC oscillator Enable", + "offset": 0, + "size": 1 + }, + "IRC8MSTB": { + "description": "IRC8M Internal 8MHz RC Oscillator stabilization Flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "IRC8MADJ": { + "description": "Internal 8MHz RC Oscillator clock trim adjust value", + "offset": 3, + "size": 5 + }, + "IRC8MCALIB": { + "description": "Internal 8MHz RC Oscillator calibration value register", + "offset": 8, + "size": 8, + "access": "read-only" + }, + "HXTALEN": { + "description": "External High Speed oscillator Enable", + "offset": 16, + "size": 1 + }, + "HXTALSTB": { + "description": "External crystal oscillator (HXTAL) clock stabilization flag", + "offset": 17, + "size": 1, + "access": "read-only" + }, + "HXTALBPS": { + "description": "External crystal oscillator (HXTAL) clock bypass mode enable", + "offset": 18, + "size": 1 + }, + "CKMEN": { + "description": "HXTAL Clock Monitor Enable", + "offset": 19, + "size": 1 + }, + "PLLEN": { + "description": "PLL enable", + "offset": 24, + "size": 1 + }, + "PLLSTB": { + "description": "PLL Clock Stabilization Flag", + "offset": 25, + "size": 1, + "access": "read-only" + }, + "PLL1EN": { + "description": "PLL1 enable", + "offset": 26, + "size": 1 + }, + "PLL1STB": { + "description": "PLL1 Clock Stabilization Flag", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "PLL2EN": { + "description": "PLL2 enable", + "offset": 28, + "size": 1 + }, + "PLL2STB": { + "description": "PLL2 Clock Stabilization Flag", + "offset": 29, + "size": 1, + "access": "read-only" + } + } + } + }, + "CFG0": { + "description": "Clock configuration register 0\n (RCU_CFG0)", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SCS": { + "description": "System clock switch", + "offset": 0, + "size": 2 + }, + "SCSS": { + "description": "System clock switch status", + "offset": 2, + "size": 2, + "access": "read-only" + }, + "AHBPSC": { + "description": "AHB prescaler selection", + "offset": 4, + "size": 4 + }, + "APB1PSC": { + "description": "APB1 prescaler selection", + "offset": 8, + "size": 3 + }, + "APB2PSC": { + "description": "APB2 prescaler selection", + "offset": 11, + "size": 3 + }, + "ADCPSC_1_0": { + "description": "ADC clock prescaler selection", + "offset": 14, + "size": 2 + }, + "PLLSEL": { + "description": "PLL Clock Source Selection", + "offset": 16, + "size": 1 + }, + "PREDV0_LSB": { + "description": "The LSB of PREDV0 division factor", + "offset": 17, + "size": 1 + }, + "PLLMF_3_0": { + "description": "The PLL clock multiplication factor", + "offset": 18, + "size": 4 + }, + "USBFSPSC": { + "description": "USBFS clock prescaler selection", + "offset": 22, + "size": 2 + }, + "CKOUT0SEL": { + "description": "CKOUT0 Clock Source Selection", + "offset": 24, + "size": 4 + }, + "ADCPSC_2": { + "description": "Bit 2 of ADCPSC", + "offset": 28, + "size": 1 + }, + "PLLMF_4": { + "description": "Bit 4 of PLLMF", + "offset": 29, + "size": 1 + } + } + } + }, + "INT": { + "description": "Clock interrupt register\n (RCU_INT)", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "IRC40KSTBIF": { + "description": "IRC40K stabilization interrupt flag", + "offset": 0, + "size": 1, + "access": "read-only" + }, + "LXTALSTBIF": { + "description": "LXTAL stabilization interrupt flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "IRC8MSTBIF": { + "description": "IRC8M stabilization interrupt flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "HXTALSTBIF": { + "description": "HXTAL stabilization interrupt flag", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "PLLSTBIF": { + "description": "PLL stabilization interrupt flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "PLL1STBIF": { + "description": "PLL1 stabilization interrupt flag", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "PLL2STBIF": { + "description": "PLL2 stabilization interrupt flag", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "CKMIF": { + "description": "HXTAL Clock Stuck Interrupt Flag", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "IRC40KSTBIE": { + "description": "IRC40K Stabilization interrupt enable", + "offset": 8, + "size": 1 + }, + "LXTALSTBIE": { + "description": "LXTAL Stabilization Interrupt Enable", + "offset": 9, + "size": 1 + }, + "IRC8MSTBIE": { + "description": "IRC8M Stabilization Interrupt Enable", + "offset": 10, + "size": 1 + }, + "HXTALSTBIE": { + "description": "HXTAL Stabilization Interrupt Enable", + "offset": 11, + "size": 1 + }, + "PLLSTBIE": { + "description": "PLL Stabilization Interrupt Enable", + "offset": 12, + "size": 1 + }, + "PLL1STBIE": { + "description": "PLL1 Stabilization Interrupt Enable", + "offset": 13, + "size": 1 + }, + "PLL2STBIE": { + "description": "PLL2 Stabilization Interrupt Enable", + "offset": 14, + "size": 1 + }, + "IRC40KSTBIC": { + "description": "IRC40K Stabilization Interrupt Clear", + "offset": 16, + "size": 1, + "access": "write-only" + }, + "LXTALSTBIC": { + "description": "LXTAL Stabilization Interrupt Clear", + "offset": 17, + "size": 1, + "access": "write-only" + }, + "IRC8MSTBIC": { + "description": "IRC8M Stabilization Interrupt Clear", + "offset": 18, + "size": 1, + "access": "write-only" + }, + "HXTALSTBIC": { + "description": "HXTAL Stabilization Interrupt Clear", + "offset": 19, + "size": 1, + "access": "write-only" + }, + "PLLSTBIC": { + "description": "PLL stabilization Interrupt Clear", + "offset": 20, + "size": 1, + "access": "write-only" + }, + "PLL1STBIC": { + "description": "PLL1 stabilization Interrupt Clear", + "offset": 21, + "size": 1, + "access": "write-only" + }, + "PLL2STBIC": { + "description": "PLL2 stabilization Interrupt Clear", + "offset": 22, + "size": 1, + "access": "write-only" + }, + "CKMIC": { + "description": "HXTAL Clock Stuck Interrupt Clear", + "offset": 23, + "size": 1, + "access": "write-only" + } + } + } + }, + "APB2RST": { + "description": "APB2 reset register\n (RCU_APB2RST)", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFRST": { + "description": "Alternate function I/O reset", + "offset": 0, + "size": 1 + }, + "PARST": { + "description": "GPIO port A reset", + "offset": 2, + "size": 1 + }, + "PBRST": { + "description": "GPIO port B reset", + "offset": 3, + "size": 1 + }, + "PCRST": { + "description": "GPIO port C reset", + "offset": 4, + "size": 1 + }, + "PDRST": { + "description": "GPIO port D reset", + "offset": 5, + "size": 1 + }, + "PERST": { + "description": "GPIO port E reset", + "offset": 6, + "size": 1 + }, + "ADC0RST": { + "description": "ADC0 reset", + "offset": 9, + "size": 1 + }, + "ADC1RST": { + "description": "ADC1 reset", + "offset": 10, + "size": 1 + }, + "TIMER0RST": { + "description": "Timer 0 reset", + "offset": 11, + "size": 1 + }, + "SPI0RST": { + "description": "SPI0 reset", + "offset": 12, + "size": 1 + }, + "USART0RST": { + "description": "USART0 Reset", + "offset": 14, + "size": 1 + } + } + } + }, + "APB1RST": { + "description": "APB1 reset register\n (RCU_APB1RST)", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMER1RST": { + "description": "TIMER1 timer reset", + "offset": 0, + "size": 1 + }, + "TIMER2RST": { + "description": "TIMER2 timer reset", + "offset": 1, + "size": 1 + }, + "TIMER3RST": { + "description": "TIMER3 timer reset", + "offset": 2, + "size": 1 + }, + "TIMER4RST": { + "description": "TIMER4 timer reset", + "offset": 3, + "size": 1 + }, + "TIMER5RST": { + "description": "TIMER5 timer reset", + "offset": 4, + "size": 1 + }, + "TIMER6RST": { + "description": "TIMER6 timer reset", + "offset": 5, + "size": 1 + }, + "WWDGTRST": { + "description": "Window watchdog timer reset", + "offset": 11, + "size": 1 + }, + "SPI1RST": { + "description": "SPI1 reset", + "offset": 14, + "size": 1 + }, + "SPI2RST": { + "description": "SPI2 reset", + "offset": 15, + "size": 1 + }, + "USART1RST": { + "description": "USART1 reset", + "offset": 17, + "size": 1 + }, + "USART2RST": { + "description": "USART2 reset", + "offset": 18, + "size": 1 + }, + "UART3RST": { + "description": "UART3 reset", + "offset": 19, + "size": 1 + }, + "UART4RST": { + "description": "UART4 reset", + "offset": 20, + "size": 1 + }, + "I2C0RST": { + "description": "I2C0 reset", + "offset": 21, + "size": 1 + }, + "I2C1RST": { + "description": "I2C1 reset", + "offset": 22, + "size": 1 + }, + "CAN0RST": { + "description": "CAN0 reset", + "offset": 25, + "size": 1 + }, + "CAN1RST": { + "description": "CAN1 reset", + "offset": 26, + "size": 1 + }, + "BKPIRST": { + "description": "Backup interface reset", + "offset": 27, + "size": 1 + }, + "PMURST": { + "description": "Power control reset", + "offset": 28, + "size": 1 + }, + "DACRST": { + "description": "DAC reset", + "offset": 29, + "size": 1 + } + } + } + }, + "AHBEN": { + "description": "AHB enable register", + "offset": 20, + "size": 32, + "reset_value": 20, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMA0EN": { + "description": "DMA0 clock enable", + "offset": 0, + "size": 1 + }, + "DMA1EN": { + "description": "DMA1 clock enable", + "offset": 1, + "size": 1 + }, + "SRAMSPEN": { + "description": "SRAM interface clock enable when sleep mode", + "offset": 2, + "size": 1 + }, + "FMCSPEN": { + "description": "FMC clock enable when sleep mode", + "offset": 4, + "size": 1 + }, + "CRCEN": { + "description": "CRC clock enable", + "offset": 6, + "size": 1 + }, + "EXMCEN": { + "description": "EXMC clock enable", + "offset": 8, + "size": 1 + }, + "USBFSEN": { + "description": "USBFS clock enable", + "offset": 12, + "size": 1 + } + } + } + }, + "APB2EN": { + "description": "APB2 clock enable register\n (RCU_APB2EN)", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "AFEN": { + "description": "Alternate function IO clock enable ", + "offset": 0, + "size": 1 + }, + "PAEN": { + "description": "GPIO port A clock enable", + "offset": 2, + "size": 1 + }, + "PBEN": { + "description": "GPIO port B clock enable", + "offset": 3, + "size": 1 + }, + "PCEN": { + "description": "GPIO port C clock enable", + "offset": 4, + "size": 1 + }, + "PDEN": { + "description": "GPIO port D clock enable ", + "offset": 5, + "size": 1 + }, + "PEEN": { + "description": "GPIO port E clock enable ", + "offset": 6, + "size": 1 + }, + "ADC0EN": { + "description": "ADC0 clock enable", + "offset": 9, + "size": 1 + }, + "ADC1EN": { + "description": "ADC1 clock enable", + "offset": 10, + "size": 1 + }, + "TIMER0EN": { + "description": "TIMER0 clock enable ", + "offset": 11, + "size": 1 + }, + "SPI0EN": { + "description": "SPI0 clock enable", + "offset": 12, + "size": 1 + }, + "USART0EN": { + "description": "USART0 clock enable", + "offset": 14, + "size": 1 + } + } + } + }, + "APB1EN": { + "description": "APB1 clock enable register\n (RCU_APB1EN)", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TIMER1EN": { + "description": "TIMER1 timer clock enable", + "offset": 0, + "size": 1 + }, + "TIMER2EN": { + "description": "TIMER2 timer clock enable", + "offset": 1, + "size": 1 + }, + "TIMER3EN": { + "description": "TIMER3 timer clock enable", + "offset": 2, + "size": 1 + }, + "TIMER4EN": { + "description": "TIMER4 timer clock enable", + "offset": 3, + "size": 1 + }, + "TIMER5EN": { + "description": "TIMER5 timer clock enable", + "offset": 4, + "size": 1 + }, + "TIMER6EN": { + "description": "TIMER6 timer clock enable", + "offset": 5, + "size": 1 + }, + "WWDGTEN": { + "description": "Window watchdog timer clock enable", + "offset": 11, + "size": 1 + }, + "SPI1EN": { + "description": "SPI1 clock enable", + "offset": 14, + "size": 1 + }, + "SPI2EN": { + "description": "SPI2 clock enable", + "offset": 15, + "size": 1 + }, + "USART1EN": { + "description": "USART1 clock enable", + "offset": 17, + "size": 1 + }, + "USART2EN": { + "description": "USART2 clock enable", + "offset": 18, + "size": 1 + }, + "UART3EN": { + "description": "UART3 clock enable", + "offset": 19, + "size": 1 + }, + "UART4EN": { + "description": "UART4 clock enable", + "offset": 20, + "size": 1 + }, + "I2C0EN": { + "description": "I2C0 clock enable", + "offset": 21, + "size": 1 + }, + "I2C1EN": { + "description": "I2C1 clock enable", + "offset": 22, + "size": 1 + }, + "CAN0EN": { + "description": "CAN0 clock enable", + "offset": 25, + "size": 1 + }, + "CAN1EN": { + "description": "CAN1 clock enable", + "offset": 26, + "size": 1 + }, + "BKPIEN": { + "description": "Backup interface clock enable ", + "offset": 27, + "size": 1 + }, + "PMUEN": { + "description": "Power control clock enable ", + "offset": 28, + "size": 1 + }, + "DACEN": { + "description": "DAC clock enable", + "offset": 29, + "size": 1 + } + } + } + }, + "BDCTL": { + "description": "Backup domain control register\n (RCU_BDCTL)", + "offset": 32, + "size": 32, + "reset_value": 24, + "reset_mask": 4294967295, + "children": { + "fields": { + "LXTALEN": { + "description": "LXTAL enable", + "offset": 0, + "size": 1 + }, + "LXTALSTB": { + "description": "External low-speed oscillator stabilization", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "LXTALBPS": { + "description": "LXTAL bypass mode enable", + "offset": 2, + "size": 1 + }, + "RTCSRC": { + "description": "RTC clock entry selection", + "offset": 8, + "size": 2 + }, + "RTCEN": { + "description": "RTC clock enable", + "offset": 15, + "size": 1 + }, + "BKPRST": { + "description": "Backup domain reset", + "offset": 16, + "size": 1 + } + } + } + }, + "RSTSCK": { + "description": "Reset source /clock register\n (RCU_RSTSCK)", + "offset": 36, + "size": 32, + "reset_value": 201326592, + "reset_mask": 4294967295, + "children": { + "fields": { + "IRC40KEN": { + "description": "IRC40K enable", + "offset": 0, + "size": 1 + }, + "IRC40KSTB": { + "description": "IRC40K stabilization", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RSTFC": { + "description": "Reset flag clear", + "offset": 24, + "size": 1 + }, + "EPRSTF": { + "description": "External PIN reset flag", + "offset": 26, + "size": 1, + "access": "read-only" + }, + "PORRSTF": { + "description": "Power reset flag", + "offset": 27, + "size": 1, + "access": "read-only" + }, + "SWRSTF": { + "description": "Software reset flag", + "offset": 28, + "size": 1, + "access": "read-only" + }, + "FWDGTRSTF": { + "description": "Free Watchdog timer reset flag", + "offset": 29, + "size": 1, + "access": "read-only" + }, + "WWDGTRSTF": { + "description": "Window watchdog timer reset flag", + "offset": 30, + "size": 1, + "access": "read-only" + }, + "LPRSTF": { + "description": "Low-power reset flag", + "offset": 31, + "size": 1, + "access": "read-only" + } + } + } + }, + "AHBRST": { + "description": "AHB reset register", + "offset": 40, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "USBFSRST": { + "description": "USBFS reset", + "offset": 12, + "size": 1 + } + } + } + }, + "CFG1": { + "description": "Clock Configuration register 1", + "offset": 44, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PREDV0": { + "description": "PREDV0 division factor", + "offset": 0, + "size": 4 + }, + "PREDV1": { + "description": "PREDV1 division factor", + "offset": 4, + "size": 4 + }, + "PLL1MF": { + "description": "The PLL1 clock multiplication factor", + "offset": 8, + "size": 4 + }, + "PLL2MF": { + "description": "The PLL2 clock multiplication factor", + "offset": 12, + "size": 4 + }, + "PREDV0SEL": { + "description": "PREDV0 input Clock Source Selection", + "offset": 16, + "size": 1 + }, + "I2S1SEL": { + "description": "I2S1 Clock Source Selection", + "offset": 17, + "size": 1 + }, + "I2S2SEL": { + "description": "I2S2 Clock Source Selection", + "offset": 18, + "size": 1 + } + } + } + }, + "DSV": { + "description": "Deep sleep mode Voltage register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DSLPVS": { + "description": "Deep-sleep mode voltage select", + "offset": 0, + "size": 2 + } + } + } + } + } + } + }, + "RTC": { + "description": "Real-time clock", + "children": { + "registers": { + "INTEN": { + "description": "RTC interrupt enable register", + "offset": 0, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "OVIE": { + "description": "Overflow interrupt enable", + "offset": 2, + "size": 1 + }, + "ALRMIE": { + "description": "Alarm interrupt enable", + "offset": 1, + "size": 1 + }, + "SCIE": { + "description": "Second interrupt", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL": { + "description": "control register", + "offset": 4, + "size": 32, + "reset_value": 32, + "reset_mask": 4294967295, + "children": { + "fields": { + "LWOFF": { + "description": "Last write operation finished flag", + "offset": 5, + "size": 1 + }, + "CMF": { + "description": "Configuration mode flag", + "offset": 4, + "size": 1 + }, + "RSYNF": { + "description": "Registers synchronized flag", + "offset": 3, + "size": 1 + }, + "OVIF": { + "description": "Overflow interrupt flag", + "offset": 2, + "size": 1 + }, + "ALRMIF": { + "description": "Alarm interrupt flag", + "offset": 1, + "size": 1 + }, + "SCIF": { + "description": "Sencond interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "PSCH": { + "description": "RTC prescaler high register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295 + }, + "PSCL": { + "description": " RTC prescaler low\n register", + "offset": 12, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295 + }, + "DIVH": { + "description": "RTC divider high register", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DIV": { + "description": "RTC divider value high", + "offset": 0, + "size": 4 + } + } + } + }, + "DIVL": { + "description": "RTC divider low register", + "offset": 20, + "size": 32, + "reset_value": 32768, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "DIV": { + "description": "RTC divider value low", + "offset": 0, + "size": 16 + } + } + } + }, + "CNTH": { + "description": "RTC counter high register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "RTC counter value high", + "offset": 0, + "size": 16 + } + } + } + }, + "CNTL": { + "description": "RTC counter low register", + "offset": 28, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "RTC counter value low", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "SPI0": { + "description": "Serial peripheral interface", + "children": { + "registers": { + "CTL0": { + "description": "control register 0", + "offset": 0, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "BDEN": { + "description": "Bidirectional \n enable", + "offset": 15, + "size": 1 + }, + "BDOEN": { + "description": "Bidirectional Transmit output enable\n ", + "offset": 14, + "size": 1 + }, + "CRCEN": { + "description": "CRC Calculation Enable", + "offset": 13, + "size": 1 + }, + "CRCNT": { + "description": "CRC Next Transfer", + "offset": 12, + "size": 1 + }, + "FF16": { + "description": "Data frame format", + "offset": 11, + "size": 1 + }, + "RO": { + "description": "Receive only", + "offset": 10, + "size": 1 + }, + "SWNSSEN": { + "description": "NSS Software Mode Selection", + "offset": 9, + "size": 1 + }, + "SWNSS": { + "description": "NSS Pin Selection In NSS Software Mode", + "offset": 8, + "size": 1 + }, + "LF": { + "description": "LSB First Mode", + "offset": 7, + "size": 1 + }, + "SPIEN": { + "description": "SPI enable", + "offset": 6, + "size": 1 + }, + "PSC": { + "description": "Master Clock Prescaler Selection", + "offset": 3, + "size": 3 + }, + "MSTMOD": { + "description": "Master Mode Enable", + "offset": 2, + "size": 1 + }, + "CKPL": { + "description": "Clock polarity Selection", + "offset": 1, + "size": 1 + }, + "CKPH": { + "description": "Clock Phase Selection", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TBEIE": { + "description": "Tx buffer empty interrupt\n enable", + "offset": 7, + "size": 1 + }, + "RBNEIE": { + "description": "RX buffer not empty interrupt\n enable", + "offset": 6, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 5, + "size": 1 + }, + "TMOD": { + "description": "SPI TI mode enable", + "offset": 4, + "size": 1 + }, + "NSSP": { + "description": "SPI NSS pulse mode enable", + "offset": 3, + "size": 1 + }, + "NSSDRV": { + "description": "Drive NSS Output", + "offset": 2, + "size": 1 + }, + "DMATEN": { + "description": "Transmit Buffer DMA Enable", + "offset": 1, + "size": 1 + }, + "DMAREN": { + "description": "Rx buffer DMA enable", + "offset": 0, + "size": 1 + } + } + } + }, + "STAT": { + "description": "status register", + "offset": 8, + "size": 16, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "FERR": { + "description": "Format error", + "offset": 8, + "size": 1, + "access": "read-only" + }, + "TRANS": { + "description": "Transmitting On-going Bit", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "RXORERR": { + "description": "Reception Overrun Error Bit", + "offset": 6, + "size": 1, + "access": "read-only" + }, + "CONFERR": { + "description": "SPI Configuration error", + "offset": 5, + "size": 1, + "access": "read-only" + }, + "CRCERR": { + "description": "SPI CRC Error Bit", + "offset": 4, + "size": 1 + }, + "TXURERR": { + "description": "Transmission underrun error bit", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "I2SCH": { + "description": "I2S channel side", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "TBE": { + "description": "Transmit Buffer Empty", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "RBNE": { + "description": "Receive Buffer Not Empty", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DATA": { + "description": "data register", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "SPI_DATA": { + "description": "Data transfer register", + "offset": 0, + "size": 16 + } + } + } + }, + "CRCPOLY": { + "description": "CRC polynomial register", + "offset": 16, + "size": 16, + "reset_value": 7, + "reset_mask": 4294967295, + "children": { + "fields": { + "CRCPOLY": { + "description": "CRC polynomial value", + "offset": 0, + "size": 16 + } + } + } + }, + "RCRC": { + "description": "RX CRC register", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "RCRC": { + "description": "RX CRC value", + "offset": 0, + "size": 16 + } + } + } + }, + "TCRC": { + "description": "TX CRC register", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "read-only", + "children": { + "fields": { + "TCRC": { + "description": "Tx CRC value", + "offset": 0, + "size": 16 + } + } + } + }, + "I2SCTL": { + "description": "I2S control register", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "I2SSEL": { + "description": "I2S mode selection", + "offset": 11, + "size": 1 + }, + "I2SEN": { + "description": "I2S Enable", + "offset": 10, + "size": 1 + }, + "I2SOPMOD": { + "description": "I2S operation mode", + "offset": 8, + "size": 2 + }, + "PCMSMOD": { + "description": "PCM frame synchronization mode", + "offset": 7, + "size": 1 + }, + "I2SSTD": { + "description": "I2S standard selection", + "offset": 4, + "size": 2 + }, + "CKPL": { + "description": "Idle state clock polarity", + "offset": 3, + "size": 1 + }, + "DTLEN": { + "description": "Data length", + "offset": 1, + "size": 2 + }, + "CHLEN": { + "description": "Channel length (number of bits per audio\n channel)", + "offset": 0, + "size": 1 + } + } + } + }, + "I2SPSC": { + "description": "I2S prescaler register", + "offset": 32, + "size": 16, + "reset_value": 2, + "reset_mask": 4294967295, + "children": { + "fields": { + "MCKOEN": { + "description": "I2S_MCK output enable", + "offset": 9, + "size": 1 + }, + "OF": { + "description": "Odd factor for the\n prescaler", + "offset": 8, + "size": 1 + }, + "DIV": { + "description": "Dividing factor for the prescaler", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "UART3": { + "description": "Universal asynchronous receiver\n transmitter", + "children": { + "registers": { + "STAT": { + "description": "Status register ", + "offset": 0, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "children": { + "fields": { + "LBDF": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TBE": { + "description": "Transmit data buffer empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RBNE": { + "description": "Read data buffer not empty", + "offset": 5, + "size": 1 + }, + "IDLEF": { + "description": "IDLE frame detected flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORERR": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NERR": { + "description": "Noise error flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FERR": { + "description": "Frame error flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PERR": { + "description": "Parity error flag", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DATA": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Transmit or read data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BAUD": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTDIV": { + "description": "Integer part of baud-rate divider", + "offset": 4, + "size": 12 + }, + "FRADIV": { + "description": "Fraction part of baud-rate divider", + "offset": 0, + "size": 4 + } + } + } + }, + "CTL0": { + "description": "Control register 0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UEN": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "WL": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WM": { + "description": "Wakeup method in mute mode", + "offset": 11, + "size": 1 + }, + "PCEN": { + "description": "Parity check function enable", + "offset": 10, + "size": 1 + }, + "PM": { + "description": "Parity mode", + "offset": 9, + "size": 1 + }, + "PERRIE": { + "description": "Parity error interrupt enable", + "offset": 8, + "size": 1 + }, + "TBEIE": { + "description": "Transmitter buffer empty interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt enable", + "offset": 6, + "size": 1 + }, + "RBNEIE": { + "description": "Read data buffer not empty interrupt and overrun error interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE line detected interrupt enable", + "offset": 4, + "size": 1 + }, + "TEN": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "REN": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup from mute mode", + "offset": 1, + "size": 1 + }, + "SBKCMD": { + "description": "Send break command", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "Control register 1", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LMEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STB": { + "description": "STOP bits length", + "offset": 12, + "size": 2 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBLEN": { + "description": "LIN break frame length", + "offset": 5, + "size": 1 + }, + "ADDR": { + "description": "Address of the USART", + "offset": 0, + "size": 4 + } + } + } + }, + "CTL2": { + "description": "Control register 2", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DENT": { + "description": "DMA request enable for transmission", + "offset": 7, + "size": 1 + }, + "DENR": { + "description": "DMA request enable for reception", + "offset": 6, + "size": 1 + }, + "HDEN": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GP": { + "description": "Guard time and prescaler\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "USART0": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "children": { + "registers": { + "STAT": { + "description": "Status register ", + "offset": 0, + "size": 32, + "reset_value": 192, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTSF": { + "description": "CTS change flag", + "offset": 9, + "size": 1 + }, + "LBDF": { + "description": "LIN break detection flag", + "offset": 8, + "size": 1 + }, + "TBE": { + "description": "Transmit data buffer empty", + "offset": 7, + "size": 1, + "access": "read-only" + }, + "TC": { + "description": "Transmission complete", + "offset": 6, + "size": 1 + }, + "RBNE": { + "description": "Read data buffer not empty", + "offset": 5, + "size": 1 + }, + "IDLEF": { + "description": "IDLE frame detected flag", + "offset": 4, + "size": 1, + "access": "read-only" + }, + "ORERR": { + "description": "Overrun error", + "offset": 3, + "size": 1, + "access": "read-only" + }, + "NERR": { + "description": "Noise error flag", + "offset": 2, + "size": 1, + "access": "read-only" + }, + "FERR": { + "description": "Frame error flag", + "offset": 1, + "size": 1, + "access": "read-only" + }, + "PERR": { + "description": "Parity error flag", + "offset": 0, + "size": 1, + "access": "read-only" + } + } + } + }, + "DATA": { + "description": "Data register", + "offset": 4, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DATA": { + "description": "Transmit or read data value", + "offset": 0, + "size": 9 + } + } + } + }, + "BAUD": { + "description": "Baud rate register", + "offset": 8, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "INTDIV": { + "description": "Integer part of baud-rate divider", + "offset": 4, + "size": 12 + }, + "FRADIV": { + "description": "Fraction part of baud-rate divider", + "offset": 0, + "size": 4 + } + } + } + }, + "CTL0": { + "description": "Control register 0", + "offset": 12, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "UEN": { + "description": "USART enable", + "offset": 13, + "size": 1 + }, + "WL": { + "description": "Word length", + "offset": 12, + "size": 1 + }, + "WM": { + "description": "Wakeup method in mute mode", + "offset": 11, + "size": 1 + }, + "PCEN": { + "description": "Parity check function enable", + "offset": 10, + "size": 1 + }, + "PM": { + "description": "Parity mode", + "offset": 9, + "size": 1 + }, + "PERRIE": { + "description": "Parity error interrupt enable", + "offset": 8, + "size": 1 + }, + "TBEIE": { + "description": "Transmitter buffer empty interrupt enable", + "offset": 7, + "size": 1 + }, + "TCIE": { + "description": "Transmission complete interrupt enable", + "offset": 6, + "size": 1 + }, + "RBNEIE": { + "description": "Read data buffer not empty interrupt and overrun error interrupt enable", + "offset": 5, + "size": 1 + }, + "IDLEIE": { + "description": "IDLE line detected interrupt enable", + "offset": 4, + "size": 1 + }, + "TEN": { + "description": "Transmitter enable", + "offset": 3, + "size": 1 + }, + "REN": { + "description": "Receiver enable", + "offset": 2, + "size": 1 + }, + "RWU": { + "description": "Receiver wakeup from mute mode", + "offset": 1, + "size": 1 + }, + "SBKCMD": { + "description": "Send break command", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "Control register 1", + "offset": 16, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "LMEN": { + "description": "LIN mode enable", + "offset": 14, + "size": 1 + }, + "STB": { + "description": "STOP bits length", + "offset": 12, + "size": 2 + }, + "CKEN": { + "description": "CK pin enable", + "offset": 11, + "size": 1 + }, + "CPL": { + "description": "Clock polarity", + "offset": 10, + "size": 1 + }, + "CPH": { + "description": "Clock phase", + "offset": 9, + "size": 1 + }, + "CLEN": { + "description": "CK Length", + "offset": 8, + "size": 1 + }, + "LBDIE": { + "description": "LIN break detection interrupt\n enable", + "offset": 6, + "size": 1 + }, + "LBLEN": { + "description": "LIN break frame length", + "offset": 5, + "size": 1 + }, + "ADDR": { + "description": "Address of the USART", + "offset": 0, + "size": 4 + } + } + } + }, + "CTL2": { + "description": "Control register 2", + "offset": 20, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CTSIE": { + "description": "CTS interrupt enable", + "offset": 10, + "size": 1 + }, + "CTSEN": { + "description": "CTS enable", + "offset": 9, + "size": 1 + }, + "RTSEN": { + "description": "RTS enable", + "offset": 8, + "size": 1 + }, + "DENT": { + "description": "DMA request enable for transmission", + "offset": 7, + "size": 1 + }, + "DENR": { + "description": "DMA request enable for reception", + "offset": 6, + "size": 1 + }, + "SCEN": { + "description": "Smartcard mode enable", + "offset": 5, + "size": 1 + }, + "NKEN": { + "description": "Smartcard NACK enable", + "offset": 4, + "size": 1 + }, + "HDEN": { + "description": "Half-duplex selection", + "offset": 3, + "size": 1 + }, + "IRLP": { + "description": "IrDA low-power", + "offset": 2, + "size": 1 + }, + "IREN": { + "description": "IrDA mode enable", + "offset": 1, + "size": 1 + }, + "ERRIE": { + "description": "Error interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "GP": { + "description": "Guard time and prescaler\n register", + "offset": 24, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "GUAT": { + "description": "Guard time value in Smartcard mode", + "offset": 8, + "size": 8 + }, + "PSC": { + "description": "Prescaler value", + "offset": 0, + "size": 8 + } + } + } + } + } + } + }, + "TIMER0": { + "description": "Advanced-timers", + "children": { + "registers": { + "CTL0": { + "description": "control register 0", + "offset": 0, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKDIV": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARSE": { + "description": "Auto-reload shadow enable", + "offset": 7, + "size": 1 + }, + "CAM": { + "description": "Counter aligns mode\n selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "SPM": { + "description": "Single pulse mode", + "offset": 3, + "size": 1 + }, + "UPS": { + "description": "Update source", + "offset": 2, + "size": 1 + }, + "UPDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ISO3": { + "description": "Idle state of channel 3 output", + "offset": 14, + "size": 1 + }, + "ISO2N": { + "description": "Idle state of channel 2 complementary output", + "offset": 13, + "size": 1 + }, + "ISO2": { + "description": "Idle state of channel 2 output", + "offset": 12, + "size": 1 + }, + "ISO1N": { + "description": "Idle state of channel 1 complementary output", + "offset": 11, + "size": 1 + }, + "ISO1": { + "description": "Idle state of channel 1 output", + "offset": 10, + "size": 1 + }, + "ISO0N": { + "description": "Idle state of channel 0 complementary output", + "offset": 9, + "size": 1 + }, + "ISO0": { + "description": "Idle state of channel 0 output", + "offset": 8, + "size": 1 + }, + "TI0S": { + "description": "Channel 0 trigger input selection", + "offset": 7, + "size": 1 + }, + "MMC": { + "description": "Master mode control", + "offset": 4, + "size": 3 + }, + "DMAS": { + "description": "DMA request source selection", + "offset": 3, + "size": 1 + }, + "CCUC": { + "description": "Commutation control shadow register update control", + "offset": 2, + "size": 1 + }, + "CCSE": { + "description": "Commutation control shadow enable", + "offset": 0, + "size": 1 + } + } + } + }, + "SMCFG": { + "description": "slave mode configuration register", + "offset": 8, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "SMC1": { + "description": "Part of SMC for enable External clock mode1", + "offset": 14, + "size": 1 + }, + "ETPSC": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETFC": { + "description": "External trigger filter control", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master/Slave mode", + "offset": 7, + "size": 1 + }, + "TRGS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMC": { + "description": "Slave mode selection", + "offset": 0, + "size": 3 + } + } + } + }, + "DMAINTEN": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRGDEN": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CMTDEN": { + "description": "Commutation DMA request enable", + "offset": 13, + "size": 1 + }, + "CH3DEN": { + "description": "Channel 3 capture/compare DMA request enable", + "offset": 12, + "size": 1 + }, + "CH2DEN": { + "description": "Channel 2 capture/compare DMA request enable", + "offset": 11, + "size": 1 + }, + "CH1DEN": { + "description": "Channel 1 capture/compare DMA request enable", + "offset": 10, + "size": 1 + }, + "CH0DEN": { + "description": "Channel 0 capture/compare DMA request enable", + "offset": 9, + "size": 1 + }, + "UPDEN": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "BRKIE": { + "description": "Break interrupt enable", + "offset": 7, + "size": 1 + }, + "TRGIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CMTIE": { + "description": "commutation interrupt enable", + "offset": 5, + "size": 1 + }, + "CH3IE": { + "description": "Channel 3 capture/compare interrupt enable", + "offset": 4, + "size": 1 + }, + "CH2IE": { + "description": "Channel 2 capture/compare interrupt enable", + "offset": 3, + "size": 1 + }, + "CH1IE": { + "description": "Channel 1 capture/compare interrupt enable", + "offset": 2, + "size": 1 + }, + "CH0IE": { + "description": "Channel 0 capture/compare interrupt enable", + "offset": 1, + "size": 1 + }, + "UPIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "INTF": { + "description": "Interrupt flag register", + "offset": 16, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3OF": { + "description": "Channel 3 over capture flag", + "offset": 12, + "size": 1 + }, + "CH2OF": { + "description": "Channel 2 over capture flag", + "offset": 11, + "size": 1 + }, + "CH1OF": { + "description": "Channel 1 over capture flag", + "offset": 10, + "size": 1 + }, + "CH0OF": { + "description": "Channel 0 over capture flag", + "offset": 9, + "size": 1 + }, + "BRKIF": { + "description": "Break interrupt flag", + "offset": 7, + "size": 1 + }, + "TRGIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CMTIF": { + "description": "Channel commutation interrupt flag", + "offset": 5, + "size": 1 + }, + "CH3IF": { + "description": "Channel 3 capture/compare interrupt flag", + "offset": 4, + "size": 1 + }, + "CH2IF": { + "description": " Channel 2 capture/compare interrupt flag", + "offset": 3, + "size": 1 + }, + "CH1IF": { + "description": "Channel 1 capture/compare interrupt flag", + "offset": 2, + "size": 1 + }, + "CH0IF": { + "description": "Channel 0 capture/compare interrupt flag", + "offset": 1, + "size": 1 + }, + "UPIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SWEVG": { + "description": "Software event generation register", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "BRKG": { + "description": "Break event generation", + "offset": 7, + "size": 1 + }, + "TRGG": { + "description": "Trigger event generation", + "offset": 6, + "size": 1 + }, + "CMTG": { + "description": "Channel commutation event generation", + "offset": 5, + "size": 1 + }, + "CH3G": { + "description": "Channel 3 capture or compare event generation", + "offset": 4, + "size": 1 + }, + "CH2G": { + "description": "Channel 2 capture or compare event generation", + "offset": 3, + "size": 1 + }, + "CH1G": { + "description": "Channel 1 capture or compare event generation", + "offset": 2, + "size": 1 + }, + "CH0G": { + "description": "Channel 0 capture or compare event generation", + "offset": 1, + "size": 1 + }, + "UPG": { + "description": "Update event generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CHCTL0_Output": { + "description": "Channel control register 0 (output\n mode)", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1COMCEN": { + "description": "Channel 1 output compare clear enable", + "offset": 15, + "size": 1 + }, + "CH1COMCTL": { + "description": "Channel 1 compare output control", + "offset": 12, + "size": 3 + }, + "CH1COMSEN": { + "description": "Channel 1 output compare shadow enable", + "offset": 11, + "size": 1 + }, + "CH1COMFEN": { + "description": "Channel 1 output compare fast enable", + "offset": 10, + "size": 1 + }, + "CH1MS": { + "description": "Channel 1 mode selection", + "offset": 8, + "size": 2 + }, + "CH0COMCEN": { + "description": "Channel 0 output compare clear enable", + "offset": 7, + "size": 1 + }, + "CH0COMCTL": { + "description": "Channel 0 compare output control", + "offset": 4, + "size": 3 + }, + "CH0COMSEN": { + "description": "Channel 0 compare output shadow enable", + "offset": 3, + "size": 1 + }, + "CH0COMFEN": { + "description": "Channel 0 output compare fast enable", + "offset": 2, + "size": 1 + }, + "CH0MS": { + "description": "Channel 0 I/O mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL0_Input": { + "description": "Channel control register 0 (input\n mode)", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1CAPFLT": { + "description": "Channel 1 input capture filter control", + "offset": 12, + "size": 4 + }, + "CH1CAPPSC": { + "description": "Channel 1 input capture prescaler", + "offset": 10, + "size": 2 + }, + "CH1MS": { + "description": "Channel 1 mode selection", + "offset": 8, + "size": 2 + }, + "CH0CAPFLT": { + "description": "Channel 0 input capture filter control", + "offset": 4, + "size": 4 + }, + "CH0CAPPSC": { + "description": "Channel 0 input capture prescaler", + "offset": 2, + "size": 2 + }, + "CH0MS": { + "description": "Channel 0 mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL1_Output": { + "description": "Channel control register 1 (output\n mode)", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3COMCEN": { + "description": "Channel 3 output compare clear enable", + "offset": 15, + "size": 1 + }, + "CH3COMCTL": { + "description": "Channel 3 compare output control", + "offset": 12, + "size": 3 + }, + "CH3COMSEN": { + "description": "Channel 3 output compare shadow enable", + "offset": 11, + "size": 1 + }, + "CH3COMFEN": { + "description": "Channel 3 output compare fast enable", + "offset": 10, + "size": 1 + }, + "CH3MS": { + "description": "Channel 3 mode selection", + "offset": 8, + "size": 2 + }, + "CH2COMCEN": { + "description": "Channel 2 output compare clear enable", + "offset": 7, + "size": 1 + }, + "CH2COMCTL": { + "description": "Channel 2 compare output control", + "offset": 4, + "size": 3 + }, + "CH2COMSEN": { + "description": "Channel 2 compare output shadow enable", + "offset": 3, + "size": 1 + }, + "CH2COMFEN": { + "description": "Channel 2 output compare fast enable", + "offset": 2, + "size": 1 + }, + "CH2MS": { + "description": "Channel 2 I/O mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL1_Input": { + "description": "Channel control register 1 (input\n mode)", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3CAPFLT": { + "description": "Channel 3 input capture filter control", + "offset": 12, + "size": 4 + }, + "CH3CAPPSC": { + "description": "Channel 3 input capture prescaler", + "offset": 10, + "size": 2 + }, + "CH3MS": { + "description": "Channel 3 mode selection", + "offset": 8, + "size": 2 + }, + "CH2CAPFLT": { + "description": "Channel 2 input capture filter control", + "offset": 4, + "size": 4 + }, + "CH2CAPPSC": { + "description": "Channel 2 input capture prescaler", + "offset": 2, + "size": 2 + }, + "CH2MS": { + "description": "Channel 2 mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL2": { + "description": "Channel control register 2", + "offset": 32, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3P": { + "description": "Channel 3 capture/compare function polarity", + "offset": 13, + "size": 1 + }, + "CH3EN": { + "description": "Channel 3 capture/compare function enable", + "offset": 12, + "size": 1 + }, + "CH2NP": { + "description": "Channel 2 complementary output polarity", + "offset": 11, + "size": 1 + }, + "CH2NEN": { + "description": "Channel 2 complementary output enable", + "offset": 10, + "size": 1 + }, + "CH2P": { + "description": "Channel 2 capture/compare function polarity", + "offset": 9, + "size": 1 + }, + "CH2EN": { + "description": "Channel 2 capture/compare function enable", + "offset": 8, + "size": 1 + }, + "CH1NP": { + "description": "Channel 1 complementary output polarity", + "offset": 7, + "size": 1 + }, + "CH1NEN": { + "description": "Channel 1 complementary output enable", + "offset": 6, + "size": 1 + }, + "CH1P": { + "description": "Channel 1 capture/compare function polarity", + "offset": 5, + "size": 1 + }, + "CH1EN": { + "description": "Channel 1 capture/compare function enable", + "offset": 4, + "size": 1 + }, + "CH0NP": { + "description": "Channel 0 complementary output polarity", + "offset": 3, + "size": 1 + }, + "CH0NEN": { + "description": "Channel 0 complementary output enable", + "offset": 2, + "size": 1 + }, + "CH0P": { + "description": "Channel 0 capture/compare function polarity", + "offset": 1, + "size": 1 + }, + "CH0EN": { + "description": "Channel 0 capture/compare function enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "counter", + "offset": 36, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "current counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "prescaler", + "offset": 40, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value of the counter clock", + "offset": 0, + "size": 16 + } + } + } + }, + "CAR": { + "description": "Counter auto reload register", + "offset": 44, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CARL": { + "description": "Counter auto reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CREP": { + "description": "Counter repetition register", + "offset": 48, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CREP": { + "description": "Counter repetition value", + "offset": 0, + "size": 8 + } + } + } + }, + "CH0CV": { + "description": "Channel 0 capture/compare value register", + "offset": 52, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0VAL": { + "description": "Capture or compare value of channel0", + "offset": 0, + "size": 16 + } + } + } + }, + "CH1CV": { + "description": "Channel 1 capture/compare value register", + "offset": 56, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1VAL": { + "description": "Capture or compare value of channel1", + "offset": 0, + "size": 16 + } + } + } + }, + "CH2CV": { + "description": "Channel 2 capture/compare value register", + "offset": 60, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH2VAL": { + "description": "Capture or compare value of channel 2", + "offset": 0, + "size": 16 + } + } + } + }, + "CH3CV": { + "description": "Channel 3 capture/compare value register", + "offset": 64, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3VAL": { + "description": "Capture or compare value of channel 3", + "offset": 0, + "size": 16 + } + } + } + }, + "CCHP": { + "description": "channel complementary protection register", + "offset": 68, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "POEN": { + "description": "Primary output enable", + "offset": 15, + "size": 1 + }, + "OAEN": { + "description": "Output automatic enable", + "offset": 14, + "size": 1 + }, + "BRKP": { + "description": "Break polarity", + "offset": 13, + "size": 1 + }, + "BRKEN": { + "description": "Break enable", + "offset": 12, + "size": 1 + }, + "ROS": { + "description": "Run mode off-state configure", + "offset": 11, + "size": 1 + }, + "IOS": { + "description": "Idle mode off-state configure", + "offset": 10, + "size": 1 + }, + "PROT": { + "description": "Complementary register protect control", + "offset": 8, + "size": 2 + }, + "DTCFG": { + "description": "Dead time configure", + "offset": 0, + "size": 8 + } + } + } + }, + "DMACFG": { + "description": "DMA configuration register", + "offset": 72, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMATC": { + "description": "DMA transfer count", + "offset": 8, + "size": 5 + }, + "DMATA": { + "description": "DMA transfer access start address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMATB": { + "description": "DMA transfer buffer register", + "offset": 76, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMATB": { + "description": "DMA transfer buffer", + "offset": 0, + "size": 16 + } + } + } + } + } + } + }, + "TIMER1": { + "description": "General-purpose-timers", + "children": { + "registers": { + "CTL0": { + "description": "control register 0", + "offset": 0, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CKDIV": { + "description": "Clock division", + "offset": 8, + "size": 2 + }, + "ARSE": { + "description": "Auto-reload shadow enable", + "offset": 7, + "size": 1 + }, + "CAM": { + "description": "Counter aligns mode selection", + "offset": 5, + "size": 2 + }, + "DIR": { + "description": "Direction", + "offset": 4, + "size": 1 + }, + "SPM": { + "description": "Single pulse mode", + "offset": 3, + "size": 1 + }, + "UPS": { + "description": "Update source", + "offset": 2, + "size": 1 + }, + "UPDIS": { + "description": "Update disable", + "offset": 1, + "size": 1 + }, + "CEN": { + "description": "Counter enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CTL1": { + "description": "control register 1", + "offset": 4, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TI0S": { + "description": "Channel 0 trigger input selection", + "offset": 7, + "size": 1 + }, + "MMC": { + "description": "Master mode control", + "offset": 4, + "size": 3 + }, + "DMAS": { + "description": "DMA request source selection", + "offset": 3, + "size": 1 + } + } + } + }, + "SMCFG": { + "description": "slave mode control register", + "offset": 8, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "ETP": { + "description": "External trigger polarity", + "offset": 15, + "size": 1 + }, + "SMC1": { + "description": "Part of SMC for enable External clock mode1", + "offset": 14, + "size": 1 + }, + "ETPSC": { + "description": "External trigger prescaler", + "offset": 12, + "size": 2 + }, + "ETFC": { + "description": "External trigger filter control", + "offset": 8, + "size": 4 + }, + "MSM": { + "description": "Master-slave mode", + "offset": 7, + "size": 1 + }, + "TRGS": { + "description": "Trigger selection", + "offset": 4, + "size": 3 + }, + "SMC": { + "description": "Slave mode control", + "offset": 0, + "size": 3 + } + } + } + }, + "DMAINTEN": { + "description": "DMA/Interrupt enable register", + "offset": 12, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "TRGDEN": { + "description": "Trigger DMA request enable", + "offset": 14, + "size": 1 + }, + "CH3DEN": { + "description": "Channel 3 capture/compare DMA request enable", + "offset": 12, + "size": 1 + }, + "CH2DEN": { + "description": "Channel 2 capture/compare DMA request enable", + "offset": 11, + "size": 1 + }, + "CH1DEN": { + "description": "Channel 1 capture/compare DMA request enable", + "offset": 10, + "size": 1 + }, + "CH0DEN": { + "description": "Channel 0 capture/compare DMA request enable", + "offset": 9, + "size": 1 + }, + "UPDEN": { + "description": "Update DMA request enable", + "offset": 8, + "size": 1 + }, + "TRGIE": { + "description": "Trigger interrupt enable", + "offset": 6, + "size": 1 + }, + "CH3IE": { + "description": "Channel 3 capture/compare interrupt enable", + "offset": 4, + "size": 1 + }, + "CH2IE": { + "description": "Channel 2 capture/compare interrupt enable", + "offset": 3, + "size": 1 + }, + "CH1IE": { + "description": "Channel 1 capture/compare interrupt enable", + "offset": 2, + "size": 1 + }, + "CH0IE": { + "description": "Channel 0 capture/compare interrupt enable", + "offset": 1, + "size": 1 + }, + "UPIE": { + "description": "Update interrupt enable", + "offset": 0, + "size": 1 + } + } + } + }, + "INTF": { + "description": "interrupt flag register", + "offset": 16, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3OF": { + "description": "Channel 3 over capture flag", + "offset": 12, + "size": 1 + }, + "CH2OF": { + "description": "Channel 2 over capture flag", + "offset": 11, + "size": 1 + }, + "CH1OF": { + "description": "Channel 1 over capture flag", + "offset": 10, + "size": 1 + }, + "CH0OF": { + "description": "Channel 0 over capture flag", + "offset": 9, + "size": 1 + }, + "TRGIF": { + "description": "Trigger interrupt flag", + "offset": 6, + "size": 1 + }, + "CH3IF": { + "description": "Channel 3 capture/compare interrupt enable", + "offset": 4, + "size": 1 + }, + "CH2IF": { + "description": "Channel 2 capture/compare interrupt enable", + "offset": 3, + "size": 1 + }, + "CH1IF": { + "description": "Channel 1 capture/compare interrupt flag", + "offset": 2, + "size": 1 + }, + "CH0IF": { + "description": "Channel 0 capture/compare interrupt flag", + "offset": 1, + "size": 1 + }, + "UPIF": { + "description": "Update interrupt flag", + "offset": 0, + "size": 1 + } + } + } + }, + "SWEVG": { + "description": "event generation register", + "offset": 20, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "access": "write-only", + "children": { + "fields": { + "TRGG": { + "description": "Trigger event generation", + "offset": 6, + "size": 1 + }, + "CH3G": { + "description": "Channel 3 capture or compare event generation", + "offset": 4, + "size": 1 + }, + "CH2G": { + "description": "Channel 2 capture or compare event generation", + "offset": 3, + "size": 1 + }, + "CH1G": { + "description": "Channel 1 capture or compare event generation", + "offset": 2, + "size": 1 + }, + "CH0G": { + "description": "Channel 0 capture or compare event generation", + "offset": 1, + "size": 1 + }, + "UPG": { + "description": "Update generation", + "offset": 0, + "size": 1 + } + } + } + }, + "CHCTL0_Output": { + "description": "Channel control register 0 (output\n mode)", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1COMCEN": { + "description": "Channel 1 output compare clear enable", + "offset": 15, + "size": 1 + }, + "CH1COMCTL": { + "description": "Channel 1 compare output control", + "offset": 12, + "size": 3 + }, + "CH1COMSEN": { + "description": "Channel 1 output compare shadow enable", + "offset": 11, + "size": 1 + }, + "CH1COMFEN": { + "description": "Channel 1 output compare fast enable", + "offset": 10, + "size": 1 + }, + "CH1MS": { + "description": "Channel 1 mode selection", + "offset": 8, + "size": 2 + }, + "CH0COMCEN": { + "description": "Channel 0 output compare clear enable", + "offset": 7, + "size": 1 + }, + "CH0COMCTL": { + "description": " Channel 0 compare output control", + "offset": 4, + "size": 3 + }, + "CH0COMSEN": { + "description": "Channel 0 compare output shadow enable", + "offset": 3, + "size": 1 + }, + "CH0COMFEN": { + "description": "Channel 0 output compare fast enable", + "offset": 2, + "size": 1 + }, + "CH0MS": { + "description": "Channel 0 I/O mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL0_Input": { + "description": "Channel control register 0 (input\n mode)", + "offset": 24, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1CAPFLT": { + "description": "Channel 1 input capture filter control", + "offset": 12, + "size": 4 + }, + "CH1CAPPSC": { + "description": "Channel 1 input capture prescaler", + "offset": 10, + "size": 2 + }, + "CH1MS": { + "description": "Channel 1 mode selection", + "offset": 8, + "size": 2 + }, + "CH0CAPFLT": { + "description": "Channel 0 input capture filter control", + "offset": 4, + "size": 4 + }, + "CH0CAPPSC": { + "description": "Channel 0 input capture prescaler", + "offset": 2, + "size": 2 + }, + "CH0MS": { + "description": "Channel 0 mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL1_Output": { + "description": "Channel control register 1 (output mode)", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3COMCEN": { + "description": "Channel 3 output compare clear enable", + "offset": 15, + "size": 1 + }, + "CH3COMCTL": { + "description": "Channel 3 compare output control", + "offset": 12, + "size": 3 + }, + "CH3COMSEN": { + "description": "Channel 3 output compare shadow enable", + "offset": 11, + "size": 1 + }, + "CH3COMFEN": { + "description": "Channel 3 output compare fast enable", + "offset": 10, + "size": 1 + }, + "CH3MS": { + "description": "Channel 3 mode selection", + "offset": 8, + "size": 2 + }, + "CH2COMCEN": { + "description": "Channel 2 output compare clear enable", + "offset": 7, + "size": 1 + }, + "CH2COMCTL": { + "description": "Channel 2 compare output control", + "offset": 4, + "size": 3 + }, + "CH2COMSEN": { + "description": "Channel 2 compare output shadow enable", + "offset": 3, + "size": 1 + }, + "CH2COMFEN": { + "description": "Channel 2 output compare fast enable", + "offset": 2, + "size": 1 + }, + "CH2MS": { + "description": "Channel 2 I/O mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL1_Input": { + "description": "Channel control register 1 (input\n mode)", + "offset": 28, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3CAPFLT": { + "description": "Channel 3 input capture filter control", + "offset": 12, + "size": 4 + }, + "CH3CAPPSC": { + "description": "Channel 3 input capture prescaler", + "offset": 10, + "size": 2 + }, + "CH3MS": { + "description": "Channel 3 mode selection", + "offset": 8, + "size": 2 + }, + "CH2CAPFLT": { + "description": "Channel 2 input capture filter control", + "offset": 4, + "size": 4 + }, + "CH2CAPPSC": { + "description": "Channel 2 input capture prescaler", + "offset": 2, + "size": 2 + }, + "CH2MS": { + "description": "Channel 2 mode selection", + "offset": 0, + "size": 2 + } + } + } + }, + "CHCTL2": { + "description": "Channel control register 2", + "offset": 32, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3P": { + "description": "Channel 3 capture/compare function polarity", + "offset": 13, + "size": 1 + }, + "CH3EN": { + "description": "Channel 3 capture/compare function enable", + "offset": 12, + "size": 1 + }, + "CH2P": { + "description": "Channel 2 capture/compare function polarity", + "offset": 9, + "size": 1 + }, + "CH2EN": { + "description": "Channel 2 capture/compare function enable", + "offset": 8, + "size": 1 + }, + "CH1P": { + "description": "Channel 1 capture/compare function polarity", + "offset": 5, + "size": 1 + }, + "CH1EN": { + "description": "Channel 1 capture/compare function enable", + "offset": 4, + "size": 1 + }, + "CH0P": { + "description": "Channel 0 capture/compare function polarity", + "offset": 1, + "size": 1 + }, + "CH0EN": { + "description": "Channel 0 capture/compare function enable", + "offset": 0, + "size": 1 + } + } + } + }, + "CNT": { + "description": "Counter register", + "offset": 36, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CNT": { + "description": "counter value", + "offset": 0, + "size": 16 + } + } + } + }, + "PSC": { + "description": "Prescaler register", + "offset": 40, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "PSC": { + "description": "Prescaler value of the counter clock", + "offset": 0, + "size": 16 + } + } + } + }, + "CAR": { + "description": "Counter auto reload register", + "offset": 44, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CARL": { + "description": "Counter auto reload value", + "offset": 0, + "size": 16 + } + } + } + }, + "CH0CV": { + "description": "Channel 0 capture/compare value register", + "offset": 52, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH0VAL": { + "description": "Capture or compare value of channel 0", + "offset": 0, + "size": 16 + } + } + } + }, + "CH1CV": { + "description": "Channel 1 capture/compare value register", + "offset": 56, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH1VAL": { + "description": "Capture or compare value of channel1", + "offset": 0, + "size": 16 + } + } + } + }, + "CH2CV": { + "description": "Channel 2 capture/compare value register", + "offset": 60, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH2VAL": { + "description": "Capture or compare value of channel 2", + "offset": 0, + "size": 16 + } + } + } + }, + "CH3CV": { + "description": "Channel 3 capture/compare value register", + "offset": 64, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "CH3VAL": { + "description": "Capture or compare value of channel 3", + "offset": 0, + "size": 16 + } + } + } + }, + "DMACFG": { + "description": "DMA configuration register", + "offset": 72, + "size": 16, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMATC": { + "description": "DMA transfer count", + "offset": 8, + "size": 5 + }, + "DMATA": { + "description": "DMA transfer access start address", + "offset": 0, + "size": 5 + } + } + } + }, + "DMATB": { + "description": "DMA transfer buffer register", + "offset": 76, + "size": 32, + "reset_value": 0, + "reset_mask": 4294967295, + "children": { + "fields": { + "DMATB": { + "description": "DMA transfer buffer", + "offset": 0, + "size": 16 + } + } + } + } + } + } + } + } + }, + "devices": { + "GD32VF103": { + "arch": "cortex_m3", + "description": "GD32VF103 RISC-V Microcontroller based device", + "properties": { + "cpu.nvic_prio_bits": "4", + "cpu.mpu": "0", + "cpu.fpu": "0", + "cpu.revision": "r2p1", + "cpu.vendor_systick_config": "0", + "license": "\n Copyright 2019 Sipeed Co.,Ltd.\n \n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n", + "cpu.name": "CM3", + "cpu.endian": "little" + }, + "children": { + "interrupts": { + "MemManageFault": { + "index": -12 + }, + "BusFault": { + "index": -11 + }, + "UsageFault": { + "index": -10 + }, + "DebugMonitor": { + "index": -4 + }, + "NMI": { + "index": -14 + }, + "HardFault": { + "index": -13 + }, + "SVCall": { + "index": -5 + }, + "PendSV": { + "index": -2 + }, + "SysTick": { + "index": -1 + }, + "ADC0_1": { + "index": 37 + }, + "Tamper": { + "index": 21 + }, + "CAN0_TX": { + "index": 38 + }, + "CAN0_RX0": { + "index": 39 + }, + "CAN0_RX1": { + "index": 40 + }, + "CAN0_EWMC": { + "index": 41 + }, + "CAN1_TX": { + "index": 82 + }, + "CAN1_RX0": { + "index": 83 + }, + "CAN1_RX1": { + "index": 84 + }, + "CAN1_EWMC": { + "index": 85 + }, + "DMA0_Channel0": { + "index": 30 + }, + "DMA0_Channel1": { + "index": 31 + }, + "DMA0_Channel2": { + "index": 32 + }, + "DMA0_Channel3": { + "index": 33 + }, + "DMA0_Channel4": { + "index": 34 + }, + "DMA0_Channel5": { + "index": 35 + }, + "DMA0_Channel6": { + "index": 36 + }, + "DMA1_Channel0": { + "index": 75 + }, + "DMA1_Channel1": { + "index": 76 + }, + "DMA1_Channel2": { + "index": 77 + }, + "DMA1_Channel3": { + "index": 78 + }, + "DMA1_Channel4": { + "index": 79 + }, + "EXTI_Line0": { + "index": 25 + }, + "EXTI_Line1": { + "index": 26 + }, + "EXTI_Line2": { + "index": 27 + }, + "EXTI_Line3": { + "index": 28 + }, + "EXTI_Line4": { + "index": 29 + }, + "EXTI_line9_5": { + "index": 42 + }, + "EXTI_line15_10": { + "index": 59 + }, + "FMC": { + "index": 23 + }, + "I2C0_EV": { + "index": 50 + }, + "I2C0_ER": { + "index": 51 + }, + "I2C1_EV": { + "index": 52 + }, + "I2C1_ER": { + "index": 53 + }, + "RCU": { + "index": 24 + }, + "RTC": { + "index": 22 + }, + "RTC_Alarm": { + "index": 60 + }, + "SPI0": { + "index": 54 + }, + "SPI1": { + "index": 55 + }, + "SPI2": { + "index": 70 + }, + "TIMER0_BRK": { + "index": 43 + }, + "TIMER0_UP": { + "index": 44 + }, + "TIMER0_TRG_CMT": { + "index": 45 + }, + "TIMER0_Channel": { + "index": 46 + }, + "TIMER1": { + "index": 47 + }, + "TIMER2": { + "index": 48 + }, + "TIMER3": { + "index": 49 + }, + "TIMER4": { + "index": 69 + }, + "TIMER5": { + "index": 73 + }, + "TIMER6": { + "index": 74 + }, + "USART0": { + "index": 56 + }, + "USART1": { + "index": 57 + }, + "USART2": { + "index": 58 + }, + "UART3": { + "index": 71 + }, + "UART4": { + "index": 72 + }, + "USBFS_WKUP": { + "index": 61 + }, + "USBFS": { + "index": 86 + }, + "WWDGT": { + "index": 0 + } + }, + "peripheral_instances": { + "SysTick": { + "offset": 3758153744, + "type": "types.peripherals.SCS.children.register_groups.SysTick" + }, + "ADC0": { + "description": "Analog to digital converter", + "offset": 1073816576, + "type": "types.peripherals.ADC0" + }, + "ADC1": { + "description": "Analog to digital converter", + "offset": 1073817600, + "type": "types.peripherals.ADC1" + }, + "AFIO": { + "description": "Alternate-function I/Os", + "offset": 1073807360, + "type": "types.peripherals.AFIO" + }, + "BKP": { + "description": "Backup registers", + "offset": 1073769472, + "type": "types.peripherals.BKP" + }, + "CAN0": { + "description": "Controller area network", + "offset": 1073767424, + "type": "types.peripherals.CAN0" + }, + "CAN1": { + "offset": 1073768448, + "type": "types.peripherals.CAN0" + }, + "CRC": { + "description": "cyclic redundancy check calculation unit", + "offset": 1073885184, + "type": "types.peripherals.CRC" + }, + "DAC": { + "description": "Digital-to-analog converter", + "offset": 1073771520, + "type": "types.peripherals.DAC" + }, + "DBG": { + "description": "Debug support", + "offset": 3758366720, + "type": "types.peripherals.DBG" + }, + "DMA0": { + "description": "DMA controller", + "offset": 1073872896, + "type": "types.peripherals.DMA0" + }, + "DMA1": { + "description": "Direct memory access controller", + "offset": 1073872896, + "type": "types.peripherals.DMA1" + }, + "EXMC": { + "description": "External memory controller", + "offset": 2684354560, + "type": "types.peripherals.EXMC" + }, + "EXTI": { + "description": "External interrupt/event\n controller", + "offset": 1073808384, + "type": "types.peripherals.EXTI" + }, + "FMC": { + "description": "FMC", + "offset": 1073881088, + "type": "types.peripherals.FMC" + }, + "FWDGT": { + "description": "free watchdog timer", + "offset": 1073754112, + "type": "types.peripherals.FWDGT" + }, + "GPIOA": { + "description": "General-purpose I/Os", + "offset": 1073809408, + "type": "types.peripherals.GPIOA" + }, + "GPIOB": { + "offset": 1073810432, + "type": "types.peripherals.GPIOA" + }, + "GPIOC": { + "offset": 1073811456, + "type": "types.peripherals.GPIOA" + }, + "GPIOD": { + "offset": 1073812480, + "type": "types.peripherals.GPIOA" + }, + "GPIOE": { + "offset": 1073813504, + "type": "types.peripherals.GPIOA" + }, + "I2C0": { + "description": "Inter integrated circuit", + "offset": 1073763328, + "type": "types.peripherals.I2C0" + }, + "I2C1": { + "offset": 1073764352, + "type": "types.peripherals.I2C0" + }, + "ECLIC": { + "description": "Enhanced Core Local Interrupt Controller", + "offset": 3523215360, + "type": "types.peripherals.ECLIC" + }, + "PMU": { + "description": "Power management unit", + "offset": 1073770496, + "type": "types.peripherals.PMU" + }, + "RCU": { + "description": "Reset and clock unit", + "offset": 1073876992, + "type": "types.peripherals.RCU" + }, + "RTC": { + "description": "Real-time clock", + "offset": 1073752064, + "type": "types.peripherals.RTC" + }, + "SPI0": { + "description": "Serial peripheral interface", + "offset": 1073819648, + "type": "types.peripherals.SPI0" + }, + "SPI1": { + "offset": 1073756160, + "type": "types.peripherals.SPI0" + }, + "SPI2": { + "offset": 1073757184, + "type": "types.peripherals.SPI0" + }, + "TIMER0": { + "description": "Advanced-timers", + "offset": 1073818624, + "type": "types.peripherals.TIMER0" + }, + "TIMER1": { + "description": "General-purpose-timers", + "offset": 1073741824, + "type": "types.peripherals.TIMER1" + }, + "TIMER2": { + "offset": 1073742848, + "type": "types.peripherals.TIMER1" + }, + "TIMER3": { + "offset": 1073743872, + "type": "types.peripherals.TIMER1" + }, + "TIMER4": { + "offset": 1073744896, + "type": "types.peripherals.TIMER1" + }, + "TIMER5": { + "description": "Basic-timers", + "offset": 1073745920, + "type": "types.peripherals.TIMER5" + }, + "TIMER6": { + "offset": 1073746944, + "type": "types.peripherals.TIMER5" + }, + "USART0": { + "description": "Universal synchronous asynchronous receiver\n transmitter", + "offset": 1073821696, + "type": "types.peripherals.USART0" + }, + "USART1": { + "offset": 1073759232, + "type": "types.peripherals.USART0" + }, + "USART2": { + "offset": 1073760256, + "type": "types.peripherals.USART0" + }, + "UART3": { + "description": "Universal asynchronous receiver\n transmitter", + "offset": 1073761280, + "type": "types.peripherals.UART3" + }, + "UART4": { + "offset": 1073762304, + "type": "types.peripherals.UART3" + }, + "USBFS_GLOBAL": { + "description": "USB full speed global registers", + "offset": 1342177280, + "type": "types.peripherals.USBFS_GLOBAL" + }, + "USBFS_HOST": { + "description": "USB on the go full speed host", + "offset": 1342178304, + "type": "types.peripherals.USBFS_HOST" + }, + "USBFS_DEVICE": { + "description": "USB on the go full speed device", + "offset": 1342179328, + "type": "types.peripherals.USBFS_DEVICE" + }, + "USBFS_PWRCLK": { + "description": "USB on the go full speed", + "offset": 1342180864, + "type": "types.peripherals.USBFS_PWRCLK" + }, + "WWDGT": { + "description": "Window watchdog timer", + "offset": 1073753088, + "type": "types.peripherals.WWDGT" + } + } + } + } + } +} \ No newline at end of file diff --git a/src/chips/GD32VF103.zig b/src/chips/GD32VF103.zig new file mode 100644 index 0000000..77618b4 --- /dev/null +++ b/src/chips/GD32VF103.zig @@ -0,0 +1,12849 @@ +const micro = @import("microzig"); +const mmio = micro.mmio; + +pub const devices = struct { + /// GD32VF103 RISC-V Microcontroller based device + pub const GD32VF103 = struct { + pub const properties = struct { + pub const @"cpu.nvic_prio_bits" = "4"; + pub const @"cpu.mpu" = "0"; + pub const @"cpu.fpu" = "0"; + pub const @"cpu.revision" = "r2p1"; + pub const @"cpu.vendor_systick_config" = "0"; + pub const license = + \\ + \\ Copyright 2019 Sipeed Co.,Ltd. + \\ + \\ Licensed under the Apache License, Version 2.0 (the "License"); + \\ you may not use this file except in compliance with the License. + \\ You may obtain a copy of the License at + \\ + \\ http://www.apache.org/licenses/LICENSE-2.0 + \\ + \\ Unless required by applicable law or agreed to in writing, software + \\ distributed under the License is distributed on an "AS IS" BASIS, + \\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + \\ See the License for the specific language governing permissions and + \\ limitations under the License. + \\ + ; + pub const @"cpu.name" = "CM3"; + pub const @"cpu.endian" = "little"; + }; + + pub const VectorTable = extern struct { + const Handler = micro.interrupt.Handler; + const unhandled = micro.interrupt.unhandled; + + initial_stack_pointer: u32, + Reset: Handler = unhandled, + NMI: Handler = unhandled, + HardFault: Handler = unhandled, + MemManageFault: Handler = unhandled, + BusFault: Handler = unhandled, + UsageFault: Handler = unhandled, + reserved5: [4]u32 = undefined, + SVCall: Handler = unhandled, + DebugMonitor: Handler = unhandled, + reserved11: [1]u32 = undefined, + PendSV: Handler = unhandled, + SysTick: Handler = unhandled, + WWDGT: Handler = unhandled, + reserved15: [20]u32 = undefined, + Tamper: Handler = unhandled, + RTC: Handler = unhandled, + FMC: Handler = unhandled, + RCU: Handler = unhandled, + EXTI_Line0: Handler = unhandled, + EXTI_Line1: Handler = unhandled, + EXTI_Line2: Handler = unhandled, + EXTI_Line3: Handler = unhandled, + EXTI_Line4: Handler = unhandled, + DMA0_Channel0: Handler = unhandled, + DMA0_Channel1: Handler = unhandled, + DMA0_Channel2: Handler = unhandled, + DMA0_Channel3: Handler = unhandled, + DMA0_Channel4: Handler = unhandled, + DMA0_Channel5: Handler = unhandled, + DMA0_Channel6: Handler = unhandled, + ADC0_1: Handler = unhandled, + CAN0_TX: Handler = unhandled, + CAN0_RX0: Handler = unhandled, + CAN0_RX1: Handler = unhandled, + CAN0_EWMC: Handler = unhandled, + EXTI_line9_5: Handler = unhandled, + TIMER0_BRK: Handler = unhandled, + TIMER0_UP: Handler = unhandled, + TIMER0_TRG_CMT: Handler = unhandled, + TIMER0_Channel: Handler = unhandled, + TIMER1: Handler = unhandled, + TIMER2: Handler = unhandled, + TIMER3: Handler = unhandled, + I2C0_EV: Handler = unhandled, + I2C0_ER: Handler = unhandled, + I2C1_EV: Handler = unhandled, + I2C1_ER: Handler = unhandled, + SPI0: Handler = unhandled, + SPI1: Handler = unhandled, + USART0: Handler = unhandled, + USART1: Handler = unhandled, + USART2: Handler = unhandled, + EXTI_line15_10: Handler = unhandled, + RTC_Alarm: Handler = unhandled, + USBFS_WKUP: Handler = unhandled, + reserved76: [7]u32 = undefined, + TIMER4: Handler = unhandled, + SPI2: Handler = unhandled, + UART3: Handler = unhandled, + UART4: Handler = unhandled, + TIMER5: Handler = unhandled, + TIMER6: Handler = unhandled, + DMA1_Channel0: Handler = unhandled, + DMA1_Channel1: Handler = unhandled, + DMA1_Channel2: Handler = unhandled, + DMA1_Channel3: Handler = unhandled, + DMA1_Channel4: Handler = unhandled, + reserved94: [2]u32 = undefined, + CAN1_TX: Handler = unhandled, + CAN1_RX0: Handler = unhandled, + CAN1_RX1: Handler = unhandled, + CAN1_EWMC: Handler = unhandled, + USBFS: Handler = unhandled, + }; + + pub const peripherals = struct { + /// General-purpose-timers + pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000000); + /// General-purpose-timers + pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000400); + /// General-purpose-timers + pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000800); + /// General-purpose-timers + pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000c00); + /// Basic-timers + pub const TIMER5 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001000); + /// Basic-timers + pub const TIMER6 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001400); + /// Real-time clock + pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x40002800); + /// Window watchdog timer + pub const WWDGT = @intToPtr(*volatile types.peripherals.WWDGT, 0x40002c00); + /// free watchdog timer + pub const FWDGT = @intToPtr(*volatile types.peripherals.FWDGT, 0x40003000); + /// Serial peripheral interface + pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003800); + /// Serial peripheral interface + pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003c00); + /// Universal synchronous asynchronous receiver transmitter + pub const USART1 = @intToPtr(*volatile types.peripherals.USART0, 0x40004400); + /// Universal synchronous asynchronous receiver transmitter + pub const USART2 = @intToPtr(*volatile types.peripherals.USART0, 0x40004800); + /// Universal asynchronous receiver transmitter + pub const UART3 = @intToPtr(*volatile types.peripherals.UART3, 0x40004c00); + /// Universal asynchronous receiver transmitter + pub const UART4 = @intToPtr(*volatile types.peripherals.UART3, 0x40005000); + /// Inter integrated circuit + pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005400); + /// Inter integrated circuit + pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005800); + /// Controller area network + pub const CAN0 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006400); + /// Controller area network + pub const CAN1 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006800); + /// Backup registers + pub const BKP = @intToPtr(*volatile types.peripherals.BKP, 0x40006c00); + /// Power management unit + pub const PMU = @intToPtr(*volatile types.peripherals.PMU, 0x40007000); + /// Digital-to-analog converter + pub const DAC = @intToPtr(*volatile types.peripherals.DAC, 0x40007400); + /// Alternate-function I/Os + pub const AFIO = @intToPtr(*volatile types.peripherals.AFIO, 0x40010000); + /// External interrupt/event controller + pub const EXTI = @intToPtr(*volatile types.peripherals.EXTI, 0x40010400); + /// General-purpose I/Os + pub const GPIOA = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010800); + /// General-purpose I/Os + pub const GPIOB = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010c00); + /// General-purpose I/Os + pub const GPIOC = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011000); + /// General-purpose I/Os + pub const GPIOD = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011400); + /// General-purpose I/Os + pub const GPIOE = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011800); + /// Analog to digital converter + pub const ADC0 = @intToPtr(*volatile types.peripherals.ADC0, 0x40012400); + /// Analog to digital converter + pub const ADC1 = @intToPtr(*volatile types.peripherals.ADC1, 0x40012800); + /// Advanced-timers + pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40012c00); + /// Serial peripheral interface + pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40013000); + /// Universal synchronous asynchronous receiver transmitter + pub const USART0 = @intToPtr(*volatile types.peripherals.USART0, 0x40013800); + /// DMA controller + pub const DMA0 = @intToPtr(*volatile types.peripherals.DMA0, 0x40020000); + /// Direct memory access controller + pub const DMA1 = @intToPtr(*volatile types.peripherals.DMA1, 0x40020000); + /// Reset and clock unit + pub const RCU = @intToPtr(*volatile types.peripherals.RCU, 0x40021000); + /// FMC + pub const FMC = @intToPtr(*volatile types.peripherals.FMC, 0x40022000); + /// cyclic redundancy check calculation unit + pub const CRC = @intToPtr(*volatile types.peripherals.CRC, 0x40023000); + /// USB full speed global registers + pub const USBFS_GLOBAL = @intToPtr(*volatile types.peripherals.USBFS_GLOBAL, 0x50000000); + /// USB on the go full speed host + pub const USBFS_HOST = @intToPtr(*volatile types.peripherals.USBFS_HOST, 0x50000400); + /// USB on the go full speed device + pub const USBFS_DEVICE = @intToPtr(*volatile types.peripherals.USBFS_DEVICE, 0x50000800); + /// USB on the go full speed + pub const USBFS_PWRCLK = @intToPtr(*volatile types.peripherals.USBFS_PWRCLK, 0x50000e00); + /// External memory controller + pub const EXMC = @intToPtr(*volatile types.peripherals.EXMC, 0xa0000000); + /// Enhanced Core Local Interrupt Controller + pub const ECLIC = @intToPtr(*volatile types.peripherals.ECLIC, 0xd2000000); + /// System Tick Timer + pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); + /// Debug support + pub const DBG = @intToPtr(*volatile types.peripherals.DBG, 0xe0042000); + }; + }; +}; + +pub const types = struct { + pub const peripherals = struct { + /// System Control Space + pub const SCS = struct { + /// System Tick Timer + pub const SysTick = extern struct { + /// SysTick Control and Status Register + CTRL: mmio.Mmio(packed struct(u32) { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved16: u13, + COUNTFLAG: u1, + padding: u15, + }), + /// SysTick Reload Value Register + LOAD: mmio.Mmio(packed struct(u32) { + RELOAD: u24, + padding: u8, + }), + /// SysTick Current Value Register + VAL: mmio.Mmio(packed struct(u32) { + CURRENT: u24, + padding: u8, + }), + /// SysTick Calibration Register + CALIB: mmio.Mmio(packed struct(u32) { + TENMS: u24, + reserved30: u6, + SKEW: u1, + NOREF: u1, + }), + }; + }; + + /// Analog to digital converter + pub const ADC0 = extern struct { + /// status register + STAT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog event flag + WDE: u1, + /// End of group conversion flag + EOC: u1, + /// End of inserted group conversion flag + EOIC: u1, + /// Start flag of inserted channel group + STIC: u1, + /// Start flag of regular channel group + STRC: u1, + padding: u27, + }), + /// control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select + WDCHSEL: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Interrupt enable for WDE + WDEIE: u1, + /// Interrupt enable for EOIC + EOICIE: u1, + /// Scan mode + SM: u1, + /// When in scan mode, analog watchdog is effective on a single channel + WDSC: u1, + /// Inserted channel group convert automatically + ICA: u1, + /// Discontinuous mode on regular channels + DISRC: u1, + /// Discontinuous mode on inserted channels + DISIC: u1, + /// Number of conversions in discontinuous mode + DISNUM: u3, + /// sync mode selection + SYNCM: u4, + reserved22: u2, + /// Inserted channel analog watchdog enable + IWDEN: u1, + /// Regular channel analog watchdog enable + RWDEN: u1, + padding: u8, + }), + /// control register 1 + CTL1: mmio.Mmio(packed struct(u32) { + /// ADC on + ADCON: u1, + /// Continuous mode + CTN: u1, + /// ADC calibration + CLB: u1, + /// Reset calibration + RSTCLB: u1, + reserved8: u4, + /// DMA request enable + DMA: u1, + reserved11: u2, + /// Data alignment + DAL: u1, + /// External trigger select for inserted channel + ETSIC: u3, + /// External trigger select for inserted channel + ETEIC: u1, + reserved17: u1, + /// External trigger select for regular channel + ETSRC: u3, + /// External trigger enable for regular channel + ETERC: u1, + /// Start on inserted channel + SWICST: u1, + /// Start on regular channel + SWRCST: u1, + /// Channel 16 and 17 enable of ADC0 + TSVREN: u1, + padding: u8, + }), + /// Sample time register 0 + SAMPT0: mmio.Mmio(packed struct(u32) { + /// Channel 10 sample time selection + SPT10: u3, + /// Channel 11 sample time selection + SPT11: u3, + /// Channel 12 sample time selection + SPT12: u3, + /// Channel 13 sample time selection + SPT13: u3, + /// Channel 14 sample time selection + SPT14: u3, + /// Channel 15 sample time selection + SPT15: u3, + /// Channel 16 sample time selection + SPT16: u3, + /// Channel 17 sample time selection + SPT17: u3, + padding: u8, + }), + /// Sample time register 1 + SAMPT1: mmio.Mmio(packed struct(u32) { + /// Channel 0 sample time selection + SPT0: u3, + /// Channel 1 sample time selection + SPT1: u3, + /// Channel 2 sample time selection + SPT2: u3, + /// Channel 3 sample time selection + SPT3: u3, + /// Channel 4 sample time selection + SPT4: u3, + /// Channel 5 sample time selection + SPT5: u3, + /// Channel 6 sample time selection + SPT6: u3, + /// Channel 7 sample time selection + SPT7: u3, + /// Channel 8 sample time selection + SPT8: u3, + /// Channel 9 sample time selection + SPT9: u3, + padding: u2, + }), + /// Inserted channel data offset register 0 + IOFF0: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 0 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 1 + IOFF1: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 1 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 2 + IOFF2: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 2 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 3 + IOFF3: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 3 + IOFF: u12, + padding: u20, + }), + /// watchdog higher threshold register + WDHT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + WDHT: u12, + padding: u20, + }), + /// watchdog lower threshold register + WDLT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + WDLT: u12, + padding: u20, + }), + /// regular sequence register 0 + RSQ0: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + RSQ12: u5, + /// 14th conversion in regular sequence + RSQ13: u5, + /// 15th conversion in regular sequence + RSQ14: u5, + /// 16th conversion in regular sequence + RSQ15: u5, + /// Regular channel group length + RL: u4, + padding: u8, + }), + /// regular sequence register 1 + RSQ1: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + RSQ6: u5, + /// 8th conversion in regular sequence + RSQ7: u5, + /// 9th conversion in regular sequence + RSQ8: u5, + /// 10th conversion in regular sequence + RSQ9: u5, + /// 11th conversion in regular sequence + RSQ10: u5, + /// 12th conversion in regular sequence + RSQ11: u5, + padding: u2, + }), + /// regular sequence register 2 + RSQ2: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + RSQ0: u5, + /// 2nd conversion in regular sequence + RSQ1: u5, + /// 3rd conversion in regular sequence + RSQ2: u5, + /// 4th conversion in regular sequence + RSQ3: u5, + /// 5th conversion in regular sequence + RSQ4: u5, + /// 6th conversion in regular sequence + RSQ5: u5, + padding: u2, + }), + /// Inserted sequence register + ISQ: mmio.Mmio(packed struct(u32) { + /// 1st conversion in inserted sequence + ISQ0: u5, + /// 2nd conversion in inserted sequence + ISQ1: u5, + /// 3rd conversion in inserted sequence + ISQ2: u5, + /// 4th conversion in inserted sequence + ISQ3: u5, + /// Inserted channel group length + IL: u2, + padding: u10, + }), + /// Inserted data register 0 + IDATA0: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 1 + IDATA1: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 2 + IDATA2: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 3 + IDATA3: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// regular data register + RDATA: mmio.Mmio(packed struct(u32) { + /// Regular channel data + RDATA: u16, + /// ADC regular channel data + ADC1RDTR: u16, + }), + reserved128: [48]u8, + /// Oversample control register + OVSAMPCTL: mmio.Mmio(packed struct(u32) { + /// Oversampler Enable + OVSEN: u1, + reserved2: u1, + /// Oversampling ratio + OVSR: u3, + /// Oversampling shift + OVSS: u4, + /// Triggered Oversampling + TOVS: u1, + reserved12: u2, + /// ADC resolution + DRES: u2, + padding: u18, + }), + }; + + /// Analog to digital converter + pub const ADC1 = extern struct { + /// status register + STAT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog event flag + WDE: u1, + /// End of group conversion flag + EOC: u1, + /// End of inserted group conversion flag + EOIC: u1, + /// Start flag of inserted channel group + STIC: u1, + /// Start flag of regular channel group + STRC: u1, + padding: u27, + }), + /// control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Analog watchdog channel select + WDCHSEL: u5, + /// Interrupt enable for EOC + EOCIE: u1, + /// Interrupt enable for WDE + WDEIE: u1, + /// Interrupt enable for EOIC + EOICIE: u1, + /// Scan mode + SM: u1, + /// When in scan mode, analog watchdog is effective on a single channel + WDSC: u1, + /// Inserted channel group convert automatically + ICA: u1, + /// Discontinuous mode on regular channels + DISRC: u1, + /// Discontinuous mode on inserted channels + DISIC: u1, + /// Number of conversions in discontinuous mode + DISNUM: u3, + reserved22: u6, + /// Inserted channel analog watchdog enable + IWDEN: u1, + /// Regular channel analog watchdog enable + RWDEN: u1, + padding: u8, + }), + /// control register 1 + CTL1: mmio.Mmio(packed struct(u32) { + /// ADC on + ADCON: u1, + /// Continuous mode + CTN: u1, + /// ADC calibration + CLB: u1, + /// Reset calibration + RSTCLB: u1, + reserved8: u4, + /// DMA request enable + DMA: u1, + reserved11: u2, + /// Data alignment + DAL: u1, + /// External trigger select for inserted channel + ETSIC: u3, + /// External trigger enable for inserted channel + ETEIC: u1, + reserved17: u1, + /// External trigger select for regular channel + ETSRC: u3, + /// External trigger enable for regular channel + ETERC: u1, + /// Start on inserted channel + SWICST: u1, + /// Start on regular channel + SWRCST: u1, + padding: u9, + }), + /// Sample time register 0 + SAMPT0: mmio.Mmio(packed struct(u32) { + /// Channel 10 sample time selection + SPT10: u3, + /// Channel 11 sample time selection + SPT11: u3, + /// Channel 12 sample time selection + SPT12: u3, + /// Channel 13 sample time selection + SPT13: u3, + /// Channel 14 sample time selection + SPT14: u3, + /// Channel 15 sample time selection + SPT15: u3, + /// Channel 16 sample time selection + SPT16: u3, + /// Channel 17 sample time selection + SPT17: u3, + padding: u8, + }), + /// Sample time register 1 + SAMPT1: mmio.Mmio(packed struct(u32) { + /// Channel 0 sample time selection + SPT0: u3, + /// Channel 1 sample time selection + SPT1: u3, + /// Channel 2 sample time selection + SPT2: u3, + /// Channel 3 sample time selection + SPT3: u3, + /// Channel 4 sample time selection + SPT4: u3, + /// Channel 5 sample time selection + SPT5: u3, + /// Channel 6 sample time selection + SPT6: u3, + /// Channel 7 sample time selection + SPT7: u3, + /// Channel 8 sample time selection + SPT8: u3, + /// Channel 9 sample time selection + SPT9: u3, + padding: u2, + }), + /// Inserted channel data offset register 0 + IOFF0: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 0 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 1 + IOFF1: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 1 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 2 + IOFF2: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 2 + IOFF: u12, + padding: u20, + }), + /// Inserted channel data offset register 3 + IOFF3: mmio.Mmio(packed struct(u32) { + /// Data offset for inserted channel 3 + IOFF: u12, + padding: u20, + }), + /// watchdog higher threshold register + WDHT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog higher threshold + WDHT: u12, + padding: u20, + }), + /// watchdog lower threshold register + WDLT: mmio.Mmio(packed struct(u32) { + /// Analog watchdog lower threshold + WDLT: u12, + padding: u20, + }), + /// regular sequence register 0 + RSQ0: mmio.Mmio(packed struct(u32) { + /// 13th conversion in regular sequence + RSQ12: u5, + /// 14th conversion in regular sequence + RSQ13: u5, + /// 15th conversion in regular sequence + RSQ14: u5, + /// 16th conversion in regular sequence + RSQ15: u5, + /// Regular channel group length + RL: u4, + padding: u8, + }), + /// regular sequence register 1 + RSQ1: mmio.Mmio(packed struct(u32) { + /// 7th conversion in regular sequence + RSQ6: u5, + /// 8th conversion in regular sequence + RSQ7: u5, + /// 9th conversion in regular sequence + RSQ8: u5, + /// 10th conversion in regular sequence + RSQ9: u5, + /// 11th conversion in regular sequence + RSQ10: u5, + /// 12th conversion in regular sequence + RSQ11: u5, + padding: u2, + }), + /// regular sequence register 2 + RSQ2: mmio.Mmio(packed struct(u32) { + /// 1st conversion in regular sequence + RSQ0: u5, + /// 2nd conversion in regular sequence + RSQ1: u5, + /// 3rd conversion in regular sequence + RSQ2: u5, + /// 4th conversion in regular sequence + RSQ3: u5, + /// 5th conversion in regular sequence + RSQ4: u5, + /// 6th conversion in regular sequence + RSQ5: u5, + padding: u2, + }), + /// Inserted sequence register + ISQ: mmio.Mmio(packed struct(u32) { + /// 1st conversion in inserted sequence + ISQ0: u5, + /// 2nd conversion in inserted sequence + ISQ1: u5, + /// 3rd conversion in inserted sequence + ISQ2: u5, + /// 4th conversion in inserted sequence + ISQ3: u5, + /// Inserted channel group length + IL: u2, + padding: u10, + }), + /// Inserted data register 0 + IDATA0: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 1 + IDATA1: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 2 + IDATA2: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// Inserted data register 3 + IDATA3: mmio.Mmio(packed struct(u32) { + /// Inserted number n conversion data + IDATAn: u16, + padding: u16, + }), + /// regular data register + RDATA: mmio.Mmio(packed struct(u32) { + /// Regular channel data + RDATA: u16, + padding: u16, + }), + }; + + /// Alternate-function I/Os + pub const AFIO = extern struct { + /// Event control register + EC: mmio.Mmio(packed struct(u32) { + /// Event output pin selection + PIN: u4, + /// Event output port selection + PORT: u3, + /// Event output enable + EOE: u1, + padding: u24, + }), + /// AFIO port configuration register 0 + PCF0: mmio.Mmio(packed struct(u32) { + /// SPI0 remapping + SPI0_REMAP: u1, + /// I2C0 remapping + I2C0_REMAP: u1, + /// USART0 remapping + USART0_REMAP: u1, + /// USART1 remapping + USART1_REMAP: u1, + /// USART2 remapping + USART2_REMAP: u2, + /// TIMER0 remapping + TIMER0_REMAP: u2, + /// TIMER1 remapping + TIMER1_REMAP: u2, + /// TIMER2 remapping + TIMER2_REMAP: u2, + /// TIMER3 remapping + TIMER3_REMAP: u1, + /// CAN0 alternate interface remapping + CAN0_REMAP: u2, + /// Port D0/Port D1 mapping on OSC_IN/OSC_OUT + PD01_REMAP: u1, + /// TIMER4 channel3 internal remapping + TIMER4CH3_IREMAP: u1, + reserved22: u5, + /// CAN1 I/O remapping + CAN1_REMAP: u1, + reserved24: u1, + /// Serial wire JTAG configuration + SWJ_CFG: u3, + reserved28: u1, + /// SPI2/I2S2 remapping + SPI2_REMAP: u1, + /// TIMER1 internal trigger 1 remapping + TIMER1ITI1_REMAP: u1, + padding: u2, + }), + /// EXTI sources selection register 0 + EXTISS0: mmio.Mmio(packed struct(u32) { + /// EXTI 0 sources selection + EXTI0_SS: u4, + /// EXTI 1 sources selection + EXTI1_SS: u4, + /// EXTI 2 sources selection + EXTI2_SS: u4, + /// EXTI 3 sources selection + EXTI3_SS: u4, + padding: u16, + }), + /// EXTI sources selection register 1 + EXTISS1: mmio.Mmio(packed struct(u32) { + /// EXTI 4 sources selection + EXTI4_SS: u4, + /// EXTI 5 sources selection + EXTI5_SS: u4, + /// EXTI 6 sources selection + EXTI6_SS: u4, + /// EXTI 7 sources selection + EXTI7_SS: u4, + padding: u16, + }), + /// EXTI sources selection register 2 + EXTISS2: mmio.Mmio(packed struct(u32) { + /// EXTI 8 sources selection + EXTI8_SS: u4, + /// EXTI 9 sources selection + EXTI9_SS: u4, + /// EXTI 10 sources selection + EXTI10_SS: u4, + /// EXTI 11 sources selection + EXTI11_SS: u4, + padding: u16, + }), + /// EXTI sources selection register 3 + EXTISS3: mmio.Mmio(packed struct(u32) { + /// EXTI 12 sources selection + EXTI12_SS: u4, + /// EXTI 13 sources selection + EXTI13_SS: u4, + /// EXTI 14 sources selection + EXTI14_SS: u4, + /// EXTI 15 sources selection + EXTI15_SS: u4, + padding: u16, + }), + reserved28: [4]u8, + /// AFIO port configuration register 1 + PCF1: mmio.Mmio(packed struct(u32) { + reserved10: u10, + /// EXMC_NADV connect/disconnect + EXMC_NADV: u1, + padding: u21, + }), + }; + + /// Backup registers + pub const BKP = extern struct { + reserved4: [4]u8, + /// Backup data register 0 + DATA0: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved8: [2]u8, + /// Backup data register 1 + DATA1: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved12: [2]u8, + /// Backup data register 2 + DATA2: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved16: [2]u8, + /// Backup data register 3 + DATA3: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved20: [2]u8, + /// Backup data register 4 + DATA4: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved24: [2]u8, + /// Backup data register 5 + DATA5: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved28: [2]u8, + /// Backup data register 6 + DATA6: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved32: [2]u8, + /// Backup data register 7 + DATA7: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved36: [2]u8, + /// Backup data register 8 + DATA8: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved40: [2]u8, + /// Backup data register 9 + DATA9: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved44: [2]u8, + /// RTC signal output control register + OCTL: mmio.Mmio(packed struct(u16) { + /// RTC clock calibration value + RCCV: u7, + /// RTC clock calibration output enable + COEN: u1, + /// RTC alarm or second signal output enable + ASOEN: u1, + /// RTC output selection + ROSEL: u1, + padding: u6, + }), + reserved48: [2]u8, + /// Tamper pin control register + TPCTL: mmio.Mmio(packed struct(u16) { + /// TAMPER detection enable + TPEN: u1, + /// TAMPER pin active level + TPAL: u1, + padding: u14, + }), + reserved52: [2]u8, + /// Tamper control and status register + TPCS: mmio.Mmio(packed struct(u16) { + /// Tamper event reset + TER: u1, + /// Tamper interrupt reset + TIR: u1, + /// Tamper interrupt enable + TPIE: u1, + reserved8: u5, + /// Tamper event flag + TEF: u1, + /// Tamper interrupt flag + TIF: u1, + padding: u6, + }), + reserved64: [10]u8, + /// Backup data register 10 + DATA10: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved68: [2]u8, + /// Backup data register 11 + DATA11: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved72: [2]u8, + /// Backup data register 12 + DATA12: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved76: [2]u8, + /// Backup data register 13 + DATA13: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved80: [2]u8, + /// Backup data register 14 + DATA14: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved84: [2]u8, + /// Backup data register 15 + DATA15: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved88: [2]u8, + /// Backup data register 16 + DATA16: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved92: [2]u8, + /// Backup data register 17 + DATA17: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved96: [2]u8, + /// Backup data register 18 + DATA18: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved100: [2]u8, + /// Backup data register 19 + DATA19: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved104: [2]u8, + /// Backup data register 20 + DATA20: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved108: [2]u8, + /// Backup data register 21 + DATA21: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved112: [2]u8, + /// Backup data register 22 + DATA22: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved116: [2]u8, + /// Backup data register 23 + DATA23: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved120: [2]u8, + /// Backup data register 24 + DATA24: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved124: [2]u8, + /// Backup data register 25 + DATA25: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved128: [2]u8, + /// Backup data register 26 + DATA26: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved132: [2]u8, + /// Backup data register 27 + DATA27: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved136: [2]u8, + /// Backup data register 28 + DATA28: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved140: [2]u8, + /// Backup data register 29 + DATA29: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved144: [2]u8, + /// Backup data register 30 + DATA30: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved148: [2]u8, + /// Backup data register 31 + DATA31: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved152: [2]u8, + /// Backup data register 32 + DATA32: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved156: [2]u8, + /// Backup data register 33 + DATA33: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved160: [2]u8, + /// Backup data register 34 + DATA34: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved164: [2]u8, + /// Backup data register 35 + DATA35: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved168: [2]u8, + /// Backup data register 36 + DATA36: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved172: [2]u8, + /// Backup data register 37 + DATA37: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved176: [2]u8, + /// Backup data register 38 + DATA38: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved180: [2]u8, + /// Backup data register 39 + DATA39: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved184: [2]u8, + /// Backup data register 40 + DATA40: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + reserved188: [2]u8, + /// Backup data register 41 + DATA41: mmio.Mmio(packed struct(u16) { + /// Backup data + DATA: u16, + }), + }; + + /// Controller area network + pub const CAN0 = extern struct { + /// Control register + CTL: mmio.Mmio(packed struct(u32) { + /// Initial working mode + IWMOD: u1, + /// Sleep working mode + SLPWMOD: u1, + /// Transmit FIFO order + TFO: u1, + /// Receive FIFO overwrite disable + RFOD: u1, + /// Automatic retransmission disable + ARD: u1, + /// Automatic wakeup + AWU: u1, + /// Automatic bus-off recovery + ABOR: u1, + /// Time-triggered communication + TTC: u1, + reserved15: u7, + /// Software reset + SWRST: u1, + /// Debug freeze + DFZ: u1, + padding: u15, + }), + /// Status register + STAT: mmio.Mmio(packed struct(u32) { + /// Initial working state + IWS: u1, + /// Sleep working state + SLPWS: u1, + /// Error interrupt flag + ERRIF: u1, + /// Status change interrupt flag of wakeup from sleep working mode + WUIF: u1, + /// Status change interrupt flag of sleep working mode entering + SLPIF: u1, + reserved8: u3, + /// Transmitting state + TS: u1, + /// Receiving state + RS: u1, + /// Last sample value of RX pin + LASTRX: u1, + /// RX level + RXL: u1, + padding: u20, + }), + /// Transmit status register + TSTAT: mmio.Mmio(packed struct(u32) { + /// Mailbox 0 transmit finished + MTF0: u1, + /// Mailbox 0 transmit finished and no error + MTFNERR0: u1, + /// Mailbox 0 arbitration lost + MAL0: u1, + /// Mailbox 0 transmit error + MTE0: u1, + reserved7: u3, + /// Mailbox 0 stop transmitting + MST0: u1, + /// Mailbox 1 transmit finished + MTF1: u1, + /// Mailbox 1 transmit finished and no error + MTFNERR1: u1, + /// Mailbox 1 arbitration lost + MAL1: u1, + /// Mailbox 1 transmit error + MTE1: u1, + reserved15: u3, + /// Mailbox 1 stop transmitting + MST1: u1, + /// Mailbox 2 transmit finished + MTF2: u1, + /// Mailbox 2 transmit finished and no error + MTFNERR2: u1, + /// Mailbox 2 arbitration lost + MAL2: u1, + /// Mailbox 2 transmit error + MTE2: u1, + reserved23: u3, + /// Mailbox 2 stop transmitting + MST2: u1, + /// number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty + NUM: u2, + /// Transmit mailbox 0 empty + TME0: u1, + /// Transmit mailbox 1 empty + TME1: u1, + /// Transmit mailbox 2 empty + TME2: u1, + /// Transmit mailbox 0 last sending in transmit FIFO + TMLS0: u1, + /// Transmit mailbox 1 last sending in transmit FIFO + TMLS1: u1, + /// Transmit mailbox 2 last sending in transmit FIFO + TMLS2: u1, + }), + /// Receive message FIFO0 register + RFIFO0: mmio.Mmio(packed struct(u32) { + /// Receive FIFO0 length + RFL0: u2, + reserved3: u1, + /// Receive FIFO0 full + RFF0: u1, + /// Receive FIFO0 overfull + RFO0: u1, + /// Receive FIFO0 dequeue + RFD0: u1, + padding: u26, + }), + /// Receive message FIFO1 register + RFIFO1: mmio.Mmio(packed struct(u32) { + /// Receive FIFO1 length + RFL1: u2, + reserved3: u1, + /// Receive FIFO1 full + RFF1: u1, + /// Receive FIFO1 overfull + RFO1: u1, + /// Receive FIFO1 dequeue + RFD1: u1, + padding: u26, + }), + /// Interrupt enable register + INTEN: mmio.Mmio(packed struct(u32) { + /// Transmit mailbox empty interrupt enable + TMEIE: u1, + /// Receive FIFO0 not empty interrupt enable + RFNEIE0: u1, + /// Receive FIFO0 full interrupt enable + RFFIE0: u1, + /// Receive FIFO0 overfull interrupt enable + RFOIE0: u1, + /// Receive FIFO1 not empty interrupt enable + RFNEIE1: u1, + /// Receive FIFO1 full interrupt enable + RFFIE1: u1, + /// Receive FIFO1 overfull interrupt enable + RFOIE1: u1, + reserved8: u1, + /// Warning error interrupt enable + WERRIE: u1, + /// Passive error interrupt enable + PERRIE: u1, + /// Bus-off interrupt enable + BOIE: u1, + /// Error number interrupt enable + ERRNIE: u1, + reserved15: u3, + /// Error interrupt enable + ERRIE: u1, + /// Wakeup interrupt enable + WIE: u1, + /// Sleep working interrupt enable + SLPWIE: u1, + padding: u14, + }), + /// Error register + ERR: mmio.Mmio(packed struct(u32) { + /// Warning error + WERR: u1, + /// Passive error + PERR: u1, + /// Bus-off error + BOERR: u1, + reserved4: u1, + /// Error number + ERRN: u3, + reserved16: u9, + /// Transmit Error Count defined by the CAN standard + TECNT: u8, + /// Receive Error Count defined by the CAN standard + RECNT: u8, + }), + /// Bit timing register + BT: mmio.Mmio(packed struct(u32) { + /// Baud rate prescaler + BAUDPSC: u10, + reserved16: u6, + /// Bit segment 1 + BS1: u4, + /// Bit segment 2 + BS2: u3, + reserved24: u1, + /// Resynchronization jump width + SJW: u2, + reserved30: u4, + /// Loopback communication mode + LCMOD: u1, + /// Silent communication mode + SCMOD: u1, + }), + reserved384: [352]u8, + /// Transmit mailbox identifier register 0 + TMI0: mmio.Mmio(packed struct(u32) { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), + /// Transmit mailbox property register 0 + TMP0: mmio.Mmio(packed struct(u32) { + /// Data length code + DLENC: u4, + reserved8: u4, + /// Time stamp enable + TSEN: u1, + reserved16: u7, + /// Time stamp + TS: u16, + }), + /// Transmit mailbox data0 register + TMDATA00: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), + /// Transmit mailbox data1 register + TMDATA10: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), + /// Transmit mailbox identifier register 1 + TMI1: mmio.Mmio(packed struct(u32) { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), + /// Transmit mailbox property register 1 + TMP1: mmio.Mmio(packed struct(u32) { + /// Data length code + DLENC: u4, + reserved8: u4, + /// Time stamp enable + TSEN: u1, + reserved16: u7, + /// Time stamp + TS: u16, + }), + /// Transmit mailbox data0 register + TMDATA01: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), + /// Transmit mailbox data1 register + TMDATA11: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), + /// Transmit mailbox identifier register 2 + TMI2: mmio.Mmio(packed struct(u32) { + /// Transmit enable + TEN: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), + /// Transmit mailbox property register 2 + TMP2: mmio.Mmio(packed struct(u32) { + /// Data length code + DLENC: u4, + reserved8: u4, + /// Time stamp enable + TSEN: u1, + reserved16: u7, + /// Time stamp + TS: u16, + }), + /// Transmit mailbox data0 register + TMDATA02: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), + /// Transmit mailbox data1 register + TMDATA12: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), + /// Receive FIFO mailbox identifier register + RFIFOMI0: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), + /// Receive FIFO0 mailbox property register + RFIFOMP0: mmio.Mmio(packed struct(u32) { + /// Data length code + DLENC: u4, + reserved8: u4, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), + /// Receive FIFO0 mailbox data0 register + RFIFOMDATA00: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), + /// Receive FIFO0 mailbox data1 register + RFIFOMDATA10: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), + /// Receive FIFO1 mailbox identifier register + RFIFOMI1: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Frame type + FT: u1, + /// Frame format + FF: u1, + /// The frame identifier + EFID: u18, + /// The frame identifier + SFID_EFID: u11, + }), + /// Receive FIFO1 mailbox property register + RFIFOMP1: mmio.Mmio(packed struct(u32) { + /// Data length code + DLENC: u4, + reserved8: u4, + /// Filtering index + FI: u8, + /// Time stamp + TS: u16, + }), + /// Receive FIFO1 mailbox data0 register + RFIFOMDATA01: mmio.Mmio(packed struct(u32) { + /// Data byte 0 + DB0: u8, + /// Data byte 1 + DB1: u8, + /// Data byte 2 + DB2: u8, + /// Data byte 3 + DB3: u8, + }), + /// Receive FIFO1 mailbox data1 register + RFIFOMDATA11: mmio.Mmio(packed struct(u32) { + /// Data byte 4 + DB4: u8, + /// Data byte 5 + DB5: u8, + /// Data byte 6 + DB6: u8, + /// Data byte 7 + DB7: u8, + }), + reserved512: [48]u8, + /// Filter control register + FCTL: mmio.Mmio(packed struct(u32) { + /// Filter lock disable + FLD: u1, + reserved8: u7, + /// Header bank of CAN1 filter + HBC1F: u6, + padding: u18, + }), + /// Filter mode configuration register + FMCFG: mmio.Mmio(packed struct(u32) { + /// Filter mode + FMOD0: u1, + /// Filter mode + FMOD1: u1, + /// Filter mode + FMOD2: u1, + /// Filter mode + FMOD3: u1, + /// Filter mode + FMOD4: u1, + /// Filter mode + FMOD5: u1, + /// Filter mode + FMOD6: u1, + /// Filter mode + FMOD7: u1, + /// Filter mode + FMOD8: u1, + /// Filter mode + FMOD9: u1, + /// Filter mode + FMOD10: u1, + /// Filter mode + FMOD11: u1, + /// Filter mode + FMOD12: u1, + /// Filter mode + FMOD13: u1, + /// Filter mode + FMOD14: u1, + /// Filter mode + FMOD15: u1, + /// Filter mode + FMOD16: u1, + /// Filter mode + FMOD17: u1, + /// Filter mode + FMOD18: u1, + /// Filter mode + FMOD19: u1, + /// Filter mode + FMOD20: u1, + /// Filter mode + FMOD21: u1, + /// Filter mode + FMOD22: u1, + /// Filter mode + FMOD23: u1, + /// Filter mode + FMOD24: u1, + /// Filter mode + FMOD25: u1, + /// Filter mode + FMOD26: u1, + /// Filter mode + FMOD27: u1, + padding: u4, + }), + reserved524: [4]u8, + /// Filter scale configuration register + FSCFG: mmio.Mmio(packed struct(u32) { + /// Filter scale configuration + FS0: u1, + /// Filter scale configuration + FS1: u1, + /// Filter scale configuration + FS2: u1, + /// Filter scale configuration + FS3: u1, + /// Filter scale configuration + FS4: u1, + /// Filter scale configuration + FS5: u1, + /// Filter scale configuration + FS6: u1, + /// Filter scale configuration + FS7: u1, + /// Filter scale configuration + FS8: u1, + /// Filter scale configuration + FS9: u1, + /// Filter scale configuration + FS10: u1, + /// Filter scale configuration + FS11: u1, + /// Filter scale configuration + FS12: u1, + /// Filter scale configuration + FS13: u1, + /// Filter scale configuration + FS14: u1, + /// Filter scale configuration + FS15: u1, + /// Filter scale configuration + FS16: u1, + /// Filter scale configuration + FS17: u1, + /// Filter scale configuration + FS18: u1, + /// Filter scale configuration + FS19: u1, + /// Filter scale configuration + FS20: u1, + /// Filter scale configuration + FS21: u1, + /// Filter scale configuration + FS22: u1, + /// Filter scale configuration + FS23: u1, + /// Filter scale configuration + FS24: u1, + /// Filter scale configuration + FS25: u1, + /// Filter scale configuration + FS26: u1, + /// Filter scale configuration + FS27: u1, + padding: u4, + }), + reserved532: [4]u8, + /// Filter associated FIFO register + FAFIFO: mmio.Mmio(packed struct(u32) { + /// Filter 0 associated with FIFO + FAF0: u1, + /// Filter 1 associated with FIFO + FAF1: u1, + /// Filter 2 associated with FIFO + FAF2: u1, + /// Filter 3 associated with FIFO + FAF3: u1, + /// Filter 4 associated with FIFO + FAF4: u1, + /// Filter 5 associated with FIFO + FAF5: u1, + /// Filter 6 associated with FIFO + FAF6: u1, + /// Filter 7 associated with FIFO + FAF7: u1, + /// Filter 8 associated with FIFO + FAF8: u1, + /// Filter 9 associated with FIFO + FAF9: u1, + /// Filter 10 associated with FIFO + FAF10: u1, + /// Filter 11 associated with FIFO + FAF11: u1, + /// Filter 12 associated with FIFO + FAF12: u1, + /// Filter 13 associated with FIFO + FAF13: u1, + /// Filter 14 associated with FIFO + FAF14: u1, + /// Filter 15 associated with FIFO + FAF15: u1, + /// Filter 16 associated with FIFO + FAF16: u1, + /// Filter 17 associated with FIFO + FAF17: u1, + /// Filter 18 associated with FIFO + FAF18: u1, + /// Filter 19 associated with FIFO + FAF19: u1, + /// Filter 20 associated with FIFO + FAF20: u1, + /// Filter 21 associated with FIFO + FAF21: u1, + /// Filter 22 associated with FIFO + FAF22: u1, + /// Filter 23 associated with FIFO + FAF23: u1, + /// Filter 24 associated with FIFO + FAF24: u1, + /// Filter 25 associated with FIFO + FAF25: u1, + /// Filter 26 associated with FIFO + FAF26: u1, + /// Filter 27 associated with FIFO + FAF27: u1, + padding: u4, + }), + reserved540: [4]u8, + /// Filter working register + FW: mmio.Mmio(packed struct(u32) { + /// Filter working + FW0: u1, + /// Filter working + FW1: u1, + /// Filter working + FW2: u1, + /// Filter working + FW3: u1, + /// Filter working + FW4: u1, + /// Filter working + FW5: u1, + /// Filter working + FW6: u1, + /// Filter working + FW7: u1, + /// Filter working + FW8: u1, + /// Filter working + FW9: u1, + /// Filter working + FW10: u1, + /// Filter working + FW11: u1, + /// Filter working + FW12: u1, + /// Filter working + FW13: u1, + /// Filter working + FW14: u1, + /// Filter working + FW15: u1, + /// Filter working + FW16: u1, + /// Filter working + FW17: u1, + /// Filter working + FW18: u1, + /// Filter working + FW19: u1, + /// Filter working + FW20: u1, + /// Filter working + FW21: u1, + /// Filter working + FW22: u1, + /// Filter working + FW23: u1, + /// Filter working + FW24: u1, + /// Filter working + FW25: u1, + /// Filter working + FW26: u1, + /// Filter working + FW27: u1, + padding: u4, + }), + reserved576: [32]u8, + /// Filter 0 data 0 register + F0DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 0 data 1 register + F0DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 1 data 0 register + F1DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 1 data 1 register + F1DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 2 data 0 register + F2DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 2 data 1 register + F2DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 3 data 0 register + F3DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 3 data 1 register + F3DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 4 data 0 register + F4DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 4 data 1 register + F4DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 5 data 0 register + F5DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 5 data 1 register + F5DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 6 data 0 register + F6DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 6 data 1 register + F6DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 7 data 0 register + F7DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 7 data 1 register + F7DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 8 data 0 register + F8DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 8 data 1 register + F8DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 9 data 0 register + F9DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 9 data 1 register + F9DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 10 data 0 register + F10DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 10 data 1 register + F10DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 11 data 0 register + F11DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 11 data 1 register + F11DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 12 data 0 register + F12DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 12 data 1 register + F12DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 13 data 0 register + F13DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 13 data 1 register + F13DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 14 data 0 register + F14DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 14 data 1 register + F14DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 15 data 0 register + F15DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 15 data 1 register + F15DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 16 data 0 register + F16DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 16 data 1 register + F16DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 17 data 0 register + F17DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 17 data 1 register + F17DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 18 data 0 register + F18DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 18 data 1 register + F18DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 19 data 0 register + F19DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 19 data 1 register + F19DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 20 data 0 register + F20DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 20 data 1 register + F20DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 21 data 0 register + F21DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 21 data 1 register + F21DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 22 data 0 register + F22DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 22 data 1 register + F22DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 23 data 0 register + F23DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 23 data 1 register + F23DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 24 data 0 register + F24DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 24 data 1 register + F24DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 25 data 0 register + F25DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 25 data 1 register + F25DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 26 data 0 register + F26DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 26 data 1 register + F26DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 27 data 0 register + F27DATA0: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + /// Filter 27 data 1 register + F27DATA1: mmio.Mmio(packed struct(u32) { + /// Filter bits + FD0: u1, + /// Filter bits + FD1: u1, + /// Filter bits + FD2: u1, + /// Filter bits + FD3: u1, + /// Filter bits + FD4: u1, + /// Filter bits + FD5: u1, + /// Filter bits + FD6: u1, + /// Filter bits + FD7: u1, + /// Filter bits + FD8: u1, + /// Filter bits + FD9: u1, + /// Filter bits + FD10: u1, + /// Filter bits + FD11: u1, + /// Filter bits + FD12: u1, + /// Filter bits + FD13: u1, + /// Filter bits + FD14: u1, + /// Filter bits + FD15: u1, + /// Filter bits + FD16: u1, + /// Filter bits + FD17: u1, + /// Filter bits + FD18: u1, + /// Filter bits + FD19: u1, + /// Filter bits + FD20: u1, + /// Filter bits + FD21: u1, + /// Filter bits + FD22: u1, + /// Filter bits + FD23: u1, + /// Filter bits + FD24: u1, + /// Filter bits + FD25: u1, + /// Filter bits + FD26: u1, + /// Filter bits + FD27: u1, + /// Filter bits + FD28: u1, + /// Filter bits + FD29: u1, + /// Filter bits + FD30: u1, + /// Filter bits + FD31: u1, + }), + }; + + /// Window watchdog timer + pub const WWDGT = extern struct { + /// Control register + CTL: mmio.Mmio(packed struct(u32) { + /// 7-bit counter + CNT: u7, + /// Activation bit + WDGTEN: u1, + padding: u24, + }), + /// Configuration register + CFG: mmio.Mmio(packed struct(u32) { + /// 7-bit window value + WIN: u7, + /// Prescaler + PSC: u2, + /// Early wakeup interrupt + EWIE: u1, + padding: u22, + }), + /// Status register + STAT: mmio.Mmio(packed struct(u32) { + /// Early wakeup interrupt flag + EWIF: u1, + padding: u31, + }), + }; + + /// cyclic redundancy check calculation unit + pub const CRC = extern struct { + /// Data register + DATA: mmio.Mmio(packed struct(u32) { + /// CRC calculation result bits + DATA: u32, + }), + /// Free data register + FDATA: mmio.Mmio(packed struct(u32) { + /// Free Data Register bits + FDATA: u8, + padding: u24, + }), + /// Control register + CTL: mmio.Mmio(packed struct(u32) { + /// reset bit + RST: u1, + padding: u31, + }), + }; + + /// Digital-to-analog converter + pub const DAC = extern struct { + /// control register + CTL: mmio.Mmio(packed struct(u32) { + /// DAC0 enable + DEN0: u1, + /// DAC0 output buffer turn off + DBOFF0: u1, + /// DAC0 trigger enable + DTEN0: u1, + /// DAC0 trigger selection + DTSEL0: u3, + /// DAC0 noise wave mode + DWM0: u2, + /// DAC0 noise wave bit width + DWBW0: u4, + /// DAC0 DMA enable + DDMAEN0: u1, + reserved16: u3, + /// DAC1 enable + DEN1: u1, + /// DAC1 output buffer turn off + DBOFF1: u1, + /// DAC1 trigger enable + DTEN1: u1, + /// DAC1 trigger selection + DTSEL1: u3, + /// DAC1 noise wave mode + DWM1: u2, + /// DAC1 noise wave bit width + DWBW1: u4, + /// DAC1 DMA enable + DDMAEN1: u1, + padding: u3, + }), + /// software trigger register + SWT: mmio.Mmio(packed struct(u32) { + /// DAC0 software trigger + SWTR0: u1, + /// DAC1 software trigger + SWTR1: u1, + padding: u30, + }), + /// DAC0 12-bit right-aligned data holding register + DAC0_R12DH: mmio.Mmio(packed struct(u32) { + /// DAC0 12-bit right-aligned data + DAC0_DH: u12, + padding: u20, + }), + /// DAC0 12-bit left-aligned data holding register + DAC0_L12DH: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC0 12-bit left-aligned data + DAC0_DH: u12, + padding: u16, + }), + /// DAC0 8-bit right aligned data holding register + DAC0_R8DH: mmio.Mmio(packed struct(u32) { + /// DAC0 8-bit right-aligned data + DAC0_DH: u8, + padding: u24, + }), + /// DAC1 12-bit right-aligned data holding register + DAC1_R12DH: mmio.Mmio(packed struct(u32) { + /// DAC1 12-bit right-aligned data + DAC1_DH: u12, + padding: u20, + }), + /// DAC1 12-bit left aligned data holding register + DAC1_L12DH: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC1 12-bit left-aligned data + DAC1_DH: u12, + padding: u16, + }), + /// DAC1 8-bit right aligned data holding register + DAC1_R8DH: mmio.Mmio(packed struct(u32) { + /// DAC1 8-bit right-aligned data + DAC1_DH: u8, + padding: u24, + }), + /// DAC concurrent mode 12-bit right-aligned data holding register + DACC_R12DH: mmio.Mmio(packed struct(u32) { + /// DAC0 12-bit right-aligned data + DAC0_DH: u12, + reserved16: u4, + /// DAC1 12-bit right-aligned data + DAC1_DH: u12, + padding: u4, + }), + /// DAC concurrent mode 12-bit left aligned data holding register + DACC_L12DH: mmio.Mmio(packed struct(u32) { + reserved4: u4, + /// DAC0 12-bit left-aligned data + DAC0_DH: u12, + reserved20: u4, + /// DAC1 12-bit left-aligned data + DAC1_DH: u12, + }), + /// DAC concurrent mode 8-bit right aligned data holding register + DACC_R8DH: mmio.Mmio(packed struct(u32) { + /// DAC0 8-bit right-aligned data + DAC0_DH: u8, + /// DAC1 8-bit right-aligned data + DAC1_DH: u8, + padding: u16, + }), + /// DAC0 data output register + DAC0_DO: mmio.Mmio(packed struct(u32) { + /// DAC0 data output + DAC0_DO: u12, + padding: u20, + }), + /// DAC1 data output register + DAC1_DO: mmio.Mmio(packed struct(u32) { + /// DAC1 data output + DAC1_DO: u12, + padding: u20, + }), + }; + + /// Debug support + pub const DBG = extern struct { + /// ID code register + ID: mmio.Mmio(packed struct(u32) { + /// DBG ID code register + ID_CODE: u32, + }), + /// Control register 0 + CTL: mmio.Mmio(packed struct(u32) { + /// Sleep mode hold register + SLP_HOLD: u1, + /// Deep-sleep mode hold register + DSLP_HOLD: u1, + /// Standby mode hold register + STB_HOLD: u1, + reserved8: u5, + /// FWDGT hold bit + FWDGT_HOLD: u1, + /// WWDGT hold bit + WWDGT_HOLD: u1, + /// TIMER 0 hold bit + TIMER0_HOLD: u1, + /// TIMER 1 hold bit + TIMER1_HOLD: u1, + /// TIMER 2 hold bit + TIMER2_HOLD: u1, + /// TIMER 23 hold bit + TIMER3_HOLD: u1, + /// CAN0 hold bit + CAN0_HOLD: u1, + /// I2C0 hold bit + I2C0_HOLD: u1, + /// I2C1 hold bit + I2C1_HOLD: u1, + reserved18: u1, + /// TIMER4_HOLD + TIMER4_HOLD: u1, + /// TIMER 5 hold bit + TIMER5_HOLD: u1, + /// TIMER 6 hold bit + TIMER6_HOLD: u1, + /// CAN1 hold bit + CAN1_HOLD: u1, + padding: u10, + }), + }; + + /// DMA controller + pub const DMA0 = extern struct { + /// Interrupt flag register + INTF: mmio.Mmio(packed struct(u32) { + /// Global interrupt flag of channel 0 + GIF0: u1, + /// Full Transfer finish flag of channe 0 + FTFIF0: u1, + /// Half transfer finish flag of channel 0 + HTFIF0: u1, + /// Error flag of channel 0 + ERRIF0: u1, + /// Global interrupt flag of channel 1 + GIF1: u1, + /// Full Transfer finish flag of channe 1 + FTFIF1: u1, + /// Half transfer finish flag of channel 1 + HTFIF1: u1, + /// Error flag of channel 1 + ERRIF1: u1, + /// Global interrupt flag of channel 2 + GIF2: u1, + /// Full Transfer finish flag of channe 2 + FTFIF2: u1, + /// Half transfer finish flag of channel 2 + HTFIF2: u1, + /// Error flag of channel 2 + ERRIF2: u1, + /// Global interrupt flag of channel 3 + GIF3: u1, + /// Full Transfer finish flag of channe 3 + FTFIF3: u1, + /// Half transfer finish flag of channel 3 + HTFIF3: u1, + /// Error flag of channel 3 + ERRIF3: u1, + /// Global interrupt flag of channel 4 + GIF4: u1, + /// Full Transfer finish flag of channe 4 + FTFIF4: u1, + /// Half transfer finish flag of channel 4 + HTFIF4: u1, + /// Error flag of channel 4 + ERRIF4: u1, + /// Global interrupt flag of channel 5 + GIF5: u1, + /// Full Transfer finish flag of channe 5 + FTFIF5: u1, + /// Half transfer finish flag of channel 5 + HTFIF5: u1, + /// Error flag of channel 5 + ERRIF5: u1, + /// Global interrupt flag of channel 6 + GIF6: u1, + /// Full Transfer finish flag of channe 6 + FTFIF6: u1, + /// Half transfer finish flag of channel 6 + HTFIF6: u1, + /// Error flag of channel 6 + ERRIF6: u1, + padding: u4, + }), + /// Interrupt flag clear register + INTC: mmio.Mmio(packed struct(u32) { + /// Clear global interrupt flag of channel 0 + GIFC0: u1, + /// Clear bit for full transfer finish flag of channel 0 + FTFIFC0: u1, + /// Clear bit for half transfer finish flag of channel 0 + HTFIFC0: u1, + /// Clear bit for error flag of channel 0 + ERRIFC0: u1, + /// Clear global interrupt flag of channel 1 + GIFC1: u1, + /// Clear bit for full transfer finish flag of channel 1 + FTFIFC1: u1, + /// Clear bit for half transfer finish flag of channel 1 + HTFIFC1: u1, + /// Clear bit for error flag of channel 1 + ERRIFC1: u1, + /// Clear global interrupt flag of channel 2 + GIFC2: u1, + /// Clear bit for full transfer finish flag of channel 2 + FTFIFC2: u1, + /// Clear bit for half transfer finish flag of channel 2 + HTFIFC2: u1, + /// Clear bit for error flag of channel 2 + ERRIFC2: u1, + /// Clear global interrupt flag of channel 3 + GIFC3: u1, + /// Clear bit for full transfer finish flag of channel 3 + FTFIFC3: u1, + /// Clear bit for half transfer finish flag of channel 3 + HTFIFC3: u1, + /// Clear bit for error flag of channel 3 + ERRIFC3: u1, + /// Clear global interrupt flag of channel 4 + GIFC4: u1, + /// Clear bit for full transfer finish flag of channel 4 + FTFIFC4: u1, + /// Clear bit for half transfer finish flag of channel 4 + HTFIFC4: u1, + /// Clear bit for error flag of channel 4 + ERRIFC4: u1, + /// Clear global interrupt flag of channel 5 + GIFC5: u1, + /// Clear bit for full transfer finish flag of channel 5 + FTFIFC5: u1, + /// Clear bit for half transfer finish flag of channel 5 + HTFIFC5: u1, + /// Clear bit for error flag of channel 5 + ERRIFC5: u1, + /// Clear global interrupt flag of channel 6 + GIFC6: u1, + /// Clear bit for full transfer finish flag of channel 6 + FTFIFC6: u1, + /// Clear bit for half transfer finish flag of channel 6 + HTFIFC6: u1, + /// Clear bit for error flag of channel 6 + ERRIFC6: u1, + padding: u4, + }), + /// Channel 0 control register + CH0CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 0 counter register + CH0CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 0 peripheral base address register + CH0PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 0 memory base address register + CH0MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved28: [4]u8, + /// Channel 1 control register + CH1CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 1 counter register + CH1CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 1 peripheral base address register + CH1PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 1 memory base address register + CH1MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved48: [4]u8, + /// Channel 2 control register + CH2CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 2 counter register + CH2CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 2 peripheral base address register + CH2PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 2 memory base address register + CH2MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved68: [4]u8, + /// Channel 3 control register + CH3CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 3 counter register + CH3CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 3 peripheral base address register + CH3PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 3 memory base address register + CH3MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved88: [4]u8, + /// Channel 4 control register + CH4CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 4 counter register + CH4CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 4 peripheral base address register + CH4PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 4 memory base address register + CH4MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved108: [4]u8, + /// Channel 5 control register + CH5CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 5 counter register + CH5CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 5 peripheral base address register + CH5PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 5 memory base address register + CH5MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved128: [4]u8, + /// Channel 6 control register + CH6CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 6 counter register + CH6CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 6 peripheral base address register + CH6PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 6 memory base address register + CH6MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + }; + + /// Direct memory access controller + pub const DMA1 = extern struct { + /// Interrupt flag register + INTF: mmio.Mmio(packed struct(u32) { + /// Global interrupt flag of channel 0 + GIF0: u1, + /// Full Transfer finish flag of channe 0 + FTFIF0: u1, + /// Half transfer finish flag of channel 0 + HTFIF0: u1, + /// Error flag of channel 0 + ERRIF0: u1, + /// Global interrupt flag of channel 1 + GIF1: u1, + /// Full Transfer finish flag of channe 1 + FTFIF1: u1, + /// Half transfer finish flag of channel 1 + HTFIF1: u1, + /// Error flag of channel 1 + ERRIF1: u1, + /// Global interrupt flag of channel 2 + GIF2: u1, + /// Full Transfer finish flag of channe 2 + FTFIF2: u1, + /// Half transfer finish flag of channel 2 + HTFIF2: u1, + /// Error flag of channel 2 + ERRIF2: u1, + /// Global interrupt flag of channel 3 + GIF3: u1, + /// Full Transfer finish flag of channe 3 + FTFIF3: u1, + /// Half transfer finish flag of channel 3 + HTFIF3: u1, + /// Error flag of channel 3 + ERRIF3: u1, + /// Global interrupt flag of channel 4 + GIF4: u1, + /// Full Transfer finish flag of channe 4 + FTFIF4: u1, + /// Half transfer finish flag of channel 4 + HTFIF4: u1, + /// Error flag of channel 4 + ERRIF4: u1, + padding: u12, + }), + /// Interrupt flag clear register + INTC: mmio.Mmio(packed struct(u32) { + /// Clear global interrupt flag of channel 0 + GIFC0: u1, + /// Clear bit for full transfer finish flag of channel 0 + FTFIFC0: u1, + /// Clear bit for half transfer finish flag of channel 0 + HTFIFC0: u1, + /// Clear bit for error flag of channel 0 + ERRIFC0: u1, + /// Clear global interrupt flag of channel 1 + GIFC1: u1, + /// Clear bit for full transfer finish flag of channel 1 + FTFIFC1: u1, + /// Clear bit for half transfer finish flag of channel 1 + HTFIFC1: u1, + /// Clear bit for error flag of channel 1 + ERRIFC1: u1, + /// Clear global interrupt flag of channel 2 + GIFC2: u1, + /// Clear bit for full transfer finish flag of channel 2 + FTFIFC2: u1, + /// Clear bit for half transfer finish flag of channel 2 + HTFIFC2: u1, + /// Clear bit for error flag of channel 2 + ERRIFC2: u1, + /// Clear global interrupt flag of channel 3 + GIFC3: u1, + /// Clear bit for full transfer finish flag of channel 3 + FTFIFC3: u1, + /// Clear bit for half transfer finish flag of channel 3 + HTFIFC3: u1, + /// Clear bit for error flag of channel 3 + ERRIFC3: u1, + /// Clear global interrupt flag of channel 4 + GIFC4: u1, + /// Clear bit for full transfer finish flag of channel 4 + FTFIFC4: u1, + /// Clear bit for half transfer finish flag of channel 4 + HTFIFC4: u1, + /// Clear bit for error flag of channel 4 + ERRIFC4: u1, + padding: u12, + }), + /// Channel 0 control register + CH0CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 0 counter register + CH0CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 0 peripheral base address register + CH0PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 0 memory base address register + CH0MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved28: [4]u8, + /// Channel 1 control register + CH1CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 1 counter register + CH1CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 1 peripheral base address register + CH1PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 1 memory base address register + CH1MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved48: [4]u8, + /// Channel 2 control register + CH2CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 2 counter register + CH2CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 2 peripheral base address register + CH2PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 2 memory base address register + CH2MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved68: [4]u8, + /// Channel 3 control register + CH3CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 3 counter register + CH3CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 3 peripheral base address register + CH3PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 3 memory base address register + CH3MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + reserved88: [4]u8, + /// Channel 4 control register + CH4CTL: mmio.Mmio(packed struct(u32) { + /// Channel enable + CHEN: u1, + /// Enable bit for channel full transfer finish interrupt + FTFIE: u1, + /// Enable bit for channel half transfer finish interrupt + HTFIE: u1, + /// Enable bit for channel error interrupt + ERRIE: u1, + /// Transfer direction + DIR: u1, + /// Circular mode enable + CMEN: u1, + /// Next address generation algorithm of peripheral + PNAGA: u1, + /// Next address generation algorithm of memory + MNAGA: u1, + /// Transfer data size of peripheral + PWIDTH: u2, + /// Transfer data size of memory + MWIDTH: u2, + /// Priority level + PRIO: u2, + /// Memory to Memory Mode + M2M: u1, + padding: u17, + }), + /// Channel 4 counter register + CH4CNT: mmio.Mmio(packed struct(u32) { + /// Transfer counter + CNT: u16, + padding: u16, + }), + /// Channel 4 peripheral base address register + CH4PADDR: mmio.Mmio(packed struct(u32) { + /// Peripheral base address + PADDR: u32, + }), + /// Channel 4 memory base address register + CH4MADDR: mmio.Mmio(packed struct(u32) { + /// Memory base address + MADDR: u32, + }), + }; + + /// External memory controller + pub const EXMC = extern struct { + /// SRAM/NOR flash control register 0 + SNCTL0: mmio.Mmio(packed struct(u32) { + /// NOR bank enable + NRBKEN: u1, + /// NOR bank memory address/data multiplexing + NRMUX: u1, + /// NOR bank memory type + NRTP: u2, + /// NOR bank memory data bus width + NRW: u2, + /// NOR Flash access enable + NREN: u1, + reserved9: u2, + /// NWAIT signal polarity + NRWTPOL: u1, + reserved12: u2, + /// Write enable + WREN: u1, + /// NWAIT signal enable + NRWTEN: u1, + reserved15: u1, + /// Asynchronous wait + ASYNCWAIT: u1, + padding: u16, + }), + /// SRAM/NOR flash timing configuration register 0 + SNTCFG0: mmio.Mmio(packed struct(u32) { + /// Address setup time + ASET: u4, + /// Address hold time + AHLD: u4, + /// Data setup time + DSET: u8, + /// Bus latency + BUSLAT: u4, + padding: u12, + }), + /// SRAM/NOR flash control register 1 + SNCTL1: mmio.Mmio(packed struct(u32) { + /// NOR bank enable + NRBKEN: u1, + /// NOR bank memory address/data multiplexing + NRMUX: u1, + /// NOR bank memory type + NRTP: u2, + /// NOR bank memory data bus width + NRW: u2, + /// NOR Flash access enable + NREN: u1, + reserved9: u2, + /// NWAIT signal polarity + NRWTPOL: u1, + reserved12: u2, + /// Write enable + WREN: u1, + /// NWAIT signal enable + NRWTEN: u1, + reserved15: u1, + /// Asynchronous wait + ASYNCWAIT: u1, + padding: u16, + }), + }; + + /// External interrupt/event controller + pub const EXTI = extern struct { + /// Interrupt enable register (EXTI_INTEN) + INTEN: mmio.Mmio(packed struct(u32) { + /// Enable Interrupt on line 0 + INTEN0: u1, + /// Enable Interrupt on line 1 + INTEN1: u1, + /// Enable Interrupt on line 2 + INTEN2: u1, + /// Enable Interrupt on line 3 + INTEN3: u1, + /// Enable Interrupt on line 4 + INTEN4: u1, + /// Enable Interrupt on line 5 + INTEN5: u1, + /// Enable Interrupt on line 6 + INTEN6: u1, + /// Enable Interrupt on line 7 + INTEN7: u1, + /// Enable Interrupt on line 8 + INTEN8: u1, + /// Enable Interrupt on line 9 + INTEN9: u1, + /// Enable Interrupt on line 10 + INTEN10: u1, + /// Enable Interrupt on line 11 + INTEN11: u1, + /// Enable Interrupt on line 12 + INTEN12: u1, + /// Enable Interrupt on line 13 + INTEN13: u1, + /// Enable Interrupt on line 14 + INTEN14: u1, + /// Enable Interrupt on line 15 + INTEN15: u1, + /// Enable Interrupt on line 16 + INTEN16: u1, + /// Enable Interrupt on line 17 + INTEN17: u1, + /// Enable Interrupt on line 18 + INTEN18: u1, + padding: u13, + }), + /// Event enable register (EXTI_EVEN) + EVEN: mmio.Mmio(packed struct(u32) { + /// Enable Event on line 0 + EVEN0: u1, + /// Enable Event on line 1 + EVEN1: u1, + /// Enable Event on line 2 + EVEN2: u1, + /// Enable Event on line 3 + EVEN3: u1, + /// Enable Event on line 4 + EVEN4: u1, + /// Enable Event on line 5 + EVEN5: u1, + /// Enable Event on line 6 + EVEN6: u1, + /// Enable Event on line 7 + EVEN7: u1, + /// Enable Event on line 8 + EVEN8: u1, + /// Enable Event on line 9 + EVEN9: u1, + /// Enable Event on line 10 + EVEN10: u1, + /// Enable Event on line 11 + EVEN11: u1, + /// Enable Event on line 12 + EVEN12: u1, + /// Enable Event on line 13 + EVEN13: u1, + /// Enable Event on line 14 + EVEN14: u1, + /// Enable Event on line 15 + EVEN15: u1, + /// Enable Event on line 16 + EVEN16: u1, + /// Enable Event on line 17 + EVEN17: u1, + /// Enable Event on line 18 + EVEN18: u1, + padding: u13, + }), + /// Rising Edge Trigger Enable register (EXTI_RTEN) + RTEN: mmio.Mmio(packed struct(u32) { + /// Rising edge trigger enable of line 0 + RTEN0: u1, + /// Rising edge trigger enable of line 1 + RTEN1: u1, + /// Rising edge trigger enable of line 2 + RTEN2: u1, + /// Rising edge trigger enable of line 3 + RTEN3: u1, + /// Rising edge trigger enable of line 4 + RTEN4: u1, + /// Rising edge trigger enable of line 5 + RTEN5: u1, + /// Rising edge trigger enable of line 6 + RTEN6: u1, + /// Rising edge trigger enable of line 7 + RTEN7: u1, + /// Rising edge trigger enable of line 8 + RTEN8: u1, + /// Rising edge trigger enable of line 9 + RTEN9: u1, + /// Rising edge trigger enable of line 10 + RTEN10: u1, + /// Rising edge trigger enable of line 11 + RTEN11: u1, + /// Rising edge trigger enable of line 12 + RTEN12: u1, + /// Rising edge trigger enable of line 13 + RTEN13: u1, + /// Rising edge trigger enable of line 14 + RTEN14: u1, + /// Rising edge trigger enable of line 15 + RTEN15: u1, + /// Rising edge trigger enable of line 16 + RTEN16: u1, + /// Rising edge trigger enable of line 17 + RTEN17: u1, + /// Rising edge trigger enable of line 18 + RTEN18: u1, + padding: u13, + }), + /// Falling Egde Trigger Enable register (EXTI_FTEN) + FTEN: mmio.Mmio(packed struct(u32) { + /// Falling edge trigger enable of line 0 + FTEN0: u1, + /// Falling edge trigger enable of line 1 + FTEN1: u1, + /// Falling edge trigger enable of line 2 + FTEN2: u1, + /// Falling edge trigger enable of line 3 + FTEN3: u1, + /// Falling edge trigger enable of line 4 + FTEN4: u1, + /// Falling edge trigger enable of line 5 + FTEN5: u1, + /// Falling edge trigger enable of line 6 + FTEN6: u1, + /// Falling edge trigger enable of line 7 + FTEN7: u1, + /// Falling edge trigger enable of line 8 + FTEN8: u1, + /// Falling edge trigger enable of line 9 + FTEN9: u1, + /// Falling edge trigger enable of line 10 + FTEN10: u1, + /// Falling edge trigger enable of line 11 + FTEN11: u1, + /// Falling edge trigger enable of line 12 + FTEN12: u1, + /// Falling edge trigger enable of line 13 + FTEN13: u1, + /// Falling edge trigger enable of line 14 + FTEN14: u1, + /// Falling edge trigger enable of line 15 + FTEN15: u1, + /// Falling edge trigger enable of line 16 + FTEN16: u1, + /// Falling edge trigger enable of line 17 + FTEN17: u1, + /// Falling edge trigger enable of line 18 + FTEN18: u1, + padding: u13, + }), + /// Software interrupt event register (EXTI_SWIEV) + SWIEV: mmio.Mmio(packed struct(u32) { + /// Interrupt/Event software trigger on line 0 + SWIEV0: u1, + /// Interrupt/Event software trigger on line 1 + SWIEV1: u1, + /// Interrupt/Event software trigger on line 2 + SWIEV2: u1, + /// Interrupt/Event software trigger on line 3 + SWIEV3: u1, + /// Interrupt/Event software trigger on line 4 + SWIEV4: u1, + /// Interrupt/Event software trigger on line 5 + SWIEV5: u1, + /// Interrupt/Event software trigger on line 6 + SWIEV6: u1, + /// Interrupt/Event software trigger on line 7 + SWIEV7: u1, + /// Interrupt/Event software trigger on line 8 + SWIEV8: u1, + /// Interrupt/Event software trigger on line 9 + SWIEV9: u1, + /// Interrupt/Event software trigger on line 10 + SWIEV10: u1, + /// Interrupt/Event software trigger on line 11 + SWIEV11: u1, + /// Interrupt/Event software trigger on line 12 + SWIEV12: u1, + /// Interrupt/Event software trigger on line 13 + SWIEV13: u1, + /// Interrupt/Event software trigger on line 14 + SWIEV14: u1, + /// Interrupt/Event software trigger on line 15 + SWIEV15: u1, + /// Interrupt/Event software trigger on line 16 + SWIEV16: u1, + /// Interrupt/Event software trigger on line 17 + SWIEV17: u1, + /// Interrupt/Event software trigger on line 18 + SWIEV18: u1, + padding: u13, + }), + /// Pending register (EXTI_PD) + PD: mmio.Mmio(packed struct(u32) { + /// Interrupt pending status of line 0 + PD0: u1, + /// Interrupt pending status of line 1 + PD1: u1, + /// Interrupt pending status of line 2 + PD2: u1, + /// Interrupt pending status of line 3 + PD3: u1, + /// Interrupt pending status of line 4 + PD4: u1, + /// Interrupt pending status of line 5 + PD5: u1, + /// Interrupt pending status of line 6 + PD6: u1, + /// Interrupt pending status of line 7 + PD7: u1, + /// Interrupt pending status of line 8 + PD8: u1, + /// Interrupt pending status of line 9 + PD9: u1, + /// Interrupt pending status of line 10 + PD10: u1, + /// Interrupt pending status of line 11 + PD11: u1, + /// Interrupt pending status of line 12 + PD12: u1, + /// Interrupt pending status of line 13 + PD13: u1, + /// Interrupt pending status of line 14 + PD14: u1, + /// Interrupt pending status of line 15 + PD15: u1, + /// Interrupt pending status of line 16 + PD16: u1, + /// Interrupt pending status of line 17 + PD17: u1, + /// Interrupt pending status of line 18 + PD18: u1, + padding: u13, + }), + }; + + /// FMC + pub const FMC = extern struct { + /// wait state counter register + WS: mmio.Mmio(packed struct(u32) { + /// wait state counter register + WSCNT: u3, + padding: u29, + }), + /// Unlock key register 0 + KEY0: mmio.Mmio(packed struct(u32) { + /// FMC_CTL0 unlock key + KEY: u32, + }), + /// Option byte unlock key register + OBKEY: mmio.Mmio(packed struct(u32) { + /// FMC_ CTL0 option byte operation unlock register + OBKEY: u32, + }), + /// Status register 0 + STAT0: mmio.Mmio(packed struct(u32) { + /// The flash is busy bit + BUSY: u1, + reserved2: u1, + /// Program error flag bit + PGERR: u1, + reserved4: u1, + /// Erase/Program protection error flag bit + WPERR: u1, + /// End of operation flag bit + ENDF: u1, + padding: u26, + }), + /// Control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Main flash program for bank0 command bit + PG: u1, + /// Main flash page erase for bank0 command bit + PER: u1, + /// Main flash mass erase for bank0 command bit + MER: u1, + reserved4: u1, + /// Option bytes program command bit + OBPG: u1, + /// Option bytes erase command bit + OBER: u1, + /// Send erase command to FMC bit + START: u1, + /// FMC_CTL0 lock bit + LK: u1, + reserved9: u1, + /// Option byte erase/program enable bit + OBWEN: u1, + /// Error interrupt enable bit + ERRIE: u1, + reserved12: u1, + /// End of operation interrupt enable bit + ENDIE: u1, + padding: u19, + }), + /// Address register 0 + ADDR0: mmio.Mmio(packed struct(u32) { + /// Flash erase/program command address bits + ADDR: u32, + }), + reserved28: [4]u8, + /// Option byte status register + OBSTAT: mmio.Mmio(packed struct(u32) { + /// Option bytes read error bit + OBERR: u1, + /// Option bytes security protection code + SPC: u1, + /// Store USER of option bytes block after system reset + USER: u8, + /// Store DATA[15:0] of option bytes block after system reset + DATA: u16, + padding: u6, + }), + /// Erase/Program Protection register + WP: mmio.Mmio(packed struct(u32) { + /// Store WP[31:0] of option bytes block after system reset + WP: u32, + }), + reserved256: [220]u8, + /// Product ID register + PID: mmio.Mmio(packed struct(u32) { + /// Product reserved ID code register + PID: u32, + }), + }; + + /// free watchdog timer + pub const FWDGT = extern struct { + /// Control register + CTL: mmio.Mmio(packed struct(u32) { + /// Key value + CMD: u16, + padding: u16, + }), + /// Prescaler register + PSC: mmio.Mmio(packed struct(u32) { + /// Free watchdog timer prescaler selection + PSC: u3, + padding: u29, + }), + /// Reload register + RLD: mmio.Mmio(packed struct(u32) { + /// Free watchdog timer counter reload value + RLD: u12, + padding: u20, + }), + /// Status register + STAT: mmio.Mmio(packed struct(u32) { + /// Free watchdog timer prescaler value update + PUD: u1, + /// Free watchdog timer counter reload value update + RUD: u1, + padding: u30, + }), + }; + + /// General-purpose I/Os + pub const GPIOA = extern struct { + /// port control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Port x mode bits (x = 0) + MD0: u2, + /// Port x configuration bits (x = 0) + CTL0: u2, + /// Port x mode bits (x = 1) + MD1: u2, + /// Port x configuration bits (x = 1) + CTL1: u2, + /// Port x mode bits (x = 2 ) + MD2: u2, + /// Port x configuration bits (x = 2) + CTL2: u2, + /// Port x mode bits (x = 3 ) + MD3: u2, + /// Port x configuration bits (x = 3) + CTL3: u2, + /// Port x mode bits (x = 4) + MD4: u2, + /// Port x configuration bits (x = 4) + CTL4: u2, + /// Port x mode bits (x = 5) + MD5: u2, + /// Port x configuration bits (x = 5) + CTL5: u2, + /// Port x mode bits (x = 6) + MD6: u2, + /// Port x configuration bits (x = 6) + CTL6: u2, + /// Port x mode bits (x = 7) + MD7: u2, + /// Port x configuration bits (x = 7) + CTL7: u2, + }), + /// port control register 1 + CTL1: mmio.Mmio(packed struct(u32) { + /// Port x mode bits (x = 8) + MD8: u2, + /// Port x configuration bits (x = 8) + CTL8: u2, + /// Port x mode bits (x = 9) + MD9: u2, + /// Port x configuration bits (x = 9) + CTL9: u2, + /// Port x mode bits (x = 10 ) + MD10: u2, + /// Port x configuration bits (x = 10) + CTL10: u2, + /// Port x mode bits (x = 11 ) + MD11: u2, + /// Port x configuration bits (x = 11) + CTL11: u2, + /// Port x mode bits (x = 12) + MD12: u2, + /// Port x configuration bits (x = 12) + CTL12: u2, + /// Port x mode bits (x = 13) + MD13: u2, + /// Port x configuration bits (x = 13) + CTL13: u2, + /// Port x mode bits (x = 14) + MD14: u2, + /// Port x configuration bits (x = 14) + CTL14: u2, + /// Port x mode bits (x = 15) + MD15: u2, + /// Port x configuration bits (x = 15) + CTL15: u2, + }), + /// Port input status register + ISTAT: mmio.Mmio(packed struct(u32) { + /// Port input status + ISTAT0: u1, + /// Port input status + ISTAT1: u1, + /// Port input status + ISTAT2: u1, + /// Port input status + ISTAT3: u1, + /// Port input status + ISTAT4: u1, + /// Port input status + ISTAT5: u1, + /// Port input status + ISTAT6: u1, + /// Port input status + ISTAT7: u1, + /// Port input status + ISTAT8: u1, + /// Port input status + ISTAT9: u1, + /// Port input status + ISTAT10: u1, + /// Port input status + ISTAT11: u1, + /// Port input status + ISTAT12: u1, + /// Port input status + ISTAT13: u1, + /// Port input status + ISTAT14: u1, + /// Port input status + ISTAT15: u1, + padding: u16, + }), + /// Port output control register + OCTL: mmio.Mmio(packed struct(u32) { + /// Port output control + OCTL0: u1, + /// Port output control + OCTL1: u1, + /// Port output control + OCTL2: u1, + /// Port output control + OCTL3: u1, + /// Port output control + OCTL4: u1, + /// Port output control + OCTL5: u1, + /// Port output control + OCTL6: u1, + /// Port output control + OCTL7: u1, + /// Port output control + OCTL8: u1, + /// Port output control + OCTL9: u1, + /// Port output control + OCTL10: u1, + /// Port output control + OCTL11: u1, + /// Port output control + OCTL12: u1, + /// Port output control + OCTL13: u1, + /// Port output control + OCTL14: u1, + /// Port output control + OCTL15: u1, + padding: u16, + }), + /// Port bit operate register + BOP: mmio.Mmio(packed struct(u32) { + /// Port 0 Set bit + BOP0: u1, + /// Port 1 Set bit + BOP1: u1, + /// Port 2 Set bit + BOP2: u1, + /// Port 3 Set bit + BOP3: u1, + /// Port 4 Set bit + BOP4: u1, + /// Port 5 Set bit + BOP5: u1, + /// Port 6 Set bit + BOP6: u1, + /// Port 7 Set bit + BOP7: u1, + /// Port 8 Set bit + BOP8: u1, + /// Port 9 Set bit + BOP9: u1, + /// Port 10 Set bit + BOP10: u1, + /// Port 11 Set bit + BOP11: u1, + /// Port 12 Set bit + BOP12: u1, + /// Port 13 Set bit + BOP13: u1, + /// Port 14 Set bit + BOP14: u1, + /// Port 15 Set bit + BOP15: u1, + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + }), + /// Port bit clear register + BC: mmio.Mmio(packed struct(u32) { + /// Port 0 Clear bit + CR0: u1, + /// Port 1 Clear bit + CR1: u1, + /// Port 2 Clear bit + CR2: u1, + /// Port 3 Clear bit + CR3: u1, + /// Port 4 Clear bit + CR4: u1, + /// Port 5 Clear bit + CR5: u1, + /// Port 6 Clear bit + CR6: u1, + /// Port 7 Clear bit + CR7: u1, + /// Port 8 Clear bit + CR8: u1, + /// Port 9 Clear bit + CR9: u1, + /// Port 10 Clear bit + CR10: u1, + /// Port 11 Clear bit + CR11: u1, + /// Port 12 Clear bit + CR12: u1, + /// Port 13 Clear bit + CR13: u1, + /// Port 14 Clear bit + CR14: u1, + /// Port 15 Clear bit + CR15: u1, + padding: u16, + }), + /// GPIO port configuration lock register + LOCK: mmio.Mmio(packed struct(u32) { + /// Port Lock bit 0 + LK0: u1, + /// Port Lock bit 1 + LK1: u1, + /// Port Lock bit 2 + LK2: u1, + /// Port Lock bit 3 + LK3: u1, + /// Port Lock bit 4 + LK4: u1, + /// Port Lock bit 5 + LK5: u1, + /// Port Lock bit 6 + LK6: u1, + /// Port Lock bit 7 + LK7: u1, + /// Port Lock bit 8 + LK8: u1, + /// Port Lock bit 9 + LK9: u1, + /// Port Lock bit 10 + LK10: u1, + /// Port Lock bit 11 + LK11: u1, + /// Port Lock bit 12 + LK12: u1, + /// Port Lock bit 13 + LK13: u1, + /// Port Lock bit 14 + LK14: u1, + /// Port Lock bit 15 + LK15: u1, + /// Lock sequence key + LKK: u1, + padding: u15, + }), + }; + + /// USB on the go full speed + pub const USBFS_PWRCLK = extern struct { + /// power and clock gating control register (PWRCLKCTL) + PWRCLKCTL: mmio.Mmio(packed struct(u32) { + /// Stop the USB clock + SUCLK: u1, + /// Stop HCLK + SHCLK: u1, + padding: u30, + }), + }; + + /// USB on the go full speed device + pub const USBFS_DEVICE = extern struct { + /// device configuration register (DCFG) + DCFG: mmio.Mmio(packed struct(u32) { + /// Device speed + DS: u2, + /// Non-zero-length status OUT handshake + NZLSOH: u1, + reserved4: u1, + /// Device address + DAR: u7, + /// end of periodic frame time + EOPFT: u2, + padding: u19, + }), + /// device control register (DCTL) + DCTL: mmio.Mmio(packed struct(u32) { + /// Remote wakeup + RWKUP: u1, + /// Soft disconnect + SD: u1, + /// Global IN NAK status + GINS: u1, + /// Global OUT NAK status + GONS: u1, + reserved7: u3, + /// Set global IN NAK + SGINAK: u1, + /// Clear global IN NAK + CGINAK: u1, + /// Set global OUT NAK + SGONAK: u1, + /// Clear global OUT NAK + CGONAK: u1, + /// Power-on initialization flag + POIF: u1, + padding: u20, + }), + /// device status register (DSTAT) + DSTAT: mmio.Mmio(packed struct(u32) { + /// Suspend status + SPST: u1, + /// Enumerated speed + ES: u2, + reserved8: u5, + /// Frame number of the received SOF + FNRSOF: u14, + padding: u10, + }), + reserved16: [4]u8, + /// device IN endpoint common interrupt mask register (DIEPINTEN) + DIEPINTEN: mmio.Mmio(packed struct(u32) { + /// Transfer finished interrupt enable + TFEN: u1, + /// Endpoint disabled interrupt enable + EPDISEN: u1, + reserved3: u1, + /// Control IN timeout condition interrupt enable (Non-isochronous endpoints) + CITOEN: u1, + /// Endpoint Tx FIFO underrun interrupt enable bit + EPTXFUDEN: u1, + reserved6: u1, + /// IN endpoint NAK effective interrupt enable + IEPNEEN: u1, + padding: u25, + }), + /// device OUT endpoint common interrupt enable register (DOEPINTEN) + DOEPINTEN: mmio.Mmio(packed struct(u32) { + /// Transfer finished interrupt enable + TFEN: u1, + /// Endpoint disabled interrupt enable + EPDISEN: u1, + reserved3: u1, + /// SETUP phase finished interrupt enable + STPFEN: u1, + /// Endpoint Rx FIFO overrun interrupt enable + EPRXFOVREN: u1, + reserved6: u1, + /// Back-to-back SETUP packets interrupt enable + BTBSTPEN: u1, + padding: u25, + }), + /// device all endpoints interrupt register (DAEPINT) + DAEPINT: mmio.Mmio(packed struct(u32) { + /// Device all IN endpoint interrupt bits + IEPITB: u4, + reserved16: u12, + /// Device all OUT endpoint interrupt bits + OEPITB: u4, + padding: u12, + }), + /// Device all endpoints interrupt enable register (DAEPINTEN) + DAEPINTEN: mmio.Mmio(packed struct(u32) { + /// IN EP interrupt interrupt enable bits + IEPIE: u4, + reserved16: u12, + /// OUT endpoint interrupt enable bits + OEPIE: u4, + padding: u12, + }), + reserved40: [8]u8, + /// device VBUS discharge time register + DVBUSDT: mmio.Mmio(packed struct(u32) { + /// Device VBUS discharge time + DVBUSDT: u16, + padding: u16, + }), + /// device VBUS pulsing time register + DVBUSPT: mmio.Mmio(packed struct(u32) { + /// Device VBUS pulsing time + DVBUSPT: u12, + padding: u20, + }), + reserved52: [4]u8, + /// device IN endpoint FIFO empty interrupt enable register + DIEPFEINTEN: mmio.Mmio(packed struct(u32) { + /// IN EP Tx FIFO empty interrupt enable bits + IEPTXFEIE: u4, + padding: u28, + }), + reserved256: [200]u8, + /// device IN endpoint 0 control register (DIEP0CTL) + DIEP0CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet length + MPL: u2, + reserved15: u13, + /// endpoint active + EPACT: u1, + reserved17: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// TxFIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved264: [4]u8, + /// device endpoint-0 interrupt register + DIEP0INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved3: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved6: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding: u24, + }), + reserved272: [4]u8, + /// device IN endpoint-0 transfer length register + DIEP0LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u7, + reserved19: u12, + /// Packet count + PCNT: u2, + padding: u11, + }), + reserved280: [4]u8, + /// device IN endpoint 0 transmit FIFO status register + DIEP0TFSTAT: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space remaining + IEPTFS: u16, + padding: u16, + }), + reserved288: [4]u8, + /// device in endpoint-1 control register + DIEP1CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved296: [4]u8, + /// device endpoint-1 interrupt register + DIEP1INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved3: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved6: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding: u24, + }), + reserved304: [4]u8, + /// device IN endpoint-1 transfer length register + DIEP1LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding: u1, + }), + reserved312: [4]u8, + /// device IN endpoint 1 transmit FIFO status register + DIEP1TFSTAT: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space remaining + IEPTFS: u16, + padding: u16, + }), + reserved320: [4]u8, + /// device endpoint-2 control register + DIEP2CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved328: [4]u8, + /// device endpoint-2 interrupt register + DIEP2INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved3: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved6: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding: u24, + }), + reserved336: [4]u8, + /// device IN endpoint-2 transfer length register + DIEP2LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding: u1, + }), + reserved344: [4]u8, + /// device IN endpoint 2 transmit FIFO status register + DIEP2TFSTAT: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space remaining + IEPTFS: u16, + padding: u16, + }), + reserved352: [4]u8, + /// device endpoint-3 control register + DIEP3CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + reserved21: u1, + /// STALL handshake + STALL: u1, + /// Tx FIFO number + TXFNUM: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVNFRM + SD0PID_SEVENFRM: u1, + /// Set DATA1 PID/Set odd frame + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved360: [4]u8, + /// device endpoint-3 interrupt register + DIEP3INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint finished + EPDIS: u1, + reserved3: u1, + /// Control in timeout interrupt + CITO: u1, + /// Endpoint Tx FIFO underrun + EPTXFUD: u1, + reserved6: u1, + /// IN endpoint NAK effective + IEPNE: u1, + /// Transmit FIFO empty + TXFE: u1, + padding: u24, + }), + reserved368: [4]u8, + /// device IN endpoint-3 transfer length register + DIEP3LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Multi packet count per frame + MCPF: u2, + padding: u1, + }), + reserved376: [4]u8, + /// device IN endpoint 3 transmit FIFO status register + DIEP3TFSTAT: mmio.Mmio(packed struct(u32) { + /// IN endpoint TxFIFO space remaining + IEPTFS: u16, + padding: u16, + }), + reserved768: [388]u8, + /// device endpoint-0 control register + DOEP0CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet length + MPL: u2, + reserved15: u13, + /// Endpoint active + EPACT: u1, + reserved17: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + reserved30: u2, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved776: [4]u8, + /// device out endpoint-0 interrupt flag register + DOEP0INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved3: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved6: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding: u25, + }), + reserved784: [4]u8, + /// device OUT endpoint-0 transfer length register + DOEP0LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u7, + reserved19: u12, + /// Packet count + PCNT: u1, + reserved29: u9, + /// SETUP packet count + STPCNT: u2, + padding: u1, + }), + reserved800: [12]u8, + /// device endpoint-1 control register + DOEP1CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved808: [4]u8, + /// device out endpoint-1 interrupt flag register + DOEP1INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved3: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved6: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding: u25, + }), + reserved816: [4]u8, + /// device OUT endpoint-1 transfer length register + DOEP1LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding: u1, + }), + reserved832: [12]u8, + /// device endpoint-2 control register + DOEP2CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved840: [4]u8, + /// device out endpoint-2 interrupt flag register + DOEP2INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved3: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved6: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding: u25, + }), + reserved848: [4]u8, + /// device OUT endpoint-2 transfer length register + DOEP2LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding: u1, + }), + reserved864: [12]u8, + /// device endpoint-3 control register + DOEP3CTL: mmio.Mmio(packed struct(u32) { + /// maximum packet length + MPL: u11, + reserved15: u4, + /// Endpoint active + EPACT: u1, + /// EOFRM/DPID + EOFRM_DPID: u1, + /// NAK status + NAKS: u1, + /// Endpoint type + EPTYPE: u2, + /// Snoop mode + SNOOP: u1, + /// STALL handshake + STALL: u1, + reserved26: u4, + /// Clear NAK + CNAK: u1, + /// Set NAK + SNAK: u1, + /// SD0PID/SEVENFRM + SD0PID_SEVENFRM: u1, + /// SD1PID/SODDFRM + SD1PID_SODDFRM: u1, + /// Endpoint disable + EPD: u1, + /// Endpoint enable + EPEN: u1, + }), + reserved872: [4]u8, + /// device out endpoint-3 interrupt flag register + DOEP3INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Endpoint disabled + EPDIS: u1, + reserved3: u1, + /// Setup phase finished + STPF: u1, + /// Endpoint Rx FIFO overrun + EPRXFOVR: u1, + reserved6: u1, + /// Back-to-back SETUP packets + BTBSTP: u1, + padding: u25, + }), + reserved880: [4]u8, + /// device OUT endpoint-3 transfer length register + DOEP3LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// SETUP packet count/Received data PID + STPCNT_RXDPID: u2, + padding: u1, + }), + }; + + /// USB on the go full speed host + pub const USBFS_HOST = extern struct { + /// host configuration register (HCTL) + HCTL: mmio.Mmio(packed struct(u32) { + /// clock select for USB clock + CLKSEL: u2, + padding: u30, + }), + /// Host frame interval register + HFT: mmio.Mmio(packed struct(u32) { + /// Frame interval + FRI: u16, + padding: u16, + }), + /// FS host frame number/frame time remaining register (HFINFR) + HFINFR: mmio.Mmio(packed struct(u32) { + /// Frame number + FRNUM: u16, + /// Frame remaining time + FRT: u16, + }), + reserved16: [4]u8, + /// Host periodic transmit FIFO/queue status register (HPTFQSTAT) + HPTFQSTAT: mmio.Mmio(packed struct(u32) { + /// Periodic transmit data FIFO space available + PTXFS: u16, + /// Periodic transmit request queue space available + PTXREQS: u8, + /// Top of the periodic transmit request queue + PTXREQT: u8, + }), + /// Host all channels interrupt register + HACHINT: mmio.Mmio(packed struct(u32) { + /// Host all channel interrupts + HACHINT: u8, + padding: u24, + }), + /// host all channels interrupt mask register + HACHINTEN: mmio.Mmio(packed struct(u32) { + /// Channel interrupt enable + CINTEN: u8, + padding: u24, + }), + reserved64: [36]u8, + /// Host port control and status register (USBFS_HPCS) + HPCS: mmio.Mmio(packed struct(u32) { + /// Port connect status + PCST: u1, + /// Port connect detected + PCD: u1, + /// Port enable + PE: u1, + /// Port enable/disable change + PEDC: u1, + reserved6: u2, + /// Port resume + PREM: u1, + /// Port suspend + PSP: u1, + /// Port reset + PRST: u1, + reserved10: u1, + /// Port line status + PLST: u2, + /// Port power + PP: u1, + reserved17: u4, + /// Port speed + PS: u2, + padding: u13, + }), + reserved256: [188]u8, + /// host channel-0 characteristics register (HCH0CTL) + HCH0CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved264: [4]u8, + /// host channel-0 interrupt register (USBFS_HCHxINTF) + HCH0INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-0 interrupt enable register (HCH0INTEN) + HCH0INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-0 transfer length register + HCH0LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved288: [12]u8, + /// host channel-1 characteristics register (HCH1CTL) + HCH1CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved296: [4]u8, + /// host channel-1 interrupt register (HCH1INTF) + HCH1INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-1 interrupt enable register (HCH1INTEN) + HCH1INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-1 transfer length register + HCH1LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved320: [12]u8, + /// host channel-2 characteristics register (HCH2CTL) + HCH2CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved328: [4]u8, + /// host channel-2 interrupt register (HCH2INTF) + HCH2INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-2 interrupt enable register (HCH2INTEN) + HCH2INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-2 transfer length register + HCH2LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved352: [12]u8, + /// host channel-3 characteristics register (HCH3CTL) + HCH3CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved360: [4]u8, + /// host channel-3 interrupt register (HCH3INTF) + HCH3INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-3 interrupt enable register (HCH3INTEN) + HCH3INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-3 transfer length register + HCH3LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved384: [12]u8, + /// host channel-4 characteristics register (HCH4CTL) + HCH4CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved392: [4]u8, + /// host channel-4 interrupt register (HCH4INTF) + HCH4INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-4 interrupt enable register (HCH4INTEN) + HCH4INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-4 transfer length register + HCH4LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved416: [12]u8, + /// host channel-5 characteristics register (HCH5CTL) + HCH5CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved424: [4]u8, + /// host channel-5 interrupt register (HCH5INTF) + HCH5INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-5 interrupt enable register (HCH5INTEN) + HCH5INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-5 transfer length register + HCH5LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved448: [12]u8, + /// host channel-6 characteristics register (HCH6CTL) + HCH6CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved456: [4]u8, + /// host channel-6 interrupt register (HCH6INTF) + HCH6INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-6 interrupt enable register (HCH6INTEN) + HCH6INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-6 transfer length register + HCH6LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + reserved480: [12]u8, + /// host channel-7 characteristics register (HCH7CTL) + HCH7CTL: mmio.Mmio(packed struct(u32) { + /// Maximum packet size + MPL: u11, + /// Endpoint number + EPNUM: u4, + /// Endpoint direction + EPDIR: u1, + reserved17: u1, + /// Low-speed device + LSD: u1, + /// Endpoint type + EPTYPE: u2, + reserved22: u2, + /// Device address + DAR: u7, + /// Odd frame + ODDFRM: u1, + /// Channel disable + CDIS: u1, + /// Channel enable + CEN: u1, + }), + reserved488: [4]u8, + /// host channel-7 interrupt register (HCH7INTF) + HCH7INTF: mmio.Mmio(packed struct(u32) { + /// Transfer finished + TF: u1, + /// Channel halted + CH: u1, + reserved3: u1, + /// STALL response received interrupt + STALL: u1, + /// NAK response received interrupt + NAK: u1, + /// ACK response received/transmitted interrupt + ACK: u1, + reserved7: u1, + /// USB bus error + USBER: u1, + /// Babble error + BBER: u1, + /// Request queue overrun + REQOVR: u1, + /// Data toggle error + DTER: u1, + padding: u21, + }), + /// host channel-7 interrupt enable register (HCH7INTEN) + HCH7INTEN: mmio.Mmio(packed struct(u32) { + /// Transfer completed interrupt enable + TFIE: u1, + /// Channel halted interrupt enable + CHIE: u1, + reserved3: u1, + /// STALL interrupt enable + STALLIE: u1, + /// NAK interrupt enable + NAKIE: u1, + /// ACK interrupt enable + ACKIE: u1, + reserved7: u1, + /// USB bus error interrupt enable + USBERIE: u1, + /// Babble error interrupt enable + BBERIE: u1, + /// request queue overrun interrupt enable + REQOVRIE: u1, + /// Data toggle error interrupt enable + DTERIE: u1, + padding: u21, + }), + /// host channel-7 transfer length register + HCH7LEN: mmio.Mmio(packed struct(u32) { + /// Transfer length + TLEN: u19, + /// Packet count + PCNT: u10, + /// Data PID + DPID: u2, + padding: u1, + }), + }; + + /// USB full speed global registers + pub const USBFS_GLOBAL = extern struct { + /// Global OTG control and status register (USBFS_GOTGCS) + GOTGCS: mmio.Mmio(packed struct(u32) { + /// SRP success + SRPS: u1, + /// SRP request + SRPREQ: u1, + reserved8: u6, + /// Host success + HNPS: u1, + /// HNP request + HNPREQ: u1, + /// Host HNP enable + HHNPEN: u1, + /// Device HNP enabled + DHNPEN: u1, + reserved16: u4, + /// ID pin status + IDPS: u1, + /// Debounce interval + DI: u1, + /// A-session valid + ASV: u1, + /// B-session valid + BSV: u1, + padding: u12, + }), + /// Global OTG interrupt flag register (USBFS_GOTGINTF) + GOTGINTF: mmio.Mmio(packed struct(u32) { + reserved2: u2, + /// Session end + SESEND: u1, + reserved8: u5, + /// Session request success status change + SRPEND: u1, + /// HNP end + HNPEND: u1, + reserved17: u7, + /// Host negotiation request detected + HNPDET: u1, + /// A-device timeout + ADTO: u1, + /// Debounce finish + DF: u1, + padding: u12, + }), + /// Global AHB control and status register (USBFS_GAHBCS) + GAHBCS: mmio.Mmio(packed struct(u32) { + /// Global interrupt enable + GINTEN: u1, + reserved7: u6, + /// Tx FIFO threshold + TXFTH: u1, + /// Periodic Tx FIFO threshold + PTXFTH: u1, + padding: u23, + }), + /// Global USB control and status register (USBFS_GUSBCSR) + GUSBCS: mmio.Mmio(packed struct(u32) { + /// Timeout calibration + TOC: u3, + reserved8: u5, + /// SRP capability enable + SRPCEN: u1, + /// HNP capability enable + HNPCEN: u1, + /// USB turnaround time + UTT: u4, + reserved29: u15, + /// Force host mode + FHM: u1, + /// Force device mode + FDM: u1, + padding: u1, + }), + /// Global reset control register (USBFS_GRSTCTL) + GRSTCTL: mmio.Mmio(packed struct(u32) { + /// Core soft reset + CSRST: u1, + /// HCLK soft reset + HCSRST: u1, + /// Host frame counter reset + HFCRST: u1, + reserved4: u1, + /// RxFIFO flush + RXFF: u1, + /// TxFIFO flush + TXFF: u1, + /// TxFIFO number + TXFNUM: u5, + padding: u21, + }), + /// Global interrupt flag register (USBFS_GINTF) + GINTF: mmio.Mmio(packed struct(u32) { + /// Current operation mode + COPM: u1, + /// Mode fault interrupt flag + MFIF: u1, + /// OTG interrupt flag + OTGIF: u1, + /// Start of frame + SOF: u1, + /// RxFIFO non-empty interrupt flag + RXFNEIF: u1, + /// Non-periodic TxFIFO empty interrupt flag + NPTXFEIF: u1, + /// Global Non-Periodic IN NAK effective + GNPINAK: u1, + /// Global OUT NAK effective + GONAK: u1, + reserved10: u2, + /// Early suspend + ESP: u1, + /// USB suspend + SP: u1, + /// USB reset + RST: u1, + /// Enumeration finished + ENUMF: u1, + /// Isochronous OUT packet dropped interrupt + ISOOPDIF: u1, + /// End of periodic frame interrupt flag + EOPFIF: u1, + reserved18: u2, + /// IN endpoint interrupt flag + IEPIF: u1, + /// OUT endpoint interrupt flag + OEPIF: u1, + /// Isochronous IN transfer Not Complete Interrupt Flag + ISOINCIF: u1, + /// periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) + PXNCIF_ISOONCIF: u1, + reserved24: u2, + /// Host port interrupt flag + HPIF: u1, + /// Host channels interrupt flag + HCIF: u1, + /// Periodic TxFIFO empty interrupt flag + PTXFEIF: u1, + reserved28: u1, + /// ID pin status change + IDPSC: u1, + /// Disconnect interrupt flag + DISCIF: u1, + /// Session interrupt flag + SESIF: u1, + /// Wakeup interrupt flag + WKUPIF: u1, + }), + /// Global interrupt enable register (USBFS_GINTEN) + GINTEN: mmio.Mmio(packed struct(u32) { + reserved1: u1, + /// Mode fault interrupt enable + MFIE: u1, + /// OTG interrupt enable + OTGIE: u1, + /// Start of frame interrupt enable + SOFIE: u1, + /// Receive FIFO non-empty interrupt enable + RXFNEIE: u1, + /// Non-periodic TxFIFO empty interrupt enable + NPTXFEIE: u1, + /// Global non-periodic IN NAK effective interrupt enable + GNPINAKIE: u1, + /// Global OUT NAK effective interrupt enable + GONAKIE: u1, + reserved10: u2, + /// Early suspend interrupt enable + ESPIE: u1, + /// USB suspend interrupt enable + SPIE: u1, + /// USB reset interrupt enable + RSTIE: u1, + /// Enumeration finish interrupt enable + ENUMFIE: u1, + /// Isochronous OUT packet dropped interrupt enable + ISOOPDIE: u1, + /// End of periodic frame interrupt enable + EOPFIE: u1, + reserved18: u2, + /// IN endpoints interrupt enable + IEPIE: u1, + /// OUT endpoints interrupt enable + OEPIE: u1, + /// isochronous IN transfer not complete interrupt enable + ISOINCIE: u1, + /// periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) + PXNCIE_ISOONCIE: u1, + reserved24: u2, + /// Host port interrupt enable + HPIE: u1, + /// Host channels interrupt enable + HCIE: u1, + /// Periodic TxFIFO empty interrupt enable + PTXFEIE: u1, + reserved28: u1, + /// ID pin status change interrupt enable + IDPSCIE: u1, + /// Disconnect interrupt enable + DISCIE: u1, + /// Session interrupt enable + SESIE: u1, + /// Wakeup interrupt enable + WKUPIE: u1, + }), + /// Global Receive status read(Device mode) + GRSTATR_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Recieve packet status + RPCKST: u4, + padding: u11, + }), + /// Global Receive status pop(Device mode) + GRSTATP_Device: mmio.Mmio(packed struct(u32) { + /// Endpoint number + EPNUM: u4, + /// Byte count + BCOUNT: u11, + /// Data PID + DPID: u2, + /// Recieve packet status + RPCKST: u4, + padding: u11, + }), + /// Global Receive FIFO size register (USBFS_GRFLEN) + GRFLEN: mmio.Mmio(packed struct(u32) { + /// Rx FIFO depth + RXFD: u16, + padding: u16, + }), + /// Host non-periodic transmit FIFO length register (Host mode) + HNPTFLEN: mmio.Mmio(packed struct(u32) { + /// host non-periodic transmit Tx RAM start address + HNPTXRSAR: u16, + /// host non-periodic TxFIFO depth + HNPTXFD: u16, + }), + /// Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) + HNPTFQSTAT: mmio.Mmio(packed struct(u32) { + /// Non-periodic TxFIFO space + NPTXFS: u16, + /// Non-periodic transmit request queue space + NPTXRQS: u8, + /// Top of the non-periodic transmit request queue + NPTXRQTOP: u7, + padding: u1, + }), + reserved56: [8]u8, + /// Global core configuration register (USBFS_GCCFG) + GCCFG: mmio.Mmio(packed struct(u32) { + reserved16: u16, + /// Power on + PWRON: u1, + reserved18: u1, + /// The VBUS A-device Comparer enable + VBUSACEN: u1, + /// The VBUS B-device Comparer enable + VBUSBCEN: u1, + /// SOF output enable + SOFOEN: u1, + /// VBUS ignored + VBUSIG: u1, + padding: u10, + }), + /// core ID register + CID: mmio.Mmio(packed struct(u32) { + /// Core ID + CID: u32, + }), + reserved256: [192]u8, + /// Host periodic transmit FIFO length register (HPTFLEN) + HPTFLEN: mmio.Mmio(packed struct(u32) { + /// Host periodic TxFIFO start address + HPTXFSAR: u16, + /// Host periodic TxFIFO depth + HPTXFD: u16, + }), + /// device IN endpoint transmit FIFO size register (DIEP1TFLEN) + DIEP1TFLEN: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO transmit RAM start address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), + /// device IN endpoint transmit FIFO size register (DIEP2TFLEN) + DIEP2TFLEN: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO transmit RAM start address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), + /// device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN) + DIEP3TFLEN: mmio.Mmio(packed struct(u32) { + /// IN endpoint FIFO4 transmit RAM start address + IEPTXRSAR: u16, + /// IN endpoint TxFIFO depth + IEPTXFD: u16, + }), + }; + + /// Inter integrated circuit + pub const I2C0 = extern struct { + /// Control register 0 + CTL0: mmio.Mmio(packed struct(u16) { + /// I2C peripheral enable + I2CEN: u1, + /// SMBus/I2C mode switch + SMBEN: u1, + reserved3: u1, + /// SMBusType Selection + SMBSEL: u1, + /// ARP protocol in SMBus switch + ARPEN: u1, + /// PEC Calculation Switch + PECEN: u1, + /// Whether or not to response to a General Call (0x00) + GCEN: u1, + /// Whether to stretch SCL low when data is not ready in slave mode + SS: u1, + /// Generate a START condition on I2C bus + START: u1, + /// Generate a STOP condition on I2C bus + STOP: u1, + /// Whether or not to send an ACK + ACKEN: u1, + /// Position of ACK and PEC when receiving + POAP: u1, + /// PEC Transfer + PECTRANS: u1, + /// SMBus alert + SALT: u1, + reserved15: u1, + /// Software reset + SRESET: u1, + }), + reserved4: [2]u8, + /// Control register 1 + CTL1: mmio.Mmio(packed struct(u16) { + /// I2C Peripheral clock frequency + I2CCLK: u6, + reserved8: u2, + /// Error interrupt enable + ERRIE: u1, + /// Event interrupt enable + EVIE: u1, + /// Buffer interrupt enable + BUFIE: u1, + /// DMA mode switch + DMAON: u1, + /// Flag indicating DMA last transfer + DMALST: u1, + padding: u3, + }), + reserved8: [2]u8, + /// Slave address register 0 + SADDR0: mmio.Mmio(packed struct(u16) { + /// Bit 0 of a 10-bit address + ADDRESS0: u1, + /// 7-bit address or bits 7:1 of a 10-bit address + ADDRESS7_1: u7, + /// Highest two bits of a 10-bit address + ADDRESS9_8: u2, + reserved15: u5, + /// Address mode for the I2C slave + ADDFORMAT: u1, + }), + reserved12: [2]u8, + /// Slave address register 1 + SADDR1: mmio.Mmio(packed struct(u16) { + /// Dual-Address mode switch + DUADEN: u1, + /// Second I2C address for the slave in Dual-Address mode + ADDRESS2: u7, + padding: u8, + }), + reserved16: [2]u8, + /// Transfer buffer register + DATA: mmio.Mmio(packed struct(u16) { + /// Transmission or reception data buffer register + TRB: u8, + padding: u8, + }), + reserved20: [2]u8, + /// Transfer status register 0 + STAT0: mmio.Mmio(packed struct(u16) { + /// START condition sent out in master mode + SBSEND: u1, + /// Address is sent in master mode or received and matches in slave mode + ADDSEND: u1, + /// Byte transmission completed + BTC: u1, + /// Header of 10-bit address is sent in master mode + ADD10SEND: u1, + /// STOP condition detected in slave mode + STPDET: u1, + reserved6: u1, + /// I2C_DATA is not Empty during receiving + RBNE: u1, + /// I2C_DATA is Empty during transmitting + TBE: u1, + /// A bus error occurs indication a unexpected START or STOP condition on I2C bus + BERR: u1, + /// Arbitration Lost in master mode + LOSTARB: u1, + /// Acknowledge error + AERR: u1, + /// Over-run or under-run situation occurs in slave mode + OUERR: u1, + /// PEC error when receiving data + PECERR: u1, + reserved14: u1, + /// Timeout signal in SMBus mode + SMBTO: u1, + /// SMBus Alert status + SMBALT: u1, + }), + reserved24: [2]u8, + /// Transfer status register 1 + STAT1: mmio.Mmio(packed struct(u16) { + /// A flag indicating whether I2C block is in master or slave mode + MASTER: u1, + /// Busy flag + I2CBSY: u1, + /// Whether the I2C is a transmitter or a receiver + TR: u1, + reserved4: u1, + /// General call address (00h) received + RXGC: u1, + /// Default address of SMBusDevice + DEFSMB: u1, + /// SMBus Host Header detected in slave mode + HSTSMB: u1, + /// Dual Flag in slave mode + DUMODF: u1, + /// Packet Error Checking Value that calculated by hardware when PEC is enabled + PECV: u8, + }), + reserved28: [2]u8, + /// Clock configure register + CKCFG: mmio.Mmio(packed struct(u16) { + /// I2C Clock control in master mode + CLKC: u12, + reserved14: u2, + /// Duty cycle in fast mode + DTCY: u1, + /// I2C speed selection in master mode + FAST: u1, + }), + reserved32: [2]u8, + /// Rise time register + RT: mmio.Mmio(packed struct(u16) { + /// Maximum rise time in master mode + RISETIME: u6, + padding: u10, + }), + }; + + /// Basic-timers + pub const TIMER5 = extern struct { + /// control register 0 + CTL0: mmio.Mmio(packed struct(u16) { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + reserved7: u3, + /// Auto-reload shadow enable + ARSE: u1, + padding: u8, + }), + reserved4: [2]u8, + /// control register 1 + CTL1: mmio.Mmio(packed struct(u16) { + reserved4: u4, + /// Master mode control + MMC: u3, + padding: u9, + }), + reserved12: [6]u8, + /// DMA/Interrupt enable register + DMAINTEN: mmio.Mmio(packed struct(u16) { + /// Update interrupt enable + UPIE: u1, + reserved8: u7, + /// Update DMA request enable + UPDEN: u1, + padding: u7, + }), + reserved16: [2]u8, + /// Interrupt flag register + INTF: mmio.Mmio(packed struct(u16) { + /// Update interrupt flag + UPIF: u1, + padding: u15, + }), + reserved20: [2]u8, + /// event generation register + SWEVG: mmio.Mmio(packed struct(u16) { + /// Update generation + UPG: u1, + padding: u15, + }), + reserved36: [14]u8, + /// Counter register + CNT: mmio.Mmio(packed struct(u16) { + /// Low counter value + CNT: u16, + }), + reserved40: [2]u8, + /// Prescaler register + PSC: mmio.Mmio(packed struct(u16) { + /// Prescaler value of the counter clock + PSC: u16, + }), + reserved44: [2]u8, + /// Counter auto reload register + CAR: mmio.Mmio(packed struct(u16) { + /// Counter auto reload value + CARL: u16, + }), + }; + + /// Enhanced Core Local Interrupt Controller + pub const ECLIC = extern struct { + /// cliccfg Register + CLICCFG: mmio.Mmio(packed struct(u8) { + reserved1: u1, + /// NLBITS + NLBITS: u4, + padding: u3, + }), + reserved4: [3]u8, + /// clicinfo Register + CLICINFO: mmio.Mmio(packed struct(u32) { + /// NUM_INTERRUPT + NUM_INTERRUPT: u13, + /// VERSION + VERSION: u8, + /// CLICINTCTLBITS + CLICINTCTLBITS: u4, + padding: u7, + }), + reserved11: [3]u8, + /// MTH Register + MTH: mmio.Mmio(packed struct(u8) { + /// MTH + MTH: u8, + }), + reserved4096: [4084]u8, + /// clicintip Register + CLICINTIP_0: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_0: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_0: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_0: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_1: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_1: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_1: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_1: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_2: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_2: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_2: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_2: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_3: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_3: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_3: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_3: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_4: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_4: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_4: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_4: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_5: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_5: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_5: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_5: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_6: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_6: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_6: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_6: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_7: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_7: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_7: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_7: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_8: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_8: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_8: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_8: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_9: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_9: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_9: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_9: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_10: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_10: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_10: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_10: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_11: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_11: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_11: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_11: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_12: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_12: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_12: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_12: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_13: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_13: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_13: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_13: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_14: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_14: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_14: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_14: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_15: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_15: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_15: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_15: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_16: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_16: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_16: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_16: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_17: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_17: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_17: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_17: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_18: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_18: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_18: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_18: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_19: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_19: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_19: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_19: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_20: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_20: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_20: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_20: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_21: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_21: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_21: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_21: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_22: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_22: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_22: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_22: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_23: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_23: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_23: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_23: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_24: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_24: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_24: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_24: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_25: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_25: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_25: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_25: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_26: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_26: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_26: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_26: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_27: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_27: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_27: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_27: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_28: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_28: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_28: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_28: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_29: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_29: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_29: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_29: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_30: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_30: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_30: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_30: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_31: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_31: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_31: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_31: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_32: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_32: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_32: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_32: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_33: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_33: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_33: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_33: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_34: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_34: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_34: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_34: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_35: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_35: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_35: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_35: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_36: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_36: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_36: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_36: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_37: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_37: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_37: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_37: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_38: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_38: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_38: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_38: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_39: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_39: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_39: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_39: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_40: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_40: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_40: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_40: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_41: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_41: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_41: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_41: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_42: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_42: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_42: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_42: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_43: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_43: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_43: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_43: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_44: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_44: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_44: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_44: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_45: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_45: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_45: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_45: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_46: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_46: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_46: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_46: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_47: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_47: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_47: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_47: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_48: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_48: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_48: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_48: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_49: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_49: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_49: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_49: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_50: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_50: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_50: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_50: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_51: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_51: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_51: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_51: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_52: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_52: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_52: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_52: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_53: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_53: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_53: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_53: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_54: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_54: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_54: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_54: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_55: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_55: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_55: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_55: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_56: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_56: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_56: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_56: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_57: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_57: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_57: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_57: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_58: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_58: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_58: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_58: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_59: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_59: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_59: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_59: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_60: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_60: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_60: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_60: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_61: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_61: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_61: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_61: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_62: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_62: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_62: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_62: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_63: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_63: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_63: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_63: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_64: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_64: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_64: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_64: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_65: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_65: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_65: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_65: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_66: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_66: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_66: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_66: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_67: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_67: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_67: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_67: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_68: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_68: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_68: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_68: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_69: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_69: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_69: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_69: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_70: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_70: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_70: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_70: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_71: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_71: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_71: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_71: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_72: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_72: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_72: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_72: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_73: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_73: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_73: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_73: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_74: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_74: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_74: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_74: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_75: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_75: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_75: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_75: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_76: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_76: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_76: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_76: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_77: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_77: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_77: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_77: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_78: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_78: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_78: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_78: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_79: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_79: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_79: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_79: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_80: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_80: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_80: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_80: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_81: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_81: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_81: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_81: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_82: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_82: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_82: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_82: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_83: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_83: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_83: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_83: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_84: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_84: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_84: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_84: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + reserved4437: [1]u8, + /// clicintie Register + CLICINTIE_85: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_85: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_85: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_85: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + /// clicintie Register + CLICINTIE_86: mmio.Mmio(packed struct(u8) { + /// IE + IE: u1, + padding: u7, + }), + /// clicintattr Register + CLICINTATTR_86: mmio.Mmio(packed struct(u8) { + /// SHV + SHV: u1, + /// TRIG + TRIG: u2, + padding: u5, + }), + /// clicintctl Register + CLICINTCTL_86: mmio.Mmio(packed struct(u8) { + /// LEVEL_PRIORITY + LEVEL_PRIORITY: u8, + }), + /// clicintip Register + CLICINTIP_86: mmio.Mmio(packed struct(u8) { + /// IP + IP: u1, + padding: u7, + }), + }; + + /// Power management unit + pub const PMU = extern struct { + /// power control register + CTL: mmio.Mmio(packed struct(u32) { + /// LDO Low Power Mode + LDOLP: u1, + /// Standby Mode + STBMOD: u1, + /// Wakeup Flag Reset + WURST: u1, + /// Standby Flag Reset + STBRST: u1, + /// Low Voltage Detector Enable + LVDEN: u1, + /// Low Voltage Detector Threshold + LVDT: u3, + /// Backup Domain Write Enable + BKPWEN: u1, + padding: u23, + }), + /// power control/status register + CS: mmio.Mmio(packed struct(u32) { + /// Wakeup flag + WUF: u1, + /// Standby flag + STBF: u1, + /// Low Voltage Detector Status Flag + LVDF: u1, + reserved8: u5, + /// Enable WKUP pin + WUPEN: u1, + padding: u23, + }), + }; + + /// Reset and clock unit + pub const RCU = extern struct { + /// Control register + CTL: mmio.Mmio(packed struct(u32) { + /// Internal 8MHz RC oscillator Enable + IRC8MEN: u1, + /// IRC8M Internal 8MHz RC Oscillator stabilization Flag + IRC8MSTB: u1, + reserved3: u1, + /// Internal 8MHz RC Oscillator clock trim adjust value + IRC8MADJ: u5, + /// Internal 8MHz RC Oscillator calibration value register + IRC8MCALIB: u8, + /// External High Speed oscillator Enable + HXTALEN: u1, + /// External crystal oscillator (HXTAL) clock stabilization flag + HXTALSTB: u1, + /// External crystal oscillator (HXTAL) clock bypass mode enable + HXTALBPS: u1, + /// HXTAL Clock Monitor Enable + CKMEN: u1, + reserved24: u4, + /// PLL enable + PLLEN: u1, + /// PLL Clock Stabilization Flag + PLLSTB: u1, + /// PLL1 enable + PLL1EN: u1, + /// PLL1 Clock Stabilization Flag + PLL1STB: u1, + /// PLL2 enable + PLL2EN: u1, + /// PLL2 Clock Stabilization Flag + PLL2STB: u1, + padding: u2, + }), + /// Clock configuration register 0 (RCU_CFG0) + CFG0: mmio.Mmio(packed struct(u32) { + /// System clock switch + SCS: u2, + /// System clock switch status + SCSS: u2, + /// AHB prescaler selection + AHBPSC: u4, + /// APB1 prescaler selection + APB1PSC: u3, + /// APB2 prescaler selection + APB2PSC: u3, + /// ADC clock prescaler selection + ADCPSC_1_0: u2, + /// PLL Clock Source Selection + PLLSEL: u1, + /// The LSB of PREDV0 division factor + PREDV0_LSB: u1, + /// The PLL clock multiplication factor + PLLMF_3_0: u4, + /// USBFS clock prescaler selection + USBFSPSC: u2, + /// CKOUT0 Clock Source Selection + CKOUT0SEL: u4, + /// Bit 2 of ADCPSC + ADCPSC_2: u1, + /// Bit 4 of PLLMF + PLLMF_4: u1, + padding: u2, + }), + /// Clock interrupt register (RCU_INT) + INT: mmio.Mmio(packed struct(u32) { + /// IRC40K stabilization interrupt flag + IRC40KSTBIF: u1, + /// LXTAL stabilization interrupt flag + LXTALSTBIF: u1, + /// IRC8M stabilization interrupt flag + IRC8MSTBIF: u1, + /// HXTAL stabilization interrupt flag + HXTALSTBIF: u1, + /// PLL stabilization interrupt flag + PLLSTBIF: u1, + /// PLL1 stabilization interrupt flag + PLL1STBIF: u1, + /// PLL2 stabilization interrupt flag + PLL2STBIF: u1, + /// HXTAL Clock Stuck Interrupt Flag + CKMIF: u1, + /// IRC40K Stabilization interrupt enable + IRC40KSTBIE: u1, + /// LXTAL Stabilization Interrupt Enable + LXTALSTBIE: u1, + /// IRC8M Stabilization Interrupt Enable + IRC8MSTBIE: u1, + /// HXTAL Stabilization Interrupt Enable + HXTALSTBIE: u1, + /// PLL Stabilization Interrupt Enable + PLLSTBIE: u1, + /// PLL1 Stabilization Interrupt Enable + PLL1STBIE: u1, + /// PLL2 Stabilization Interrupt Enable + PLL2STBIE: u1, + reserved16: u1, + /// IRC40K Stabilization Interrupt Clear + IRC40KSTBIC: u1, + /// LXTAL Stabilization Interrupt Clear + LXTALSTBIC: u1, + /// IRC8M Stabilization Interrupt Clear + IRC8MSTBIC: u1, + /// HXTAL Stabilization Interrupt Clear + HXTALSTBIC: u1, + /// PLL stabilization Interrupt Clear + PLLSTBIC: u1, + /// PLL1 stabilization Interrupt Clear + PLL1STBIC: u1, + /// PLL2 stabilization Interrupt Clear + PLL2STBIC: u1, + /// HXTAL Clock Stuck Interrupt Clear + CKMIC: u1, + padding: u8, + }), + /// APB2 reset register (RCU_APB2RST) + APB2RST: mmio.Mmio(packed struct(u32) { + /// Alternate function I/O reset + AFRST: u1, + reserved2: u1, + /// GPIO port A reset + PARST: u1, + /// GPIO port B reset + PBRST: u1, + /// GPIO port C reset + PCRST: u1, + /// GPIO port D reset + PDRST: u1, + /// GPIO port E reset + PERST: u1, + reserved9: u2, + /// ADC0 reset + ADC0RST: u1, + /// ADC1 reset + ADC1RST: u1, + /// Timer 0 reset + TIMER0RST: u1, + /// SPI0 reset + SPI0RST: u1, + reserved14: u1, + /// USART0 Reset + USART0RST: u1, + padding: u17, + }), + /// APB1 reset register (RCU_APB1RST) + APB1RST: mmio.Mmio(packed struct(u32) { + /// TIMER1 timer reset + TIMER1RST: u1, + /// TIMER2 timer reset + TIMER2RST: u1, + /// TIMER3 timer reset + TIMER3RST: u1, + /// TIMER4 timer reset + TIMER4RST: u1, + /// TIMER5 timer reset + TIMER5RST: u1, + /// TIMER6 timer reset + TIMER6RST: u1, + reserved11: u5, + /// Window watchdog timer reset + WWDGTRST: u1, + reserved14: u2, + /// SPI1 reset + SPI1RST: u1, + /// SPI2 reset + SPI2RST: u1, + reserved17: u1, + /// USART1 reset + USART1RST: u1, + /// USART2 reset + USART2RST: u1, + /// UART3 reset + UART3RST: u1, + /// UART4 reset + UART4RST: u1, + /// I2C0 reset + I2C0RST: u1, + /// I2C1 reset + I2C1RST: u1, + reserved25: u2, + /// CAN0 reset + CAN0RST: u1, + /// CAN1 reset + CAN1RST: u1, + /// Backup interface reset + BKPIRST: u1, + /// Power control reset + PMURST: u1, + /// DAC reset + DACRST: u1, + padding: u2, + }), + /// AHB enable register + AHBEN: mmio.Mmio(packed struct(u32) { + /// DMA0 clock enable + DMA0EN: u1, + /// DMA1 clock enable + DMA1EN: u1, + /// SRAM interface clock enable when sleep mode + SRAMSPEN: u1, + reserved4: u1, + /// FMC clock enable when sleep mode + FMCSPEN: u1, + reserved6: u1, + /// CRC clock enable + CRCEN: u1, + reserved8: u1, + /// EXMC clock enable + EXMCEN: u1, + reserved12: u3, + /// USBFS clock enable + USBFSEN: u1, + padding: u19, + }), + /// APB2 clock enable register (RCU_APB2EN) + APB2EN: mmio.Mmio(packed struct(u32) { + /// Alternate function IO clock enable + AFEN: u1, + reserved2: u1, + /// GPIO port A clock enable + PAEN: u1, + /// GPIO port B clock enable + PBEN: u1, + /// GPIO port C clock enable + PCEN: u1, + /// GPIO port D clock enable + PDEN: u1, + /// GPIO port E clock enable + PEEN: u1, + reserved9: u2, + /// ADC0 clock enable + ADC0EN: u1, + /// ADC1 clock enable + ADC1EN: u1, + /// TIMER0 clock enable + TIMER0EN: u1, + /// SPI0 clock enable + SPI0EN: u1, + reserved14: u1, + /// USART0 clock enable + USART0EN: u1, + padding: u17, + }), + /// APB1 clock enable register (RCU_APB1EN) + APB1EN: mmio.Mmio(packed struct(u32) { + /// TIMER1 timer clock enable + TIMER1EN: u1, + /// TIMER2 timer clock enable + TIMER2EN: u1, + /// TIMER3 timer clock enable + TIMER3EN: u1, + /// TIMER4 timer clock enable + TIMER4EN: u1, + /// TIMER5 timer clock enable + TIMER5EN: u1, + /// TIMER6 timer clock enable + TIMER6EN: u1, + reserved11: u5, + /// Window watchdog timer clock enable + WWDGTEN: u1, + reserved14: u2, + /// SPI1 clock enable + SPI1EN: u1, + /// SPI2 clock enable + SPI2EN: u1, + reserved17: u1, + /// USART1 clock enable + USART1EN: u1, + /// USART2 clock enable + USART2EN: u1, + /// UART3 clock enable + UART3EN: u1, + /// UART4 clock enable + UART4EN: u1, + /// I2C0 clock enable + I2C0EN: u1, + /// I2C1 clock enable + I2C1EN: u1, + reserved25: u2, + /// CAN0 clock enable + CAN0EN: u1, + /// CAN1 clock enable + CAN1EN: u1, + /// Backup interface clock enable + BKPIEN: u1, + /// Power control clock enable + PMUEN: u1, + /// DAC clock enable + DACEN: u1, + padding: u2, + }), + /// Backup domain control register (RCU_BDCTL) + BDCTL: mmio.Mmio(packed struct(u32) { + /// LXTAL enable + LXTALEN: u1, + /// External low-speed oscillator stabilization + LXTALSTB: u1, + /// LXTAL bypass mode enable + LXTALBPS: u1, + reserved8: u5, + /// RTC clock entry selection + RTCSRC: u2, + reserved15: u5, + /// RTC clock enable + RTCEN: u1, + /// Backup domain reset + BKPRST: u1, + padding: u15, + }), + /// Reset source /clock register (RCU_RSTSCK) + RSTSCK: mmio.Mmio(packed struct(u32) { + /// IRC40K enable + IRC40KEN: u1, + /// IRC40K stabilization + IRC40KSTB: u1, + reserved24: u22, + /// Reset flag clear + RSTFC: u1, + reserved26: u1, + /// External PIN reset flag + EPRSTF: u1, + /// Power reset flag + PORRSTF: u1, + /// Software reset flag + SWRSTF: u1, + /// Free Watchdog timer reset flag + FWDGTRSTF: u1, + /// Window watchdog timer reset flag + WWDGTRSTF: u1, + /// Low-power reset flag + LPRSTF: u1, + }), + /// AHB reset register + AHBRST: mmio.Mmio(packed struct(u32) { + reserved12: u12, + /// USBFS reset + USBFSRST: u1, + padding: u19, + }), + /// Clock Configuration register 1 + CFG1: mmio.Mmio(packed struct(u32) { + /// PREDV0 division factor + PREDV0: u4, + /// PREDV1 division factor + PREDV1: u4, + /// The PLL1 clock multiplication factor + PLL1MF: u4, + /// The PLL2 clock multiplication factor + PLL2MF: u4, + /// PREDV0 input Clock Source Selection + PREDV0SEL: u1, + /// I2S1 Clock Source Selection + I2S1SEL: u1, + /// I2S2 Clock Source Selection + I2S2SEL: u1, + padding: u13, + }), + reserved52: [4]u8, + /// Deep sleep mode Voltage register + DSV: mmio.Mmio(packed struct(u32) { + /// Deep-sleep mode voltage select + DSLPVS: u2, + padding: u30, + }), + }; + + /// Real-time clock + pub const RTC = extern struct { + /// RTC interrupt enable register + INTEN: mmio.Mmio(packed struct(u32) { + /// Second interrupt + SCIE: u1, + /// Alarm interrupt enable + ALRMIE: u1, + /// Overflow interrupt enable + OVIE: u1, + padding: u29, + }), + /// control register + CTL: mmio.Mmio(packed struct(u32) { + /// Sencond interrupt flag + SCIF: u1, + /// Alarm interrupt flag + ALRMIF: u1, + /// Overflow interrupt flag + OVIF: u1, + /// Registers synchronized flag + RSYNF: u1, + /// Configuration mode flag + CMF: u1, + /// Last write operation finished flag + LWOFF: u1, + padding: u26, + }), + /// RTC prescaler high register + PSCH: mmio.Mmio(packed struct(u32) { + padding: u32, + }), + /// RTC prescaler low register + PSCL: mmio.Mmio(packed struct(u32) { + padding: u32, + }), + /// RTC divider high register + DIVH: mmio.Mmio(packed struct(u32) { + /// RTC divider value high + DIV: u4, + padding: u28, + }), + /// RTC divider low register + DIVL: mmio.Mmio(packed struct(u32) { + /// RTC divider value low + DIV: u16, + padding: u16, + }), + /// RTC counter high register + CNTH: mmio.Mmio(packed struct(u32) { + /// RTC counter value high + CNT: u16, + padding: u16, + }), + /// RTC counter low register + CNTL: mmio.Mmio(packed struct(u32) { + /// RTC counter value low + CNT: u16, + padding: u16, + }), + }; + + /// Serial peripheral interface + pub const SPI0 = extern struct { + /// control register 0 + CTL0: mmio.Mmio(packed struct(u16) { + /// Clock Phase Selection + CKPH: u1, + /// Clock polarity Selection + CKPL: u1, + /// Master Mode Enable + MSTMOD: u1, + /// Master Clock Prescaler Selection + PSC: u3, + /// SPI enable + SPIEN: u1, + /// LSB First Mode + LF: u1, + /// NSS Pin Selection In NSS Software Mode + SWNSS: u1, + /// NSS Software Mode Selection + SWNSSEN: u1, + /// Receive only + RO: u1, + /// Data frame format + FF16: u1, + /// CRC Next Transfer + CRCNT: u1, + /// CRC Calculation Enable + CRCEN: u1, + /// Bidirectional Transmit output enable + BDOEN: u1, + /// Bidirectional enable + BDEN: u1, + }), + reserved4: [2]u8, + /// control register 1 + CTL1: mmio.Mmio(packed struct(u16) { + /// Rx buffer DMA enable + DMAREN: u1, + /// Transmit Buffer DMA Enable + DMATEN: u1, + /// Drive NSS Output + NSSDRV: u1, + /// SPI NSS pulse mode enable + NSSP: u1, + /// SPI TI mode enable + TMOD: u1, + /// Error interrupt enable + ERRIE: u1, + /// RX buffer not empty interrupt enable + RBNEIE: u1, + /// Tx buffer empty interrupt enable + TBEIE: u1, + padding: u8, + }), + reserved8: [2]u8, + /// status register + STAT: mmio.Mmio(packed struct(u16) { + /// Receive Buffer Not Empty + RBNE: u1, + /// Transmit Buffer Empty + TBE: u1, + /// I2S channel side + I2SCH: u1, + /// Transmission underrun error bit + TXURERR: u1, + /// SPI CRC Error Bit + CRCERR: u1, + /// SPI Configuration error + CONFERR: u1, + /// Reception Overrun Error Bit + RXORERR: u1, + /// Transmitting On-going Bit + TRANS: u1, + /// Format error + FERR: u1, + padding: u7, + }), + reserved12: [2]u8, + /// data register + DATA: mmio.Mmio(packed struct(u16) { + /// Data transfer register + SPI_DATA: u16, + }), + reserved16: [2]u8, + /// CRC polynomial register + CRCPOLY: mmio.Mmio(packed struct(u16) { + /// CRC polynomial value + CRCPOLY: u16, + }), + reserved20: [2]u8, + /// RX CRC register + RCRC: mmio.Mmio(packed struct(u16) { + /// RX CRC value + RCRC: u16, + }), + reserved24: [2]u8, + /// TX CRC register + TCRC: mmio.Mmio(packed struct(u16) { + /// Tx CRC value + TCRC: u16, + }), + reserved28: [2]u8, + /// I2S control register + I2SCTL: mmio.Mmio(packed struct(u16) { + /// Channel length (number of bits per audio channel) + CHLEN: u1, + /// Data length + DTLEN: u2, + /// Idle state clock polarity + CKPL: u1, + /// I2S standard selection + I2SSTD: u2, + reserved7: u1, + /// PCM frame synchronization mode + PCMSMOD: u1, + /// I2S operation mode + I2SOPMOD: u2, + /// I2S Enable + I2SEN: u1, + /// I2S mode selection + I2SSEL: u1, + padding: u4, + }), + reserved32: [2]u8, + /// I2S prescaler register + I2SPSC: mmio.Mmio(packed struct(u16) { + /// Dividing factor for the prescaler + DIV: u8, + /// Odd factor for the prescaler + OF: u1, + /// I2S_MCK output enable + MCKOEN: u1, + padding: u6, + }), + }; + + /// Universal asynchronous receiver transmitter + pub const UART3 = extern struct { + /// Status register + STAT: mmio.Mmio(packed struct(u32) { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + padding: u23, + }), + /// Data register + DATA: mmio.Mmio(packed struct(u32) { + /// Transmit or read data value + DATA: u9, + padding: u23, + }), + /// Baud rate register + BAUD: mmio.Mmio(packed struct(u32) { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding: u16, + }), + /// Control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding: u18, + }), + /// Control register 1 + CTL1: mmio.Mmio(packed struct(u32) { + /// Address of the USART + ADDR: u4, + reserved5: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved12: u5, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding: u17, + }), + /// Control register 2 + CTL2: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + reserved6: u2, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + padding: u24, + }), + /// Guard time and prescaler register + GP: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + padding: u24, + }), + }; + + /// Universal synchronous asynchronous receiver transmitter + pub const USART0 = extern struct { + /// Status register + STAT: mmio.Mmio(packed struct(u32) { + /// Parity error flag + PERR: u1, + /// Frame error flag + FERR: u1, + /// Noise error flag + NERR: u1, + /// Overrun error + ORERR: u1, + /// IDLE frame detected flag + IDLEF: u1, + /// Read data buffer not empty + RBNE: u1, + /// Transmission complete + TC: u1, + /// Transmit data buffer empty + TBE: u1, + /// LIN break detection flag + LBDF: u1, + /// CTS change flag + CTSF: u1, + padding: u22, + }), + /// Data register + DATA: mmio.Mmio(packed struct(u32) { + /// Transmit or read data value + DATA: u9, + padding: u23, + }), + /// Baud rate register + BAUD: mmio.Mmio(packed struct(u32) { + /// Fraction part of baud-rate divider + FRADIV: u4, + /// Integer part of baud-rate divider + INTDIV: u12, + padding: u16, + }), + /// Control register 0 + CTL0: mmio.Mmio(packed struct(u32) { + /// Send break command + SBKCMD: u1, + /// Receiver wakeup from mute mode + RWU: u1, + /// Receiver enable + REN: u1, + /// Transmitter enable + TEN: u1, + /// IDLE line detected interrupt enable + IDLEIE: u1, + /// Read data buffer not empty interrupt and overrun error interrupt enable + RBNEIE: u1, + /// Transmission complete interrupt enable + TCIE: u1, + /// Transmitter buffer empty interrupt enable + TBEIE: u1, + /// Parity error interrupt enable + PERRIE: u1, + /// Parity mode + PM: u1, + /// Parity check function enable + PCEN: u1, + /// Wakeup method in mute mode + WM: u1, + /// Word length + WL: u1, + /// USART enable + UEN: u1, + padding: u18, + }), + /// Control register 1 + CTL1: mmio.Mmio(packed struct(u32) { + /// Address of the USART + ADDR: u4, + reserved5: u1, + /// LIN break frame length + LBLEN: u1, + /// LIN break detection interrupt enable + LBDIE: u1, + reserved8: u1, + /// CK Length + CLEN: u1, + /// Clock phase + CPH: u1, + /// Clock polarity + CPL: u1, + /// CK pin enable + CKEN: u1, + /// STOP bits length + STB: u2, + /// LIN mode enable + LMEN: u1, + padding: u17, + }), + /// Control register 2 + CTL2: mmio.Mmio(packed struct(u32) { + /// Error interrupt enable + ERRIE: u1, + /// IrDA mode enable + IREN: u1, + /// IrDA low-power + IRLP: u1, + /// Half-duplex selection + HDEN: u1, + /// Smartcard NACK enable + NKEN: u1, + /// Smartcard mode enable + SCEN: u1, + /// DMA request enable for reception + DENR: u1, + /// DMA request enable for transmission + DENT: u1, + /// RTS enable + RTSEN: u1, + /// CTS enable + CTSEN: u1, + /// CTS interrupt enable + CTSIE: u1, + padding: u21, + }), + /// Guard time and prescaler register + GP: mmio.Mmio(packed struct(u32) { + /// Prescaler value + PSC: u8, + /// Guard time value in Smartcard mode + GUAT: u8, + padding: u16, + }), + }; + + /// Advanced-timers + pub const TIMER0 = extern struct { + /// control register 0 + CTL0: mmio.Mmio(packed struct(u16) { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding: u6, + }), + reserved4: [2]u8, + /// control register 1 + CTL1: mmio.Mmio(packed struct(u16) { + /// Commutation control shadow enable + CCSE: u1, + reserved2: u1, + /// Commutation control shadow register update control + CCUC: u1, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + /// Idle state of channel 0 output + ISO0: u1, + /// Idle state of channel 0 complementary output + ISO0N: u1, + /// Idle state of channel 1 output + ISO1: u1, + /// Idle state of channel 1 complementary output + ISO1N: u1, + /// Idle state of channel 2 output + ISO2: u1, + /// Idle state of channel 2 complementary output + ISO2N: u1, + /// Idle state of channel 3 output + ISO3: u1, + padding: u1, + }), + reserved8: [2]u8, + /// slave mode configuration register + SMCFG: mmio.Mmio(packed struct(u16) { + /// Slave mode selection + SMC: u3, + reserved4: u1, + /// Trigger selection + TRGS: u3, + /// Master/Slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), + reserved12: [2]u8, + /// DMA/Interrupt enable register + DMAINTEN: mmio.Mmio(packed struct(u16) { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + /// commutation interrupt enable + CMTIE: u1, + /// Trigger interrupt enable + TRGIE: u1, + /// Break interrupt enable + BRKIE: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + /// Commutation DMA request enable + CMTDEN: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding: u1, + }), + reserved16: [2]u8, + /// Interrupt flag register + INTF: mmio.Mmio(packed struct(u16) { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt flag + CH2IF: u1, + /// Channel 3 capture/compare interrupt flag + CH3IF: u1, + /// Channel commutation interrupt flag + CMTIF: u1, + /// Trigger interrupt flag + TRGIF: u1, + /// Break interrupt flag + BRKIF: u1, + reserved9: u1, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding: u3, + }), + reserved20: [2]u8, + /// Software event generation register + SWEVG: mmio.Mmio(packed struct(u16) { + /// Update event generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + /// Channel commutation event generation + CMTG: u1, + /// Trigger event generation + TRGG: u1, + /// Break event generation + BRKG: u1, + padding: u8, + }), + reserved24: [2]u8, + /// Channel control register 0 (output mode) + CHCTL0_Output: mmio.Mmio(packed struct(u16) { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), + reserved28: [2]u8, + /// Channel control register 1 (output mode) + CHCTL1_Output: mmio.Mmio(packed struct(u16) { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), + reserved32: [2]u8, + /// Channel control register 2 + CHCTL2: mmio.Mmio(packed struct(u16) { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + /// Channel 0 complementary output enable + CH0NEN: u1, + /// Channel 0 complementary output polarity + CH0NP: u1, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + /// Channel 1 complementary output enable + CH1NEN: u1, + /// Channel 1 complementary output polarity + CH1NP: u1, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + /// Channel 2 complementary output enable + CH2NEN: u1, + /// Channel 2 complementary output polarity + CH2NP: u1, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding: u2, + }), + reserved36: [2]u8, + /// counter + CNT: mmio.Mmio(packed struct(u16) { + /// current counter value + CNT: u16, + }), + reserved40: [2]u8, + /// prescaler + PSC: mmio.Mmio(packed struct(u16) { + /// Prescaler value of the counter clock + PSC: u16, + }), + reserved44: [2]u8, + /// Counter auto reload register + CAR: mmio.Mmio(packed struct(u16) { + /// Counter auto reload value + CARL: u16, + }), + reserved48: [2]u8, + /// Counter repetition register + CREP: mmio.Mmio(packed struct(u16) { + /// Counter repetition value + CREP: u8, + padding: u8, + }), + reserved52: [2]u8, + /// Channel 0 capture/compare value register + CH0CV: mmio.Mmio(packed struct(u16) { + /// Capture or compare value of channel0 + CH0VAL: u16, + }), + reserved56: [2]u8, + /// Channel 1 capture/compare value register + CH1CV: mmio.Mmio(packed struct(u16) { + /// Capture or compare value of channel1 + CH1VAL: u16, + }), + reserved60: [2]u8, + /// Channel 2 capture/compare value register + CH2CV: mmio.Mmio(packed struct(u16) { + /// Capture or compare value of channel 2 + CH2VAL: u16, + }), + reserved64: [2]u8, + /// Channel 3 capture/compare value register + CH3CV: mmio.Mmio(packed struct(u16) { + /// Capture or compare value of channel 3 + CH3VAL: u16, + }), + reserved68: [2]u8, + /// channel complementary protection register + CCHP: mmio.Mmio(packed struct(u16) { + /// Dead time configure + DTCFG: u8, + /// Complementary register protect control + PROT: u2, + /// Idle mode off-state configure + IOS: u1, + /// Run mode off-state configure + ROS: u1, + /// Break enable + BRKEN: u1, + /// Break polarity + BRKP: u1, + /// Output automatic enable + OAEN: u1, + /// Primary output enable + POEN: u1, + }), + reserved72: [2]u8, + /// DMA configuration register + DMACFG: mmio.Mmio(packed struct(u16) { + /// DMA transfer access start address + DMATA: u5, + reserved8: u3, + /// DMA transfer count + DMATC: u5, + padding: u3, + }), + reserved76: [2]u8, + /// DMA transfer buffer register + DMATB: mmio.Mmio(packed struct(u16) { + /// DMA transfer buffer + DMATB: u16, + }), + }; + + /// General-purpose-timers + pub const TIMER1 = extern struct { + /// control register 0 + CTL0: mmio.Mmio(packed struct(u16) { + /// Counter enable + CEN: u1, + /// Update disable + UPDIS: u1, + /// Update source + UPS: u1, + /// Single pulse mode + SPM: u1, + /// Direction + DIR: u1, + /// Counter aligns mode selection + CAM: u2, + /// Auto-reload shadow enable + ARSE: u1, + /// Clock division + CKDIV: u2, + padding: u6, + }), + reserved4: [2]u8, + /// control register 1 + CTL1: mmio.Mmio(packed struct(u16) { + reserved3: u3, + /// DMA request source selection + DMAS: u1, + /// Master mode control + MMC: u3, + /// Channel 0 trigger input selection + TI0S: u1, + padding: u8, + }), + reserved8: [2]u8, + /// slave mode control register + SMCFG: mmio.Mmio(packed struct(u16) { + /// Slave mode control + SMC: u3, + reserved4: u1, + /// Trigger selection + TRGS: u3, + /// Master-slave mode + MSM: u1, + /// External trigger filter control + ETFC: u4, + /// External trigger prescaler + ETPSC: u2, + /// Part of SMC for enable External clock mode1 + SMC1: u1, + /// External trigger polarity + ETP: u1, + }), + reserved12: [2]u8, + /// DMA/Interrupt enable register + DMAINTEN: mmio.Mmio(packed struct(u16) { + /// Update interrupt enable + UPIE: u1, + /// Channel 0 capture/compare interrupt enable + CH0IE: u1, + /// Channel 1 capture/compare interrupt enable + CH1IE: u1, + /// Channel 2 capture/compare interrupt enable + CH2IE: u1, + /// Channel 3 capture/compare interrupt enable + CH3IE: u1, + reserved6: u1, + /// Trigger interrupt enable + TRGIE: u1, + reserved8: u1, + /// Update DMA request enable + UPDEN: u1, + /// Channel 0 capture/compare DMA request enable + CH0DEN: u1, + /// Channel 1 capture/compare DMA request enable + CH1DEN: u1, + /// Channel 2 capture/compare DMA request enable + CH2DEN: u1, + /// Channel 3 capture/compare DMA request enable + CH3DEN: u1, + reserved14: u1, + /// Trigger DMA request enable + TRGDEN: u1, + padding: u1, + }), + reserved16: [2]u8, + /// interrupt flag register + INTF: mmio.Mmio(packed struct(u16) { + /// Update interrupt flag + UPIF: u1, + /// Channel 0 capture/compare interrupt flag + CH0IF: u1, + /// Channel 1 capture/compare interrupt flag + CH1IF: u1, + /// Channel 2 capture/compare interrupt enable + CH2IF: u1, + /// Channel 3 capture/compare interrupt enable + CH3IF: u1, + reserved6: u1, + /// Trigger interrupt flag + TRGIF: u1, + reserved9: u2, + /// Channel 0 over capture flag + CH0OF: u1, + /// Channel 1 over capture flag + CH1OF: u1, + /// Channel 2 over capture flag + CH2OF: u1, + /// Channel 3 over capture flag + CH3OF: u1, + padding: u3, + }), + reserved20: [2]u8, + /// event generation register + SWEVG: mmio.Mmio(packed struct(u16) { + /// Update generation + UPG: u1, + /// Channel 0 capture or compare event generation + CH0G: u1, + /// Channel 1 capture or compare event generation + CH1G: u1, + /// Channel 2 capture or compare event generation + CH2G: u1, + /// Channel 3 capture or compare event generation + CH3G: u1, + reserved6: u1, + /// Trigger event generation + TRGG: u1, + padding: u9, + }), + reserved24: [2]u8, + /// Channel control register 0 (output mode) + CHCTL0_Output: mmio.Mmio(packed struct(u16) { + /// Channel 0 I/O mode selection + CH0MS: u2, + /// Channel 0 output compare fast enable + CH0COMFEN: u1, + /// Channel 0 compare output shadow enable + CH0COMSEN: u1, + /// Channel 0 compare output control + CH0COMCTL: u3, + /// Channel 0 output compare clear enable + CH0COMCEN: u1, + /// Channel 1 mode selection + CH1MS: u2, + /// Channel 1 output compare fast enable + CH1COMFEN: u1, + /// Channel 1 output compare shadow enable + CH1COMSEN: u1, + /// Channel 1 compare output control + CH1COMCTL: u3, + /// Channel 1 output compare clear enable + CH1COMCEN: u1, + }), + reserved28: [2]u8, + /// Channel control register 1 (output mode) + CHCTL1_Output: mmio.Mmio(packed struct(u16) { + /// Channel 2 I/O mode selection + CH2MS: u2, + /// Channel 2 output compare fast enable + CH2COMFEN: u1, + /// Channel 2 compare output shadow enable + CH2COMSEN: u1, + /// Channel 2 compare output control + CH2COMCTL: u3, + /// Channel 2 output compare clear enable + CH2COMCEN: u1, + /// Channel 3 mode selection + CH3MS: u2, + /// Channel 3 output compare fast enable + CH3COMFEN: u1, + /// Channel 3 output compare shadow enable + CH3COMSEN: u1, + /// Channel 3 compare output control + CH3COMCTL: u3, + /// Channel 3 output compare clear enable + CH3COMCEN: u1, + }), + reserved32: [2]u8, + /// Channel control register 2 + CHCTL2: mmio.Mmio(packed struct(u16) { + /// Channel 0 capture/compare function enable + CH0EN: u1, + /// Channel 0 capture/compare function polarity + CH0P: u1, + reserved4: u2, + /// Channel 1 capture/compare function enable + CH1EN: u1, + /// Channel 1 capture/compare function polarity + CH1P: u1, + reserved8: u2, + /// Channel 2 capture/compare function enable + CH2EN: u1, + /// Channel 2 capture/compare function polarity + CH2P: u1, + reserved12: u2, + /// Channel 3 capture/compare function enable + CH3EN: u1, + /// Channel 3 capture/compare function polarity + CH3P: u1, + padding: u2, + }), + reserved36: [2]u8, + /// Counter register + CNT: mmio.Mmio(packed struct(u16) { + /// counter value + CNT: u16, + }), + reserved40: [2]u8, + /// Prescaler register + PSC: mmio.Mmio(packed struct(u16) { + /// Prescaler value of the counter clock + PSC: u16, + }), + reserved44: [2]u8, + /// Counter auto reload register + CAR: mmio.Mmio(packed struct(u16) { + /// Counter auto reload value + CARL: u16, + }), + reserved52: [6]u8, + /// Channel 0 capture/compare value register + CH0CV: mmio.Mmio(packed struct(u32) { + /// Capture or compare value of channel 0 + CH0VAL: u16, + padding: u16, + }), + /// Channel 1 capture/compare value register + CH1CV: mmio.Mmio(packed struct(u32) { + /// Capture or compare value of channel1 + CH1VAL: u16, + padding: u16, + }), + /// Channel 2 capture/compare value register + CH2CV: mmio.Mmio(packed struct(u32) { + /// Capture or compare value of channel 2 + CH2VAL: u16, + padding: u16, + }), + /// Channel 3 capture/compare value register + CH3CV: mmio.Mmio(packed struct(u32) { + /// Capture or compare value of channel 3 + CH3VAL: u16, + padding: u16, + }), + reserved72: [4]u8, + /// DMA configuration register + DMACFG: mmio.Mmio(packed struct(u16) { + /// DMA transfer access start address + DMATA: u5, + reserved8: u3, + /// DMA transfer count + DMATC: u5, + padding: u3, + }), + reserved76: [2]u8, + /// DMA transfer buffer register + DMATB: mmio.Mmio(packed struct(u32) { + /// DMA transfer buffer + DMATB: u16, + padding: u16, + }), + }; + }; +}; diff --git a/src/hals/GD32VF103.zig b/src/hals/GD32VF103.zig new file mode 100644 index 0000000..8b5c728 --- /dev/null +++ b/src/hals/GD32VF103.zig @@ -0,0 +1,112 @@ +const micro = @import("microzig"); +const peripherals = micro.chip.peripherals; +const UART3 = peripherals.UART3; +const UART4 = peripherals.UART4; + +pub const clock_frequencies = .{ + .cpu = 8_000_000, // 8 MHz +}; + +pub fn parse_pin(comptime spec: []const u8) type { + const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme."; + + if (spec[0] != 'P') + @compileError(invalid_format_msg); + if (spec[1] < 'A' or spec[1] > 'E') + @compileError(invalid_format_msg); + + return struct { + const pin_number: comptime_int = @import("std").fmt.parseInt(u2, spec[2..], 10) catch @compileError(invalid_format_msg); + // 'A'...'E' + const gpio_port_name = spec[1..2]; + const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name); + const suffix = @import("std").fmt.comptimePrint("{d}", .{pin_number}); + }; +} + +fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void { + var temp = reg.read(); + @field(temp, field_name) = value; + reg.write(temp); +} + +pub const gpio = struct { + pub fn set_output(comptime pin: type) void { + _ = pin; + // TODO: check if pin is already configured as output + } + pub fn set_input(comptime pin: type) void { + _ = pin; + // TODO: check if pin is already configured as input + } + + pub fn read(comptime pin: type) micro.gpio.State { + _ = pin; + // TODO: check if pin is configured as input + return .low; + } + + pub fn write(comptime pin: type, state: micro.gpio.State) void { + _ = pin; + _ = state; + // TODO: check if pin is configured as output + } +}; + +pub const uart = struct { + pub const DataBits = enum(u2) { + five = 0, + six = 1, + seven = 2, + eight = 3, + }; + + pub const StopBits = enum(u1) { + one = 0, + two = 1, + }; + + pub const Parity = enum(u2) { + odd = 0, + even = 1, + mark = 2, + space = 3, + }; +}; + +pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type { + if (pins.tx != null or pins.rx != null) + @compileError("TODO: custom pins are not currently supported"); + + return struct { + const UARTn = switch (index) { + 0 => UART3, + 1 => UART4, + else => @compileError("GD32VF103 has 2 UARTs available."), + }; + const Self = @This(); + + pub fn init(config: micro.uart.Config) !Self { + _ = config; + return Self{}; + } + + pub fn can_write(self: Self) bool { + _ = self; + return false; + } + pub fn tx(self: Self, ch: u8) void { + _ = ch; + while (!self.can_write()) {} // Wait for Previous transmission + } + + pub fn can_read(self: Self) bool { + _ = self; + return false; + } + pub fn rx(self: Self) u8 { + while (!self.can_read()) {} // Wait till the data is received + return 1; // Read received data + } + }; +} From f26efd50424daa962d7aa11cac1edecacc63d1a4 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 20 Feb 2023 11:10:08 -0800 Subject: [PATCH 03/20] update microzig (#2) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 97ca549..831cfff 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 97ca5497da0f22d025e18bced9311efed088d893 +Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec From 0e22da698beee3bca49af1ebd400b5bb02f8c151 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 24 Feb 2023 09:12:06 -0800 Subject: [PATCH 04/20] Update microzig (#3) * update microzig * update paths and for loops --------- Co-authored-by: mattnite --- build.zig | 2 +- deps/microzig | 2 +- src/boards.zig | 2 +- src/chips.zig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/build.zig b/build.zig index 3b787fe..30cd9c9 100644 --- a/build.zig +++ b/build.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const microzig = @import("deps/microzig/src/main.zig"); +const microzig = @import("deps/microzig/build.zig"); const boards = @import("src/boards.zig"); const chips = @import("src/chips.zig"); diff --git a/deps/microzig b/deps/microzig index 831cfff..11214ed 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec +Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732 diff --git a/src/boards.zig b/src/boards.zig index d9a73b5..264bfee 100644 --- a/src/boards.zig +++ b/src/boards.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/build.zig"); const chips = @import("chips.zig"); fn root_dir() []const u8 { diff --git a/src/chips.zig b/src/chips.zig index ac1beef..2822bd7 100644 --- a/src/chips.zig +++ b/src/chips.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const micro = @import("../deps/microzig/src/main.zig"); +const micro = @import("../deps/microzig/build.zig"); const Chip = micro.Chip; const MemoryRegion = micro.MemoryRegion; From 1a9e4cdbc3c2cfdd3ecfef1df447d67283f1f7b5 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 28 Feb 2023 01:26:24 -0800 Subject: [PATCH 05/20] Update microzig (#4) * update microzig * update to new api --------- Co-authored-by: mattnite --- build.zig | 35 +++++++++++++++++++---------------- deps/microzig | 2 +- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/build.zig b/build.zig index 30cd9c9..86ad216 100644 --- a/build.zig +++ b/build.zig @@ -1,7 +1,8 @@ const std = @import("std"); const microzig = @import("deps/microzig/build.zig"); -const boards = @import("src/boards.zig"); -const chips = @import("src/chips.zig"); + +pub const boards = @import("src/boards.zig"); +pub const chips = @import("src/chips.zig"); pub fn build(b: *std.build.Builder) void { const optimize = b.standardOptimizeOption(.{}); @@ -9,13 +10,14 @@ pub fn build(b: *std.build.Builder) void { if (!decl.is_pub) continue; - const exe = microzig.addEmbeddedExecutable( - b, - @field(boards, decl.name).name ++ ".minimal", - "test/programs/minimal.zig", - .{ .board = @field(boards, decl.name) }, - .{ .optimize = optimize }, - ); + const exe = microzig.addEmbeddedExecutable(b, .{ + .name = @field(boards, decl.name).name ++ ".minimal", + .source_file = .{ + .path = "test/programs/minimal.zig", + }, + .backing = .{ .board = @field(boards, decl.name) }, + .optimize = optimize, + }); exe.install(); } @@ -23,13 +25,14 @@ pub fn build(b: *std.build.Builder) void { if (!decl.is_pub) continue; - const exe = microzig.addEmbeddedExecutable( - b, - @field(chips, decl.name).name ++ ".minimal", - "test/programs/minimal.zig", - .{ .chip = @field(chips, decl.name) }, - .{ .optimize = optimize }, - ); + const exe = microzig.addEmbeddedExecutable(b, .{ + .name = @field(chips, decl.name).name ++ ".minimal", + .source_file = .{ + .path = "test/programs/minimal.zig", + }, + .backing = .{ .chip = @field(chips, decl.name) }, + .optimize = optimize, + }); exe.install(); } } diff --git a/deps/microzig b/deps/microzig index 11214ed..b6fc3ab 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732 +Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84 From d31c4ce02ce4e8f1be9e7fc6b730e1d7a4aa7639 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 28 Feb 2023 01:46:06 -0800 Subject: [PATCH 06/20] update microzig (#5) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index b6fc3ab..08e7d5b 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84 +Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725 From 63ea5efd3719edbf92dae57e7ab9896c115de7a0 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 19 Mar 2023 16:31:43 -0700 Subject: [PATCH 07/20] update microzig (#7) --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 08e7d5b..6f5b726 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725 +Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde From 8031b4cf20fcee88104f45592f4cca5698141fe0 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 22 Mar 2023 00:54:47 -0700 Subject: [PATCH 08/20] update microzig (#8) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 6f5b726..dabc932 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde +Subproject commit dabc9325cdee394ff66e28c91803cb814954b157 From 215711d807f5a983a660ff3adefbe49e38ae9acd Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:28:29 -0700 Subject: [PATCH 09/20] Update microzig (#9) * update microzig * add zig version --------- Co-authored-by: mattnite --- README.adoc | 5 +++++ deps/microzig | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/README.adoc b/README.adoc index f23b1bf..daa2bcc 100644 --- a/README.adoc +++ b/README.adoc @@ -1 +1,6 @@ = GigaDevice GD32 Hardware Support Package + +== What version of Zig to use + +Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. + diff --git a/deps/microzig b/deps/microzig index dabc932..5b0176e 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit dabc9325cdee394ff66e28c91803cb814954b157 +Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5 From bdba656f9baa0bbfafe456a1d150bc35dfad4f05 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 23 Mar 2023 08:42:47 -0700 Subject: [PATCH 10/20] Update microzig (#10) * update microzig * fix link --------- Co-authored-by: mattnite --- README.adoc | 2 +- deps/microzig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README.adoc b/README.adoc index daa2bcc..9985edf 100644 --- a/README.adoc +++ b/README.adoc @@ -2,5 +2,5 @@ == What version of Zig to use -Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig. +Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig. diff --git a/deps/microzig b/deps/microzig index 5b0176e..ceaa9dd 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5 +Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e From 7df8396558ade478266f3182e7be6f9a3bd466c4 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 5 Apr 2023 17:19:42 -0700 Subject: [PATCH 11/20] update microzig (#11) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index ceaa9dd..23482a6 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e +Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7 From 9a8df1477bd2753928cb55c5e4f1a13feb7a0590 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 13 Apr 2023 22:23:57 -0700 Subject: [PATCH 12/20] Update microzig (#12) * update microzig * fixed build.zig --------- Co-authored-by: mattnite --- build.zig | 4 ++-- deps/microzig | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/build.zig b/build.zig index 86ad216..56ed4e5 100644 --- a/build.zig +++ b/build.zig @@ -18,7 +18,7 @@ pub fn build(b: *std.build.Builder) void { .backing = .{ .board = @field(boards, decl.name) }, .optimize = optimize, }); - exe.install(); + exe.installArtifact(b); } inline for (@typeInfo(chips).Struct.decls) |decl| { @@ -33,6 +33,6 @@ pub fn build(b: *std.build.Builder) void { .backing = .{ .chip = @field(chips, decl.name) }, .optimize = optimize, }); - exe.install(); + exe.installArtifact(b); } } diff --git a/deps/microzig b/deps/microzig index 23482a6..ae6e619 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7 +Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763 From d96ce9cc50db93a416185d0eeff102322659227c Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 23 Apr 2023 11:56:24 -0700 Subject: [PATCH 13/20] update microzig (#14) --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index ae6e619..dd491cc 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763 +Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab From 4e2cdae13e35438ff72dcdc85c8bb4b51b46bd13 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 25 Apr 2023 23:41:16 -0700 Subject: [PATCH 14/20] update microzig (#15) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index dd491cc..658648b 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab +Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1 From cc882413bbc170789f71b634fa852f3aca0e935d Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 26 Apr 2023 00:29:15 -0700 Subject: [PATCH 15/20] update microzig (#17) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 658648b..b5edf6d 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1 +Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d From 5f9de91f22a0b1f9bec9bef7ed994c7c67104c57 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 3 May 2023 21:41:03 -0700 Subject: [PATCH 16/20] update microzig (#18) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index b5edf6d..4e62e99 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d +Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be From 83443705dfe789b4996342f0af7e4e01bb9d1f73 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 15 May 2023 21:48:23 -0700 Subject: [PATCH 17/20] update microzig (#19) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 4e62e99..9588941 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be +Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5 From e539cce4e54b27871d6ea69deaf1af23f594aa31 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 27 Jun 2023 20:32:35 -0700 Subject: [PATCH 18/20] update microzig (#20) Co-authored-by: mattnite --- deps/microzig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 9588941..9392fe0 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5 +Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791 From 7b528f927119682e50d2501e2178169f6bde64f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 22 Sep 2023 09:03:54 +0200 Subject: [PATCH 19/20] Update to MicroZig Gen 2 build interface. (#21) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- .gitmodules | 3 - build.zig | 120 +- deps/microzig | 1 - src/boards.zig | 13 - src/chips.zig | 26 - src/chips/GD32VF103.zig | 12849 -------------------------------------- 6 files changed, 88 insertions(+), 12924 deletions(-) delete mode 160000 deps/microzig delete mode 100644 src/boards.zig delete mode 100644 src/chips.zig delete mode 100644 src/chips/GD32VF103.zig diff --git a/.gitmodules b/.gitmodules index 32e895c..e69de29 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +0,0 @@ -[submodule "deps/microzig"] - path = deps/microzig - url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/build.zig b/build.zig index 56ed4e5..61f41a4 100644 --- a/build.zig +++ b/build.zig @@ -1,38 +1,94 @@ const std = @import("std"); -const microzig = @import("deps/microzig/build.zig"); -pub const boards = @import("src/boards.zig"); -pub const chips = @import("src/chips.zig"); +fn path(comptime suffix: []const u8) std.Build.LazyPath { + return .{ + .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix), + }; +} -pub fn build(b: *std.build.Builder) void { - const optimize = b.standardOptimizeOption(.{}); - inline for (@typeInfo(boards).Struct.decls) |decl| { - if (!decl.is_pub) - continue; - - const exe = microzig.addEmbeddedExecutable(b, .{ - .name = @field(boards, decl.name).name ++ ".minimal", - .source_file = .{ - .path = "test/programs/minimal.zig", +const hal = .{ + .source_file = path("/src/hals/GD32VF103.zig"), +}; + +pub const chips = struct { + pub const gd32vf103xb = .{ + .preferred_format = .elf, + .chip = .{ + .name = "GD32VF103", + .cpu = .riscv32_imac, + .memory_regions = &.{ + .{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, + .{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, }, - .backing = .{ .board = @field(boards, decl.name) }, - .optimize = optimize, - }); - exe.installArtifact(b); - } - - inline for (@typeInfo(chips).Struct.decls) |decl| { - if (!decl.is_pub) - continue; - - const exe = microzig.addEmbeddedExecutable(b, .{ - .name = @field(chips, decl.name).name ++ ".minimal", - .source_file = .{ - .path = "test/programs/minimal.zig", + .register_definition = .{ + .json = path("/src/chips/GD32VF103.json"), }, - .backing = .{ .chip = @field(chips, decl.name) }, - .optimize = optimize, - }); - exe.installArtifact(b); - } + }, + .hal = hal, + }; + + pub const gd32vf103x8 = .{ + .preferred_format = .elf, + .chip = .{ + .name = "GD32VF103", + .cpu = .riscv32_imac, + .memory_regions = &.{ + .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, + .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, + }, + .register_definition = .{ + .json = path("/src/chips/GD32VF103.json"), + }, + }, + .hal = hal, + }; +}; + +pub const boards = struct { + pub const sipeed = struct { + pub const longan_nano = .{ + .preferred_format = .elf, + .chip = chips.gd32vf103xb.chip, + .hal = hal, + .board = .{ + .name = "Longan Nano", + .url = "https://longan.sipeed.com/en/", + .source_file = path("/src/boards/longan_nano.zig"), + }, + }; + }; +}; + +pub fn build(b: *std.build.Builder) void { + _ = b; + // const optimize = b.standardOptimizeOption(.{}); + // inline for (@typeInfo(boards).Struct.decls) |decl| { + // if (!decl.is_pub) + // continue; + + // const exe = microzig.addEmbeddedExecutable(b, .{ + // .name = @field(boards, decl.name).name ++ ".minimal", + // .source_file = .{ + // .path = "test/programs/minimal.zig", + // }, + // .backing = .{ .board = @field(boards, decl.name) }, + // .optimize = optimize, + // }); + // exe.installArtifact(b); + // } + + // inline for (@typeInfo(chips).Struct.decls) |decl| { + // if (!decl.is_pub) + // continue; + + // const exe = microzig.addEmbeddedExecutable(b, .{ + // .name = @field(chips, decl.name).name ++ ".minimal", + // .source_file = .{ + // .path = "test/programs/minimal.zig", + // }, + // .backing = .{ .chip = @field(chips, decl.name) }, + // .optimize = optimize, + // }); + // exe.installArtifact(b); + // } } diff --git a/deps/microzig b/deps/microzig deleted file mode 160000 index 9392fe0..0000000 --- a/deps/microzig +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791 diff --git a/src/boards.zig b/src/boards.zig deleted file mode 100644 index 264bfee..0000000 --- a/src/boards.zig +++ /dev/null @@ -1,13 +0,0 @@ -const std = @import("std"); -const micro = @import("../deps/microzig/build.zig"); -const chips = @import("chips.zig"); - -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse "."; -} - -pub const longan_nano = micro.Board{ - .name = "Longan Nano", - .source = .{ .path = root_dir() ++ "/boards/longan_nano.zig" }, - .chip = chips.gd32vf103xb, -}; diff --git a/src/chips.zig b/src/chips.zig deleted file mode 100644 index 2822bd7..0000000 --- a/src/chips.zig +++ /dev/null @@ -1,26 +0,0 @@ -const std = @import("std"); -const micro = @import("../deps/microzig/build.zig"); -const Chip = micro.Chip; -const MemoryRegion = micro.MemoryRegion; - -fn root_dir() []const u8 { - return std.fs.path.dirname(@src().file) orelse unreachable; -} - -pub const gd32vf103xb = Chip.from_standard_paths(root_dir(), .{ - .name = "GD32VF103", - .cpu = micro.cpus.riscv32_imac, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram }, - }, -}); - -pub const gd32vf103x8 = Chip.from_standard_paths(root_dir(), .{ - .name = "GD32VF103", - .cpu = micro.cpus.riscv32_imac, - .memory_regions = &.{ - MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash }, - MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram }, - }, -}); diff --git a/src/chips/GD32VF103.zig b/src/chips/GD32VF103.zig deleted file mode 100644 index 77618b4..0000000 --- a/src/chips/GD32VF103.zig +++ /dev/null @@ -1,12849 +0,0 @@ -const micro = @import("microzig"); -const mmio = micro.mmio; - -pub const devices = struct { - /// GD32VF103 RISC-V Microcontroller based device - pub const GD32VF103 = struct { - pub const properties = struct { - pub const @"cpu.nvic_prio_bits" = "4"; - pub const @"cpu.mpu" = "0"; - pub const @"cpu.fpu" = "0"; - pub const @"cpu.revision" = "r2p1"; - pub const @"cpu.vendor_systick_config" = "0"; - pub const license = - \\ - \\ Copyright 2019 Sipeed Co.,Ltd. - \\ - \\ Licensed under the Apache License, Version 2.0 (the "License"); - \\ you may not use this file except in compliance with the License. - \\ You may obtain a copy of the License at - \\ - \\ http://www.apache.org/licenses/LICENSE-2.0 - \\ - \\ Unless required by applicable law or agreed to in writing, software - \\ distributed under the License is distributed on an "AS IS" BASIS, - \\ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - \\ See the License for the specific language governing permissions and - \\ limitations under the License. - \\ - ; - pub const @"cpu.name" = "CM3"; - pub const @"cpu.endian" = "little"; - }; - - pub const VectorTable = extern struct { - const Handler = micro.interrupt.Handler; - const unhandled = micro.interrupt.unhandled; - - initial_stack_pointer: u32, - Reset: Handler = unhandled, - NMI: Handler = unhandled, - HardFault: Handler = unhandled, - MemManageFault: Handler = unhandled, - BusFault: Handler = unhandled, - UsageFault: Handler = unhandled, - reserved5: [4]u32 = undefined, - SVCall: Handler = unhandled, - DebugMonitor: Handler = unhandled, - reserved11: [1]u32 = undefined, - PendSV: Handler = unhandled, - SysTick: Handler = unhandled, - WWDGT: Handler = unhandled, - reserved15: [20]u32 = undefined, - Tamper: Handler = unhandled, - RTC: Handler = unhandled, - FMC: Handler = unhandled, - RCU: Handler = unhandled, - EXTI_Line0: Handler = unhandled, - EXTI_Line1: Handler = unhandled, - EXTI_Line2: Handler = unhandled, - EXTI_Line3: Handler = unhandled, - EXTI_Line4: Handler = unhandled, - DMA0_Channel0: Handler = unhandled, - DMA0_Channel1: Handler = unhandled, - DMA0_Channel2: Handler = unhandled, - DMA0_Channel3: Handler = unhandled, - DMA0_Channel4: Handler = unhandled, - DMA0_Channel5: Handler = unhandled, - DMA0_Channel6: Handler = unhandled, - ADC0_1: Handler = unhandled, - CAN0_TX: Handler = unhandled, - CAN0_RX0: Handler = unhandled, - CAN0_RX1: Handler = unhandled, - CAN0_EWMC: Handler = unhandled, - EXTI_line9_5: Handler = unhandled, - TIMER0_BRK: Handler = unhandled, - TIMER0_UP: Handler = unhandled, - TIMER0_TRG_CMT: Handler = unhandled, - TIMER0_Channel: Handler = unhandled, - TIMER1: Handler = unhandled, - TIMER2: Handler = unhandled, - TIMER3: Handler = unhandled, - I2C0_EV: Handler = unhandled, - I2C0_ER: Handler = unhandled, - I2C1_EV: Handler = unhandled, - I2C1_ER: Handler = unhandled, - SPI0: Handler = unhandled, - SPI1: Handler = unhandled, - USART0: Handler = unhandled, - USART1: Handler = unhandled, - USART2: Handler = unhandled, - EXTI_line15_10: Handler = unhandled, - RTC_Alarm: Handler = unhandled, - USBFS_WKUP: Handler = unhandled, - reserved76: [7]u32 = undefined, - TIMER4: Handler = unhandled, - SPI2: Handler = unhandled, - UART3: Handler = unhandled, - UART4: Handler = unhandled, - TIMER5: Handler = unhandled, - TIMER6: Handler = unhandled, - DMA1_Channel0: Handler = unhandled, - DMA1_Channel1: Handler = unhandled, - DMA1_Channel2: Handler = unhandled, - DMA1_Channel3: Handler = unhandled, - DMA1_Channel4: Handler = unhandled, - reserved94: [2]u32 = undefined, - CAN1_TX: Handler = unhandled, - CAN1_RX0: Handler = unhandled, - CAN1_RX1: Handler = unhandled, - CAN1_EWMC: Handler = unhandled, - USBFS: Handler = unhandled, - }; - - pub const peripherals = struct { - /// General-purpose-timers - pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000000); - /// General-purpose-timers - pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000400); - /// General-purpose-timers - pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000800); - /// General-purpose-timers - pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000c00); - /// Basic-timers - pub const TIMER5 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001000); - /// Basic-timers - pub const TIMER6 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001400); - /// Real-time clock - pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x40002800); - /// Window watchdog timer - pub const WWDGT = @intToPtr(*volatile types.peripherals.WWDGT, 0x40002c00); - /// free watchdog timer - pub const FWDGT = @intToPtr(*volatile types.peripherals.FWDGT, 0x40003000); - /// Serial peripheral interface - pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003800); - /// Serial peripheral interface - pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003c00); - /// Universal synchronous asynchronous receiver transmitter - pub const USART1 = @intToPtr(*volatile types.peripherals.USART0, 0x40004400); - /// Universal synchronous asynchronous receiver transmitter - pub const USART2 = @intToPtr(*volatile types.peripherals.USART0, 0x40004800); - /// Universal asynchronous receiver transmitter - pub const UART3 = @intToPtr(*volatile types.peripherals.UART3, 0x40004c00); - /// Universal asynchronous receiver transmitter - pub const UART4 = @intToPtr(*volatile types.peripherals.UART3, 0x40005000); - /// Inter integrated circuit - pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005400); - /// Inter integrated circuit - pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005800); - /// Controller area network - pub const CAN0 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006400); - /// Controller area network - pub const CAN1 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006800); - /// Backup registers - pub const BKP = @intToPtr(*volatile types.peripherals.BKP, 0x40006c00); - /// Power management unit - pub const PMU = @intToPtr(*volatile types.peripherals.PMU, 0x40007000); - /// Digital-to-analog converter - pub const DAC = @intToPtr(*volatile types.peripherals.DAC, 0x40007400); - /// Alternate-function I/Os - pub const AFIO = @intToPtr(*volatile types.peripherals.AFIO, 0x40010000); - /// External interrupt/event controller - pub const EXTI = @intToPtr(*volatile types.peripherals.EXTI, 0x40010400); - /// General-purpose I/Os - pub const GPIOA = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010800); - /// General-purpose I/Os - pub const GPIOB = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010c00); - /// General-purpose I/Os - pub const GPIOC = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011000); - /// General-purpose I/Os - pub const GPIOD = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011400); - /// General-purpose I/Os - pub const GPIOE = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011800); - /// Analog to digital converter - pub const ADC0 = @intToPtr(*volatile types.peripherals.ADC0, 0x40012400); - /// Analog to digital converter - pub const ADC1 = @intToPtr(*volatile types.peripherals.ADC1, 0x40012800); - /// Advanced-timers - pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40012c00); - /// Serial peripheral interface - pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40013000); - /// Universal synchronous asynchronous receiver transmitter - pub const USART0 = @intToPtr(*volatile types.peripherals.USART0, 0x40013800); - /// DMA controller - pub const DMA0 = @intToPtr(*volatile types.peripherals.DMA0, 0x40020000); - /// Direct memory access controller - pub const DMA1 = @intToPtr(*volatile types.peripherals.DMA1, 0x40020000); - /// Reset and clock unit - pub const RCU = @intToPtr(*volatile types.peripherals.RCU, 0x40021000); - /// FMC - pub const FMC = @intToPtr(*volatile types.peripherals.FMC, 0x40022000); - /// cyclic redundancy check calculation unit - pub const CRC = @intToPtr(*volatile types.peripherals.CRC, 0x40023000); - /// USB full speed global registers - pub const USBFS_GLOBAL = @intToPtr(*volatile types.peripherals.USBFS_GLOBAL, 0x50000000); - /// USB on the go full speed host - pub const USBFS_HOST = @intToPtr(*volatile types.peripherals.USBFS_HOST, 0x50000400); - /// USB on the go full speed device - pub const USBFS_DEVICE = @intToPtr(*volatile types.peripherals.USBFS_DEVICE, 0x50000800); - /// USB on the go full speed - pub const USBFS_PWRCLK = @intToPtr(*volatile types.peripherals.USBFS_PWRCLK, 0x50000e00); - /// External memory controller - pub const EXMC = @intToPtr(*volatile types.peripherals.EXMC, 0xa0000000); - /// Enhanced Core Local Interrupt Controller - pub const ECLIC = @intToPtr(*volatile types.peripherals.ECLIC, 0xd2000000); - /// System Tick Timer - pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010); - /// Debug support - pub const DBG = @intToPtr(*volatile types.peripherals.DBG, 0xe0042000); - }; - }; -}; - -pub const types = struct { - pub const peripherals = struct { - /// System Control Space - pub const SCS = struct { - /// System Tick Timer - pub const SysTick = extern struct { - /// SysTick Control and Status Register - CTRL: mmio.Mmio(packed struct(u32) { - ENABLE: u1, - TICKINT: u1, - CLKSOURCE: u1, - reserved16: u13, - COUNTFLAG: u1, - padding: u15, - }), - /// SysTick Reload Value Register - LOAD: mmio.Mmio(packed struct(u32) { - RELOAD: u24, - padding: u8, - }), - /// SysTick Current Value Register - VAL: mmio.Mmio(packed struct(u32) { - CURRENT: u24, - padding: u8, - }), - /// SysTick Calibration Register - CALIB: mmio.Mmio(packed struct(u32) { - TENMS: u24, - reserved30: u6, - SKEW: u1, - NOREF: u1, - }), - }; - }; - - /// Analog to digital converter - pub const ADC0 = extern struct { - /// status register - STAT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog event flag - WDE: u1, - /// End of group conversion flag - EOC: u1, - /// End of inserted group conversion flag - EOIC: u1, - /// Start flag of inserted channel group - STIC: u1, - /// Start flag of regular channel group - STRC: u1, - padding: u27, - }), - /// control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Analog watchdog channel select - WDCHSEL: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Interrupt enable for WDE - WDEIE: u1, - /// Interrupt enable for EOIC - EOICIE: u1, - /// Scan mode - SM: u1, - /// When in scan mode, analog watchdog is effective on a single channel - WDSC: u1, - /// Inserted channel group convert automatically - ICA: u1, - /// Discontinuous mode on regular channels - DISRC: u1, - /// Discontinuous mode on inserted channels - DISIC: u1, - /// Number of conversions in discontinuous mode - DISNUM: u3, - /// sync mode selection - SYNCM: u4, - reserved22: u2, - /// Inserted channel analog watchdog enable - IWDEN: u1, - /// Regular channel analog watchdog enable - RWDEN: u1, - padding: u8, - }), - /// control register 1 - CTL1: mmio.Mmio(packed struct(u32) { - /// ADC on - ADCON: u1, - /// Continuous mode - CTN: u1, - /// ADC calibration - CLB: u1, - /// Reset calibration - RSTCLB: u1, - reserved8: u4, - /// DMA request enable - DMA: u1, - reserved11: u2, - /// Data alignment - DAL: u1, - /// External trigger select for inserted channel - ETSIC: u3, - /// External trigger select for inserted channel - ETEIC: u1, - reserved17: u1, - /// External trigger select for regular channel - ETSRC: u3, - /// External trigger enable for regular channel - ETERC: u1, - /// Start on inserted channel - SWICST: u1, - /// Start on regular channel - SWRCST: u1, - /// Channel 16 and 17 enable of ADC0 - TSVREN: u1, - padding: u8, - }), - /// Sample time register 0 - SAMPT0: mmio.Mmio(packed struct(u32) { - /// Channel 10 sample time selection - SPT10: u3, - /// Channel 11 sample time selection - SPT11: u3, - /// Channel 12 sample time selection - SPT12: u3, - /// Channel 13 sample time selection - SPT13: u3, - /// Channel 14 sample time selection - SPT14: u3, - /// Channel 15 sample time selection - SPT15: u3, - /// Channel 16 sample time selection - SPT16: u3, - /// Channel 17 sample time selection - SPT17: u3, - padding: u8, - }), - /// Sample time register 1 - SAMPT1: mmio.Mmio(packed struct(u32) { - /// Channel 0 sample time selection - SPT0: u3, - /// Channel 1 sample time selection - SPT1: u3, - /// Channel 2 sample time selection - SPT2: u3, - /// Channel 3 sample time selection - SPT3: u3, - /// Channel 4 sample time selection - SPT4: u3, - /// Channel 5 sample time selection - SPT5: u3, - /// Channel 6 sample time selection - SPT6: u3, - /// Channel 7 sample time selection - SPT7: u3, - /// Channel 8 sample time selection - SPT8: u3, - /// Channel 9 sample time selection - SPT9: u3, - padding: u2, - }), - /// Inserted channel data offset register 0 - IOFF0: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 0 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 1 - IOFF1: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 1 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 2 - IOFF2: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 2 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 3 - IOFF3: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 3 - IOFF: u12, - padding: u20, - }), - /// watchdog higher threshold register - WDHT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog higher threshold - WDHT: u12, - padding: u20, - }), - /// watchdog lower threshold register - WDLT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - WDLT: u12, - padding: u20, - }), - /// regular sequence register 0 - RSQ0: mmio.Mmio(packed struct(u32) { - /// 13th conversion in regular sequence - RSQ12: u5, - /// 14th conversion in regular sequence - RSQ13: u5, - /// 15th conversion in regular sequence - RSQ14: u5, - /// 16th conversion in regular sequence - RSQ15: u5, - /// Regular channel group length - RL: u4, - padding: u8, - }), - /// regular sequence register 1 - RSQ1: mmio.Mmio(packed struct(u32) { - /// 7th conversion in regular sequence - RSQ6: u5, - /// 8th conversion in regular sequence - RSQ7: u5, - /// 9th conversion in regular sequence - RSQ8: u5, - /// 10th conversion in regular sequence - RSQ9: u5, - /// 11th conversion in regular sequence - RSQ10: u5, - /// 12th conversion in regular sequence - RSQ11: u5, - padding: u2, - }), - /// regular sequence register 2 - RSQ2: mmio.Mmio(packed struct(u32) { - /// 1st conversion in regular sequence - RSQ0: u5, - /// 2nd conversion in regular sequence - RSQ1: u5, - /// 3rd conversion in regular sequence - RSQ2: u5, - /// 4th conversion in regular sequence - RSQ3: u5, - /// 5th conversion in regular sequence - RSQ4: u5, - /// 6th conversion in regular sequence - RSQ5: u5, - padding: u2, - }), - /// Inserted sequence register - ISQ: mmio.Mmio(packed struct(u32) { - /// 1st conversion in inserted sequence - ISQ0: u5, - /// 2nd conversion in inserted sequence - ISQ1: u5, - /// 3rd conversion in inserted sequence - ISQ2: u5, - /// 4th conversion in inserted sequence - ISQ3: u5, - /// Inserted channel group length - IL: u2, - padding: u10, - }), - /// Inserted data register 0 - IDATA0: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 1 - IDATA1: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 2 - IDATA2: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 3 - IDATA3: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// regular data register - RDATA: mmio.Mmio(packed struct(u32) { - /// Regular channel data - RDATA: u16, - /// ADC regular channel data - ADC1RDTR: u16, - }), - reserved128: [48]u8, - /// Oversample control register - OVSAMPCTL: mmio.Mmio(packed struct(u32) { - /// Oversampler Enable - OVSEN: u1, - reserved2: u1, - /// Oversampling ratio - OVSR: u3, - /// Oversampling shift - OVSS: u4, - /// Triggered Oversampling - TOVS: u1, - reserved12: u2, - /// ADC resolution - DRES: u2, - padding: u18, - }), - }; - - /// Analog to digital converter - pub const ADC1 = extern struct { - /// status register - STAT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog event flag - WDE: u1, - /// End of group conversion flag - EOC: u1, - /// End of inserted group conversion flag - EOIC: u1, - /// Start flag of inserted channel group - STIC: u1, - /// Start flag of regular channel group - STRC: u1, - padding: u27, - }), - /// control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Analog watchdog channel select - WDCHSEL: u5, - /// Interrupt enable for EOC - EOCIE: u1, - /// Interrupt enable for WDE - WDEIE: u1, - /// Interrupt enable for EOIC - EOICIE: u1, - /// Scan mode - SM: u1, - /// When in scan mode, analog watchdog is effective on a single channel - WDSC: u1, - /// Inserted channel group convert automatically - ICA: u1, - /// Discontinuous mode on regular channels - DISRC: u1, - /// Discontinuous mode on inserted channels - DISIC: u1, - /// Number of conversions in discontinuous mode - DISNUM: u3, - reserved22: u6, - /// Inserted channel analog watchdog enable - IWDEN: u1, - /// Regular channel analog watchdog enable - RWDEN: u1, - padding: u8, - }), - /// control register 1 - CTL1: mmio.Mmio(packed struct(u32) { - /// ADC on - ADCON: u1, - /// Continuous mode - CTN: u1, - /// ADC calibration - CLB: u1, - /// Reset calibration - RSTCLB: u1, - reserved8: u4, - /// DMA request enable - DMA: u1, - reserved11: u2, - /// Data alignment - DAL: u1, - /// External trigger select for inserted channel - ETSIC: u3, - /// External trigger enable for inserted channel - ETEIC: u1, - reserved17: u1, - /// External trigger select for regular channel - ETSRC: u3, - /// External trigger enable for regular channel - ETERC: u1, - /// Start on inserted channel - SWICST: u1, - /// Start on regular channel - SWRCST: u1, - padding: u9, - }), - /// Sample time register 0 - SAMPT0: mmio.Mmio(packed struct(u32) { - /// Channel 10 sample time selection - SPT10: u3, - /// Channel 11 sample time selection - SPT11: u3, - /// Channel 12 sample time selection - SPT12: u3, - /// Channel 13 sample time selection - SPT13: u3, - /// Channel 14 sample time selection - SPT14: u3, - /// Channel 15 sample time selection - SPT15: u3, - /// Channel 16 sample time selection - SPT16: u3, - /// Channel 17 sample time selection - SPT17: u3, - padding: u8, - }), - /// Sample time register 1 - SAMPT1: mmio.Mmio(packed struct(u32) { - /// Channel 0 sample time selection - SPT0: u3, - /// Channel 1 sample time selection - SPT1: u3, - /// Channel 2 sample time selection - SPT2: u3, - /// Channel 3 sample time selection - SPT3: u3, - /// Channel 4 sample time selection - SPT4: u3, - /// Channel 5 sample time selection - SPT5: u3, - /// Channel 6 sample time selection - SPT6: u3, - /// Channel 7 sample time selection - SPT7: u3, - /// Channel 8 sample time selection - SPT8: u3, - /// Channel 9 sample time selection - SPT9: u3, - padding: u2, - }), - /// Inserted channel data offset register 0 - IOFF0: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 0 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 1 - IOFF1: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 1 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 2 - IOFF2: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 2 - IOFF: u12, - padding: u20, - }), - /// Inserted channel data offset register 3 - IOFF3: mmio.Mmio(packed struct(u32) { - /// Data offset for inserted channel 3 - IOFF: u12, - padding: u20, - }), - /// watchdog higher threshold register - WDHT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog higher threshold - WDHT: u12, - padding: u20, - }), - /// watchdog lower threshold register - WDLT: mmio.Mmio(packed struct(u32) { - /// Analog watchdog lower threshold - WDLT: u12, - padding: u20, - }), - /// regular sequence register 0 - RSQ0: mmio.Mmio(packed struct(u32) { - /// 13th conversion in regular sequence - RSQ12: u5, - /// 14th conversion in regular sequence - RSQ13: u5, - /// 15th conversion in regular sequence - RSQ14: u5, - /// 16th conversion in regular sequence - RSQ15: u5, - /// Regular channel group length - RL: u4, - padding: u8, - }), - /// regular sequence register 1 - RSQ1: mmio.Mmio(packed struct(u32) { - /// 7th conversion in regular sequence - RSQ6: u5, - /// 8th conversion in regular sequence - RSQ7: u5, - /// 9th conversion in regular sequence - RSQ8: u5, - /// 10th conversion in regular sequence - RSQ9: u5, - /// 11th conversion in regular sequence - RSQ10: u5, - /// 12th conversion in regular sequence - RSQ11: u5, - padding: u2, - }), - /// regular sequence register 2 - RSQ2: mmio.Mmio(packed struct(u32) { - /// 1st conversion in regular sequence - RSQ0: u5, - /// 2nd conversion in regular sequence - RSQ1: u5, - /// 3rd conversion in regular sequence - RSQ2: u5, - /// 4th conversion in regular sequence - RSQ3: u5, - /// 5th conversion in regular sequence - RSQ4: u5, - /// 6th conversion in regular sequence - RSQ5: u5, - padding: u2, - }), - /// Inserted sequence register - ISQ: mmio.Mmio(packed struct(u32) { - /// 1st conversion in inserted sequence - ISQ0: u5, - /// 2nd conversion in inserted sequence - ISQ1: u5, - /// 3rd conversion in inserted sequence - ISQ2: u5, - /// 4th conversion in inserted sequence - ISQ3: u5, - /// Inserted channel group length - IL: u2, - padding: u10, - }), - /// Inserted data register 0 - IDATA0: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 1 - IDATA1: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 2 - IDATA2: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// Inserted data register 3 - IDATA3: mmio.Mmio(packed struct(u32) { - /// Inserted number n conversion data - IDATAn: u16, - padding: u16, - }), - /// regular data register - RDATA: mmio.Mmio(packed struct(u32) { - /// Regular channel data - RDATA: u16, - padding: u16, - }), - }; - - /// Alternate-function I/Os - pub const AFIO = extern struct { - /// Event control register - EC: mmio.Mmio(packed struct(u32) { - /// Event output pin selection - PIN: u4, - /// Event output port selection - PORT: u3, - /// Event output enable - EOE: u1, - padding: u24, - }), - /// AFIO port configuration register 0 - PCF0: mmio.Mmio(packed struct(u32) { - /// SPI0 remapping - SPI0_REMAP: u1, - /// I2C0 remapping - I2C0_REMAP: u1, - /// USART0 remapping - USART0_REMAP: u1, - /// USART1 remapping - USART1_REMAP: u1, - /// USART2 remapping - USART2_REMAP: u2, - /// TIMER0 remapping - TIMER0_REMAP: u2, - /// TIMER1 remapping - TIMER1_REMAP: u2, - /// TIMER2 remapping - TIMER2_REMAP: u2, - /// TIMER3 remapping - TIMER3_REMAP: u1, - /// CAN0 alternate interface remapping - CAN0_REMAP: u2, - /// Port D0/Port D1 mapping on OSC_IN/OSC_OUT - PD01_REMAP: u1, - /// TIMER4 channel3 internal remapping - TIMER4CH3_IREMAP: u1, - reserved22: u5, - /// CAN1 I/O remapping - CAN1_REMAP: u1, - reserved24: u1, - /// Serial wire JTAG configuration - SWJ_CFG: u3, - reserved28: u1, - /// SPI2/I2S2 remapping - SPI2_REMAP: u1, - /// TIMER1 internal trigger 1 remapping - TIMER1ITI1_REMAP: u1, - padding: u2, - }), - /// EXTI sources selection register 0 - EXTISS0: mmio.Mmio(packed struct(u32) { - /// EXTI 0 sources selection - EXTI0_SS: u4, - /// EXTI 1 sources selection - EXTI1_SS: u4, - /// EXTI 2 sources selection - EXTI2_SS: u4, - /// EXTI 3 sources selection - EXTI3_SS: u4, - padding: u16, - }), - /// EXTI sources selection register 1 - EXTISS1: mmio.Mmio(packed struct(u32) { - /// EXTI 4 sources selection - EXTI4_SS: u4, - /// EXTI 5 sources selection - EXTI5_SS: u4, - /// EXTI 6 sources selection - EXTI6_SS: u4, - /// EXTI 7 sources selection - EXTI7_SS: u4, - padding: u16, - }), - /// EXTI sources selection register 2 - EXTISS2: mmio.Mmio(packed struct(u32) { - /// EXTI 8 sources selection - EXTI8_SS: u4, - /// EXTI 9 sources selection - EXTI9_SS: u4, - /// EXTI 10 sources selection - EXTI10_SS: u4, - /// EXTI 11 sources selection - EXTI11_SS: u4, - padding: u16, - }), - /// EXTI sources selection register 3 - EXTISS3: mmio.Mmio(packed struct(u32) { - /// EXTI 12 sources selection - EXTI12_SS: u4, - /// EXTI 13 sources selection - EXTI13_SS: u4, - /// EXTI 14 sources selection - EXTI14_SS: u4, - /// EXTI 15 sources selection - EXTI15_SS: u4, - padding: u16, - }), - reserved28: [4]u8, - /// AFIO port configuration register 1 - PCF1: mmio.Mmio(packed struct(u32) { - reserved10: u10, - /// EXMC_NADV connect/disconnect - EXMC_NADV: u1, - padding: u21, - }), - }; - - /// Backup registers - pub const BKP = extern struct { - reserved4: [4]u8, - /// Backup data register 0 - DATA0: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved8: [2]u8, - /// Backup data register 1 - DATA1: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved12: [2]u8, - /// Backup data register 2 - DATA2: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved16: [2]u8, - /// Backup data register 3 - DATA3: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved20: [2]u8, - /// Backup data register 4 - DATA4: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved24: [2]u8, - /// Backup data register 5 - DATA5: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved28: [2]u8, - /// Backup data register 6 - DATA6: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved32: [2]u8, - /// Backup data register 7 - DATA7: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved36: [2]u8, - /// Backup data register 8 - DATA8: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved40: [2]u8, - /// Backup data register 9 - DATA9: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved44: [2]u8, - /// RTC signal output control register - OCTL: mmio.Mmio(packed struct(u16) { - /// RTC clock calibration value - RCCV: u7, - /// RTC clock calibration output enable - COEN: u1, - /// RTC alarm or second signal output enable - ASOEN: u1, - /// RTC output selection - ROSEL: u1, - padding: u6, - }), - reserved48: [2]u8, - /// Tamper pin control register - TPCTL: mmio.Mmio(packed struct(u16) { - /// TAMPER detection enable - TPEN: u1, - /// TAMPER pin active level - TPAL: u1, - padding: u14, - }), - reserved52: [2]u8, - /// Tamper control and status register - TPCS: mmio.Mmio(packed struct(u16) { - /// Tamper event reset - TER: u1, - /// Tamper interrupt reset - TIR: u1, - /// Tamper interrupt enable - TPIE: u1, - reserved8: u5, - /// Tamper event flag - TEF: u1, - /// Tamper interrupt flag - TIF: u1, - padding: u6, - }), - reserved64: [10]u8, - /// Backup data register 10 - DATA10: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved68: [2]u8, - /// Backup data register 11 - DATA11: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved72: [2]u8, - /// Backup data register 12 - DATA12: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved76: [2]u8, - /// Backup data register 13 - DATA13: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved80: [2]u8, - /// Backup data register 14 - DATA14: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved84: [2]u8, - /// Backup data register 15 - DATA15: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved88: [2]u8, - /// Backup data register 16 - DATA16: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved92: [2]u8, - /// Backup data register 17 - DATA17: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved96: [2]u8, - /// Backup data register 18 - DATA18: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved100: [2]u8, - /// Backup data register 19 - DATA19: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved104: [2]u8, - /// Backup data register 20 - DATA20: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved108: [2]u8, - /// Backup data register 21 - DATA21: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved112: [2]u8, - /// Backup data register 22 - DATA22: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved116: [2]u8, - /// Backup data register 23 - DATA23: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved120: [2]u8, - /// Backup data register 24 - DATA24: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved124: [2]u8, - /// Backup data register 25 - DATA25: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved128: [2]u8, - /// Backup data register 26 - DATA26: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved132: [2]u8, - /// Backup data register 27 - DATA27: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved136: [2]u8, - /// Backup data register 28 - DATA28: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved140: [2]u8, - /// Backup data register 29 - DATA29: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved144: [2]u8, - /// Backup data register 30 - DATA30: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved148: [2]u8, - /// Backup data register 31 - DATA31: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved152: [2]u8, - /// Backup data register 32 - DATA32: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved156: [2]u8, - /// Backup data register 33 - DATA33: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved160: [2]u8, - /// Backup data register 34 - DATA34: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved164: [2]u8, - /// Backup data register 35 - DATA35: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved168: [2]u8, - /// Backup data register 36 - DATA36: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved172: [2]u8, - /// Backup data register 37 - DATA37: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved176: [2]u8, - /// Backup data register 38 - DATA38: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved180: [2]u8, - /// Backup data register 39 - DATA39: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved184: [2]u8, - /// Backup data register 40 - DATA40: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - reserved188: [2]u8, - /// Backup data register 41 - DATA41: mmio.Mmio(packed struct(u16) { - /// Backup data - DATA: u16, - }), - }; - - /// Controller area network - pub const CAN0 = extern struct { - /// Control register - CTL: mmio.Mmio(packed struct(u32) { - /// Initial working mode - IWMOD: u1, - /// Sleep working mode - SLPWMOD: u1, - /// Transmit FIFO order - TFO: u1, - /// Receive FIFO overwrite disable - RFOD: u1, - /// Automatic retransmission disable - ARD: u1, - /// Automatic wakeup - AWU: u1, - /// Automatic bus-off recovery - ABOR: u1, - /// Time-triggered communication - TTC: u1, - reserved15: u7, - /// Software reset - SWRST: u1, - /// Debug freeze - DFZ: u1, - padding: u15, - }), - /// Status register - STAT: mmio.Mmio(packed struct(u32) { - /// Initial working state - IWS: u1, - /// Sleep working state - SLPWS: u1, - /// Error interrupt flag - ERRIF: u1, - /// Status change interrupt flag of wakeup from sleep working mode - WUIF: u1, - /// Status change interrupt flag of sleep working mode entering - SLPIF: u1, - reserved8: u3, - /// Transmitting state - TS: u1, - /// Receiving state - RS: u1, - /// Last sample value of RX pin - LASTRX: u1, - /// RX level - RXL: u1, - padding: u20, - }), - /// Transmit status register - TSTAT: mmio.Mmio(packed struct(u32) { - /// Mailbox 0 transmit finished - MTF0: u1, - /// Mailbox 0 transmit finished and no error - MTFNERR0: u1, - /// Mailbox 0 arbitration lost - MAL0: u1, - /// Mailbox 0 transmit error - MTE0: u1, - reserved7: u3, - /// Mailbox 0 stop transmitting - MST0: u1, - /// Mailbox 1 transmit finished - MTF1: u1, - /// Mailbox 1 transmit finished and no error - MTFNERR1: u1, - /// Mailbox 1 arbitration lost - MAL1: u1, - /// Mailbox 1 transmit error - MTE1: u1, - reserved15: u3, - /// Mailbox 1 stop transmitting - MST1: u1, - /// Mailbox 2 transmit finished - MTF2: u1, - /// Mailbox 2 transmit finished and no error - MTFNERR2: u1, - /// Mailbox 2 arbitration lost - MAL2: u1, - /// Mailbox 2 transmit error - MTE2: u1, - reserved23: u3, - /// Mailbox 2 stop transmitting - MST2: u1, - /// number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty - NUM: u2, - /// Transmit mailbox 0 empty - TME0: u1, - /// Transmit mailbox 1 empty - TME1: u1, - /// Transmit mailbox 2 empty - TME2: u1, - /// Transmit mailbox 0 last sending in transmit FIFO - TMLS0: u1, - /// Transmit mailbox 1 last sending in transmit FIFO - TMLS1: u1, - /// Transmit mailbox 2 last sending in transmit FIFO - TMLS2: u1, - }), - /// Receive message FIFO0 register - RFIFO0: mmio.Mmio(packed struct(u32) { - /// Receive FIFO0 length - RFL0: u2, - reserved3: u1, - /// Receive FIFO0 full - RFF0: u1, - /// Receive FIFO0 overfull - RFO0: u1, - /// Receive FIFO0 dequeue - RFD0: u1, - padding: u26, - }), - /// Receive message FIFO1 register - RFIFO1: mmio.Mmio(packed struct(u32) { - /// Receive FIFO1 length - RFL1: u2, - reserved3: u1, - /// Receive FIFO1 full - RFF1: u1, - /// Receive FIFO1 overfull - RFO1: u1, - /// Receive FIFO1 dequeue - RFD1: u1, - padding: u26, - }), - /// Interrupt enable register - INTEN: mmio.Mmio(packed struct(u32) { - /// Transmit mailbox empty interrupt enable - TMEIE: u1, - /// Receive FIFO0 not empty interrupt enable - RFNEIE0: u1, - /// Receive FIFO0 full interrupt enable - RFFIE0: u1, - /// Receive FIFO0 overfull interrupt enable - RFOIE0: u1, - /// Receive FIFO1 not empty interrupt enable - RFNEIE1: u1, - /// Receive FIFO1 full interrupt enable - RFFIE1: u1, - /// Receive FIFO1 overfull interrupt enable - RFOIE1: u1, - reserved8: u1, - /// Warning error interrupt enable - WERRIE: u1, - /// Passive error interrupt enable - PERRIE: u1, - /// Bus-off interrupt enable - BOIE: u1, - /// Error number interrupt enable - ERRNIE: u1, - reserved15: u3, - /// Error interrupt enable - ERRIE: u1, - /// Wakeup interrupt enable - WIE: u1, - /// Sleep working interrupt enable - SLPWIE: u1, - padding: u14, - }), - /// Error register - ERR: mmio.Mmio(packed struct(u32) { - /// Warning error - WERR: u1, - /// Passive error - PERR: u1, - /// Bus-off error - BOERR: u1, - reserved4: u1, - /// Error number - ERRN: u3, - reserved16: u9, - /// Transmit Error Count defined by the CAN standard - TECNT: u8, - /// Receive Error Count defined by the CAN standard - RECNT: u8, - }), - /// Bit timing register - BT: mmio.Mmio(packed struct(u32) { - /// Baud rate prescaler - BAUDPSC: u10, - reserved16: u6, - /// Bit segment 1 - BS1: u4, - /// Bit segment 2 - BS2: u3, - reserved24: u1, - /// Resynchronization jump width - SJW: u2, - reserved30: u4, - /// Loopback communication mode - LCMOD: u1, - /// Silent communication mode - SCMOD: u1, - }), - reserved384: [352]u8, - /// Transmit mailbox identifier register 0 - TMI0: mmio.Mmio(packed struct(u32) { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), - /// Transmit mailbox property register 0 - TMP0: mmio.Mmio(packed struct(u32) { - /// Data length code - DLENC: u4, - reserved8: u4, - /// Time stamp enable - TSEN: u1, - reserved16: u7, - /// Time stamp - TS: u16, - }), - /// Transmit mailbox data0 register - TMDATA00: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), - /// Transmit mailbox data1 register - TMDATA10: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), - /// Transmit mailbox identifier register 1 - TMI1: mmio.Mmio(packed struct(u32) { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), - /// Transmit mailbox property register 1 - TMP1: mmio.Mmio(packed struct(u32) { - /// Data length code - DLENC: u4, - reserved8: u4, - /// Time stamp enable - TSEN: u1, - reserved16: u7, - /// Time stamp - TS: u16, - }), - /// Transmit mailbox data0 register - TMDATA01: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), - /// Transmit mailbox data1 register - TMDATA11: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), - /// Transmit mailbox identifier register 2 - TMI2: mmio.Mmio(packed struct(u32) { - /// Transmit enable - TEN: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), - /// Transmit mailbox property register 2 - TMP2: mmio.Mmio(packed struct(u32) { - /// Data length code - DLENC: u4, - reserved8: u4, - /// Time stamp enable - TSEN: u1, - reserved16: u7, - /// Time stamp - TS: u16, - }), - /// Transmit mailbox data0 register - TMDATA02: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), - /// Transmit mailbox data1 register - TMDATA12: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), - /// Receive FIFO mailbox identifier register - RFIFOMI0: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), - /// Receive FIFO0 mailbox property register - RFIFOMP0: mmio.Mmio(packed struct(u32) { - /// Data length code - DLENC: u4, - reserved8: u4, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), - /// Receive FIFO0 mailbox data0 register - RFIFOMDATA00: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), - /// Receive FIFO0 mailbox data1 register - RFIFOMDATA10: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), - /// Receive FIFO1 mailbox identifier register - RFIFOMI1: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Frame type - FT: u1, - /// Frame format - FF: u1, - /// The frame identifier - EFID: u18, - /// The frame identifier - SFID_EFID: u11, - }), - /// Receive FIFO1 mailbox property register - RFIFOMP1: mmio.Mmio(packed struct(u32) { - /// Data length code - DLENC: u4, - reserved8: u4, - /// Filtering index - FI: u8, - /// Time stamp - TS: u16, - }), - /// Receive FIFO1 mailbox data0 register - RFIFOMDATA01: mmio.Mmio(packed struct(u32) { - /// Data byte 0 - DB0: u8, - /// Data byte 1 - DB1: u8, - /// Data byte 2 - DB2: u8, - /// Data byte 3 - DB3: u8, - }), - /// Receive FIFO1 mailbox data1 register - RFIFOMDATA11: mmio.Mmio(packed struct(u32) { - /// Data byte 4 - DB4: u8, - /// Data byte 5 - DB5: u8, - /// Data byte 6 - DB6: u8, - /// Data byte 7 - DB7: u8, - }), - reserved512: [48]u8, - /// Filter control register - FCTL: mmio.Mmio(packed struct(u32) { - /// Filter lock disable - FLD: u1, - reserved8: u7, - /// Header bank of CAN1 filter - HBC1F: u6, - padding: u18, - }), - /// Filter mode configuration register - FMCFG: mmio.Mmio(packed struct(u32) { - /// Filter mode - FMOD0: u1, - /// Filter mode - FMOD1: u1, - /// Filter mode - FMOD2: u1, - /// Filter mode - FMOD3: u1, - /// Filter mode - FMOD4: u1, - /// Filter mode - FMOD5: u1, - /// Filter mode - FMOD6: u1, - /// Filter mode - FMOD7: u1, - /// Filter mode - FMOD8: u1, - /// Filter mode - FMOD9: u1, - /// Filter mode - FMOD10: u1, - /// Filter mode - FMOD11: u1, - /// Filter mode - FMOD12: u1, - /// Filter mode - FMOD13: u1, - /// Filter mode - FMOD14: u1, - /// Filter mode - FMOD15: u1, - /// Filter mode - FMOD16: u1, - /// Filter mode - FMOD17: u1, - /// Filter mode - FMOD18: u1, - /// Filter mode - FMOD19: u1, - /// Filter mode - FMOD20: u1, - /// Filter mode - FMOD21: u1, - /// Filter mode - FMOD22: u1, - /// Filter mode - FMOD23: u1, - /// Filter mode - FMOD24: u1, - /// Filter mode - FMOD25: u1, - /// Filter mode - FMOD26: u1, - /// Filter mode - FMOD27: u1, - padding: u4, - }), - reserved524: [4]u8, - /// Filter scale configuration register - FSCFG: mmio.Mmio(packed struct(u32) { - /// Filter scale configuration - FS0: u1, - /// Filter scale configuration - FS1: u1, - /// Filter scale configuration - FS2: u1, - /// Filter scale configuration - FS3: u1, - /// Filter scale configuration - FS4: u1, - /// Filter scale configuration - FS5: u1, - /// Filter scale configuration - FS6: u1, - /// Filter scale configuration - FS7: u1, - /// Filter scale configuration - FS8: u1, - /// Filter scale configuration - FS9: u1, - /// Filter scale configuration - FS10: u1, - /// Filter scale configuration - FS11: u1, - /// Filter scale configuration - FS12: u1, - /// Filter scale configuration - FS13: u1, - /// Filter scale configuration - FS14: u1, - /// Filter scale configuration - FS15: u1, - /// Filter scale configuration - FS16: u1, - /// Filter scale configuration - FS17: u1, - /// Filter scale configuration - FS18: u1, - /// Filter scale configuration - FS19: u1, - /// Filter scale configuration - FS20: u1, - /// Filter scale configuration - FS21: u1, - /// Filter scale configuration - FS22: u1, - /// Filter scale configuration - FS23: u1, - /// Filter scale configuration - FS24: u1, - /// Filter scale configuration - FS25: u1, - /// Filter scale configuration - FS26: u1, - /// Filter scale configuration - FS27: u1, - padding: u4, - }), - reserved532: [4]u8, - /// Filter associated FIFO register - FAFIFO: mmio.Mmio(packed struct(u32) { - /// Filter 0 associated with FIFO - FAF0: u1, - /// Filter 1 associated with FIFO - FAF1: u1, - /// Filter 2 associated with FIFO - FAF2: u1, - /// Filter 3 associated with FIFO - FAF3: u1, - /// Filter 4 associated with FIFO - FAF4: u1, - /// Filter 5 associated with FIFO - FAF5: u1, - /// Filter 6 associated with FIFO - FAF6: u1, - /// Filter 7 associated with FIFO - FAF7: u1, - /// Filter 8 associated with FIFO - FAF8: u1, - /// Filter 9 associated with FIFO - FAF9: u1, - /// Filter 10 associated with FIFO - FAF10: u1, - /// Filter 11 associated with FIFO - FAF11: u1, - /// Filter 12 associated with FIFO - FAF12: u1, - /// Filter 13 associated with FIFO - FAF13: u1, - /// Filter 14 associated with FIFO - FAF14: u1, - /// Filter 15 associated with FIFO - FAF15: u1, - /// Filter 16 associated with FIFO - FAF16: u1, - /// Filter 17 associated with FIFO - FAF17: u1, - /// Filter 18 associated with FIFO - FAF18: u1, - /// Filter 19 associated with FIFO - FAF19: u1, - /// Filter 20 associated with FIFO - FAF20: u1, - /// Filter 21 associated with FIFO - FAF21: u1, - /// Filter 22 associated with FIFO - FAF22: u1, - /// Filter 23 associated with FIFO - FAF23: u1, - /// Filter 24 associated with FIFO - FAF24: u1, - /// Filter 25 associated with FIFO - FAF25: u1, - /// Filter 26 associated with FIFO - FAF26: u1, - /// Filter 27 associated with FIFO - FAF27: u1, - padding: u4, - }), - reserved540: [4]u8, - /// Filter working register - FW: mmio.Mmio(packed struct(u32) { - /// Filter working - FW0: u1, - /// Filter working - FW1: u1, - /// Filter working - FW2: u1, - /// Filter working - FW3: u1, - /// Filter working - FW4: u1, - /// Filter working - FW5: u1, - /// Filter working - FW6: u1, - /// Filter working - FW7: u1, - /// Filter working - FW8: u1, - /// Filter working - FW9: u1, - /// Filter working - FW10: u1, - /// Filter working - FW11: u1, - /// Filter working - FW12: u1, - /// Filter working - FW13: u1, - /// Filter working - FW14: u1, - /// Filter working - FW15: u1, - /// Filter working - FW16: u1, - /// Filter working - FW17: u1, - /// Filter working - FW18: u1, - /// Filter working - FW19: u1, - /// Filter working - FW20: u1, - /// Filter working - FW21: u1, - /// Filter working - FW22: u1, - /// Filter working - FW23: u1, - /// Filter working - FW24: u1, - /// Filter working - FW25: u1, - /// Filter working - FW26: u1, - /// Filter working - FW27: u1, - padding: u4, - }), - reserved576: [32]u8, - /// Filter 0 data 0 register - F0DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 0 data 1 register - F0DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 1 data 0 register - F1DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 1 data 1 register - F1DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 2 data 0 register - F2DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 2 data 1 register - F2DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 3 data 0 register - F3DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 3 data 1 register - F3DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 4 data 0 register - F4DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 4 data 1 register - F4DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 5 data 0 register - F5DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 5 data 1 register - F5DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 6 data 0 register - F6DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 6 data 1 register - F6DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 7 data 0 register - F7DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 7 data 1 register - F7DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 8 data 0 register - F8DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 8 data 1 register - F8DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 9 data 0 register - F9DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 9 data 1 register - F9DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 10 data 0 register - F10DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 10 data 1 register - F10DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 11 data 0 register - F11DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 11 data 1 register - F11DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 12 data 0 register - F12DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 12 data 1 register - F12DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 13 data 0 register - F13DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 13 data 1 register - F13DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 14 data 0 register - F14DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 14 data 1 register - F14DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 15 data 0 register - F15DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 15 data 1 register - F15DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 16 data 0 register - F16DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 16 data 1 register - F16DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 17 data 0 register - F17DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 17 data 1 register - F17DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 18 data 0 register - F18DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 18 data 1 register - F18DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 19 data 0 register - F19DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 19 data 1 register - F19DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 20 data 0 register - F20DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 20 data 1 register - F20DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 21 data 0 register - F21DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 21 data 1 register - F21DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 22 data 0 register - F22DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 22 data 1 register - F22DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 23 data 0 register - F23DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 23 data 1 register - F23DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 24 data 0 register - F24DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 24 data 1 register - F24DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 25 data 0 register - F25DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 25 data 1 register - F25DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 26 data 0 register - F26DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 26 data 1 register - F26DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 27 data 0 register - F27DATA0: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - /// Filter 27 data 1 register - F27DATA1: mmio.Mmio(packed struct(u32) { - /// Filter bits - FD0: u1, - /// Filter bits - FD1: u1, - /// Filter bits - FD2: u1, - /// Filter bits - FD3: u1, - /// Filter bits - FD4: u1, - /// Filter bits - FD5: u1, - /// Filter bits - FD6: u1, - /// Filter bits - FD7: u1, - /// Filter bits - FD8: u1, - /// Filter bits - FD9: u1, - /// Filter bits - FD10: u1, - /// Filter bits - FD11: u1, - /// Filter bits - FD12: u1, - /// Filter bits - FD13: u1, - /// Filter bits - FD14: u1, - /// Filter bits - FD15: u1, - /// Filter bits - FD16: u1, - /// Filter bits - FD17: u1, - /// Filter bits - FD18: u1, - /// Filter bits - FD19: u1, - /// Filter bits - FD20: u1, - /// Filter bits - FD21: u1, - /// Filter bits - FD22: u1, - /// Filter bits - FD23: u1, - /// Filter bits - FD24: u1, - /// Filter bits - FD25: u1, - /// Filter bits - FD26: u1, - /// Filter bits - FD27: u1, - /// Filter bits - FD28: u1, - /// Filter bits - FD29: u1, - /// Filter bits - FD30: u1, - /// Filter bits - FD31: u1, - }), - }; - - /// Window watchdog timer - pub const WWDGT = extern struct { - /// Control register - CTL: mmio.Mmio(packed struct(u32) { - /// 7-bit counter - CNT: u7, - /// Activation bit - WDGTEN: u1, - padding: u24, - }), - /// Configuration register - CFG: mmio.Mmio(packed struct(u32) { - /// 7-bit window value - WIN: u7, - /// Prescaler - PSC: u2, - /// Early wakeup interrupt - EWIE: u1, - padding: u22, - }), - /// Status register - STAT: mmio.Mmio(packed struct(u32) { - /// Early wakeup interrupt flag - EWIF: u1, - padding: u31, - }), - }; - - /// cyclic redundancy check calculation unit - pub const CRC = extern struct { - /// Data register - DATA: mmio.Mmio(packed struct(u32) { - /// CRC calculation result bits - DATA: u32, - }), - /// Free data register - FDATA: mmio.Mmio(packed struct(u32) { - /// Free Data Register bits - FDATA: u8, - padding: u24, - }), - /// Control register - CTL: mmio.Mmio(packed struct(u32) { - /// reset bit - RST: u1, - padding: u31, - }), - }; - - /// Digital-to-analog converter - pub const DAC = extern struct { - /// control register - CTL: mmio.Mmio(packed struct(u32) { - /// DAC0 enable - DEN0: u1, - /// DAC0 output buffer turn off - DBOFF0: u1, - /// DAC0 trigger enable - DTEN0: u1, - /// DAC0 trigger selection - DTSEL0: u3, - /// DAC0 noise wave mode - DWM0: u2, - /// DAC0 noise wave bit width - DWBW0: u4, - /// DAC0 DMA enable - DDMAEN0: u1, - reserved16: u3, - /// DAC1 enable - DEN1: u1, - /// DAC1 output buffer turn off - DBOFF1: u1, - /// DAC1 trigger enable - DTEN1: u1, - /// DAC1 trigger selection - DTSEL1: u3, - /// DAC1 noise wave mode - DWM1: u2, - /// DAC1 noise wave bit width - DWBW1: u4, - /// DAC1 DMA enable - DDMAEN1: u1, - padding: u3, - }), - /// software trigger register - SWT: mmio.Mmio(packed struct(u32) { - /// DAC0 software trigger - SWTR0: u1, - /// DAC1 software trigger - SWTR1: u1, - padding: u30, - }), - /// DAC0 12-bit right-aligned data holding register - DAC0_R12DH: mmio.Mmio(packed struct(u32) { - /// DAC0 12-bit right-aligned data - DAC0_DH: u12, - padding: u20, - }), - /// DAC0 12-bit left-aligned data holding register - DAC0_L12DH: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// DAC0 12-bit left-aligned data - DAC0_DH: u12, - padding: u16, - }), - /// DAC0 8-bit right aligned data holding register - DAC0_R8DH: mmio.Mmio(packed struct(u32) { - /// DAC0 8-bit right-aligned data - DAC0_DH: u8, - padding: u24, - }), - /// DAC1 12-bit right-aligned data holding register - DAC1_R12DH: mmio.Mmio(packed struct(u32) { - /// DAC1 12-bit right-aligned data - DAC1_DH: u12, - padding: u20, - }), - /// DAC1 12-bit left aligned data holding register - DAC1_L12DH: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// DAC1 12-bit left-aligned data - DAC1_DH: u12, - padding: u16, - }), - /// DAC1 8-bit right aligned data holding register - DAC1_R8DH: mmio.Mmio(packed struct(u32) { - /// DAC1 8-bit right-aligned data - DAC1_DH: u8, - padding: u24, - }), - /// DAC concurrent mode 12-bit right-aligned data holding register - DACC_R12DH: mmio.Mmio(packed struct(u32) { - /// DAC0 12-bit right-aligned data - DAC0_DH: u12, - reserved16: u4, - /// DAC1 12-bit right-aligned data - DAC1_DH: u12, - padding: u4, - }), - /// DAC concurrent mode 12-bit left aligned data holding register - DACC_L12DH: mmio.Mmio(packed struct(u32) { - reserved4: u4, - /// DAC0 12-bit left-aligned data - DAC0_DH: u12, - reserved20: u4, - /// DAC1 12-bit left-aligned data - DAC1_DH: u12, - }), - /// DAC concurrent mode 8-bit right aligned data holding register - DACC_R8DH: mmio.Mmio(packed struct(u32) { - /// DAC0 8-bit right-aligned data - DAC0_DH: u8, - /// DAC1 8-bit right-aligned data - DAC1_DH: u8, - padding: u16, - }), - /// DAC0 data output register - DAC0_DO: mmio.Mmio(packed struct(u32) { - /// DAC0 data output - DAC0_DO: u12, - padding: u20, - }), - /// DAC1 data output register - DAC1_DO: mmio.Mmio(packed struct(u32) { - /// DAC1 data output - DAC1_DO: u12, - padding: u20, - }), - }; - - /// Debug support - pub const DBG = extern struct { - /// ID code register - ID: mmio.Mmio(packed struct(u32) { - /// DBG ID code register - ID_CODE: u32, - }), - /// Control register 0 - CTL: mmio.Mmio(packed struct(u32) { - /// Sleep mode hold register - SLP_HOLD: u1, - /// Deep-sleep mode hold register - DSLP_HOLD: u1, - /// Standby mode hold register - STB_HOLD: u1, - reserved8: u5, - /// FWDGT hold bit - FWDGT_HOLD: u1, - /// WWDGT hold bit - WWDGT_HOLD: u1, - /// TIMER 0 hold bit - TIMER0_HOLD: u1, - /// TIMER 1 hold bit - TIMER1_HOLD: u1, - /// TIMER 2 hold bit - TIMER2_HOLD: u1, - /// TIMER 23 hold bit - TIMER3_HOLD: u1, - /// CAN0 hold bit - CAN0_HOLD: u1, - /// I2C0 hold bit - I2C0_HOLD: u1, - /// I2C1 hold bit - I2C1_HOLD: u1, - reserved18: u1, - /// TIMER4_HOLD - TIMER4_HOLD: u1, - /// TIMER 5 hold bit - TIMER5_HOLD: u1, - /// TIMER 6 hold bit - TIMER6_HOLD: u1, - /// CAN1 hold bit - CAN1_HOLD: u1, - padding: u10, - }), - }; - - /// DMA controller - pub const DMA0 = extern struct { - /// Interrupt flag register - INTF: mmio.Mmio(packed struct(u32) { - /// Global interrupt flag of channel 0 - GIF0: u1, - /// Full Transfer finish flag of channe 0 - FTFIF0: u1, - /// Half transfer finish flag of channel 0 - HTFIF0: u1, - /// Error flag of channel 0 - ERRIF0: u1, - /// Global interrupt flag of channel 1 - GIF1: u1, - /// Full Transfer finish flag of channe 1 - FTFIF1: u1, - /// Half transfer finish flag of channel 1 - HTFIF1: u1, - /// Error flag of channel 1 - ERRIF1: u1, - /// Global interrupt flag of channel 2 - GIF2: u1, - /// Full Transfer finish flag of channe 2 - FTFIF2: u1, - /// Half transfer finish flag of channel 2 - HTFIF2: u1, - /// Error flag of channel 2 - ERRIF2: u1, - /// Global interrupt flag of channel 3 - GIF3: u1, - /// Full Transfer finish flag of channe 3 - FTFIF3: u1, - /// Half transfer finish flag of channel 3 - HTFIF3: u1, - /// Error flag of channel 3 - ERRIF3: u1, - /// Global interrupt flag of channel 4 - GIF4: u1, - /// Full Transfer finish flag of channe 4 - FTFIF4: u1, - /// Half transfer finish flag of channel 4 - HTFIF4: u1, - /// Error flag of channel 4 - ERRIF4: u1, - /// Global interrupt flag of channel 5 - GIF5: u1, - /// Full Transfer finish flag of channe 5 - FTFIF5: u1, - /// Half transfer finish flag of channel 5 - HTFIF5: u1, - /// Error flag of channel 5 - ERRIF5: u1, - /// Global interrupt flag of channel 6 - GIF6: u1, - /// Full Transfer finish flag of channe 6 - FTFIF6: u1, - /// Half transfer finish flag of channel 6 - HTFIF6: u1, - /// Error flag of channel 6 - ERRIF6: u1, - padding: u4, - }), - /// Interrupt flag clear register - INTC: mmio.Mmio(packed struct(u32) { - /// Clear global interrupt flag of channel 0 - GIFC0: u1, - /// Clear bit for full transfer finish flag of channel 0 - FTFIFC0: u1, - /// Clear bit for half transfer finish flag of channel 0 - HTFIFC0: u1, - /// Clear bit for error flag of channel 0 - ERRIFC0: u1, - /// Clear global interrupt flag of channel 1 - GIFC1: u1, - /// Clear bit for full transfer finish flag of channel 1 - FTFIFC1: u1, - /// Clear bit for half transfer finish flag of channel 1 - HTFIFC1: u1, - /// Clear bit for error flag of channel 1 - ERRIFC1: u1, - /// Clear global interrupt flag of channel 2 - GIFC2: u1, - /// Clear bit for full transfer finish flag of channel 2 - FTFIFC2: u1, - /// Clear bit for half transfer finish flag of channel 2 - HTFIFC2: u1, - /// Clear bit for error flag of channel 2 - ERRIFC2: u1, - /// Clear global interrupt flag of channel 3 - GIFC3: u1, - /// Clear bit for full transfer finish flag of channel 3 - FTFIFC3: u1, - /// Clear bit for half transfer finish flag of channel 3 - HTFIFC3: u1, - /// Clear bit for error flag of channel 3 - ERRIFC3: u1, - /// Clear global interrupt flag of channel 4 - GIFC4: u1, - /// Clear bit for full transfer finish flag of channel 4 - FTFIFC4: u1, - /// Clear bit for half transfer finish flag of channel 4 - HTFIFC4: u1, - /// Clear bit for error flag of channel 4 - ERRIFC4: u1, - /// Clear global interrupt flag of channel 5 - GIFC5: u1, - /// Clear bit for full transfer finish flag of channel 5 - FTFIFC5: u1, - /// Clear bit for half transfer finish flag of channel 5 - HTFIFC5: u1, - /// Clear bit for error flag of channel 5 - ERRIFC5: u1, - /// Clear global interrupt flag of channel 6 - GIFC6: u1, - /// Clear bit for full transfer finish flag of channel 6 - FTFIFC6: u1, - /// Clear bit for half transfer finish flag of channel 6 - HTFIFC6: u1, - /// Clear bit for error flag of channel 6 - ERRIFC6: u1, - padding: u4, - }), - /// Channel 0 control register - CH0CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 0 counter register - CH0CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 0 peripheral base address register - CH0PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 0 memory base address register - CH0MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved28: [4]u8, - /// Channel 1 control register - CH1CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 1 counter register - CH1CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 1 peripheral base address register - CH1PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 1 memory base address register - CH1MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved48: [4]u8, - /// Channel 2 control register - CH2CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 2 counter register - CH2CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 2 peripheral base address register - CH2PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 2 memory base address register - CH2MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved68: [4]u8, - /// Channel 3 control register - CH3CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 3 counter register - CH3CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 3 peripheral base address register - CH3PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 3 memory base address register - CH3MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved88: [4]u8, - /// Channel 4 control register - CH4CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 4 counter register - CH4CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 4 peripheral base address register - CH4PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 4 memory base address register - CH4MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved108: [4]u8, - /// Channel 5 control register - CH5CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 5 counter register - CH5CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 5 peripheral base address register - CH5PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 5 memory base address register - CH5MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved128: [4]u8, - /// Channel 6 control register - CH6CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 6 counter register - CH6CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 6 peripheral base address register - CH6PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 6 memory base address register - CH6MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - }; - - /// Direct memory access controller - pub const DMA1 = extern struct { - /// Interrupt flag register - INTF: mmio.Mmio(packed struct(u32) { - /// Global interrupt flag of channel 0 - GIF0: u1, - /// Full Transfer finish flag of channe 0 - FTFIF0: u1, - /// Half transfer finish flag of channel 0 - HTFIF0: u1, - /// Error flag of channel 0 - ERRIF0: u1, - /// Global interrupt flag of channel 1 - GIF1: u1, - /// Full Transfer finish flag of channe 1 - FTFIF1: u1, - /// Half transfer finish flag of channel 1 - HTFIF1: u1, - /// Error flag of channel 1 - ERRIF1: u1, - /// Global interrupt flag of channel 2 - GIF2: u1, - /// Full Transfer finish flag of channe 2 - FTFIF2: u1, - /// Half transfer finish flag of channel 2 - HTFIF2: u1, - /// Error flag of channel 2 - ERRIF2: u1, - /// Global interrupt flag of channel 3 - GIF3: u1, - /// Full Transfer finish flag of channe 3 - FTFIF3: u1, - /// Half transfer finish flag of channel 3 - HTFIF3: u1, - /// Error flag of channel 3 - ERRIF3: u1, - /// Global interrupt flag of channel 4 - GIF4: u1, - /// Full Transfer finish flag of channe 4 - FTFIF4: u1, - /// Half transfer finish flag of channel 4 - HTFIF4: u1, - /// Error flag of channel 4 - ERRIF4: u1, - padding: u12, - }), - /// Interrupt flag clear register - INTC: mmio.Mmio(packed struct(u32) { - /// Clear global interrupt flag of channel 0 - GIFC0: u1, - /// Clear bit for full transfer finish flag of channel 0 - FTFIFC0: u1, - /// Clear bit for half transfer finish flag of channel 0 - HTFIFC0: u1, - /// Clear bit for error flag of channel 0 - ERRIFC0: u1, - /// Clear global interrupt flag of channel 1 - GIFC1: u1, - /// Clear bit for full transfer finish flag of channel 1 - FTFIFC1: u1, - /// Clear bit for half transfer finish flag of channel 1 - HTFIFC1: u1, - /// Clear bit for error flag of channel 1 - ERRIFC1: u1, - /// Clear global interrupt flag of channel 2 - GIFC2: u1, - /// Clear bit for full transfer finish flag of channel 2 - FTFIFC2: u1, - /// Clear bit for half transfer finish flag of channel 2 - HTFIFC2: u1, - /// Clear bit for error flag of channel 2 - ERRIFC2: u1, - /// Clear global interrupt flag of channel 3 - GIFC3: u1, - /// Clear bit for full transfer finish flag of channel 3 - FTFIFC3: u1, - /// Clear bit for half transfer finish flag of channel 3 - HTFIFC3: u1, - /// Clear bit for error flag of channel 3 - ERRIFC3: u1, - /// Clear global interrupt flag of channel 4 - GIFC4: u1, - /// Clear bit for full transfer finish flag of channel 4 - FTFIFC4: u1, - /// Clear bit for half transfer finish flag of channel 4 - HTFIFC4: u1, - /// Clear bit for error flag of channel 4 - ERRIFC4: u1, - padding: u12, - }), - /// Channel 0 control register - CH0CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 0 counter register - CH0CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 0 peripheral base address register - CH0PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 0 memory base address register - CH0MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved28: [4]u8, - /// Channel 1 control register - CH1CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 1 counter register - CH1CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 1 peripheral base address register - CH1PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 1 memory base address register - CH1MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved48: [4]u8, - /// Channel 2 control register - CH2CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 2 counter register - CH2CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 2 peripheral base address register - CH2PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 2 memory base address register - CH2MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved68: [4]u8, - /// Channel 3 control register - CH3CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 3 counter register - CH3CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 3 peripheral base address register - CH3PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 3 memory base address register - CH3MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - reserved88: [4]u8, - /// Channel 4 control register - CH4CTL: mmio.Mmio(packed struct(u32) { - /// Channel enable - CHEN: u1, - /// Enable bit for channel full transfer finish interrupt - FTFIE: u1, - /// Enable bit for channel half transfer finish interrupt - HTFIE: u1, - /// Enable bit for channel error interrupt - ERRIE: u1, - /// Transfer direction - DIR: u1, - /// Circular mode enable - CMEN: u1, - /// Next address generation algorithm of peripheral - PNAGA: u1, - /// Next address generation algorithm of memory - MNAGA: u1, - /// Transfer data size of peripheral - PWIDTH: u2, - /// Transfer data size of memory - MWIDTH: u2, - /// Priority level - PRIO: u2, - /// Memory to Memory Mode - M2M: u1, - padding: u17, - }), - /// Channel 4 counter register - CH4CNT: mmio.Mmio(packed struct(u32) { - /// Transfer counter - CNT: u16, - padding: u16, - }), - /// Channel 4 peripheral base address register - CH4PADDR: mmio.Mmio(packed struct(u32) { - /// Peripheral base address - PADDR: u32, - }), - /// Channel 4 memory base address register - CH4MADDR: mmio.Mmio(packed struct(u32) { - /// Memory base address - MADDR: u32, - }), - }; - - /// External memory controller - pub const EXMC = extern struct { - /// SRAM/NOR flash control register 0 - SNCTL0: mmio.Mmio(packed struct(u32) { - /// NOR bank enable - NRBKEN: u1, - /// NOR bank memory address/data multiplexing - NRMUX: u1, - /// NOR bank memory type - NRTP: u2, - /// NOR bank memory data bus width - NRW: u2, - /// NOR Flash access enable - NREN: u1, - reserved9: u2, - /// NWAIT signal polarity - NRWTPOL: u1, - reserved12: u2, - /// Write enable - WREN: u1, - /// NWAIT signal enable - NRWTEN: u1, - reserved15: u1, - /// Asynchronous wait - ASYNCWAIT: u1, - padding: u16, - }), - /// SRAM/NOR flash timing configuration register 0 - SNTCFG0: mmio.Mmio(packed struct(u32) { - /// Address setup time - ASET: u4, - /// Address hold time - AHLD: u4, - /// Data setup time - DSET: u8, - /// Bus latency - BUSLAT: u4, - padding: u12, - }), - /// SRAM/NOR flash control register 1 - SNCTL1: mmio.Mmio(packed struct(u32) { - /// NOR bank enable - NRBKEN: u1, - /// NOR bank memory address/data multiplexing - NRMUX: u1, - /// NOR bank memory type - NRTP: u2, - /// NOR bank memory data bus width - NRW: u2, - /// NOR Flash access enable - NREN: u1, - reserved9: u2, - /// NWAIT signal polarity - NRWTPOL: u1, - reserved12: u2, - /// Write enable - WREN: u1, - /// NWAIT signal enable - NRWTEN: u1, - reserved15: u1, - /// Asynchronous wait - ASYNCWAIT: u1, - padding: u16, - }), - }; - - /// External interrupt/event controller - pub const EXTI = extern struct { - /// Interrupt enable register (EXTI_INTEN) - INTEN: mmio.Mmio(packed struct(u32) { - /// Enable Interrupt on line 0 - INTEN0: u1, - /// Enable Interrupt on line 1 - INTEN1: u1, - /// Enable Interrupt on line 2 - INTEN2: u1, - /// Enable Interrupt on line 3 - INTEN3: u1, - /// Enable Interrupt on line 4 - INTEN4: u1, - /// Enable Interrupt on line 5 - INTEN5: u1, - /// Enable Interrupt on line 6 - INTEN6: u1, - /// Enable Interrupt on line 7 - INTEN7: u1, - /// Enable Interrupt on line 8 - INTEN8: u1, - /// Enable Interrupt on line 9 - INTEN9: u1, - /// Enable Interrupt on line 10 - INTEN10: u1, - /// Enable Interrupt on line 11 - INTEN11: u1, - /// Enable Interrupt on line 12 - INTEN12: u1, - /// Enable Interrupt on line 13 - INTEN13: u1, - /// Enable Interrupt on line 14 - INTEN14: u1, - /// Enable Interrupt on line 15 - INTEN15: u1, - /// Enable Interrupt on line 16 - INTEN16: u1, - /// Enable Interrupt on line 17 - INTEN17: u1, - /// Enable Interrupt on line 18 - INTEN18: u1, - padding: u13, - }), - /// Event enable register (EXTI_EVEN) - EVEN: mmio.Mmio(packed struct(u32) { - /// Enable Event on line 0 - EVEN0: u1, - /// Enable Event on line 1 - EVEN1: u1, - /// Enable Event on line 2 - EVEN2: u1, - /// Enable Event on line 3 - EVEN3: u1, - /// Enable Event on line 4 - EVEN4: u1, - /// Enable Event on line 5 - EVEN5: u1, - /// Enable Event on line 6 - EVEN6: u1, - /// Enable Event on line 7 - EVEN7: u1, - /// Enable Event on line 8 - EVEN8: u1, - /// Enable Event on line 9 - EVEN9: u1, - /// Enable Event on line 10 - EVEN10: u1, - /// Enable Event on line 11 - EVEN11: u1, - /// Enable Event on line 12 - EVEN12: u1, - /// Enable Event on line 13 - EVEN13: u1, - /// Enable Event on line 14 - EVEN14: u1, - /// Enable Event on line 15 - EVEN15: u1, - /// Enable Event on line 16 - EVEN16: u1, - /// Enable Event on line 17 - EVEN17: u1, - /// Enable Event on line 18 - EVEN18: u1, - padding: u13, - }), - /// Rising Edge Trigger Enable register (EXTI_RTEN) - RTEN: mmio.Mmio(packed struct(u32) { - /// Rising edge trigger enable of line 0 - RTEN0: u1, - /// Rising edge trigger enable of line 1 - RTEN1: u1, - /// Rising edge trigger enable of line 2 - RTEN2: u1, - /// Rising edge trigger enable of line 3 - RTEN3: u1, - /// Rising edge trigger enable of line 4 - RTEN4: u1, - /// Rising edge trigger enable of line 5 - RTEN5: u1, - /// Rising edge trigger enable of line 6 - RTEN6: u1, - /// Rising edge trigger enable of line 7 - RTEN7: u1, - /// Rising edge trigger enable of line 8 - RTEN8: u1, - /// Rising edge trigger enable of line 9 - RTEN9: u1, - /// Rising edge trigger enable of line 10 - RTEN10: u1, - /// Rising edge trigger enable of line 11 - RTEN11: u1, - /// Rising edge trigger enable of line 12 - RTEN12: u1, - /// Rising edge trigger enable of line 13 - RTEN13: u1, - /// Rising edge trigger enable of line 14 - RTEN14: u1, - /// Rising edge trigger enable of line 15 - RTEN15: u1, - /// Rising edge trigger enable of line 16 - RTEN16: u1, - /// Rising edge trigger enable of line 17 - RTEN17: u1, - /// Rising edge trigger enable of line 18 - RTEN18: u1, - padding: u13, - }), - /// Falling Egde Trigger Enable register (EXTI_FTEN) - FTEN: mmio.Mmio(packed struct(u32) { - /// Falling edge trigger enable of line 0 - FTEN0: u1, - /// Falling edge trigger enable of line 1 - FTEN1: u1, - /// Falling edge trigger enable of line 2 - FTEN2: u1, - /// Falling edge trigger enable of line 3 - FTEN3: u1, - /// Falling edge trigger enable of line 4 - FTEN4: u1, - /// Falling edge trigger enable of line 5 - FTEN5: u1, - /// Falling edge trigger enable of line 6 - FTEN6: u1, - /// Falling edge trigger enable of line 7 - FTEN7: u1, - /// Falling edge trigger enable of line 8 - FTEN8: u1, - /// Falling edge trigger enable of line 9 - FTEN9: u1, - /// Falling edge trigger enable of line 10 - FTEN10: u1, - /// Falling edge trigger enable of line 11 - FTEN11: u1, - /// Falling edge trigger enable of line 12 - FTEN12: u1, - /// Falling edge trigger enable of line 13 - FTEN13: u1, - /// Falling edge trigger enable of line 14 - FTEN14: u1, - /// Falling edge trigger enable of line 15 - FTEN15: u1, - /// Falling edge trigger enable of line 16 - FTEN16: u1, - /// Falling edge trigger enable of line 17 - FTEN17: u1, - /// Falling edge trigger enable of line 18 - FTEN18: u1, - padding: u13, - }), - /// Software interrupt event register (EXTI_SWIEV) - SWIEV: mmio.Mmio(packed struct(u32) { - /// Interrupt/Event software trigger on line 0 - SWIEV0: u1, - /// Interrupt/Event software trigger on line 1 - SWIEV1: u1, - /// Interrupt/Event software trigger on line 2 - SWIEV2: u1, - /// Interrupt/Event software trigger on line 3 - SWIEV3: u1, - /// Interrupt/Event software trigger on line 4 - SWIEV4: u1, - /// Interrupt/Event software trigger on line 5 - SWIEV5: u1, - /// Interrupt/Event software trigger on line 6 - SWIEV6: u1, - /// Interrupt/Event software trigger on line 7 - SWIEV7: u1, - /// Interrupt/Event software trigger on line 8 - SWIEV8: u1, - /// Interrupt/Event software trigger on line 9 - SWIEV9: u1, - /// Interrupt/Event software trigger on line 10 - SWIEV10: u1, - /// Interrupt/Event software trigger on line 11 - SWIEV11: u1, - /// Interrupt/Event software trigger on line 12 - SWIEV12: u1, - /// Interrupt/Event software trigger on line 13 - SWIEV13: u1, - /// Interrupt/Event software trigger on line 14 - SWIEV14: u1, - /// Interrupt/Event software trigger on line 15 - SWIEV15: u1, - /// Interrupt/Event software trigger on line 16 - SWIEV16: u1, - /// Interrupt/Event software trigger on line 17 - SWIEV17: u1, - /// Interrupt/Event software trigger on line 18 - SWIEV18: u1, - padding: u13, - }), - /// Pending register (EXTI_PD) - PD: mmio.Mmio(packed struct(u32) { - /// Interrupt pending status of line 0 - PD0: u1, - /// Interrupt pending status of line 1 - PD1: u1, - /// Interrupt pending status of line 2 - PD2: u1, - /// Interrupt pending status of line 3 - PD3: u1, - /// Interrupt pending status of line 4 - PD4: u1, - /// Interrupt pending status of line 5 - PD5: u1, - /// Interrupt pending status of line 6 - PD6: u1, - /// Interrupt pending status of line 7 - PD7: u1, - /// Interrupt pending status of line 8 - PD8: u1, - /// Interrupt pending status of line 9 - PD9: u1, - /// Interrupt pending status of line 10 - PD10: u1, - /// Interrupt pending status of line 11 - PD11: u1, - /// Interrupt pending status of line 12 - PD12: u1, - /// Interrupt pending status of line 13 - PD13: u1, - /// Interrupt pending status of line 14 - PD14: u1, - /// Interrupt pending status of line 15 - PD15: u1, - /// Interrupt pending status of line 16 - PD16: u1, - /// Interrupt pending status of line 17 - PD17: u1, - /// Interrupt pending status of line 18 - PD18: u1, - padding: u13, - }), - }; - - /// FMC - pub const FMC = extern struct { - /// wait state counter register - WS: mmio.Mmio(packed struct(u32) { - /// wait state counter register - WSCNT: u3, - padding: u29, - }), - /// Unlock key register 0 - KEY0: mmio.Mmio(packed struct(u32) { - /// FMC_CTL0 unlock key - KEY: u32, - }), - /// Option byte unlock key register - OBKEY: mmio.Mmio(packed struct(u32) { - /// FMC_ CTL0 option byte operation unlock register - OBKEY: u32, - }), - /// Status register 0 - STAT0: mmio.Mmio(packed struct(u32) { - /// The flash is busy bit - BUSY: u1, - reserved2: u1, - /// Program error flag bit - PGERR: u1, - reserved4: u1, - /// Erase/Program protection error flag bit - WPERR: u1, - /// End of operation flag bit - ENDF: u1, - padding: u26, - }), - /// Control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Main flash program for bank0 command bit - PG: u1, - /// Main flash page erase for bank0 command bit - PER: u1, - /// Main flash mass erase for bank0 command bit - MER: u1, - reserved4: u1, - /// Option bytes program command bit - OBPG: u1, - /// Option bytes erase command bit - OBER: u1, - /// Send erase command to FMC bit - START: u1, - /// FMC_CTL0 lock bit - LK: u1, - reserved9: u1, - /// Option byte erase/program enable bit - OBWEN: u1, - /// Error interrupt enable bit - ERRIE: u1, - reserved12: u1, - /// End of operation interrupt enable bit - ENDIE: u1, - padding: u19, - }), - /// Address register 0 - ADDR0: mmio.Mmio(packed struct(u32) { - /// Flash erase/program command address bits - ADDR: u32, - }), - reserved28: [4]u8, - /// Option byte status register - OBSTAT: mmio.Mmio(packed struct(u32) { - /// Option bytes read error bit - OBERR: u1, - /// Option bytes security protection code - SPC: u1, - /// Store USER of option bytes block after system reset - USER: u8, - /// Store DATA[15:0] of option bytes block after system reset - DATA: u16, - padding: u6, - }), - /// Erase/Program Protection register - WP: mmio.Mmio(packed struct(u32) { - /// Store WP[31:0] of option bytes block after system reset - WP: u32, - }), - reserved256: [220]u8, - /// Product ID register - PID: mmio.Mmio(packed struct(u32) { - /// Product reserved ID code register - PID: u32, - }), - }; - - /// free watchdog timer - pub const FWDGT = extern struct { - /// Control register - CTL: mmio.Mmio(packed struct(u32) { - /// Key value - CMD: u16, - padding: u16, - }), - /// Prescaler register - PSC: mmio.Mmio(packed struct(u32) { - /// Free watchdog timer prescaler selection - PSC: u3, - padding: u29, - }), - /// Reload register - RLD: mmio.Mmio(packed struct(u32) { - /// Free watchdog timer counter reload value - RLD: u12, - padding: u20, - }), - /// Status register - STAT: mmio.Mmio(packed struct(u32) { - /// Free watchdog timer prescaler value update - PUD: u1, - /// Free watchdog timer counter reload value update - RUD: u1, - padding: u30, - }), - }; - - /// General-purpose I/Os - pub const GPIOA = extern struct { - /// port control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Port x mode bits (x = 0) - MD0: u2, - /// Port x configuration bits (x = 0) - CTL0: u2, - /// Port x mode bits (x = 1) - MD1: u2, - /// Port x configuration bits (x = 1) - CTL1: u2, - /// Port x mode bits (x = 2 ) - MD2: u2, - /// Port x configuration bits (x = 2) - CTL2: u2, - /// Port x mode bits (x = 3 ) - MD3: u2, - /// Port x configuration bits (x = 3) - CTL3: u2, - /// Port x mode bits (x = 4) - MD4: u2, - /// Port x configuration bits (x = 4) - CTL4: u2, - /// Port x mode bits (x = 5) - MD5: u2, - /// Port x configuration bits (x = 5) - CTL5: u2, - /// Port x mode bits (x = 6) - MD6: u2, - /// Port x configuration bits (x = 6) - CTL6: u2, - /// Port x mode bits (x = 7) - MD7: u2, - /// Port x configuration bits (x = 7) - CTL7: u2, - }), - /// port control register 1 - CTL1: mmio.Mmio(packed struct(u32) { - /// Port x mode bits (x = 8) - MD8: u2, - /// Port x configuration bits (x = 8) - CTL8: u2, - /// Port x mode bits (x = 9) - MD9: u2, - /// Port x configuration bits (x = 9) - CTL9: u2, - /// Port x mode bits (x = 10 ) - MD10: u2, - /// Port x configuration bits (x = 10) - CTL10: u2, - /// Port x mode bits (x = 11 ) - MD11: u2, - /// Port x configuration bits (x = 11) - CTL11: u2, - /// Port x mode bits (x = 12) - MD12: u2, - /// Port x configuration bits (x = 12) - CTL12: u2, - /// Port x mode bits (x = 13) - MD13: u2, - /// Port x configuration bits (x = 13) - CTL13: u2, - /// Port x mode bits (x = 14) - MD14: u2, - /// Port x configuration bits (x = 14) - CTL14: u2, - /// Port x mode bits (x = 15) - MD15: u2, - /// Port x configuration bits (x = 15) - CTL15: u2, - }), - /// Port input status register - ISTAT: mmio.Mmio(packed struct(u32) { - /// Port input status - ISTAT0: u1, - /// Port input status - ISTAT1: u1, - /// Port input status - ISTAT2: u1, - /// Port input status - ISTAT3: u1, - /// Port input status - ISTAT4: u1, - /// Port input status - ISTAT5: u1, - /// Port input status - ISTAT6: u1, - /// Port input status - ISTAT7: u1, - /// Port input status - ISTAT8: u1, - /// Port input status - ISTAT9: u1, - /// Port input status - ISTAT10: u1, - /// Port input status - ISTAT11: u1, - /// Port input status - ISTAT12: u1, - /// Port input status - ISTAT13: u1, - /// Port input status - ISTAT14: u1, - /// Port input status - ISTAT15: u1, - padding: u16, - }), - /// Port output control register - OCTL: mmio.Mmio(packed struct(u32) { - /// Port output control - OCTL0: u1, - /// Port output control - OCTL1: u1, - /// Port output control - OCTL2: u1, - /// Port output control - OCTL3: u1, - /// Port output control - OCTL4: u1, - /// Port output control - OCTL5: u1, - /// Port output control - OCTL6: u1, - /// Port output control - OCTL7: u1, - /// Port output control - OCTL8: u1, - /// Port output control - OCTL9: u1, - /// Port output control - OCTL10: u1, - /// Port output control - OCTL11: u1, - /// Port output control - OCTL12: u1, - /// Port output control - OCTL13: u1, - /// Port output control - OCTL14: u1, - /// Port output control - OCTL15: u1, - padding: u16, - }), - /// Port bit operate register - BOP: mmio.Mmio(packed struct(u32) { - /// Port 0 Set bit - BOP0: u1, - /// Port 1 Set bit - BOP1: u1, - /// Port 2 Set bit - BOP2: u1, - /// Port 3 Set bit - BOP3: u1, - /// Port 4 Set bit - BOP4: u1, - /// Port 5 Set bit - BOP5: u1, - /// Port 6 Set bit - BOP6: u1, - /// Port 7 Set bit - BOP7: u1, - /// Port 8 Set bit - BOP8: u1, - /// Port 9 Set bit - BOP9: u1, - /// Port 10 Set bit - BOP10: u1, - /// Port 11 Set bit - BOP11: u1, - /// Port 12 Set bit - BOP12: u1, - /// Port 13 Set bit - BOP13: u1, - /// Port 14 Set bit - BOP14: u1, - /// Port 15 Set bit - BOP15: u1, - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - }), - /// Port bit clear register - BC: mmio.Mmio(packed struct(u32) { - /// Port 0 Clear bit - CR0: u1, - /// Port 1 Clear bit - CR1: u1, - /// Port 2 Clear bit - CR2: u1, - /// Port 3 Clear bit - CR3: u1, - /// Port 4 Clear bit - CR4: u1, - /// Port 5 Clear bit - CR5: u1, - /// Port 6 Clear bit - CR6: u1, - /// Port 7 Clear bit - CR7: u1, - /// Port 8 Clear bit - CR8: u1, - /// Port 9 Clear bit - CR9: u1, - /// Port 10 Clear bit - CR10: u1, - /// Port 11 Clear bit - CR11: u1, - /// Port 12 Clear bit - CR12: u1, - /// Port 13 Clear bit - CR13: u1, - /// Port 14 Clear bit - CR14: u1, - /// Port 15 Clear bit - CR15: u1, - padding: u16, - }), - /// GPIO port configuration lock register - LOCK: mmio.Mmio(packed struct(u32) { - /// Port Lock bit 0 - LK0: u1, - /// Port Lock bit 1 - LK1: u1, - /// Port Lock bit 2 - LK2: u1, - /// Port Lock bit 3 - LK3: u1, - /// Port Lock bit 4 - LK4: u1, - /// Port Lock bit 5 - LK5: u1, - /// Port Lock bit 6 - LK6: u1, - /// Port Lock bit 7 - LK7: u1, - /// Port Lock bit 8 - LK8: u1, - /// Port Lock bit 9 - LK9: u1, - /// Port Lock bit 10 - LK10: u1, - /// Port Lock bit 11 - LK11: u1, - /// Port Lock bit 12 - LK12: u1, - /// Port Lock bit 13 - LK13: u1, - /// Port Lock bit 14 - LK14: u1, - /// Port Lock bit 15 - LK15: u1, - /// Lock sequence key - LKK: u1, - padding: u15, - }), - }; - - /// USB on the go full speed - pub const USBFS_PWRCLK = extern struct { - /// power and clock gating control register (PWRCLKCTL) - PWRCLKCTL: mmio.Mmio(packed struct(u32) { - /// Stop the USB clock - SUCLK: u1, - /// Stop HCLK - SHCLK: u1, - padding: u30, - }), - }; - - /// USB on the go full speed device - pub const USBFS_DEVICE = extern struct { - /// device configuration register (DCFG) - DCFG: mmio.Mmio(packed struct(u32) { - /// Device speed - DS: u2, - /// Non-zero-length status OUT handshake - NZLSOH: u1, - reserved4: u1, - /// Device address - DAR: u7, - /// end of periodic frame time - EOPFT: u2, - padding: u19, - }), - /// device control register (DCTL) - DCTL: mmio.Mmio(packed struct(u32) { - /// Remote wakeup - RWKUP: u1, - /// Soft disconnect - SD: u1, - /// Global IN NAK status - GINS: u1, - /// Global OUT NAK status - GONS: u1, - reserved7: u3, - /// Set global IN NAK - SGINAK: u1, - /// Clear global IN NAK - CGINAK: u1, - /// Set global OUT NAK - SGONAK: u1, - /// Clear global OUT NAK - CGONAK: u1, - /// Power-on initialization flag - POIF: u1, - padding: u20, - }), - /// device status register (DSTAT) - DSTAT: mmio.Mmio(packed struct(u32) { - /// Suspend status - SPST: u1, - /// Enumerated speed - ES: u2, - reserved8: u5, - /// Frame number of the received SOF - FNRSOF: u14, - padding: u10, - }), - reserved16: [4]u8, - /// device IN endpoint common interrupt mask register (DIEPINTEN) - DIEPINTEN: mmio.Mmio(packed struct(u32) { - /// Transfer finished interrupt enable - TFEN: u1, - /// Endpoint disabled interrupt enable - EPDISEN: u1, - reserved3: u1, - /// Control IN timeout condition interrupt enable (Non-isochronous endpoints) - CITOEN: u1, - /// Endpoint Tx FIFO underrun interrupt enable bit - EPTXFUDEN: u1, - reserved6: u1, - /// IN endpoint NAK effective interrupt enable - IEPNEEN: u1, - padding: u25, - }), - /// device OUT endpoint common interrupt enable register (DOEPINTEN) - DOEPINTEN: mmio.Mmio(packed struct(u32) { - /// Transfer finished interrupt enable - TFEN: u1, - /// Endpoint disabled interrupt enable - EPDISEN: u1, - reserved3: u1, - /// SETUP phase finished interrupt enable - STPFEN: u1, - /// Endpoint Rx FIFO overrun interrupt enable - EPRXFOVREN: u1, - reserved6: u1, - /// Back-to-back SETUP packets interrupt enable - BTBSTPEN: u1, - padding: u25, - }), - /// device all endpoints interrupt register (DAEPINT) - DAEPINT: mmio.Mmio(packed struct(u32) { - /// Device all IN endpoint interrupt bits - IEPITB: u4, - reserved16: u12, - /// Device all OUT endpoint interrupt bits - OEPITB: u4, - padding: u12, - }), - /// Device all endpoints interrupt enable register (DAEPINTEN) - DAEPINTEN: mmio.Mmio(packed struct(u32) { - /// IN EP interrupt interrupt enable bits - IEPIE: u4, - reserved16: u12, - /// OUT endpoint interrupt enable bits - OEPIE: u4, - padding: u12, - }), - reserved40: [8]u8, - /// device VBUS discharge time register - DVBUSDT: mmio.Mmio(packed struct(u32) { - /// Device VBUS discharge time - DVBUSDT: u16, - padding: u16, - }), - /// device VBUS pulsing time register - DVBUSPT: mmio.Mmio(packed struct(u32) { - /// Device VBUS pulsing time - DVBUSPT: u12, - padding: u20, - }), - reserved52: [4]u8, - /// device IN endpoint FIFO empty interrupt enable register - DIEPFEINTEN: mmio.Mmio(packed struct(u32) { - /// IN EP Tx FIFO empty interrupt enable bits - IEPTXFEIE: u4, - padding: u28, - }), - reserved256: [200]u8, - /// device IN endpoint 0 control register (DIEP0CTL) - DIEP0CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet length - MPL: u2, - reserved15: u13, - /// endpoint active - EPACT: u1, - reserved17: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved21: u1, - /// STALL handshake - STALL: u1, - /// TxFIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved30: u2, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved264: [4]u8, - /// device endpoint-0 interrupt register - DIEP0INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved3: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved6: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding: u24, - }), - reserved272: [4]u8, - /// device IN endpoint-0 transfer length register - DIEP0LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u7, - reserved19: u12, - /// Packet count - PCNT: u2, - padding: u11, - }), - reserved280: [4]u8, - /// device IN endpoint 0 transmit FIFO status register - DIEP0TFSTAT: mmio.Mmio(packed struct(u32) { - /// IN endpoint TxFIFO space remaining - IEPTFS: u16, - padding: u16, - }), - reserved288: [4]u8, - /// device in endpoint-1 control register - DIEP1CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved21: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved296: [4]u8, - /// device endpoint-1 interrupt register - DIEP1INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved3: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved6: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding: u24, - }), - reserved304: [4]u8, - /// device IN endpoint-1 transfer length register - DIEP1LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding: u1, - }), - reserved312: [4]u8, - /// device IN endpoint 1 transmit FIFO status register - DIEP1TFSTAT: mmio.Mmio(packed struct(u32) { - /// IN endpoint TxFIFO space remaining - IEPTFS: u16, - padding: u16, - }), - reserved320: [4]u8, - /// device endpoint-2 control register - DIEP2CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved21: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved328: [4]u8, - /// device endpoint-2 interrupt register - DIEP2INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved3: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved6: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding: u24, - }), - reserved336: [4]u8, - /// device IN endpoint-2 transfer length register - DIEP2LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding: u1, - }), - reserved344: [4]u8, - /// device IN endpoint 2 transmit FIFO status register - DIEP2TFSTAT: mmio.Mmio(packed struct(u32) { - /// IN endpoint TxFIFO space remaining - IEPTFS: u16, - padding: u16, - }), - reserved352: [4]u8, - /// device endpoint-3 control register - DIEP3CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - reserved21: u1, - /// STALL handshake - STALL: u1, - /// Tx FIFO number - TXFNUM: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVNFRM - SD0PID_SEVENFRM: u1, - /// Set DATA1 PID/Set odd frame - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved360: [4]u8, - /// device endpoint-3 interrupt register - DIEP3INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint finished - EPDIS: u1, - reserved3: u1, - /// Control in timeout interrupt - CITO: u1, - /// Endpoint Tx FIFO underrun - EPTXFUD: u1, - reserved6: u1, - /// IN endpoint NAK effective - IEPNE: u1, - /// Transmit FIFO empty - TXFE: u1, - padding: u24, - }), - reserved368: [4]u8, - /// device IN endpoint-3 transfer length register - DIEP3LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Multi packet count per frame - MCPF: u2, - padding: u1, - }), - reserved376: [4]u8, - /// device IN endpoint 3 transmit FIFO status register - DIEP3TFSTAT: mmio.Mmio(packed struct(u32) { - /// IN endpoint TxFIFO space remaining - IEPTFS: u16, - padding: u16, - }), - reserved768: [388]u8, - /// device endpoint-0 control register - DOEP0CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet length - MPL: u2, - reserved15: u13, - /// Endpoint active - EPACT: u1, - reserved17: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved26: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - reserved30: u2, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved776: [4]u8, - /// device out endpoint-0 interrupt flag register - DOEP0INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved3: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved6: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding: u25, - }), - reserved784: [4]u8, - /// device OUT endpoint-0 transfer length register - DOEP0LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u7, - reserved19: u12, - /// Packet count - PCNT: u1, - reserved29: u9, - /// SETUP packet count - STPCNT: u2, - padding: u1, - }), - reserved800: [12]u8, - /// device endpoint-1 control register - DOEP1CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved26: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved808: [4]u8, - /// device out endpoint-1 interrupt flag register - DOEP1INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved3: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved6: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding: u25, - }), - reserved816: [4]u8, - /// device OUT endpoint-1 transfer length register - DOEP1LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding: u1, - }), - reserved832: [12]u8, - /// device endpoint-2 control register - DOEP2CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved26: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved840: [4]u8, - /// device out endpoint-2 interrupt flag register - DOEP2INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved3: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved6: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding: u25, - }), - reserved848: [4]u8, - /// device OUT endpoint-2 transfer length register - DOEP2LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding: u1, - }), - reserved864: [12]u8, - /// device endpoint-3 control register - DOEP3CTL: mmio.Mmio(packed struct(u32) { - /// maximum packet length - MPL: u11, - reserved15: u4, - /// Endpoint active - EPACT: u1, - /// EOFRM/DPID - EOFRM_DPID: u1, - /// NAK status - NAKS: u1, - /// Endpoint type - EPTYPE: u2, - /// Snoop mode - SNOOP: u1, - /// STALL handshake - STALL: u1, - reserved26: u4, - /// Clear NAK - CNAK: u1, - /// Set NAK - SNAK: u1, - /// SD0PID/SEVENFRM - SD0PID_SEVENFRM: u1, - /// SD1PID/SODDFRM - SD1PID_SODDFRM: u1, - /// Endpoint disable - EPD: u1, - /// Endpoint enable - EPEN: u1, - }), - reserved872: [4]u8, - /// device out endpoint-3 interrupt flag register - DOEP3INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Endpoint disabled - EPDIS: u1, - reserved3: u1, - /// Setup phase finished - STPF: u1, - /// Endpoint Rx FIFO overrun - EPRXFOVR: u1, - reserved6: u1, - /// Back-to-back SETUP packets - BTBSTP: u1, - padding: u25, - }), - reserved880: [4]u8, - /// device OUT endpoint-3 transfer length register - DOEP3LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// SETUP packet count/Received data PID - STPCNT_RXDPID: u2, - padding: u1, - }), - }; - - /// USB on the go full speed host - pub const USBFS_HOST = extern struct { - /// host configuration register (HCTL) - HCTL: mmio.Mmio(packed struct(u32) { - /// clock select for USB clock - CLKSEL: u2, - padding: u30, - }), - /// Host frame interval register - HFT: mmio.Mmio(packed struct(u32) { - /// Frame interval - FRI: u16, - padding: u16, - }), - /// FS host frame number/frame time remaining register (HFINFR) - HFINFR: mmio.Mmio(packed struct(u32) { - /// Frame number - FRNUM: u16, - /// Frame remaining time - FRT: u16, - }), - reserved16: [4]u8, - /// Host periodic transmit FIFO/queue status register (HPTFQSTAT) - HPTFQSTAT: mmio.Mmio(packed struct(u32) { - /// Periodic transmit data FIFO space available - PTXFS: u16, - /// Periodic transmit request queue space available - PTXREQS: u8, - /// Top of the periodic transmit request queue - PTXREQT: u8, - }), - /// Host all channels interrupt register - HACHINT: mmio.Mmio(packed struct(u32) { - /// Host all channel interrupts - HACHINT: u8, - padding: u24, - }), - /// host all channels interrupt mask register - HACHINTEN: mmio.Mmio(packed struct(u32) { - /// Channel interrupt enable - CINTEN: u8, - padding: u24, - }), - reserved64: [36]u8, - /// Host port control and status register (USBFS_HPCS) - HPCS: mmio.Mmio(packed struct(u32) { - /// Port connect status - PCST: u1, - /// Port connect detected - PCD: u1, - /// Port enable - PE: u1, - /// Port enable/disable change - PEDC: u1, - reserved6: u2, - /// Port resume - PREM: u1, - /// Port suspend - PSP: u1, - /// Port reset - PRST: u1, - reserved10: u1, - /// Port line status - PLST: u2, - /// Port power - PP: u1, - reserved17: u4, - /// Port speed - PS: u2, - padding: u13, - }), - reserved256: [188]u8, - /// host channel-0 characteristics register (HCH0CTL) - HCH0CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved264: [4]u8, - /// host channel-0 interrupt register (USBFS_HCHxINTF) - HCH0INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-0 interrupt enable register (HCH0INTEN) - HCH0INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-0 transfer length register - HCH0LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved288: [12]u8, - /// host channel-1 characteristics register (HCH1CTL) - HCH1CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved296: [4]u8, - /// host channel-1 interrupt register (HCH1INTF) - HCH1INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-1 interrupt enable register (HCH1INTEN) - HCH1INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-1 transfer length register - HCH1LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved320: [12]u8, - /// host channel-2 characteristics register (HCH2CTL) - HCH2CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved328: [4]u8, - /// host channel-2 interrupt register (HCH2INTF) - HCH2INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-2 interrupt enable register (HCH2INTEN) - HCH2INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-2 transfer length register - HCH2LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved352: [12]u8, - /// host channel-3 characteristics register (HCH3CTL) - HCH3CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved360: [4]u8, - /// host channel-3 interrupt register (HCH3INTF) - HCH3INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-3 interrupt enable register (HCH3INTEN) - HCH3INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-3 transfer length register - HCH3LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved384: [12]u8, - /// host channel-4 characteristics register (HCH4CTL) - HCH4CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved392: [4]u8, - /// host channel-4 interrupt register (HCH4INTF) - HCH4INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-4 interrupt enable register (HCH4INTEN) - HCH4INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-4 transfer length register - HCH4LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved416: [12]u8, - /// host channel-5 characteristics register (HCH5CTL) - HCH5CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved424: [4]u8, - /// host channel-5 interrupt register (HCH5INTF) - HCH5INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-5 interrupt enable register (HCH5INTEN) - HCH5INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-5 transfer length register - HCH5LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved448: [12]u8, - /// host channel-6 characteristics register (HCH6CTL) - HCH6CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved456: [4]u8, - /// host channel-6 interrupt register (HCH6INTF) - HCH6INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-6 interrupt enable register (HCH6INTEN) - HCH6INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-6 transfer length register - HCH6LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - reserved480: [12]u8, - /// host channel-7 characteristics register (HCH7CTL) - HCH7CTL: mmio.Mmio(packed struct(u32) { - /// Maximum packet size - MPL: u11, - /// Endpoint number - EPNUM: u4, - /// Endpoint direction - EPDIR: u1, - reserved17: u1, - /// Low-speed device - LSD: u1, - /// Endpoint type - EPTYPE: u2, - reserved22: u2, - /// Device address - DAR: u7, - /// Odd frame - ODDFRM: u1, - /// Channel disable - CDIS: u1, - /// Channel enable - CEN: u1, - }), - reserved488: [4]u8, - /// host channel-7 interrupt register (HCH7INTF) - HCH7INTF: mmio.Mmio(packed struct(u32) { - /// Transfer finished - TF: u1, - /// Channel halted - CH: u1, - reserved3: u1, - /// STALL response received interrupt - STALL: u1, - /// NAK response received interrupt - NAK: u1, - /// ACK response received/transmitted interrupt - ACK: u1, - reserved7: u1, - /// USB bus error - USBER: u1, - /// Babble error - BBER: u1, - /// Request queue overrun - REQOVR: u1, - /// Data toggle error - DTER: u1, - padding: u21, - }), - /// host channel-7 interrupt enable register (HCH7INTEN) - HCH7INTEN: mmio.Mmio(packed struct(u32) { - /// Transfer completed interrupt enable - TFIE: u1, - /// Channel halted interrupt enable - CHIE: u1, - reserved3: u1, - /// STALL interrupt enable - STALLIE: u1, - /// NAK interrupt enable - NAKIE: u1, - /// ACK interrupt enable - ACKIE: u1, - reserved7: u1, - /// USB bus error interrupt enable - USBERIE: u1, - /// Babble error interrupt enable - BBERIE: u1, - /// request queue overrun interrupt enable - REQOVRIE: u1, - /// Data toggle error interrupt enable - DTERIE: u1, - padding: u21, - }), - /// host channel-7 transfer length register - HCH7LEN: mmio.Mmio(packed struct(u32) { - /// Transfer length - TLEN: u19, - /// Packet count - PCNT: u10, - /// Data PID - DPID: u2, - padding: u1, - }), - }; - - /// USB full speed global registers - pub const USBFS_GLOBAL = extern struct { - /// Global OTG control and status register (USBFS_GOTGCS) - GOTGCS: mmio.Mmio(packed struct(u32) { - /// SRP success - SRPS: u1, - /// SRP request - SRPREQ: u1, - reserved8: u6, - /// Host success - HNPS: u1, - /// HNP request - HNPREQ: u1, - /// Host HNP enable - HHNPEN: u1, - /// Device HNP enabled - DHNPEN: u1, - reserved16: u4, - /// ID pin status - IDPS: u1, - /// Debounce interval - DI: u1, - /// A-session valid - ASV: u1, - /// B-session valid - BSV: u1, - padding: u12, - }), - /// Global OTG interrupt flag register (USBFS_GOTGINTF) - GOTGINTF: mmio.Mmio(packed struct(u32) { - reserved2: u2, - /// Session end - SESEND: u1, - reserved8: u5, - /// Session request success status change - SRPEND: u1, - /// HNP end - HNPEND: u1, - reserved17: u7, - /// Host negotiation request detected - HNPDET: u1, - /// A-device timeout - ADTO: u1, - /// Debounce finish - DF: u1, - padding: u12, - }), - /// Global AHB control and status register (USBFS_GAHBCS) - GAHBCS: mmio.Mmio(packed struct(u32) { - /// Global interrupt enable - GINTEN: u1, - reserved7: u6, - /// Tx FIFO threshold - TXFTH: u1, - /// Periodic Tx FIFO threshold - PTXFTH: u1, - padding: u23, - }), - /// Global USB control and status register (USBFS_GUSBCSR) - GUSBCS: mmio.Mmio(packed struct(u32) { - /// Timeout calibration - TOC: u3, - reserved8: u5, - /// SRP capability enable - SRPCEN: u1, - /// HNP capability enable - HNPCEN: u1, - /// USB turnaround time - UTT: u4, - reserved29: u15, - /// Force host mode - FHM: u1, - /// Force device mode - FDM: u1, - padding: u1, - }), - /// Global reset control register (USBFS_GRSTCTL) - GRSTCTL: mmio.Mmio(packed struct(u32) { - /// Core soft reset - CSRST: u1, - /// HCLK soft reset - HCSRST: u1, - /// Host frame counter reset - HFCRST: u1, - reserved4: u1, - /// RxFIFO flush - RXFF: u1, - /// TxFIFO flush - TXFF: u1, - /// TxFIFO number - TXFNUM: u5, - padding: u21, - }), - /// Global interrupt flag register (USBFS_GINTF) - GINTF: mmio.Mmio(packed struct(u32) { - /// Current operation mode - COPM: u1, - /// Mode fault interrupt flag - MFIF: u1, - /// OTG interrupt flag - OTGIF: u1, - /// Start of frame - SOF: u1, - /// RxFIFO non-empty interrupt flag - RXFNEIF: u1, - /// Non-periodic TxFIFO empty interrupt flag - NPTXFEIF: u1, - /// Global Non-Periodic IN NAK effective - GNPINAK: u1, - /// Global OUT NAK effective - GONAK: u1, - reserved10: u2, - /// Early suspend - ESP: u1, - /// USB suspend - SP: u1, - /// USB reset - RST: u1, - /// Enumeration finished - ENUMF: u1, - /// Isochronous OUT packet dropped interrupt - ISOOPDIF: u1, - /// End of periodic frame interrupt flag - EOPFIF: u1, - reserved18: u2, - /// IN endpoint interrupt flag - IEPIF: u1, - /// OUT endpoint interrupt flag - OEPIF: u1, - /// Isochronous IN transfer Not Complete Interrupt Flag - ISOINCIF: u1, - /// periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) - PXNCIF_ISOONCIF: u1, - reserved24: u2, - /// Host port interrupt flag - HPIF: u1, - /// Host channels interrupt flag - HCIF: u1, - /// Periodic TxFIFO empty interrupt flag - PTXFEIF: u1, - reserved28: u1, - /// ID pin status change - IDPSC: u1, - /// Disconnect interrupt flag - DISCIF: u1, - /// Session interrupt flag - SESIF: u1, - /// Wakeup interrupt flag - WKUPIF: u1, - }), - /// Global interrupt enable register (USBFS_GINTEN) - GINTEN: mmio.Mmio(packed struct(u32) { - reserved1: u1, - /// Mode fault interrupt enable - MFIE: u1, - /// OTG interrupt enable - OTGIE: u1, - /// Start of frame interrupt enable - SOFIE: u1, - /// Receive FIFO non-empty interrupt enable - RXFNEIE: u1, - /// Non-periodic TxFIFO empty interrupt enable - NPTXFEIE: u1, - /// Global non-periodic IN NAK effective interrupt enable - GNPINAKIE: u1, - /// Global OUT NAK effective interrupt enable - GONAKIE: u1, - reserved10: u2, - /// Early suspend interrupt enable - ESPIE: u1, - /// USB suspend interrupt enable - SPIE: u1, - /// USB reset interrupt enable - RSTIE: u1, - /// Enumeration finish interrupt enable - ENUMFIE: u1, - /// Isochronous OUT packet dropped interrupt enable - ISOOPDIE: u1, - /// End of periodic frame interrupt enable - EOPFIE: u1, - reserved18: u2, - /// IN endpoints interrupt enable - IEPIE: u1, - /// OUT endpoints interrupt enable - OEPIE: u1, - /// isochronous IN transfer not complete interrupt enable - ISOINCIE: u1, - /// periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) - PXNCIE_ISOONCIE: u1, - reserved24: u2, - /// Host port interrupt enable - HPIE: u1, - /// Host channels interrupt enable - HCIE: u1, - /// Periodic TxFIFO empty interrupt enable - PTXFEIE: u1, - reserved28: u1, - /// ID pin status change interrupt enable - IDPSCIE: u1, - /// Disconnect interrupt enable - DISCIE: u1, - /// Session interrupt enable - SESIE: u1, - /// Wakeup interrupt enable - WKUPIE: u1, - }), - /// Global Receive status read(Device mode) - GRSTATR_Device: mmio.Mmio(packed struct(u32) { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Recieve packet status - RPCKST: u4, - padding: u11, - }), - /// Global Receive status pop(Device mode) - GRSTATP_Device: mmio.Mmio(packed struct(u32) { - /// Endpoint number - EPNUM: u4, - /// Byte count - BCOUNT: u11, - /// Data PID - DPID: u2, - /// Recieve packet status - RPCKST: u4, - padding: u11, - }), - /// Global Receive FIFO size register (USBFS_GRFLEN) - GRFLEN: mmio.Mmio(packed struct(u32) { - /// Rx FIFO depth - RXFD: u16, - padding: u16, - }), - /// Host non-periodic transmit FIFO length register (Host mode) - HNPTFLEN: mmio.Mmio(packed struct(u32) { - /// host non-periodic transmit Tx RAM start address - HNPTXRSAR: u16, - /// host non-periodic TxFIFO depth - HNPTXFD: u16, - }), - /// Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) - HNPTFQSTAT: mmio.Mmio(packed struct(u32) { - /// Non-periodic TxFIFO space - NPTXFS: u16, - /// Non-periodic transmit request queue space - NPTXRQS: u8, - /// Top of the non-periodic transmit request queue - NPTXRQTOP: u7, - padding: u1, - }), - reserved56: [8]u8, - /// Global core configuration register (USBFS_GCCFG) - GCCFG: mmio.Mmio(packed struct(u32) { - reserved16: u16, - /// Power on - PWRON: u1, - reserved18: u1, - /// The VBUS A-device Comparer enable - VBUSACEN: u1, - /// The VBUS B-device Comparer enable - VBUSBCEN: u1, - /// SOF output enable - SOFOEN: u1, - /// VBUS ignored - VBUSIG: u1, - padding: u10, - }), - /// core ID register - CID: mmio.Mmio(packed struct(u32) { - /// Core ID - CID: u32, - }), - reserved256: [192]u8, - /// Host periodic transmit FIFO length register (HPTFLEN) - HPTFLEN: mmio.Mmio(packed struct(u32) { - /// Host periodic TxFIFO start address - HPTXFSAR: u16, - /// Host periodic TxFIFO depth - HPTXFD: u16, - }), - /// device IN endpoint transmit FIFO size register (DIEP1TFLEN) - DIEP1TFLEN: mmio.Mmio(packed struct(u32) { - /// IN endpoint FIFO transmit RAM start address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), - /// device IN endpoint transmit FIFO size register (DIEP2TFLEN) - DIEP2TFLEN: mmio.Mmio(packed struct(u32) { - /// IN endpoint FIFO transmit RAM start address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), - /// device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN) - DIEP3TFLEN: mmio.Mmio(packed struct(u32) { - /// IN endpoint FIFO4 transmit RAM start address - IEPTXRSAR: u16, - /// IN endpoint TxFIFO depth - IEPTXFD: u16, - }), - }; - - /// Inter integrated circuit - pub const I2C0 = extern struct { - /// Control register 0 - CTL0: mmio.Mmio(packed struct(u16) { - /// I2C peripheral enable - I2CEN: u1, - /// SMBus/I2C mode switch - SMBEN: u1, - reserved3: u1, - /// SMBusType Selection - SMBSEL: u1, - /// ARP protocol in SMBus switch - ARPEN: u1, - /// PEC Calculation Switch - PECEN: u1, - /// Whether or not to response to a General Call (0x00) - GCEN: u1, - /// Whether to stretch SCL low when data is not ready in slave mode - SS: u1, - /// Generate a START condition on I2C bus - START: u1, - /// Generate a STOP condition on I2C bus - STOP: u1, - /// Whether or not to send an ACK - ACKEN: u1, - /// Position of ACK and PEC when receiving - POAP: u1, - /// PEC Transfer - PECTRANS: u1, - /// SMBus alert - SALT: u1, - reserved15: u1, - /// Software reset - SRESET: u1, - }), - reserved4: [2]u8, - /// Control register 1 - CTL1: mmio.Mmio(packed struct(u16) { - /// I2C Peripheral clock frequency - I2CCLK: u6, - reserved8: u2, - /// Error interrupt enable - ERRIE: u1, - /// Event interrupt enable - EVIE: u1, - /// Buffer interrupt enable - BUFIE: u1, - /// DMA mode switch - DMAON: u1, - /// Flag indicating DMA last transfer - DMALST: u1, - padding: u3, - }), - reserved8: [2]u8, - /// Slave address register 0 - SADDR0: mmio.Mmio(packed struct(u16) { - /// Bit 0 of a 10-bit address - ADDRESS0: u1, - /// 7-bit address or bits 7:1 of a 10-bit address - ADDRESS7_1: u7, - /// Highest two bits of a 10-bit address - ADDRESS9_8: u2, - reserved15: u5, - /// Address mode for the I2C slave - ADDFORMAT: u1, - }), - reserved12: [2]u8, - /// Slave address register 1 - SADDR1: mmio.Mmio(packed struct(u16) { - /// Dual-Address mode switch - DUADEN: u1, - /// Second I2C address for the slave in Dual-Address mode - ADDRESS2: u7, - padding: u8, - }), - reserved16: [2]u8, - /// Transfer buffer register - DATA: mmio.Mmio(packed struct(u16) { - /// Transmission or reception data buffer register - TRB: u8, - padding: u8, - }), - reserved20: [2]u8, - /// Transfer status register 0 - STAT0: mmio.Mmio(packed struct(u16) { - /// START condition sent out in master mode - SBSEND: u1, - /// Address is sent in master mode or received and matches in slave mode - ADDSEND: u1, - /// Byte transmission completed - BTC: u1, - /// Header of 10-bit address is sent in master mode - ADD10SEND: u1, - /// STOP condition detected in slave mode - STPDET: u1, - reserved6: u1, - /// I2C_DATA is not Empty during receiving - RBNE: u1, - /// I2C_DATA is Empty during transmitting - TBE: u1, - /// A bus error occurs indication a unexpected START or STOP condition on I2C bus - BERR: u1, - /// Arbitration Lost in master mode - LOSTARB: u1, - /// Acknowledge error - AERR: u1, - /// Over-run or under-run situation occurs in slave mode - OUERR: u1, - /// PEC error when receiving data - PECERR: u1, - reserved14: u1, - /// Timeout signal in SMBus mode - SMBTO: u1, - /// SMBus Alert status - SMBALT: u1, - }), - reserved24: [2]u8, - /// Transfer status register 1 - STAT1: mmio.Mmio(packed struct(u16) { - /// A flag indicating whether I2C block is in master or slave mode - MASTER: u1, - /// Busy flag - I2CBSY: u1, - /// Whether the I2C is a transmitter or a receiver - TR: u1, - reserved4: u1, - /// General call address (00h) received - RXGC: u1, - /// Default address of SMBusDevice - DEFSMB: u1, - /// SMBus Host Header detected in slave mode - HSTSMB: u1, - /// Dual Flag in slave mode - DUMODF: u1, - /// Packet Error Checking Value that calculated by hardware when PEC is enabled - PECV: u8, - }), - reserved28: [2]u8, - /// Clock configure register - CKCFG: mmio.Mmio(packed struct(u16) { - /// I2C Clock control in master mode - CLKC: u12, - reserved14: u2, - /// Duty cycle in fast mode - DTCY: u1, - /// I2C speed selection in master mode - FAST: u1, - }), - reserved32: [2]u8, - /// Rise time register - RT: mmio.Mmio(packed struct(u16) { - /// Maximum rise time in master mode - RISETIME: u6, - padding: u10, - }), - }; - - /// Basic-timers - pub const TIMER5 = extern struct { - /// control register 0 - CTL0: mmio.Mmio(packed struct(u16) { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - reserved7: u3, - /// Auto-reload shadow enable - ARSE: u1, - padding: u8, - }), - reserved4: [2]u8, - /// control register 1 - CTL1: mmio.Mmio(packed struct(u16) { - reserved4: u4, - /// Master mode control - MMC: u3, - padding: u9, - }), - reserved12: [6]u8, - /// DMA/Interrupt enable register - DMAINTEN: mmio.Mmio(packed struct(u16) { - /// Update interrupt enable - UPIE: u1, - reserved8: u7, - /// Update DMA request enable - UPDEN: u1, - padding: u7, - }), - reserved16: [2]u8, - /// Interrupt flag register - INTF: mmio.Mmio(packed struct(u16) { - /// Update interrupt flag - UPIF: u1, - padding: u15, - }), - reserved20: [2]u8, - /// event generation register - SWEVG: mmio.Mmio(packed struct(u16) { - /// Update generation - UPG: u1, - padding: u15, - }), - reserved36: [14]u8, - /// Counter register - CNT: mmio.Mmio(packed struct(u16) { - /// Low counter value - CNT: u16, - }), - reserved40: [2]u8, - /// Prescaler register - PSC: mmio.Mmio(packed struct(u16) { - /// Prescaler value of the counter clock - PSC: u16, - }), - reserved44: [2]u8, - /// Counter auto reload register - CAR: mmio.Mmio(packed struct(u16) { - /// Counter auto reload value - CARL: u16, - }), - }; - - /// Enhanced Core Local Interrupt Controller - pub const ECLIC = extern struct { - /// cliccfg Register - CLICCFG: mmio.Mmio(packed struct(u8) { - reserved1: u1, - /// NLBITS - NLBITS: u4, - padding: u3, - }), - reserved4: [3]u8, - /// clicinfo Register - CLICINFO: mmio.Mmio(packed struct(u32) { - /// NUM_INTERRUPT - NUM_INTERRUPT: u13, - /// VERSION - VERSION: u8, - /// CLICINTCTLBITS - CLICINTCTLBITS: u4, - padding: u7, - }), - reserved11: [3]u8, - /// MTH Register - MTH: mmio.Mmio(packed struct(u8) { - /// MTH - MTH: u8, - }), - reserved4096: [4084]u8, - /// clicintip Register - CLICINTIP_0: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_0: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_0: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_0: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_1: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_1: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_1: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_1: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_2: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_2: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_2: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_2: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_3: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_3: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_3: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_3: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_4: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_4: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_4: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_4: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_5: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_5: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_5: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_5: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_6: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_6: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_6: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_6: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_7: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_7: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_7: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_7: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_8: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_8: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_8: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_8: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_9: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_9: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_9: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_9: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_10: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_10: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_10: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_10: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_11: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_11: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_11: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_11: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_12: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_12: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_12: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_12: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_13: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_13: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_13: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_13: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_14: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_14: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_14: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_14: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_15: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_15: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_15: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_15: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_16: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_16: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_16: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_16: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_17: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_17: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_17: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_17: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_18: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_18: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_18: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_18: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_19: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_19: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_19: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_19: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_20: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_20: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_20: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_20: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_21: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_21: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_21: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_21: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_22: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_22: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_22: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_22: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_23: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_23: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_23: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_23: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_24: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_24: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_24: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_24: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_25: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_25: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_25: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_25: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_26: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_26: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_26: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_26: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_27: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_27: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_27: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_27: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_28: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_28: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_28: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_28: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_29: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_29: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_29: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_29: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_30: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_30: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_30: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_30: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_31: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_31: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_31: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_31: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_32: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_32: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_32: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_32: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_33: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_33: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_33: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_33: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_34: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_34: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_34: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_34: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_35: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_35: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_35: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_35: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_36: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_36: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_36: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_36: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_37: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_37: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_37: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_37: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_38: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_38: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_38: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_38: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_39: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_39: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_39: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_39: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_40: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_40: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_40: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_40: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_41: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_41: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_41: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_41: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_42: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_42: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_42: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_42: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_43: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_43: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_43: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_43: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_44: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_44: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_44: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_44: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_45: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_45: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_45: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_45: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_46: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_46: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_46: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_46: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_47: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_47: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_47: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_47: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_48: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_48: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_48: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_48: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_49: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_49: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_49: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_49: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_50: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_50: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_50: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_50: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_51: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_51: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_51: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_51: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_52: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_52: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_52: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_52: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_53: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_53: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_53: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_53: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_54: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_54: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_54: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_54: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_55: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_55: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_55: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_55: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_56: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_56: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_56: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_56: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_57: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_57: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_57: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_57: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_58: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_58: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_58: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_58: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_59: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_59: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_59: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_59: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_60: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_60: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_60: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_60: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_61: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_61: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_61: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_61: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_62: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_62: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_62: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_62: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_63: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_63: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_63: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_63: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_64: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_64: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_64: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_64: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_65: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_65: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_65: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_65: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_66: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_66: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_66: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_66: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_67: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_67: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_67: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_67: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_68: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_68: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_68: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_68: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_69: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_69: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_69: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_69: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_70: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_70: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_70: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_70: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_71: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_71: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_71: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_71: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_72: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_72: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_72: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_72: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_73: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_73: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_73: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_73: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_74: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_74: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_74: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_74: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_75: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_75: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_75: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_75: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_76: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_76: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_76: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_76: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_77: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_77: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_77: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_77: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_78: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_78: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_78: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_78: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_79: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_79: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_79: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_79: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_80: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_80: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_80: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_80: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_81: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_81: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_81: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_81: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_82: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_82: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_82: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_82: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_83: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_83: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_83: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_83: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_84: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_84: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_84: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_84: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - reserved4437: [1]u8, - /// clicintie Register - CLICINTIE_85: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_85: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_85: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_85: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - /// clicintie Register - CLICINTIE_86: mmio.Mmio(packed struct(u8) { - /// IE - IE: u1, - padding: u7, - }), - /// clicintattr Register - CLICINTATTR_86: mmio.Mmio(packed struct(u8) { - /// SHV - SHV: u1, - /// TRIG - TRIG: u2, - padding: u5, - }), - /// clicintctl Register - CLICINTCTL_86: mmio.Mmio(packed struct(u8) { - /// LEVEL_PRIORITY - LEVEL_PRIORITY: u8, - }), - /// clicintip Register - CLICINTIP_86: mmio.Mmio(packed struct(u8) { - /// IP - IP: u1, - padding: u7, - }), - }; - - /// Power management unit - pub const PMU = extern struct { - /// power control register - CTL: mmio.Mmio(packed struct(u32) { - /// LDO Low Power Mode - LDOLP: u1, - /// Standby Mode - STBMOD: u1, - /// Wakeup Flag Reset - WURST: u1, - /// Standby Flag Reset - STBRST: u1, - /// Low Voltage Detector Enable - LVDEN: u1, - /// Low Voltage Detector Threshold - LVDT: u3, - /// Backup Domain Write Enable - BKPWEN: u1, - padding: u23, - }), - /// power control/status register - CS: mmio.Mmio(packed struct(u32) { - /// Wakeup flag - WUF: u1, - /// Standby flag - STBF: u1, - /// Low Voltage Detector Status Flag - LVDF: u1, - reserved8: u5, - /// Enable WKUP pin - WUPEN: u1, - padding: u23, - }), - }; - - /// Reset and clock unit - pub const RCU = extern struct { - /// Control register - CTL: mmio.Mmio(packed struct(u32) { - /// Internal 8MHz RC oscillator Enable - IRC8MEN: u1, - /// IRC8M Internal 8MHz RC Oscillator stabilization Flag - IRC8MSTB: u1, - reserved3: u1, - /// Internal 8MHz RC Oscillator clock trim adjust value - IRC8MADJ: u5, - /// Internal 8MHz RC Oscillator calibration value register - IRC8MCALIB: u8, - /// External High Speed oscillator Enable - HXTALEN: u1, - /// External crystal oscillator (HXTAL) clock stabilization flag - HXTALSTB: u1, - /// External crystal oscillator (HXTAL) clock bypass mode enable - HXTALBPS: u1, - /// HXTAL Clock Monitor Enable - CKMEN: u1, - reserved24: u4, - /// PLL enable - PLLEN: u1, - /// PLL Clock Stabilization Flag - PLLSTB: u1, - /// PLL1 enable - PLL1EN: u1, - /// PLL1 Clock Stabilization Flag - PLL1STB: u1, - /// PLL2 enable - PLL2EN: u1, - /// PLL2 Clock Stabilization Flag - PLL2STB: u1, - padding: u2, - }), - /// Clock configuration register 0 (RCU_CFG0) - CFG0: mmio.Mmio(packed struct(u32) { - /// System clock switch - SCS: u2, - /// System clock switch status - SCSS: u2, - /// AHB prescaler selection - AHBPSC: u4, - /// APB1 prescaler selection - APB1PSC: u3, - /// APB2 prescaler selection - APB2PSC: u3, - /// ADC clock prescaler selection - ADCPSC_1_0: u2, - /// PLL Clock Source Selection - PLLSEL: u1, - /// The LSB of PREDV0 division factor - PREDV0_LSB: u1, - /// The PLL clock multiplication factor - PLLMF_3_0: u4, - /// USBFS clock prescaler selection - USBFSPSC: u2, - /// CKOUT0 Clock Source Selection - CKOUT0SEL: u4, - /// Bit 2 of ADCPSC - ADCPSC_2: u1, - /// Bit 4 of PLLMF - PLLMF_4: u1, - padding: u2, - }), - /// Clock interrupt register (RCU_INT) - INT: mmio.Mmio(packed struct(u32) { - /// IRC40K stabilization interrupt flag - IRC40KSTBIF: u1, - /// LXTAL stabilization interrupt flag - LXTALSTBIF: u1, - /// IRC8M stabilization interrupt flag - IRC8MSTBIF: u1, - /// HXTAL stabilization interrupt flag - HXTALSTBIF: u1, - /// PLL stabilization interrupt flag - PLLSTBIF: u1, - /// PLL1 stabilization interrupt flag - PLL1STBIF: u1, - /// PLL2 stabilization interrupt flag - PLL2STBIF: u1, - /// HXTAL Clock Stuck Interrupt Flag - CKMIF: u1, - /// IRC40K Stabilization interrupt enable - IRC40KSTBIE: u1, - /// LXTAL Stabilization Interrupt Enable - LXTALSTBIE: u1, - /// IRC8M Stabilization Interrupt Enable - IRC8MSTBIE: u1, - /// HXTAL Stabilization Interrupt Enable - HXTALSTBIE: u1, - /// PLL Stabilization Interrupt Enable - PLLSTBIE: u1, - /// PLL1 Stabilization Interrupt Enable - PLL1STBIE: u1, - /// PLL2 Stabilization Interrupt Enable - PLL2STBIE: u1, - reserved16: u1, - /// IRC40K Stabilization Interrupt Clear - IRC40KSTBIC: u1, - /// LXTAL Stabilization Interrupt Clear - LXTALSTBIC: u1, - /// IRC8M Stabilization Interrupt Clear - IRC8MSTBIC: u1, - /// HXTAL Stabilization Interrupt Clear - HXTALSTBIC: u1, - /// PLL stabilization Interrupt Clear - PLLSTBIC: u1, - /// PLL1 stabilization Interrupt Clear - PLL1STBIC: u1, - /// PLL2 stabilization Interrupt Clear - PLL2STBIC: u1, - /// HXTAL Clock Stuck Interrupt Clear - CKMIC: u1, - padding: u8, - }), - /// APB2 reset register (RCU_APB2RST) - APB2RST: mmio.Mmio(packed struct(u32) { - /// Alternate function I/O reset - AFRST: u1, - reserved2: u1, - /// GPIO port A reset - PARST: u1, - /// GPIO port B reset - PBRST: u1, - /// GPIO port C reset - PCRST: u1, - /// GPIO port D reset - PDRST: u1, - /// GPIO port E reset - PERST: u1, - reserved9: u2, - /// ADC0 reset - ADC0RST: u1, - /// ADC1 reset - ADC1RST: u1, - /// Timer 0 reset - TIMER0RST: u1, - /// SPI0 reset - SPI0RST: u1, - reserved14: u1, - /// USART0 Reset - USART0RST: u1, - padding: u17, - }), - /// APB1 reset register (RCU_APB1RST) - APB1RST: mmio.Mmio(packed struct(u32) { - /// TIMER1 timer reset - TIMER1RST: u1, - /// TIMER2 timer reset - TIMER2RST: u1, - /// TIMER3 timer reset - TIMER3RST: u1, - /// TIMER4 timer reset - TIMER4RST: u1, - /// TIMER5 timer reset - TIMER5RST: u1, - /// TIMER6 timer reset - TIMER6RST: u1, - reserved11: u5, - /// Window watchdog timer reset - WWDGTRST: u1, - reserved14: u2, - /// SPI1 reset - SPI1RST: u1, - /// SPI2 reset - SPI2RST: u1, - reserved17: u1, - /// USART1 reset - USART1RST: u1, - /// USART2 reset - USART2RST: u1, - /// UART3 reset - UART3RST: u1, - /// UART4 reset - UART4RST: u1, - /// I2C0 reset - I2C0RST: u1, - /// I2C1 reset - I2C1RST: u1, - reserved25: u2, - /// CAN0 reset - CAN0RST: u1, - /// CAN1 reset - CAN1RST: u1, - /// Backup interface reset - BKPIRST: u1, - /// Power control reset - PMURST: u1, - /// DAC reset - DACRST: u1, - padding: u2, - }), - /// AHB enable register - AHBEN: mmio.Mmio(packed struct(u32) { - /// DMA0 clock enable - DMA0EN: u1, - /// DMA1 clock enable - DMA1EN: u1, - /// SRAM interface clock enable when sleep mode - SRAMSPEN: u1, - reserved4: u1, - /// FMC clock enable when sleep mode - FMCSPEN: u1, - reserved6: u1, - /// CRC clock enable - CRCEN: u1, - reserved8: u1, - /// EXMC clock enable - EXMCEN: u1, - reserved12: u3, - /// USBFS clock enable - USBFSEN: u1, - padding: u19, - }), - /// APB2 clock enable register (RCU_APB2EN) - APB2EN: mmio.Mmio(packed struct(u32) { - /// Alternate function IO clock enable - AFEN: u1, - reserved2: u1, - /// GPIO port A clock enable - PAEN: u1, - /// GPIO port B clock enable - PBEN: u1, - /// GPIO port C clock enable - PCEN: u1, - /// GPIO port D clock enable - PDEN: u1, - /// GPIO port E clock enable - PEEN: u1, - reserved9: u2, - /// ADC0 clock enable - ADC0EN: u1, - /// ADC1 clock enable - ADC1EN: u1, - /// TIMER0 clock enable - TIMER0EN: u1, - /// SPI0 clock enable - SPI0EN: u1, - reserved14: u1, - /// USART0 clock enable - USART0EN: u1, - padding: u17, - }), - /// APB1 clock enable register (RCU_APB1EN) - APB1EN: mmio.Mmio(packed struct(u32) { - /// TIMER1 timer clock enable - TIMER1EN: u1, - /// TIMER2 timer clock enable - TIMER2EN: u1, - /// TIMER3 timer clock enable - TIMER3EN: u1, - /// TIMER4 timer clock enable - TIMER4EN: u1, - /// TIMER5 timer clock enable - TIMER5EN: u1, - /// TIMER6 timer clock enable - TIMER6EN: u1, - reserved11: u5, - /// Window watchdog timer clock enable - WWDGTEN: u1, - reserved14: u2, - /// SPI1 clock enable - SPI1EN: u1, - /// SPI2 clock enable - SPI2EN: u1, - reserved17: u1, - /// USART1 clock enable - USART1EN: u1, - /// USART2 clock enable - USART2EN: u1, - /// UART3 clock enable - UART3EN: u1, - /// UART4 clock enable - UART4EN: u1, - /// I2C0 clock enable - I2C0EN: u1, - /// I2C1 clock enable - I2C1EN: u1, - reserved25: u2, - /// CAN0 clock enable - CAN0EN: u1, - /// CAN1 clock enable - CAN1EN: u1, - /// Backup interface clock enable - BKPIEN: u1, - /// Power control clock enable - PMUEN: u1, - /// DAC clock enable - DACEN: u1, - padding: u2, - }), - /// Backup domain control register (RCU_BDCTL) - BDCTL: mmio.Mmio(packed struct(u32) { - /// LXTAL enable - LXTALEN: u1, - /// External low-speed oscillator stabilization - LXTALSTB: u1, - /// LXTAL bypass mode enable - LXTALBPS: u1, - reserved8: u5, - /// RTC clock entry selection - RTCSRC: u2, - reserved15: u5, - /// RTC clock enable - RTCEN: u1, - /// Backup domain reset - BKPRST: u1, - padding: u15, - }), - /// Reset source /clock register (RCU_RSTSCK) - RSTSCK: mmio.Mmio(packed struct(u32) { - /// IRC40K enable - IRC40KEN: u1, - /// IRC40K stabilization - IRC40KSTB: u1, - reserved24: u22, - /// Reset flag clear - RSTFC: u1, - reserved26: u1, - /// External PIN reset flag - EPRSTF: u1, - /// Power reset flag - PORRSTF: u1, - /// Software reset flag - SWRSTF: u1, - /// Free Watchdog timer reset flag - FWDGTRSTF: u1, - /// Window watchdog timer reset flag - WWDGTRSTF: u1, - /// Low-power reset flag - LPRSTF: u1, - }), - /// AHB reset register - AHBRST: mmio.Mmio(packed struct(u32) { - reserved12: u12, - /// USBFS reset - USBFSRST: u1, - padding: u19, - }), - /// Clock Configuration register 1 - CFG1: mmio.Mmio(packed struct(u32) { - /// PREDV0 division factor - PREDV0: u4, - /// PREDV1 division factor - PREDV1: u4, - /// The PLL1 clock multiplication factor - PLL1MF: u4, - /// The PLL2 clock multiplication factor - PLL2MF: u4, - /// PREDV0 input Clock Source Selection - PREDV0SEL: u1, - /// I2S1 Clock Source Selection - I2S1SEL: u1, - /// I2S2 Clock Source Selection - I2S2SEL: u1, - padding: u13, - }), - reserved52: [4]u8, - /// Deep sleep mode Voltage register - DSV: mmio.Mmio(packed struct(u32) { - /// Deep-sleep mode voltage select - DSLPVS: u2, - padding: u30, - }), - }; - - /// Real-time clock - pub const RTC = extern struct { - /// RTC interrupt enable register - INTEN: mmio.Mmio(packed struct(u32) { - /// Second interrupt - SCIE: u1, - /// Alarm interrupt enable - ALRMIE: u1, - /// Overflow interrupt enable - OVIE: u1, - padding: u29, - }), - /// control register - CTL: mmio.Mmio(packed struct(u32) { - /// Sencond interrupt flag - SCIF: u1, - /// Alarm interrupt flag - ALRMIF: u1, - /// Overflow interrupt flag - OVIF: u1, - /// Registers synchronized flag - RSYNF: u1, - /// Configuration mode flag - CMF: u1, - /// Last write operation finished flag - LWOFF: u1, - padding: u26, - }), - /// RTC prescaler high register - PSCH: mmio.Mmio(packed struct(u32) { - padding: u32, - }), - /// RTC prescaler low register - PSCL: mmio.Mmio(packed struct(u32) { - padding: u32, - }), - /// RTC divider high register - DIVH: mmio.Mmio(packed struct(u32) { - /// RTC divider value high - DIV: u4, - padding: u28, - }), - /// RTC divider low register - DIVL: mmio.Mmio(packed struct(u32) { - /// RTC divider value low - DIV: u16, - padding: u16, - }), - /// RTC counter high register - CNTH: mmio.Mmio(packed struct(u32) { - /// RTC counter value high - CNT: u16, - padding: u16, - }), - /// RTC counter low register - CNTL: mmio.Mmio(packed struct(u32) { - /// RTC counter value low - CNT: u16, - padding: u16, - }), - }; - - /// Serial peripheral interface - pub const SPI0 = extern struct { - /// control register 0 - CTL0: mmio.Mmio(packed struct(u16) { - /// Clock Phase Selection - CKPH: u1, - /// Clock polarity Selection - CKPL: u1, - /// Master Mode Enable - MSTMOD: u1, - /// Master Clock Prescaler Selection - PSC: u3, - /// SPI enable - SPIEN: u1, - /// LSB First Mode - LF: u1, - /// NSS Pin Selection In NSS Software Mode - SWNSS: u1, - /// NSS Software Mode Selection - SWNSSEN: u1, - /// Receive only - RO: u1, - /// Data frame format - FF16: u1, - /// CRC Next Transfer - CRCNT: u1, - /// CRC Calculation Enable - CRCEN: u1, - /// Bidirectional Transmit output enable - BDOEN: u1, - /// Bidirectional enable - BDEN: u1, - }), - reserved4: [2]u8, - /// control register 1 - CTL1: mmio.Mmio(packed struct(u16) { - /// Rx buffer DMA enable - DMAREN: u1, - /// Transmit Buffer DMA Enable - DMATEN: u1, - /// Drive NSS Output - NSSDRV: u1, - /// SPI NSS pulse mode enable - NSSP: u1, - /// SPI TI mode enable - TMOD: u1, - /// Error interrupt enable - ERRIE: u1, - /// RX buffer not empty interrupt enable - RBNEIE: u1, - /// Tx buffer empty interrupt enable - TBEIE: u1, - padding: u8, - }), - reserved8: [2]u8, - /// status register - STAT: mmio.Mmio(packed struct(u16) { - /// Receive Buffer Not Empty - RBNE: u1, - /// Transmit Buffer Empty - TBE: u1, - /// I2S channel side - I2SCH: u1, - /// Transmission underrun error bit - TXURERR: u1, - /// SPI CRC Error Bit - CRCERR: u1, - /// SPI Configuration error - CONFERR: u1, - /// Reception Overrun Error Bit - RXORERR: u1, - /// Transmitting On-going Bit - TRANS: u1, - /// Format error - FERR: u1, - padding: u7, - }), - reserved12: [2]u8, - /// data register - DATA: mmio.Mmio(packed struct(u16) { - /// Data transfer register - SPI_DATA: u16, - }), - reserved16: [2]u8, - /// CRC polynomial register - CRCPOLY: mmio.Mmio(packed struct(u16) { - /// CRC polynomial value - CRCPOLY: u16, - }), - reserved20: [2]u8, - /// RX CRC register - RCRC: mmio.Mmio(packed struct(u16) { - /// RX CRC value - RCRC: u16, - }), - reserved24: [2]u8, - /// TX CRC register - TCRC: mmio.Mmio(packed struct(u16) { - /// Tx CRC value - TCRC: u16, - }), - reserved28: [2]u8, - /// I2S control register - I2SCTL: mmio.Mmio(packed struct(u16) { - /// Channel length (number of bits per audio channel) - CHLEN: u1, - /// Data length - DTLEN: u2, - /// Idle state clock polarity - CKPL: u1, - /// I2S standard selection - I2SSTD: u2, - reserved7: u1, - /// PCM frame synchronization mode - PCMSMOD: u1, - /// I2S operation mode - I2SOPMOD: u2, - /// I2S Enable - I2SEN: u1, - /// I2S mode selection - I2SSEL: u1, - padding: u4, - }), - reserved32: [2]u8, - /// I2S prescaler register - I2SPSC: mmio.Mmio(packed struct(u16) { - /// Dividing factor for the prescaler - DIV: u8, - /// Odd factor for the prescaler - OF: u1, - /// I2S_MCK output enable - MCKOEN: u1, - padding: u6, - }), - }; - - /// Universal asynchronous receiver transmitter - pub const UART3 = extern struct { - /// Status register - STAT: mmio.Mmio(packed struct(u32) { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - padding: u23, - }), - /// Data register - DATA: mmio.Mmio(packed struct(u32) { - /// Transmit or read data value - DATA: u9, - padding: u23, - }), - /// Baud rate register - BAUD: mmio.Mmio(packed struct(u32) { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding: u16, - }), - /// Control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding: u18, - }), - /// Control register 1 - CTL1: mmio.Mmio(packed struct(u32) { - /// Address of the USART - ADDR: u4, - reserved5: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved12: u5, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding: u17, - }), - /// Control register 2 - CTL2: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - reserved6: u2, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - padding: u24, - }), - /// Guard time and prescaler register - GP: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - padding: u24, - }), - }; - - /// Universal synchronous asynchronous receiver transmitter - pub const USART0 = extern struct { - /// Status register - STAT: mmio.Mmio(packed struct(u32) { - /// Parity error flag - PERR: u1, - /// Frame error flag - FERR: u1, - /// Noise error flag - NERR: u1, - /// Overrun error - ORERR: u1, - /// IDLE frame detected flag - IDLEF: u1, - /// Read data buffer not empty - RBNE: u1, - /// Transmission complete - TC: u1, - /// Transmit data buffer empty - TBE: u1, - /// LIN break detection flag - LBDF: u1, - /// CTS change flag - CTSF: u1, - padding: u22, - }), - /// Data register - DATA: mmio.Mmio(packed struct(u32) { - /// Transmit or read data value - DATA: u9, - padding: u23, - }), - /// Baud rate register - BAUD: mmio.Mmio(packed struct(u32) { - /// Fraction part of baud-rate divider - FRADIV: u4, - /// Integer part of baud-rate divider - INTDIV: u12, - padding: u16, - }), - /// Control register 0 - CTL0: mmio.Mmio(packed struct(u32) { - /// Send break command - SBKCMD: u1, - /// Receiver wakeup from mute mode - RWU: u1, - /// Receiver enable - REN: u1, - /// Transmitter enable - TEN: u1, - /// IDLE line detected interrupt enable - IDLEIE: u1, - /// Read data buffer not empty interrupt and overrun error interrupt enable - RBNEIE: u1, - /// Transmission complete interrupt enable - TCIE: u1, - /// Transmitter buffer empty interrupt enable - TBEIE: u1, - /// Parity error interrupt enable - PERRIE: u1, - /// Parity mode - PM: u1, - /// Parity check function enable - PCEN: u1, - /// Wakeup method in mute mode - WM: u1, - /// Word length - WL: u1, - /// USART enable - UEN: u1, - padding: u18, - }), - /// Control register 1 - CTL1: mmio.Mmio(packed struct(u32) { - /// Address of the USART - ADDR: u4, - reserved5: u1, - /// LIN break frame length - LBLEN: u1, - /// LIN break detection interrupt enable - LBDIE: u1, - reserved8: u1, - /// CK Length - CLEN: u1, - /// Clock phase - CPH: u1, - /// Clock polarity - CPL: u1, - /// CK pin enable - CKEN: u1, - /// STOP bits length - STB: u2, - /// LIN mode enable - LMEN: u1, - padding: u17, - }), - /// Control register 2 - CTL2: mmio.Mmio(packed struct(u32) { - /// Error interrupt enable - ERRIE: u1, - /// IrDA mode enable - IREN: u1, - /// IrDA low-power - IRLP: u1, - /// Half-duplex selection - HDEN: u1, - /// Smartcard NACK enable - NKEN: u1, - /// Smartcard mode enable - SCEN: u1, - /// DMA request enable for reception - DENR: u1, - /// DMA request enable for transmission - DENT: u1, - /// RTS enable - RTSEN: u1, - /// CTS enable - CTSEN: u1, - /// CTS interrupt enable - CTSIE: u1, - padding: u21, - }), - /// Guard time and prescaler register - GP: mmio.Mmio(packed struct(u32) { - /// Prescaler value - PSC: u8, - /// Guard time value in Smartcard mode - GUAT: u8, - padding: u16, - }), - }; - - /// Advanced-timers - pub const TIMER0 = extern struct { - /// control register 0 - CTL0: mmio.Mmio(packed struct(u16) { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding: u6, - }), - reserved4: [2]u8, - /// control register 1 - CTL1: mmio.Mmio(packed struct(u16) { - /// Commutation control shadow enable - CCSE: u1, - reserved2: u1, - /// Commutation control shadow register update control - CCUC: u1, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - /// Idle state of channel 0 output - ISO0: u1, - /// Idle state of channel 0 complementary output - ISO0N: u1, - /// Idle state of channel 1 output - ISO1: u1, - /// Idle state of channel 1 complementary output - ISO1N: u1, - /// Idle state of channel 2 output - ISO2: u1, - /// Idle state of channel 2 complementary output - ISO2N: u1, - /// Idle state of channel 3 output - ISO3: u1, - padding: u1, - }), - reserved8: [2]u8, - /// slave mode configuration register - SMCFG: mmio.Mmio(packed struct(u16) { - /// Slave mode selection - SMC: u3, - reserved4: u1, - /// Trigger selection - TRGS: u3, - /// Master/Slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), - reserved12: [2]u8, - /// DMA/Interrupt enable register - DMAINTEN: mmio.Mmio(packed struct(u16) { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - /// commutation interrupt enable - CMTIE: u1, - /// Trigger interrupt enable - TRGIE: u1, - /// Break interrupt enable - BRKIE: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - /// Commutation DMA request enable - CMTDEN: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding: u1, - }), - reserved16: [2]u8, - /// Interrupt flag register - INTF: mmio.Mmio(packed struct(u16) { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt flag - CH2IF: u1, - /// Channel 3 capture/compare interrupt flag - CH3IF: u1, - /// Channel commutation interrupt flag - CMTIF: u1, - /// Trigger interrupt flag - TRGIF: u1, - /// Break interrupt flag - BRKIF: u1, - reserved9: u1, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding: u3, - }), - reserved20: [2]u8, - /// Software event generation register - SWEVG: mmio.Mmio(packed struct(u16) { - /// Update event generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - /// Channel commutation event generation - CMTG: u1, - /// Trigger event generation - TRGG: u1, - /// Break event generation - BRKG: u1, - padding: u8, - }), - reserved24: [2]u8, - /// Channel control register 0 (output mode) - CHCTL0_Output: mmio.Mmio(packed struct(u16) { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), - reserved28: [2]u8, - /// Channel control register 1 (output mode) - CHCTL1_Output: mmio.Mmio(packed struct(u16) { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), - reserved32: [2]u8, - /// Channel control register 2 - CHCTL2: mmio.Mmio(packed struct(u16) { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - /// Channel 0 complementary output enable - CH0NEN: u1, - /// Channel 0 complementary output polarity - CH0NP: u1, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - /// Channel 1 complementary output enable - CH1NEN: u1, - /// Channel 1 complementary output polarity - CH1NP: u1, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - /// Channel 2 complementary output enable - CH2NEN: u1, - /// Channel 2 complementary output polarity - CH2NP: u1, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding: u2, - }), - reserved36: [2]u8, - /// counter - CNT: mmio.Mmio(packed struct(u16) { - /// current counter value - CNT: u16, - }), - reserved40: [2]u8, - /// prescaler - PSC: mmio.Mmio(packed struct(u16) { - /// Prescaler value of the counter clock - PSC: u16, - }), - reserved44: [2]u8, - /// Counter auto reload register - CAR: mmio.Mmio(packed struct(u16) { - /// Counter auto reload value - CARL: u16, - }), - reserved48: [2]u8, - /// Counter repetition register - CREP: mmio.Mmio(packed struct(u16) { - /// Counter repetition value - CREP: u8, - padding: u8, - }), - reserved52: [2]u8, - /// Channel 0 capture/compare value register - CH0CV: mmio.Mmio(packed struct(u16) { - /// Capture or compare value of channel0 - CH0VAL: u16, - }), - reserved56: [2]u8, - /// Channel 1 capture/compare value register - CH1CV: mmio.Mmio(packed struct(u16) { - /// Capture or compare value of channel1 - CH1VAL: u16, - }), - reserved60: [2]u8, - /// Channel 2 capture/compare value register - CH2CV: mmio.Mmio(packed struct(u16) { - /// Capture or compare value of channel 2 - CH2VAL: u16, - }), - reserved64: [2]u8, - /// Channel 3 capture/compare value register - CH3CV: mmio.Mmio(packed struct(u16) { - /// Capture or compare value of channel 3 - CH3VAL: u16, - }), - reserved68: [2]u8, - /// channel complementary protection register - CCHP: mmio.Mmio(packed struct(u16) { - /// Dead time configure - DTCFG: u8, - /// Complementary register protect control - PROT: u2, - /// Idle mode off-state configure - IOS: u1, - /// Run mode off-state configure - ROS: u1, - /// Break enable - BRKEN: u1, - /// Break polarity - BRKP: u1, - /// Output automatic enable - OAEN: u1, - /// Primary output enable - POEN: u1, - }), - reserved72: [2]u8, - /// DMA configuration register - DMACFG: mmio.Mmio(packed struct(u16) { - /// DMA transfer access start address - DMATA: u5, - reserved8: u3, - /// DMA transfer count - DMATC: u5, - padding: u3, - }), - reserved76: [2]u8, - /// DMA transfer buffer register - DMATB: mmio.Mmio(packed struct(u16) { - /// DMA transfer buffer - DMATB: u16, - }), - }; - - /// General-purpose-timers - pub const TIMER1 = extern struct { - /// control register 0 - CTL0: mmio.Mmio(packed struct(u16) { - /// Counter enable - CEN: u1, - /// Update disable - UPDIS: u1, - /// Update source - UPS: u1, - /// Single pulse mode - SPM: u1, - /// Direction - DIR: u1, - /// Counter aligns mode selection - CAM: u2, - /// Auto-reload shadow enable - ARSE: u1, - /// Clock division - CKDIV: u2, - padding: u6, - }), - reserved4: [2]u8, - /// control register 1 - CTL1: mmio.Mmio(packed struct(u16) { - reserved3: u3, - /// DMA request source selection - DMAS: u1, - /// Master mode control - MMC: u3, - /// Channel 0 trigger input selection - TI0S: u1, - padding: u8, - }), - reserved8: [2]u8, - /// slave mode control register - SMCFG: mmio.Mmio(packed struct(u16) { - /// Slave mode control - SMC: u3, - reserved4: u1, - /// Trigger selection - TRGS: u3, - /// Master-slave mode - MSM: u1, - /// External trigger filter control - ETFC: u4, - /// External trigger prescaler - ETPSC: u2, - /// Part of SMC for enable External clock mode1 - SMC1: u1, - /// External trigger polarity - ETP: u1, - }), - reserved12: [2]u8, - /// DMA/Interrupt enable register - DMAINTEN: mmio.Mmio(packed struct(u16) { - /// Update interrupt enable - UPIE: u1, - /// Channel 0 capture/compare interrupt enable - CH0IE: u1, - /// Channel 1 capture/compare interrupt enable - CH1IE: u1, - /// Channel 2 capture/compare interrupt enable - CH2IE: u1, - /// Channel 3 capture/compare interrupt enable - CH3IE: u1, - reserved6: u1, - /// Trigger interrupt enable - TRGIE: u1, - reserved8: u1, - /// Update DMA request enable - UPDEN: u1, - /// Channel 0 capture/compare DMA request enable - CH0DEN: u1, - /// Channel 1 capture/compare DMA request enable - CH1DEN: u1, - /// Channel 2 capture/compare DMA request enable - CH2DEN: u1, - /// Channel 3 capture/compare DMA request enable - CH3DEN: u1, - reserved14: u1, - /// Trigger DMA request enable - TRGDEN: u1, - padding: u1, - }), - reserved16: [2]u8, - /// interrupt flag register - INTF: mmio.Mmio(packed struct(u16) { - /// Update interrupt flag - UPIF: u1, - /// Channel 0 capture/compare interrupt flag - CH0IF: u1, - /// Channel 1 capture/compare interrupt flag - CH1IF: u1, - /// Channel 2 capture/compare interrupt enable - CH2IF: u1, - /// Channel 3 capture/compare interrupt enable - CH3IF: u1, - reserved6: u1, - /// Trigger interrupt flag - TRGIF: u1, - reserved9: u2, - /// Channel 0 over capture flag - CH0OF: u1, - /// Channel 1 over capture flag - CH1OF: u1, - /// Channel 2 over capture flag - CH2OF: u1, - /// Channel 3 over capture flag - CH3OF: u1, - padding: u3, - }), - reserved20: [2]u8, - /// event generation register - SWEVG: mmio.Mmio(packed struct(u16) { - /// Update generation - UPG: u1, - /// Channel 0 capture or compare event generation - CH0G: u1, - /// Channel 1 capture or compare event generation - CH1G: u1, - /// Channel 2 capture or compare event generation - CH2G: u1, - /// Channel 3 capture or compare event generation - CH3G: u1, - reserved6: u1, - /// Trigger event generation - TRGG: u1, - padding: u9, - }), - reserved24: [2]u8, - /// Channel control register 0 (output mode) - CHCTL0_Output: mmio.Mmio(packed struct(u16) { - /// Channel 0 I/O mode selection - CH0MS: u2, - /// Channel 0 output compare fast enable - CH0COMFEN: u1, - /// Channel 0 compare output shadow enable - CH0COMSEN: u1, - /// Channel 0 compare output control - CH0COMCTL: u3, - /// Channel 0 output compare clear enable - CH0COMCEN: u1, - /// Channel 1 mode selection - CH1MS: u2, - /// Channel 1 output compare fast enable - CH1COMFEN: u1, - /// Channel 1 output compare shadow enable - CH1COMSEN: u1, - /// Channel 1 compare output control - CH1COMCTL: u3, - /// Channel 1 output compare clear enable - CH1COMCEN: u1, - }), - reserved28: [2]u8, - /// Channel control register 1 (output mode) - CHCTL1_Output: mmio.Mmio(packed struct(u16) { - /// Channel 2 I/O mode selection - CH2MS: u2, - /// Channel 2 output compare fast enable - CH2COMFEN: u1, - /// Channel 2 compare output shadow enable - CH2COMSEN: u1, - /// Channel 2 compare output control - CH2COMCTL: u3, - /// Channel 2 output compare clear enable - CH2COMCEN: u1, - /// Channel 3 mode selection - CH3MS: u2, - /// Channel 3 output compare fast enable - CH3COMFEN: u1, - /// Channel 3 output compare shadow enable - CH3COMSEN: u1, - /// Channel 3 compare output control - CH3COMCTL: u3, - /// Channel 3 output compare clear enable - CH3COMCEN: u1, - }), - reserved32: [2]u8, - /// Channel control register 2 - CHCTL2: mmio.Mmio(packed struct(u16) { - /// Channel 0 capture/compare function enable - CH0EN: u1, - /// Channel 0 capture/compare function polarity - CH0P: u1, - reserved4: u2, - /// Channel 1 capture/compare function enable - CH1EN: u1, - /// Channel 1 capture/compare function polarity - CH1P: u1, - reserved8: u2, - /// Channel 2 capture/compare function enable - CH2EN: u1, - /// Channel 2 capture/compare function polarity - CH2P: u1, - reserved12: u2, - /// Channel 3 capture/compare function enable - CH3EN: u1, - /// Channel 3 capture/compare function polarity - CH3P: u1, - padding: u2, - }), - reserved36: [2]u8, - /// Counter register - CNT: mmio.Mmio(packed struct(u16) { - /// counter value - CNT: u16, - }), - reserved40: [2]u8, - /// Prescaler register - PSC: mmio.Mmio(packed struct(u16) { - /// Prescaler value of the counter clock - PSC: u16, - }), - reserved44: [2]u8, - /// Counter auto reload register - CAR: mmio.Mmio(packed struct(u16) { - /// Counter auto reload value - CARL: u16, - }), - reserved52: [6]u8, - /// Channel 0 capture/compare value register - CH0CV: mmio.Mmio(packed struct(u32) { - /// Capture or compare value of channel 0 - CH0VAL: u16, - padding: u16, - }), - /// Channel 1 capture/compare value register - CH1CV: mmio.Mmio(packed struct(u32) { - /// Capture or compare value of channel1 - CH1VAL: u16, - padding: u16, - }), - /// Channel 2 capture/compare value register - CH2CV: mmio.Mmio(packed struct(u32) { - /// Capture or compare value of channel 2 - CH2VAL: u16, - padding: u16, - }), - /// Channel 3 capture/compare value register - CH3CV: mmio.Mmio(packed struct(u32) { - /// Capture or compare value of channel 3 - CH3VAL: u16, - padding: u16, - }), - reserved72: [4]u8, - /// DMA configuration register - DMACFG: mmio.Mmio(packed struct(u16) { - /// DMA transfer access start address - DMATA: u5, - reserved8: u3, - /// DMA transfer count - DMATC: u5, - padding: u3, - }), - reserved76: [2]u8, - /// DMA transfer buffer register - DMATB: mmio.Mmio(packed struct(u32) { - /// DMA transfer buffer - DMATB: u16, - padding: u16, - }), - }; - }; -}; From 4eeb5d95f8d23ef36cc26de814d7812d4a89fee1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Thu, 4 Jan 2024 08:59:51 +0100 Subject: [PATCH 20/20] moves gd32 to board-support/gigadevice-gd32 --- LICENSE => board-support/gigadevice-gd32/LICENSE | 0 README.adoc => board-support/gigadevice-gd32/README.adoc | 0 build.zig => board-support/gigadevice-gd32/build.zig | 0 {src => board-support/gigadevice-gd32/src}/boards/longan_nano.zig | 0 {src => board-support/gigadevice-gd32/src}/chips/GD32VF103.json | 0 {src => board-support/gigadevice-gd32/src}/hals/GD32VF103.zig | 0 {test => board-support/gigadevice-gd32/test}/programs/minimal.zig | 0 7 files changed, 0 insertions(+), 0 deletions(-) rename LICENSE => board-support/gigadevice-gd32/LICENSE (100%) rename README.adoc => board-support/gigadevice-gd32/README.adoc (100%) rename build.zig => board-support/gigadevice-gd32/build.zig (100%) rename {src => board-support/gigadevice-gd32/src}/boards/longan_nano.zig (100%) rename {src => board-support/gigadevice-gd32/src}/chips/GD32VF103.json (100%) rename {src => board-support/gigadevice-gd32/src}/hals/GD32VF103.zig (100%) rename {test => board-support/gigadevice-gd32/test}/programs/minimal.zig (100%) diff --git a/LICENSE b/board-support/gigadevice-gd32/LICENSE similarity index 100% rename from LICENSE rename to board-support/gigadevice-gd32/LICENSE diff --git a/README.adoc b/board-support/gigadevice-gd32/README.adoc similarity index 100% rename from README.adoc rename to board-support/gigadevice-gd32/README.adoc diff --git a/build.zig b/board-support/gigadevice-gd32/build.zig similarity index 100% rename from build.zig rename to board-support/gigadevice-gd32/build.zig diff --git a/src/boards/longan_nano.zig b/board-support/gigadevice-gd32/src/boards/longan_nano.zig similarity index 100% rename from src/boards/longan_nano.zig rename to board-support/gigadevice-gd32/src/boards/longan_nano.zig diff --git a/src/chips/GD32VF103.json b/board-support/gigadevice-gd32/src/chips/GD32VF103.json similarity index 100% rename from src/chips/GD32VF103.json rename to board-support/gigadevice-gd32/src/chips/GD32VF103.json diff --git a/src/hals/GD32VF103.zig b/board-support/gigadevice-gd32/src/hals/GD32VF103.zig similarity index 100% rename from src/hals/GD32VF103.zig rename to board-support/gigadevice-gd32/src/hals/GD32VF103.zig diff --git a/test/programs/minimal.zig b/board-support/gigadevice-gd32/test/programs/minimal.zig similarity index 100% rename from test/programs/minimal.zig rename to board-support/gigadevice-gd32/test/programs/minimal.zig