Runs zig fmt, implements a good bunch of I²C functions (#65)
Co-authored-by: Felix "xq" Queißner <xq@random-projects.net>wch-ch32v003
Felix Queißner
1 year ago
committed by
GitHub
parent
316e241a88
commit
371d4efde4
@ -1 +1 @@
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Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
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Subproject commit a49fad973077dffd5fa0b392720295ad033f076e
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@ -0,0 +1,413 @@
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const std = @import("std");
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const microzig = @import("microzig");
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const peripherals = microzig.chip.peripherals;
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const I2C0 = peripherals.I2C0;
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const I2C1 = peripherals.I2C1;
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const gpio = @import("gpio.zig");
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const clocks = @import("clocks.zig");
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const resets = @import("resets.zig");
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const time = @import("time.zig");
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const hw = @import("hw.zig");
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const I2cRegs = microzig.chip.types.peripherals.I2C0;
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pub const Config = struct {
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clock_config: clocks.GlobalConfiguration,
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sda_pin: ?gpio.Pin = gpio.num(20), // both pins only have I²C as alternate function
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scl_pin: ?gpio.Pin = gpio.num(21), // both pins only have I²C as alternate function
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baud_rate: u32 = 100_000,
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};
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pub fn num(n: u1) I2C {
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return @enumFromInt(I2C, n);
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}
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pub const Address = enum(u7) {
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_,
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pub fn new(addr: u7) Address {
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var a = @enumFromInt(Address, addr);
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std.debug.assert(!a.is_reserved());
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return a;
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}
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pub fn is_reserved(addr: Address) bool {
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return ((@intFromEnum(addr) & 0x78) == 0) or ((@intFromEnum(addr) & 0x78) == 0x78);
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}
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pub fn format(addr: Address, fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
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_ = fmt;
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_ = options;
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try writer.print("I2C(0x{X:0>2}", .{@intFromEnum(addr)});
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}
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};
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pub const I2C = enum(u1) {
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_,
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fn get_regs(i2c: I2C) *volatile I2cRegs {
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return switch (@intFromEnum(i2c)) {
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0 => I2C0,
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1 => I2C1,
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};
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}
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fn disable(i2c: I2C) void {
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i2c.get_regs().IC_ENABLE.write(.{
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.ENABLE = .{ .value = .DISABLED },
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.ABORT = .{ .value = .DISABLE },
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.TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
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.padding = 0,
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});
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}
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fn enable(i2c: I2C) void {
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i2c.get_regs().IC_ENABLE.write(.{
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.ENABLE = .{ .value = .ENABLED },
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.ABORT = .{ .value = .DISABLE },
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.TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
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.padding = 0,
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});
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}
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/// Initialise the I2C HW block.
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pub fn apply(i2c: I2C, comptime config: Config) u32 {
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const peri_freq = (comptime config.clock_config.get_frequency(.clk_sys)) orelse @compileError("clk_sys must be set for I²C");
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const regs = i2c.get_regs();
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i2c.disable();
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regs.IC_ENABLE.write(.{
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.ENABLE = .{ .value = .DISABLED },
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.ABORT = .{ .value = .DISABLE },
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.TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
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.padding = 0,
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});
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// Configure as a fast-mode master with RepStart support, 7-bit addresses
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regs.IC_CON.write(.{
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.MASTER_MODE = .{ .value = .ENABLED },
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.SPEED = .{ .value = .FAST },
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.IC_RESTART_EN = .{ .value = .ENABLED },
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.IC_SLAVE_DISABLE = .{ .value = .SLAVE_DISABLED },
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.TX_EMPTY_CTRL = .{ .value = .ENABLED },
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.IC_10BITADDR_SLAVE = .{ .raw = 0 },
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.IC_10BITADDR_MASTER = .{ .raw = 0 },
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.STOP_DET_IFADDRESSED = .{ .raw = 0 },
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.RX_FIFO_FULL_HLD_CTRL = .{ .raw = 0 },
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.STOP_DET_IF_MASTER_ACTIVE = 0,
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.padding = 0,
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});
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// Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0.
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regs.IC_RX_TL.write(.{ .RX_TL = 0, .padding = 0 });
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regs.IC_TX_TL.write(.{ .TX_TL = 0, .padding = 0 });
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// Always enable the DREQ signalling -- harmless if DMA isn't listening
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regs.IC_DMA_CR.write(.{
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.RDMAE = .{ .value = .ENABLED },
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.TDMAE = .{ .value = .ENABLED },
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.padding = 0,
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});
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if (config.sda_pin) |pin| {
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pin.set_function(.i2c);
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pin.set_pull(.up);
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// TODO: Set slew rate
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}
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if (config.scl_pin) |pin| {
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pin.set_function(.i2c);
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pin.set_pull(.up);
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// TODO: Set slew rate
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}
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// Re-sets regs.enable upon returning:
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return i2c.set_baudrate(config.baud_rate, peri_freq);
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}
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/// Set I2C baudrate.
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pub fn set_baudrate(i2c: I2C, baud_rate: u32, freq_in: u32) u32 {
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std.debug.assert(baud_rate != 0);
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// I2C is synchronous design that runs from clk_sys
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const regs = i2c.get_regs();
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// TODO there are some subtleties to I2C timing which we are completely ignoring here
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const period: u32 = (freq_in + baud_rate / 2) / baud_rate;
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const lcnt: u32 = period * 3 / 5; // oof this one hurts
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const hcnt: u32 = period - lcnt;
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// Check for out-of-range divisors:
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std.debug.assert(hcnt <= std.math.maxInt(u16));
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std.debug.assert(lcnt <= std.math.maxInt(u16));
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std.debug.assert(hcnt >= 8);
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std.debug.assert(lcnt >= 8);
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// Per I2C-bus specification a device in standard or fast mode must
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// internally provide a hold time of at least 300ns for the SDA signal to
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// bridge the undefined region of the falling edge of SCL. A smaller hold
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// time of 120ns is used for fast mode plus.
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const sda_tx_hold_count: u32 = if (baud_rate < 1_000_000)
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// sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns)
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// Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint.
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// Add 1 to avoid division truncation.
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((freq_in * 3) / 10000000) + 1
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else
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// sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns)
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// Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint.
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// Add 1 to avoid division truncation.
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((freq_in * 3) / 25000000) + 1;
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std.debug.assert(sda_tx_hold_count <= lcnt - 2);
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i2c.disable();
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// Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
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regs.IC_CON.modify(.{ .SPEED = .{ .value = .FAST } });
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regs.IC_FS_SCL_HCNT.write(.{ .IC_FS_SCL_HCNT = @intCast(u16, hcnt), .padding = 0 });
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regs.IC_FS_SCL_LCNT.write(.{ .IC_FS_SCL_LCNT = @intCast(u16, lcnt), .padding = 0 });
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regs.IC_FS_SPKLEN.write(.{ .IC_FS_SPKLEN = if (lcnt < 16) 1 else @intCast(u8, lcnt / 16), .padding = 0 });
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regs.IC_SDA_HOLD.modify(.{ .IC_SDA_TX_HOLD = @intCast(u16, sda_tx_hold_count) });
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i2c.enable();
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return freq_in / period;
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}
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// /// Set I2C port to slave mode.
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// pub fn set_slave_mode(i2c: I2C, slave: bool, addr: u8) void {
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// //
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// }
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pub const WriteBlockingUntilError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
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/// Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached.
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pub fn write_blocking_until(i2c: I2C, addr: Address, src: []const u8, until: time.Absolute) WriteBlockingUntilError!usize {
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const Timeout = struct {
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limit: time.Absolute,
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inline fn perform(tc: @This()) !void {
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if (tc.limit.is_reached())
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return error.Timeout;
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}
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};
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return i2c.write_blocking_internal(addr, src, Timeout{ .limit = until });
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}
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pub const ReadBlockingUntilError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
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/// Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached.
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pub fn read_blocking_until(i2c: I2C, addr: Address, dst: []u8, until: time.Absolute) ReadBlockingUntilError!usize {
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const Timeout = struct {
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limit: time.Absolute,
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inline fn perform(tc: @This()) !void {
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if (tc.limit.is_reached())
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return error.Timeout;
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}
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};
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return i2c.read_blocking_internal(addr, dst, Timeout{ .limit = until });
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}
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pub const WriteTimeoutUsError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
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/// Attempt to write specified number of bytes to address, with timeout.
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pub fn write_timeout_us(i2c: I2C, addr: Address, src: []const u8, timeout: time.Duration) WriteTimeoutUsError!usize {
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return i2c.write_blocking_until(addr, src, time.get_time_since_boot().add_duration(timeout));
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}
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pub const ReadTimeoutUsError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
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/// Attempt to read specified number of bytes from address, with timeout.
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pub fn read_timeout_us(i2c: I2C, addr: Address, dst: []u8, timeout: time.Duration) ReadTimeoutUsError!usize {
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return i2c.read_blocking_until(addr, dst, time.get_time_since_boot().add_duration(timeout));
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}
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/// Attempt to write specified number of bytes to address, blocking.
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pub const WriteBlockingError = error{ DeviceNotPresent, NoAcknowledge, Unexpected };
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pub fn write_blocking(i2c: I2C, addr: Address, src: []const u8) WriteBlockingError!usize {
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const Timeout = struct {
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inline fn perform(tc: @This()) !void {
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_ = tc;
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}
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};
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return try i2c.write_blocking_internal(addr, src, Timeout{});
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}
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/// Attempt to read specified number of bytes from address, blocking.
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pub const ReadBlockingError = error{ DeviceNotPresent, NoAcknowledge, Unexpected };
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pub fn read_blocking(i2c: I2C, addr: Address, dst: []u8) ReadBlockingError!usize {
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const Timeout = struct {
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inline fn perform(tc: @This()) !void {
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_ = tc;
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}
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};
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try i2c.read_blocking_internal(addr, dst, Timeout{});
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}
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/// Determine non-blocking write space available.
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pub inline fn get_write_available(i2c: I2C) u5 {
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return i2c.get_regs().IC_TXFLR.read().TXFLR;
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}
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/// Determine number of bytes received.
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pub inline fn get_read_available(i2c: I2C) u5 {
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return i2c.get_regs().IC_RXFLR.read().RXFLR;
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}
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// /// Write direct to TX FIFO.
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// pub fn write_raw_blocking(i2c: I2C, src: []const u8) void {
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// //
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// }
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// /// Read direct from RX FIFO.
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// pub fn read_raw_blocking(i2c: I2C, dst: []u8) void {
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// //
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// }
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// /// Pop a byte from I2C Rx FIFO.
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// pub fn read_byte_raw(i2c: I2C) u8 {
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// //
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// }
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// /// Push a byte into I2C Tx FIFO.
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// pub fn write_byte_raw(i2c: I2C, value: u8) void {
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// //
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// }
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// /// Return the DREQ to use for pacing transfers to/from a particular I2C instance.
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// pub fn get_dreq(i2c: I2C, is_tx: bool) u32 {
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// //
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// }
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fn set_address(i2c: I2C, addr: Address) void {
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i2c.disable();
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i2c.get_regs().IC_TAR.write(.{
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.IC_TAR = @intFromEnum(addr),
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.GC_OR_START = .{ .value = .GENERAL_CALL },
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.SPECIAL = .{ .value = .DISABLED },
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.padding = 0,
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});
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i2c.enable();
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}
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fn write_blocking_internal(i2c: I2C, addr: Address, src: []const u8, timeout_check: anytype) !usize {
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std.debug.assert(!addr.is_reserved());
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// Synopsys hw accepts start/stop flags alongside data items in the same
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// FIFO word, so no 0 byte transfers.
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std.debug.assert(src.len > 0);
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const regs = i2c.get_regs();
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i2c.set_address(addr);
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{
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// If the transaction was aborted or if it completed
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// successfully wait until the STOP condition has occured.
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defer blk: {
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// TODO Could there be an abort while waiting for the STOP
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// condition here? If so, additional code would be needed here
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// to take care of the abort.
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while (regs.IC_RAW_INTR_STAT.read().STOP_DET.value == .INACTIVE) {
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timeout_check.perform() catch break :blk;
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hw.tight_loop_contents();
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}
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// If there was a timeout, don't attempt to do anything else.
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_ = regs.IC_CLR_STOP_DET.read();
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}
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for (src, 0..) |byte, i| {
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const first = (i == 0);
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const last = (i == (src.len - 1));
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regs.IC_DATA_CMD.write(.{
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.RESTART = .{ .raw = @intFromBool(first) }, // TODO: Implement non-restarting variant
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.STOP = .{ .raw = @intFromBool(last) }, // TODO: Implement non-restarting variant
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.CMD = .{ .value = .WRITE },
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.DAT = byte,
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.FIRST_DATA_BYTE = .{ .value = .INACTIVE },
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.padding = 0,
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});
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// Wait until the transmission of the address/data from the internal
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// shift register has completed. For this to function correctly, the
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// TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag
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// was set in i2c_init.
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while (regs.IC_RAW_INTR_STAT.read().TX_EMPTY.value == .INACTIVE) {
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try timeout_check.perform();
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hw.tight_loop_contents();
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}
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const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
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if (@bitCast(u32, abort_reason) != 0) {
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// Note clearing the abort flag also clears the reason, and
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// this instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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_ = regs.IC_CLR_TX_ABRT.read();
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if (abort_reason.ABRT_7B_ADDR_NOACK.value == .ACTIVE) {
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// No reported errors - seems to happen if there is nothing connected to the bus.
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// Address byte not acknowledged
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return error.DeviceNotPresent;
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}
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if (abort_reason.ABRT_TXDATA_NOACK.value == .ABRT_TXDATA_NOACK_GENERATED) {
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// TODO: How to handle this, also possible to do "return i;" here to signal not everything was transferred
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return error.NoAcknowledge;
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}
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std.log.debug("unexpected i2c abort while writing to {}: {}", .{ addr, abort_reason });
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return error.Unexpected;
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}
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}
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}
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return src.len;
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}
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fn read_blocking_internal(i2c: I2C, addr: Address, dst: []u8, timeout_check: anytype) !usize {
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std.debug.assert(!addr.is_reserved());
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const regs = i2c.get_regs();
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i2c.set_address(addr);
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for (dst, 0..) |*byte, i| {
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const first = (i == 0);
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const last = (i == dst.len - 1);
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while (i2c.get_write_available(i2c) == 0) {
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hw.tight_loop_contents();
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}
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regs.IC_DATA_CMD.write(.{
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.RESTART = .{ .raw = @intFromBool(first) }, // TODO: Implement non-restarting variant
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.STOP = .{ .raw = @intFromBool(last) }, // TODO: Implement non-restarting variant
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.CMD = .{ .value = .READ },
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.DAT = 0,
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.FIRST_DATA_BYTE = .{ .value = 0 },
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.padding = 0,
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});
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while (i2c.get_read_available() == 0) {
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const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
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const abort = (regs.IC_CLR_TX_ABRT.read().CLR_TX_ABRT != 0);
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if (abort) {
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if (abort_reason.ABRT_7B_ADDR_NOACK.value == .ACTIVE)
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return error.DeviceNotPresent;
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std.log.debug("unexpected i2c abort while reading from {}: {}", .{ addr, abort_reason });
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return error.Unexpected;
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}
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try timeout_check.perform();
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}
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byte.* = regs.IC_DATA_CMD.read().DAT;
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}
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return dst.len;
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}
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};
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