impl vector_table generation for wch ch32
parent
b5d657a009
commit
263528061d
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const std = @import("std");
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const mz = @import("microzig");
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const periph = mz.chip.peripherals;
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const RCC = periph.RCC;
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const FLASH = periph.FLASH;
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pub fn rcc_init_hsi_pll() void {
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const CFG0_PLL_TRIM: *u8 = @ptrFromInt(0x1FFFF7D4); // Factory HSI clock trim value
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if (CFG0_PLL_TRIM.* != 0xFF) {
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RCC.CTLR.modify(.{ .HSITRIM = @as(u5, @truncate(CFG0_PLL_TRIM.*)) });
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}
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FLASH.ACTLR.modify(.{ .LATENCY = 1 }); // Flash wait state 1 for 48MHz clock
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RCC.CFGR0.modify(.{
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.PLLSRC = 0, // HSI
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.HPRE = 0, // Prescaler off
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});
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RCC.CTLR.modify(.{ .PLLON = 1 });
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while (RCC.CTLR.read().PLLRDY != 1) {}
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RCC.CFGR0.modify(.{ .SW = 0b10 }); // Select PLL clock source
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while (RCC.CFGR0.read().SWS != 0b10) {} // Spin until PLL selected
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}
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const std = @import("std");
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const mz = @import("microzig");
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const periph = mz.chip.peripherals;
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pub fn main() !void {
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mz.hal.rcc_init_hsi_pll();
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periph.RCC.APB2PCENR.modify(.{ .IOPCEN = 1 });
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periph.GPIOC.CFGLR.modify(.{ .CNF1 = 0b00, .MODE1 = 0b11 });
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var on: u1 = 0;
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while (true) {
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on ^= 1;
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periph.GPIOC.OUTDR.modify(.{ .ODR1 = on });
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}
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}
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@ -0,0 +1,95 @@
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//! codegen specific to riscv
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const std = @import("std");
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const assert = std.debug.assert;
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const Database = @import("../Database.zig");
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const Arch = Database.Arch;
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const EntityId = Database.EntityId;
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const gen = @import("../gen.zig");
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const InterruptWithIndexAndName = @import("InterruptWithIndexAndName.zig");
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const log = std.log.scoped(.@"gen.riscv");
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pub fn write_interrupt_vector(
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db: Database,
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device_id: EntityId,
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writer: anytype,
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) !void {
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assert(db.entity_is("instance.device", device_id));
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const arch = db.instances.devices.get(device_id).?.arch;
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assert(arch.is_riscv());
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try writer.writeAll(
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\\pub const VectorTable = extern struct {
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\\ const Handler = micro.interrupt.Handler;
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\\ const unhandled = micro.interrupt.unhandled;
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\\
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);
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var index: i32 = 0;
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if (arch == .qingke_v2) { // CPU specific vectors
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try writer.writeAll(
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\\ reserved1: [1]u32 = undefined,
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\\ NMI: Handler = unhandled,
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\\ EXC: Handler = unhandled,
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\\ reserved4: [8]u32 = undefined,
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\\ SysTick: Handler = unhandled,
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\\ reserved13: [1]u32 = undefined,
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\\ SWI: Handler = unhandled,
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\\ reserved15: [1]u32 = undefined,
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\\
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);
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index = 16;
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}
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if (db.children.interrupts.get(device_id)) |interrupt_set| {
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var interrupts = std.ArrayList(InterruptWithIndexAndName).init(db.gpa);
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defer interrupts.deinit();
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var it = interrupt_set.iterator();
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while (it.next()) |entry| {
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const interrupt_id = entry.key_ptr.*;
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const interrupt_index = db.instances.interrupts.get(interrupt_id).?;
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const name = db.attrs.name.get(interrupt_id) orelse continue;
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try interrupts.append(.{
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.id = interrupt_id,
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.name = name,
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.index = interrupt_index,
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});
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}
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std.sort.insertion(
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InterruptWithIndexAndName,
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interrupts.items,
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{},
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InterruptWithIndexAndName.less_than,
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);
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for (interrupts.items) |interrupt| {
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if (index < interrupt.index) {
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try writer.print("reserved{}: [{}]u32 = undefined,\n", .{
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index,
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interrupt.index - index,
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});
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index = interrupt.index;
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} else if (index > interrupt.index) {
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log.warn("skipping interrupt: {s}", .{interrupt.name});
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continue;
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}
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if (db.attrs.description.get(interrupt.id)) |description|
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try gen.write_comment(db.gpa, description, writer);
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try writer.print("{}: Handler = unhandled,\n", .{
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std.zig.fmtId(interrupt.name),
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});
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index += 1;
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}
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}
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try writer.writeAll("};\n\n");
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}
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