organzie (#5)

* organzie

* add buildkite pipeline

.buildkite/pipeline.yml

@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build

build.zig

@@ -1,52 +1,19 @@
 const std = @import("std");
-const microzig = @import("zpm.zig").sdks.microzig;
+const microzig = @import("deps/microzig/build.zig");
+
+pub const chips = @import("src/chips.zig");
+pub const cpus = @import("src/cpus.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
 
-    const esp32_c3_cpu = microzig.Cpu{
-        .name = "Espressif RISC-V",
-        .path = "src/package/espressif-riscv.zig",
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .riscv32,
-            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-            .cpu_features_add = std.Target.riscv.featureSet(&.{
-                std.Target.riscv.Feature.c,
-                std.Target.riscv.Feature.m,
-            }),
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    const esp32_c3 = microzig.Chip{
-        .name = "ESP32 C3",
-        .source = .{
-            .path = "src/package/esp32-c3.zig",
-        },
-        .hal = .{
-            .source = "src/hal/root.zig",
-        },
-
-        .cpu = esp32_c3_cpu,
-        .memory_regions = &.{
-            .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-            .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-        },
-    };
-
     var exe = microzig.addEmbeddedExecutable(b, .{
         .name = "esp-bringup",
         .source_file = .{
             .path = "src/example/blinky.zig",
         },
-        .backing = .{ .chip = esp32_c3 },
+        .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.setBuildMode(mode);
     exe.install();
-
-    const raw_step = exe.installRaw("firmware.bin", .{});
-
-    b.getInstallStep().dependOn(&raw_step.step);
 }

src/chips.zig

@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+const cpus = @import("cpus.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Chip{
+    .name = "ESP32-C3",
+    .source = .{
+        .path = root_dir() ++ "/chips/ESP32_C3.zig",
+    },
+    .hal = .{
+        .path = root_dir() ++ "/hals/ESP32_C3.zig",
+    },
+
+    .cpu = cpus.esp32_c3,
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+    },
+};

src/cpus.zig

@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Cpu{
+    .name = "Espressif RISC-V",
+    .source = .{
+        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
+    },
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};

src/cpus/espressif-riscv.zig

@@ -1,7 +1,41 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const root = @import("root");
 
-pub const registers = @import("registers.zig").registers;
+pub const StatusRegister = enum(u8) {
+    // machine information
+    mvendorid,
+    marchid,
+    mimpid,
+    mhartid,
+
+    // machine trap setup
+    mstatus,
+    misa,
+    mtvec,
+};
+
+pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn cli() void {
+    clearStatusBit(.mstatus, 0x08);
+}
+
+pub inline fn sei() void {
+    setStatusBit(.mstatus, 0x08);
+}
 
 pub const startup_logic = struct {
     comptime {
@@ -35,7 +69,7 @@ pub const startup_logic = struct {
         );
         asm volatile ("la gp, __global_pointer$");
         microzig.cpu.setStatusBit(.mtvec, microzig.config.end_of_stack);
-        microzig.initializeSystemMemories();
+        root.initialize_system_memories();
         microzig_main();
     }
 

src/example/blinky.zig

@@ -1,23 +1,28 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const TIMG0 = peripherals.TIMG0;
+const RTC_CNTL = peripherals.RTC_CNTL;
+const INTERRUPT_CORE0 = peripherals.INTERRUPT_CORE0;
+const GPIO = peripherals.GPIO;
 
 const dogfood: u32 = 0x50D83AA1;
 const super_dogfood: u32 = 0x8F1D312A;
 
 pub fn main() !void {
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.TIMG0.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = 0;
+    TIMG0.WDTWPROTECT.raw = dogfood;
+    TIMG0.WDTCONFIG0.raw = 0;
+    TIMG0.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.RTC_CNTL.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    RTC_CNTL.WDTCONFIG0.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
-    microzig.chip.registers.RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = 0;
+    RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    RTC_CNTL.SWD_WPROTECT.raw = 0;
 
-    microzig.chip.registers.INTERRUPT_CORE0.CPU_INT_ENABLE.* = 0;
+    INTERRUPT_CORE0.CPU_INT_ENABLE.raw = 0;
 
     microzig.hal.gpio.init(LED_R_PIN, .{
         .direction = .output,
@@ -35,15 +40,15 @@ pub fn main() !void {
     microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
     while (true) {
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
-        microzig.debug.busySleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
     }
 }
 

src/hals/ESP32_C3.zig

@@ -1,16 +1,9 @@
 const std = @import("std");
 const microzig = @import("microzig");
-const regz = microzig.chip.registers;
+const peripherals = microzig.chip.peripherals;
+const GPIO = peripherals.GPIO;
 
 pub const gpio = struct {
-    fn getRegNamed(comptime fld: []const u8) @TypeOf(@field(regz.GPIO, fld)) {
-        return @field(regz.GPIO, fld);
-    }
-
-    fn getReg(comptime template: []const u8, comptime pin: comptime_int) @TypeOf(@field(regz.GPIO, std.fmt.comptimePrint(template, .{pin}))) {
-        return getRegNamed(comptime std.fmt.comptimePrint(template, .{pin}));
-    }
-
     fn assertRange(comptime p: comptime_int) void {
         if (p < 0 or p >= 21)
             @compileError(std.fmt.comptimePrint("GPIO {} does not exist. GPIO pins can be between 0 and 21", .{p}));
@@ -19,29 +12,29 @@ pub const gpio = struct {
     pub const Config = struct {
         function: u8 = 0x80,
         invert_function: bool = false,
-        direction: microzig.gpio.Direction,
+        direction: microzig.core.experimental.gpio.Direction,
         direct_io: bool = false,
         invert_direct_io: bool = false,
     };
 
     pub fn init(comptime pin: comptime_int, comptime config: Config) void {
         assertRange(pin);
-        getReg("FUNC{}_OUT_SEL_CFG", pin).modify(.{
+        GPIO.FUNC_OUT_SEL_CFG[pin].modify(.{
             .OUT_SEL = config.function,
             .INV_SEL = @boolToInt(config.invert_function),
             .OEN_SEL = @boolToInt(config.direct_io),
             .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
         });
         switch (config.direction) {
-            .input => microzig.chip.registers.GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
-            .output => microzig.chip.registers.GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
+            .input => GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
+            .output => GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
         }
     }
 };
 
 pub const uart = struct {
-    fn reg(comptime index: comptime_int) @TypeOf(@field(regz, std.fmt.comptimePrint("UART{}", .{index}))) {
-        return @field(regz, std.fmt.comptimePrint("UART{}", .{index}));
+    fn reg(comptime index: comptime_int) @TypeOf(@field(peripherals, std.fmt.comptimePrint("UART{}", .{index}))) {
+        return @field(peripherals, std.fmt.comptimePrint("UART{}", .{index}));
     }
 
     pub fn write(comptime index: comptime_int, slice: []const u8) void {

src/package/espressif-riscv.zig

@@ -1,39 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-pub const StatusRegister = enum(u8) {
-    // machine information
-    mvendorid,
-    marchid,
-    mimpid,
-    mhartid,
-
-    // machine trap setup
-    mstatus,
-    misa,
-    mtvec,
-};
-
-pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn cli() void {
-    clearStatusBit(.mstatus, 0x08);
-}
-
-pub inline fn sei() void {
-    setStatusBit(.mstatus, 0x08);
-}
-
-pub const startup_logic = microzig.chip.startup_logic;